xref: /linux/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h (revision c771600c6af14749609b49565ffb4cac2959710d)
1*e961ec81SQiang Yu /* SPDX-License-Identifier: GPL-2.0 */
2*e961ec81SQiang Yu /*
3*e961ec81SQiang Yu  * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
4*e961ec81SQiang Yu  */
5*e961ec81SQiang Yu 
6*e961ec81SQiang Yu #ifndef QCOM_PHY_QMP_PCS_V6_30_H_
7*e961ec81SQiang Yu #define QCOM_PHY_QMP_PCS_V6_30_H_
8*e961ec81SQiang Yu 
9*e961ec81SQiang Yu /* Only for QMP V6_30 PHY - PCIe PCS registers */
10*e961ec81SQiang Yu #define QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2		0x0cc
11*e961ec81SQiang Yu #define QPHY_V6_30_PCS_G3S2_PRE_GAIN			0x17c
12*e961ec81SQiang Yu #define QPHY_V6_30_PCS_RX_SIGDET_LVL			0x194
13*e961ec81SQiang Yu #define QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7		0x1dc
14*e961ec81SQiang Yu #define QPHY_V6_30_PCS_TX_RX_CONFIG			0x1e0
15*e961ec81SQiang Yu #define QPHY_V6_30_PCS_TX_RX_CONFIG2			0x1e4
16*e961ec81SQiang Yu #define QPHY_V6_30_PCS_EQ_CONFIG4			0x1fc
17*e961ec81SQiang Yu #define QPHY_V6_30_PCS_EQ_CONFIG5			0x200
18*e961ec81SQiang Yu 
19*e961ec81SQiang Yu #endif
20