1*fdfe6417SMatthew Leung /* SPDX-License-Identifier: GPL-2.0 */ 2*fdfe6417SMatthew Leung /* 3*fdfe6417SMatthew Leung * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*fdfe6417SMatthew Leung */ 5*fdfe6417SMatthew Leung 6*fdfe6417SMatthew Leung #ifndef QCOM_PHY_QMP_PCS_V10_60_H_ 7*fdfe6417SMatthew Leung #define QCOM_PHY_QMP_PCS_V10_60_H_ 8*fdfe6417SMatthew Leung 9*fdfe6417SMatthew Leung /* Only for QMP V10_60 PHY - PCIe PCS registers */ 10*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_SW_RESET 0x000 11*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_PCS_STATUS1 0x014 12*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_POWER_DOWN_CONTROL 0x040 13*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_START_CONTROL 0x044 14*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB 0x170 15*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_G3S2_PRE_GAIN 0x178 16*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_RX_SIGDET_LVL 0x190 17*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_ELECIDLE_DLY_SEL 0x1b8 18*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1 0x1dc 19*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2 0x1e0 20*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_EQ_CONFIG4 0x1f8 21*fdfe6417SMatthew Leung #define QPHY_V10_60_PCS_EQ_CONFIG5 0x1fc 22*fdfe6417SMatthew Leung 23*fdfe6417SMatthew Leung #endif 24