1*c4364048SWesley Cheng /* SPDX-License-Identifier: GPL-2.0 */ 2*c4364048SWesley Cheng /* 3*c4364048SWesley Cheng * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4*c4364048SWesley Cheng */ 5*c4364048SWesley Cheng 6*c4364048SWesley Cheng #ifndef QCOM_PHY_QMP_PCS_USB_V8_H_ 7*c4364048SWesley Cheng #define QCOM_PHY_QMP_PCS_USB_V8_H_ 8*c4364048SWesley Cheng 9*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1 0x00 10*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS 0x04 11*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL 0x08 12*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2 0x0c 13*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10 14*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR 0x14 15*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL 0x18 16*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_TX_ECSTART 0x1c 17*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL 0x20 18*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START 0x24 19*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_LFPS_CONFIG1 0x28 20*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME 0x2c 21*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME 0x30 22*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME 0x34 23*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2 0x38 24*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2 0x3c 25*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L 0x40 26*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H 0x44 27*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD 0x48 28*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY 0x4c 29*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH 0x50 30*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL 0x54 31*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL 0x58 32*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_TEST_CONTROL 0x5c 33*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL 0x60 34*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2 0x64 35*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3 0x68 36*c4364048SWesley Cheng #define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4 0x6c 37*c4364048SWesley Cheng 38*c4364048SWesley Cheng #endif 39