1 /* Only for QMP V5 PHY - PCS_PCIE registers */ 2 /* SPDX-License-Identifier: GPL-2.0 */ 3 /* 4 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef QCOM_PHY_QMP_PCS_PCIE_V5_H_ 8 #define QCOM_PHY_QMP_PCS_PCIE_V5_H_ 9 10 /* Only for QMP V5 PHY - PCS_PCIE registers */ 11 #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 12 #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 13 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 14 #define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x44 15 #define QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x48 16 #define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x4c 17 #define QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x50 18 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 19 #define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1 0x5c 20 #define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2 0x60 21 #define QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4 0x68 22 #define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x7c 23 #define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x84 24 #define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x88 25 #define QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x8c 26 #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 27 #define QPHY_V5_PCS_PCIE_EQ_CONFIG1 0xa4 28 #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 29 #define QPHY_V5_PCS_PCIE_PRESET_P10_PRE 0xc0 30 #define QPHY_V5_PCS_PCIE_PRESET_P10_POST 0xe4 31 32 #endif 33