141ad371fSDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 241ad371fSDmitry Baryshkov /* 341ad371fSDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 441ad371fSDmitry Baryshkov */ 541ad371fSDmitry Baryshkov 641ad371fSDmitry Baryshkov #ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_ 741ad371fSDmitry Baryshkov #define QCOM_PHY_QMP_PCS_PCIE_V4_H_ 841ad371fSDmitry Baryshkov 941ad371fSDmitry Baryshkov /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 10*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0x00 11*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0x04 12*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0x08 1341ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 14*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0x10 1541ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 16*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0x18 1741ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 18*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x20 19*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x24 20*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x28 21*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x2c 22*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x30 23*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x34 24*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0x38 25*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x3c 2641ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 27*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x44 2841ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 29*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x4c 3041ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 31*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x54 32*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0x58 33*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0x5c 34*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0x60 35*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0x64 36*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0x68 37*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0x6c 38*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0x70 39*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x74 40*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x78 41*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x7c 42*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x80 43*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x84 44*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x88 45*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x8c 4641ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 47*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_LOCAL_FS 0x94 48*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_LOCAL_LF 0x98 49*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0x9c 5041ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 5141ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 52*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0xa8 53*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0xac 54*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0xb0 5541ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 56*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0xb8 5741ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 58*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0xc0 59*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0xc4 60*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0xc8 61*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0xcc 62*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0xd0 63*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0xd4 64*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0xd8 65*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0xdc 6641ad371fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 67*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0xe4 68*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0xe8 69*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0xec 70*9f2fd65fSDmitry Baryshkov #define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0xf0 7141ad371fSDmitry Baryshkov 7241ad371fSDmitry Baryshkov #endif 73