1*fdfe6417SMatthew Leung /* SPDX-License-Identifier: GPL-2.0 */ 2*fdfe6417SMatthew Leung /* 3*fdfe6417SMatthew Leung * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*fdfe6417SMatthew Leung */ 5*fdfe6417SMatthew Leung 6*fdfe6417SMatthew Leung #ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_ 7*fdfe6417SMatthew Leung #define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_ 8*fdfe6417SMatthew Leung 9*fdfe6417SMatthew Leung /* Only for QMP V10_60 PHY - PCIE PCS registers */ 10*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2 0x00c 11*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG 0x018 12*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE 0x01c 13*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS 0x090 14*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_EQ_CONFIG1 0x0a0 15*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME 0x0f0 16*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME 0x0f4 17*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5 0x108 18*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN 0x15c 19*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1 0x17c 20*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3 0x184 21*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5 0x18c 22*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5 0x1ac 23*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5 0x1c0 24*fdfe6417SMatthew Leung #define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6 0x1d0 25*fdfe6417SMatthew Leung 26*fdfe6417SMatthew Leung #endif 27