1*0696cc73SMatthew Leung /* SPDX-License-Identifier: GPL-2.0 */ 2*0696cc73SMatthew Leung /* 3*0696cc73SMatthew Leung * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4*0696cc73SMatthew Leung */ 5*0696cc73SMatthew Leung 6*0696cc73SMatthew Leung #ifndef QCOM_PHY_QMP_PCS_PCIE_V10_H_ 7*0696cc73SMatthew Leung #define QCOM_PHY_QMP_PCS_PCIE_V10_H_ 8*0696cc73SMatthew Leung 9*0696cc73SMatthew Leung /* Only for QMP V10 PHY - PCIE PCS registers */ 10*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2 0x00c 11*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4 0x014 12*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE 0x020 13*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS 0x094 14*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_EQ_CONFIG1 0x0a4 15*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_RXEQEVAL_TIME 0x0f4 16*0696cc73SMatthew Leung #define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6 0x0f8 17*0696cc73SMatthew Leung 18*0696cc73SMatthew Leung #endif 19