1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 #define PLL_READY_GATE_EN BIT(3) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 40 #define PCS_READY BIT(0) 41 42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 43 /* DP PHY soft reset */ 44 #define SW_DPPHY_RESET BIT(0) 45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_DPPHY_RESET_MUX BIT(1) 47 /* USB3 PHY soft reset */ 48 #define SW_USB3PHY_RESET BIT(2) 49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 50 #define SW_USB3PHY_RESET_MUX BIT(3) 51 52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 53 #define USB3_MODE BIT(0) /* enables USB3 mode */ 54 #define DP_MODE BIT(1) /* enables DP mode */ 55 56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 57 #define ARCVR_DTCT_EN BIT(0) 58 #define ALFPS_DTCT_EN BIT(1) 59 #define ARCVR_DTCT_EVENT_SEL BIT(4) 60 61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 62 #define IRQ_CLEAR BIT(0) 63 64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 65 #define RCVR_DETECT BIT(0) 66 67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 68 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 69 70 #define PHY_INIT_COMPLETE_TIMEOUT 10000 71 #define POWER_DOWN_DELAY_US_MIN 10 72 #define POWER_DOWN_DELAY_US_MAX 11 73 74 #define MAX_PROP_NAME 32 75 76 /* Define the assumed distance between lanes for underspecified device trees. */ 77 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 78 79 struct qmp_phy_init_tbl { 80 unsigned int offset; 81 unsigned int val; 82 /* 83 * register part of layout ? 84 * if yes, then offset gives index in the reg-layout 85 */ 86 bool in_layout; 87 /* 88 * mask of lanes for which this register is written 89 * for cases when second lane needs different values 90 */ 91 u8 lane_mask; 92 }; 93 94 #define QMP_PHY_INIT_CFG(o, v) \ 95 { \ 96 .offset = o, \ 97 .val = v, \ 98 .lane_mask = 0xff, \ 99 } 100 101 #define QMP_PHY_INIT_CFG_L(o, v) \ 102 { \ 103 .offset = o, \ 104 .val = v, \ 105 .in_layout = true, \ 106 .lane_mask = 0xff, \ 107 } 108 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 110 { \ 111 .offset = o, \ 112 .val = v, \ 113 .lane_mask = l, \ 114 } 115 116 /* set of registers with offsets different per-PHY */ 117 enum qphy_reg_layout { 118 /* Common block control registers */ 119 QPHY_COM_SW_RESET, 120 QPHY_COM_POWER_DOWN_CONTROL, 121 QPHY_COM_START_CONTROL, 122 QPHY_COM_PCS_READY_STATUS, 123 /* PCS registers */ 124 QPHY_PLL_LOCK_CHK_DLY_TIME, 125 QPHY_FLL_CNTRL1, 126 QPHY_FLL_CNTRL2, 127 QPHY_FLL_CNT_VAL_L, 128 QPHY_FLL_CNT_VAL_H_TOL, 129 QPHY_FLL_MAN_CODE, 130 QPHY_SW_RESET, 131 QPHY_START_CTRL, 132 QPHY_PCS_READY_STATUS, 133 QPHY_PCS_STATUS, 134 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 137 QPHY_PCS_POWER_DOWN_CONTROL, 138 /* PCS_MISC registers */ 139 QPHY_PCS_MISC_TYPEC_CTRL, 140 /* Keep last to ensure regs_layout arrays are properly initialized */ 141 QPHY_LAYOUT_SIZE 142 }; 143 144 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 145 [QPHY_SW_RESET] = 0x00, 146 [QPHY_START_CTRL] = 0x44, 147 [QPHY_PCS_STATUS] = 0x14, 148 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 149 }; 150 151 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 152 [QPHY_COM_SW_RESET] = 0x400, 153 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 154 [QPHY_COM_START_CONTROL] = 0x408, 155 [QPHY_COM_PCS_READY_STATUS] = 0x448, 156 [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8, 157 [QPHY_FLL_CNTRL1] = 0xc4, 158 [QPHY_FLL_CNTRL2] = 0xc8, 159 [QPHY_FLL_CNT_VAL_L] = 0xcc, 160 [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0, 161 [QPHY_FLL_MAN_CODE] = 0xd4, 162 [QPHY_SW_RESET] = 0x00, 163 [QPHY_START_CTRL] = 0x08, 164 [QPHY_PCS_STATUS] = 0x174, 165 }; 166 167 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 168 [QPHY_SW_RESET] = 0x00, 169 [QPHY_START_CTRL] = 0x08, 170 [QPHY_PCS_STATUS] = 0x174, 171 }; 172 173 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 174 [QPHY_SW_RESET] = 0x00, 175 [QPHY_START_CTRL] = 0x08, 176 [QPHY_PCS_STATUS] = 0x2ac, 177 }; 178 179 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 180 [QPHY_SW_RESET] = 0x00, 181 [QPHY_START_CTRL] = 0x44, 182 [QPHY_PCS_STATUS] = 0x14, 183 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 184 }; 185 186 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 229 }; 230 231 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 232 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 233 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 234 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 235 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 236 }; 237 238 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 239 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 240 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 241 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 242 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 243 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 244 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 245 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 246 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 247 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 248 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 250 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 251 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 252 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 253 }; 254 255 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 256 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 257 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 258 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 259 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 260 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 261 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 262 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 263 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 264 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 265 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 266 }; 267 268 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 269 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 270 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 271 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 272 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 273 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 274 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 275 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 276 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 277 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 278 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 279 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 280 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 281 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 282 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 283 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 284 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 285 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 286 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 287 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 288 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 289 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 290 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 291 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 292 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 293 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 294 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 295 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 296 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 297 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 298 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 299 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 300 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 301 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 302 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 303 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 304 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 305 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 306 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 307 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 308 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 309 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 310 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 311 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 312 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 313 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 314 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 315 }; 316 317 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 318 QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02), 319 QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06), 320 QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12), 321 }; 322 323 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 324 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c), 325 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02), 326 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 327 QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70), 328 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61), 329 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04), 330 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 331 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0), 332 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00), 333 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 334 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 335 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c), 336 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03), 337 QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14), 338 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0), 339 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01), 340 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f), 341 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3), 342 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40), 343 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01), 344 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02), 345 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8), 346 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09), 347 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1), 348 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00), 349 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02), 350 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8), 351 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09), 352 QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1), 353 QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04), 354 }; 355 356 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 357 QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01), 358 QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d), 359 QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10), 360 QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa), 361 QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 362 QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01), 363 QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01), 364 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 365 QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 366 QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 367 QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 368 QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 369 QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 370 QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11), 371 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00), 372 QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58), 373 }; 374 375 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 376 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 377 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 378 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 379 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 380 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 381 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 382 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 383 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 384 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 385 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 386 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 387 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 388 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 389 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 390 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 391 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 392 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 393 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 394 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 395 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 396 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 397 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 398 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 399 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 400 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 401 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 402 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 403 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 404 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 405 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 406 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 407 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 408 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 409 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 410 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 411 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 412 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 413 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 414 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 415 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 416 }; 417 418 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 419 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 420 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 421 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 422 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 423 QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36), 424 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 425 }; 426 427 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 428 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 429 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 430 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 431 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 432 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 433 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 434 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 435 }; 436 437 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 438 QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4), 439 QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0), 440 QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 441 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 442 QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 443 QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 444 QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 445 QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73), 446 QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99), 447 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15), 448 QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe), 449 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 450 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 451 }; 452 453 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 455 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 456 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 457 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 458 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 459 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 460 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 461 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 462 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 463 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 464 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 465 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 466 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 467 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 468 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 469 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 470 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 471 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 472 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 473 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 474 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 475 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 476 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 477 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 478 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 479 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 480 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 481 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 482 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 483 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 484 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 485 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 486 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 487 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 488 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 489 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 496 }; 497 498 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 499 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 500 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 501 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 502 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 503 }; 504 505 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 506 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 507 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 508 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 509 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 510 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 511 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 512 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 513 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 514 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 515 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 516 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 517 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 518 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 519 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 520 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 521 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 522 }; 523 524 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 525 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 526 527 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 528 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 529 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 530 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 531 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 532 533 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 534 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 535 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 536 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 537 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 538 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 539 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 540 541 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 542 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 543 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 544 545 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 546 }; 547 548 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 549 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 550 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 551 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 552 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 553 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 554 }; 555 556 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 557 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 558 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 559 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 560 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 561 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 562 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 563 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 564 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 565 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 566 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 567 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 568 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 569 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 570 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 571 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 572 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 573 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 574 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 575 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 576 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 577 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 578 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 579 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 580 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 581 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 582 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 583 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 584 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 585 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 586 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 587 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 588 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 589 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 590 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 591 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 592 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 593 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 594 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 595 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 596 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 597 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 598 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 599 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 600 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 601 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 602 }; 603 604 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 605 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 606 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 607 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 608 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 609 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 610 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 611 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 612 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 613 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 614 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 615 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 661 }; 662 663 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 664 }; 665 666 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 674 }; 675 676 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 677 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 678 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 679 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 680 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 681 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 682 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 683 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 684 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 685 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 686 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 687 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 688 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 689 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 690 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 691 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 692 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 693 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 694 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 695 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 696 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 697 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 698 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 699 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 700 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 701 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 702 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 703 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 704 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 705 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 706 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 707 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 708 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 709 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 710 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 711 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 712 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 713 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 714 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 719 }; 720 721 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 722 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 723 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 724 }; 725 726 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 739 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 740 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 741 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 742 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 743 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 744 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 745 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 746 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 747 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 763 }; 764 765 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 766 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 767 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 769 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 770 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 771 }; 772 773 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 774 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 775 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 776 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 777 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 778 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 779 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 780 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 781 }; 782 783 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 797 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 798 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 799 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 800 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 825 }; 826 827 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 829 }; 830 831 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 832 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 833 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 834 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 835 }; 836 837 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 838 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 839 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 840 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 841 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 842 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 843 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 844 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 845 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 868 }; 869 870 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 877 }; 878 879 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 880 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 881 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 882 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 883 }; 884 885 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 886 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 887 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 888 }; 889 890 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 891 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 892 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 893 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 894 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 895 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 898 }; 899 900 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 903 }; 904 905 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 907 }; 908 909 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 914 }; 915 916 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 917 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 918 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 919 }; 920 921 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 922 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 923 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 924 }; 925 926 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 938 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 939 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 940 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 941 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 942 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 943 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 944 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 945 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 946 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 947 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 948 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 949 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 950 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 951 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 952 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 966 }; 967 968 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 969 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 970 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 971 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 972 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 973 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 974 }; 975 976 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 977 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 978 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 979 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 980 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 981 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 982 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 983 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 984 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 985 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 986 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 987 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 988 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 989 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 990 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 991 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 992 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 993 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 994 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 995 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 996 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 997 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 998 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 999 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1002 }; 1003 1004 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1005 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1006 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1007 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1008 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1009 }; 1010 1011 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1012 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1013 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1014 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1015 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1016 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1017 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1018 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1019 }; 1020 1021 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1022 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1023 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1024 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1026 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1034 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1036 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1064 }; 1065 1066 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1067 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1072 }; 1073 1074 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1075 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1097 }; 1098 1099 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1100 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1101 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1102 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1103 }; 1104 1105 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1106 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1107 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1108 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1109 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1110 }; 1111 1112 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1154 }; 1155 1156 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1157 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1161 }; 1162 1163 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1164 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1188 1189 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1190 1191 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1192 1193 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1201 1202 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1211 }; 1212 1213 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1214 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1215 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1216 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1217 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1218 }; 1219 1220 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1221 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1222 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1223 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1224 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1225 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1226 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1227 }; 1228 1229 struct qmp_phy; 1230 1231 /* struct qmp_phy_cfg - per-PHY initialization config */ 1232 struct qmp_phy_cfg { 1233 /* phy-type - PCIE/UFS/USB */ 1234 unsigned int type; 1235 /* number of lanes provided by phy */ 1236 int nlanes; 1237 1238 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1239 const struct qmp_phy_init_tbl *serdes_tbl; 1240 int serdes_tbl_num; 1241 const struct qmp_phy_init_tbl *serdes_tbl_sec; 1242 int serdes_tbl_num_sec; 1243 const struct qmp_phy_init_tbl *tx_tbl; 1244 int tx_tbl_num; 1245 const struct qmp_phy_init_tbl *tx_tbl_sec; 1246 int tx_tbl_num_sec; 1247 const struct qmp_phy_init_tbl *rx_tbl; 1248 int rx_tbl_num; 1249 const struct qmp_phy_init_tbl *rx_tbl_sec; 1250 int rx_tbl_num_sec; 1251 const struct qmp_phy_init_tbl *pcs_tbl; 1252 int pcs_tbl_num; 1253 const struct qmp_phy_init_tbl *pcs_tbl_sec; 1254 int pcs_tbl_num_sec; 1255 const struct qmp_phy_init_tbl *pcs_misc_tbl; 1256 int pcs_misc_tbl_num; 1257 const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 1258 int pcs_misc_tbl_num_sec; 1259 1260 /* clock ids to be requested */ 1261 const char * const *clk_list; 1262 int num_clks; 1263 /* resets to be requested */ 1264 const char * const *reset_list; 1265 int num_resets; 1266 /* regulators to be requested */ 1267 const char * const *vreg_list; 1268 int num_vregs; 1269 1270 /* array of registers with different offsets */ 1271 const unsigned int *regs; 1272 1273 unsigned int start_ctrl; 1274 unsigned int pwrdn_ctrl; 1275 unsigned int mask_com_pcs_ready; 1276 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1277 unsigned int phy_status; 1278 1279 /* true, if PHY needs delay after POWER_DOWN */ 1280 bool has_pwrdn_delay; 1281 /* power_down delay in usec */ 1282 int pwrdn_delay_min; 1283 int pwrdn_delay_max; 1284 1285 /* true, if PHY has secondary tx/rx lanes to be configured */ 1286 bool is_dual_lane_phy; 1287 }; 1288 1289 /** 1290 * struct qmp_phy - per-lane phy descriptor 1291 * 1292 * @phy: generic phy 1293 * @cfg: phy specific configuration 1294 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1295 * @tx: iomapped memory space for lane's tx 1296 * @rx: iomapped memory space for lane's rx 1297 * @pcs: iomapped memory space for lane's pcs 1298 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1299 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1300 * @pcs_misc: iomapped memory space for lane's pcs_misc 1301 * @pipe_clk: pipe clock 1302 * @index: lane index 1303 * @qmp: QMP phy to which this lane belongs 1304 * @mode: current PHY mode 1305 */ 1306 struct qmp_phy { 1307 struct phy *phy; 1308 const struct qmp_phy_cfg *cfg; 1309 void __iomem *serdes; 1310 void __iomem *tx; 1311 void __iomem *rx; 1312 void __iomem *pcs; 1313 void __iomem *tx2; 1314 void __iomem *rx2; 1315 void __iomem *pcs_misc; 1316 struct clk *pipe_clk; 1317 unsigned int index; 1318 struct qcom_qmp *qmp; 1319 enum phy_mode mode; 1320 }; 1321 1322 /** 1323 * struct qcom_qmp - structure holding QMP phy block attributes 1324 * 1325 * @dev: device 1326 * 1327 * @clks: array of clocks required by phy 1328 * @resets: array of resets required by phy 1329 * @vregs: regulator supplies bulk data 1330 * 1331 * @phys: array of per-lane phy descriptors 1332 */ 1333 struct qcom_qmp { 1334 struct device *dev; 1335 1336 struct clk_bulk_data *clks; 1337 struct reset_control_bulk_data *resets; 1338 struct regulator_bulk_data *vregs; 1339 1340 struct qmp_phy **phys; 1341 }; 1342 1343 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1344 { 1345 u32 reg; 1346 1347 reg = readl(base + offset); 1348 reg |= val; 1349 writel(reg, base + offset); 1350 1351 /* ensure that above write is through */ 1352 readl(base + offset); 1353 } 1354 1355 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1356 { 1357 u32 reg; 1358 1359 reg = readl(base + offset); 1360 reg &= ~val; 1361 writel(reg, base + offset); 1362 1363 /* ensure that above write is through */ 1364 readl(base + offset); 1365 } 1366 1367 /* list of clocks required by phy */ 1368 static const char * const msm8996_phy_clk_l[] = { 1369 "aux", "cfg_ahb", "ref", 1370 }; 1371 1372 1373 static const char * const sdm845_pciephy_clk_l[] = { 1374 "aux", "cfg_ahb", "ref", "refgen", 1375 }; 1376 1377 /* list of regulators */ 1378 static const char * const qmp_phy_vreg_l[] = { 1379 "vdda-phy", "vdda-pll", 1380 }; 1381 1382 static const char * const ipq8074_pciephy_clk_l[] = { 1383 "aux", "cfg_ahb", 1384 }; 1385 1386 /* list of resets */ 1387 static const char * const ipq8074_pciephy_reset_l[] = { 1388 "phy", "common", 1389 }; 1390 1391 static const char * const sdm845_pciephy_reset_l[] = { 1392 "phy", 1393 }; 1394 1395 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1396 .type = PHY_TYPE_PCIE, 1397 .nlanes = 1, 1398 1399 .serdes_tbl = ipq8074_pcie_serdes_tbl, 1400 .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1401 .tx_tbl = ipq8074_pcie_tx_tbl, 1402 .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1403 .rx_tbl = ipq8074_pcie_rx_tbl, 1404 .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1405 .pcs_tbl = ipq8074_pcie_pcs_tbl, 1406 .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1407 .clk_list = ipq8074_pciephy_clk_l, 1408 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1409 .reset_list = ipq8074_pciephy_reset_l, 1410 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1411 .vreg_list = NULL, 1412 .num_vregs = 0, 1413 .regs = pciephy_regs_layout, 1414 1415 .start_ctrl = SERDES_START | PCS_START, 1416 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1417 .phy_status = PHYSTATUS, 1418 1419 .has_pwrdn_delay = true, 1420 .pwrdn_delay_min = 995, /* us */ 1421 .pwrdn_delay_max = 1005, /* us */ 1422 }; 1423 1424 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1425 .type = PHY_TYPE_PCIE, 1426 .nlanes = 1, 1427 1428 .serdes_tbl = ipq6018_pcie_serdes_tbl, 1429 .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1430 .tx_tbl = ipq6018_pcie_tx_tbl, 1431 .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1432 .rx_tbl = ipq6018_pcie_rx_tbl, 1433 .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1434 .pcs_tbl = ipq6018_pcie_pcs_tbl, 1435 .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1436 .clk_list = ipq8074_pciephy_clk_l, 1437 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1438 .reset_list = ipq8074_pciephy_reset_l, 1439 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1440 .vreg_list = NULL, 1441 .num_vregs = 0, 1442 .regs = ipq_pciephy_gen3_regs_layout, 1443 1444 .start_ctrl = SERDES_START | PCS_START, 1445 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1446 1447 .has_pwrdn_delay = true, 1448 .pwrdn_delay_min = 995, /* us */ 1449 .pwrdn_delay_max = 1005, /* us */ 1450 }; 1451 1452 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1453 .type = PHY_TYPE_PCIE, 1454 .nlanes = 1, 1455 1456 .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, 1457 .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1458 .tx_tbl = sdm845_qmp_pcie_tx_tbl, 1459 .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1460 .rx_tbl = sdm845_qmp_pcie_rx_tbl, 1461 .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1462 .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, 1463 .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1464 .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, 1465 .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1466 .clk_list = sdm845_pciephy_clk_l, 1467 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1468 .reset_list = sdm845_pciephy_reset_l, 1469 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1470 .vreg_list = qmp_phy_vreg_l, 1471 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1472 .regs = sdm845_qmp_pciephy_regs_layout, 1473 1474 .start_ctrl = PCS_START | SERDES_START, 1475 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1476 .phy_status = PHYSTATUS, 1477 1478 .has_pwrdn_delay = true, 1479 .pwrdn_delay_min = 995, /* us */ 1480 .pwrdn_delay_max = 1005, /* us */ 1481 }; 1482 1483 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1484 .type = PHY_TYPE_PCIE, 1485 .nlanes = 1, 1486 1487 .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, 1488 .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1489 .tx_tbl = sdm845_qhp_pcie_tx_tbl, 1490 .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1491 .rx_tbl = sdm845_qhp_pcie_rx_tbl, 1492 .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1493 .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, 1494 .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1495 .clk_list = sdm845_pciephy_clk_l, 1496 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1497 .reset_list = sdm845_pciephy_reset_l, 1498 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1499 .vreg_list = qmp_phy_vreg_l, 1500 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1501 .regs = sdm845_qhp_pciephy_regs_layout, 1502 1503 .start_ctrl = PCS_START | SERDES_START, 1504 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1505 .phy_status = PHYSTATUS, 1506 1507 .has_pwrdn_delay = true, 1508 .pwrdn_delay_min = 995, /* us */ 1509 .pwrdn_delay_max = 1005, /* us */ 1510 }; 1511 1512 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1513 .type = PHY_TYPE_PCIE, 1514 .nlanes = 1, 1515 1516 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 1517 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1518 .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1519 .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1520 .tx_tbl = sm8250_qmp_pcie_tx_tbl, 1521 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1522 .rx_tbl = sm8250_qmp_pcie_rx_tbl, 1523 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1524 .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl, 1525 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1526 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 1527 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1528 .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1529 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1530 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 1531 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1532 .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1533 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1534 .clk_list = sdm845_pciephy_clk_l, 1535 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1536 .reset_list = sdm845_pciephy_reset_l, 1537 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1538 .vreg_list = qmp_phy_vreg_l, 1539 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1540 .regs = sm8250_pcie_regs_layout, 1541 1542 .start_ctrl = PCS_START | SERDES_START, 1543 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1544 .phy_status = PHYSTATUS, 1545 1546 .has_pwrdn_delay = true, 1547 .pwrdn_delay_min = 995, /* us */ 1548 .pwrdn_delay_max = 1005, /* us */ 1549 }; 1550 1551 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1552 .type = PHY_TYPE_PCIE, 1553 .nlanes = 2, 1554 1555 .serdes_tbl = sm8250_qmp_pcie_serdes_tbl, 1556 .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1557 .tx_tbl = sm8250_qmp_pcie_tx_tbl, 1558 .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1559 .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl, 1560 .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1561 .rx_tbl = sm8250_qmp_pcie_rx_tbl, 1562 .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1563 .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl, 1564 .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1565 .pcs_tbl = sm8250_qmp_pcie_pcs_tbl, 1566 .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1567 .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1568 .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1569 .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl, 1570 .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1571 .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1572 .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1573 .clk_list = sdm845_pciephy_clk_l, 1574 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1575 .reset_list = sdm845_pciephy_reset_l, 1576 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1577 .vreg_list = qmp_phy_vreg_l, 1578 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1579 .regs = sm8250_pcie_regs_layout, 1580 1581 .start_ctrl = PCS_START | SERDES_START, 1582 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1583 .phy_status = PHYSTATUS, 1584 1585 .is_dual_lane_phy = true, 1586 .has_pwrdn_delay = true, 1587 .pwrdn_delay_min = 995, /* us */ 1588 .pwrdn_delay_max = 1005, /* us */ 1589 }; 1590 1591 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1592 .type = PHY_TYPE_PCIE, 1593 .nlanes = 1, 1594 1595 .serdes_tbl = msm8998_pcie_serdes_tbl, 1596 .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1597 .tx_tbl = msm8998_pcie_tx_tbl, 1598 .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1599 .rx_tbl = msm8998_pcie_rx_tbl, 1600 .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1601 .pcs_tbl = msm8998_pcie_pcs_tbl, 1602 .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1603 .clk_list = msm8996_phy_clk_l, 1604 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1605 .reset_list = ipq8074_pciephy_reset_l, 1606 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1607 .vreg_list = qmp_phy_vreg_l, 1608 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1609 .regs = pciephy_regs_layout, 1610 1611 .start_ctrl = SERDES_START | PCS_START, 1612 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1613 .phy_status = PHYSTATUS, 1614 }; 1615 1616 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1617 .type = PHY_TYPE_PCIE, 1618 .nlanes = 1, 1619 1620 .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl, 1621 .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1622 .tx_tbl = sc8180x_qmp_pcie_tx_tbl, 1623 .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1624 .rx_tbl = sc8180x_qmp_pcie_rx_tbl, 1625 .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1626 .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl, 1627 .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1628 .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl, 1629 .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1630 .clk_list = sdm845_pciephy_clk_l, 1631 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1632 .reset_list = sdm845_pciephy_reset_l, 1633 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1634 .vreg_list = qmp_phy_vreg_l, 1635 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1636 .regs = sm8250_pcie_regs_layout, 1637 1638 .start_ctrl = PCS_START | SERDES_START, 1639 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1640 1641 .has_pwrdn_delay = true, 1642 .pwrdn_delay_min = 995, /* us */ 1643 .pwrdn_delay_max = 1005, /* us */ 1644 }; 1645 1646 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1647 .type = PHY_TYPE_PCIE, 1648 .nlanes = 2, 1649 1650 .serdes_tbl = sdx55_qmp_pcie_serdes_tbl, 1651 .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1652 .tx_tbl = sdx55_qmp_pcie_tx_tbl, 1653 .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1654 .rx_tbl = sdx55_qmp_pcie_rx_tbl, 1655 .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1656 .pcs_tbl = sdx55_qmp_pcie_pcs_tbl, 1657 .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1658 .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl, 1659 .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1660 .clk_list = sdm845_pciephy_clk_l, 1661 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1662 .reset_list = sdm845_pciephy_reset_l, 1663 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1664 .vreg_list = qmp_phy_vreg_l, 1665 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1666 .regs = sm8250_pcie_regs_layout, 1667 1668 .start_ctrl = PCS_START | SERDES_START, 1669 .pwrdn_ctrl = SW_PWRDN, 1670 .phy_status = PHYSTATUS_4_20, 1671 1672 .is_dual_lane_phy = true, 1673 .has_pwrdn_delay = true, 1674 .pwrdn_delay_min = 995, /* us */ 1675 .pwrdn_delay_max = 1005, /* us */ 1676 }; 1677 1678 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1679 .type = PHY_TYPE_PCIE, 1680 .nlanes = 1, 1681 1682 .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1683 .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1684 .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl, 1685 .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1686 .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl, 1687 .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1688 .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1689 .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1690 .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1691 .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1692 .clk_list = sdm845_pciephy_clk_l, 1693 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1694 .reset_list = sdm845_pciephy_reset_l, 1695 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1696 .vreg_list = qmp_phy_vreg_l, 1697 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1698 .regs = sm8250_pcie_regs_layout, 1699 1700 .start_ctrl = SERDES_START | PCS_START, 1701 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1702 .phy_status = PHYSTATUS, 1703 1704 .has_pwrdn_delay = true, 1705 .pwrdn_delay_min = 995, /* us */ 1706 .pwrdn_delay_max = 1005, /* us */ 1707 }; 1708 1709 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1710 .type = PHY_TYPE_PCIE, 1711 .nlanes = 2, 1712 1713 .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1714 .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1715 .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl, 1716 .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1717 .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl, 1718 .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1719 .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1720 .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1721 .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1722 .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1723 .clk_list = sdm845_pciephy_clk_l, 1724 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1725 .reset_list = sdm845_pciephy_reset_l, 1726 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1727 .vreg_list = qmp_phy_vreg_l, 1728 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1729 .regs = sm8250_pcie_regs_layout, 1730 1731 .start_ctrl = SERDES_START | PCS_START, 1732 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1733 .phy_status = PHYSTATUS_4_20, 1734 1735 .is_dual_lane_phy = true, 1736 .has_pwrdn_delay = true, 1737 .pwrdn_delay_min = 995, /* us */ 1738 .pwrdn_delay_max = 1005, /* us */ 1739 }; 1740 1741 static void qcom_qmp_phy_pcie_configure_lane(void __iomem *base, 1742 const unsigned int *regs, 1743 const struct qmp_phy_init_tbl tbl[], 1744 int num, 1745 u8 lane_mask) 1746 { 1747 int i; 1748 const struct qmp_phy_init_tbl *t = tbl; 1749 1750 if (!t) 1751 return; 1752 1753 for (i = 0; i < num; i++, t++) { 1754 if (!(t->lane_mask & lane_mask)) 1755 continue; 1756 1757 if (t->in_layout) 1758 writel(t->val, base + regs[t->offset]); 1759 else 1760 writel(t->val, base + t->offset); 1761 } 1762 } 1763 1764 static void qcom_qmp_phy_pcie_configure(void __iomem *base, 1765 const unsigned int *regs, 1766 const struct qmp_phy_init_tbl tbl[], 1767 int num) 1768 { 1769 qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff); 1770 } 1771 1772 static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy) 1773 { 1774 const struct qmp_phy_cfg *cfg = qphy->cfg; 1775 void __iomem *serdes = qphy->serdes; 1776 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1777 int serdes_tbl_num = cfg->serdes_tbl_num; 1778 1779 qcom_qmp_phy_pcie_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1780 if (cfg->serdes_tbl_sec) 1781 qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 1782 cfg->serdes_tbl_num_sec); 1783 1784 return 0; 1785 } 1786 1787 static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy) 1788 { 1789 struct qcom_qmp *qmp = qphy->qmp; 1790 const struct qmp_phy_cfg *cfg = qphy->cfg; 1791 void __iomem *pcs = qphy->pcs; 1792 int ret; 1793 1794 /* turn on regulator supplies */ 1795 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1796 if (ret) { 1797 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1798 return ret; 1799 } 1800 1801 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1802 if (ret) { 1803 dev_err(qmp->dev, "reset assert failed\n"); 1804 goto err_disable_regulators; 1805 } 1806 1807 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1808 if (ret) { 1809 dev_err(qmp->dev, "reset deassert failed\n"); 1810 goto err_disable_regulators; 1811 } 1812 1813 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1814 if (ret) 1815 goto err_assert_reset; 1816 1817 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1818 qphy_setbits(pcs, 1819 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1820 cfg->pwrdn_ctrl); 1821 else 1822 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1823 cfg->pwrdn_ctrl); 1824 1825 return 0; 1826 1827 err_assert_reset: 1828 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1829 err_disable_regulators: 1830 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1831 1832 return ret; 1833 } 1834 1835 static int qcom_qmp_phy_pcie_com_exit(struct qmp_phy *qphy) 1836 { 1837 struct qcom_qmp *qmp = qphy->qmp; 1838 const struct qmp_phy_cfg *cfg = qphy->cfg; 1839 1840 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1841 1842 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1843 1844 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1845 1846 return 0; 1847 } 1848 1849 static int qcom_qmp_phy_pcie_init(struct phy *phy) 1850 { 1851 struct qmp_phy *qphy = phy_get_drvdata(phy); 1852 struct qcom_qmp *qmp = qphy->qmp; 1853 int ret; 1854 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1855 1856 ret = qcom_qmp_phy_pcie_com_init(qphy); 1857 if (ret) 1858 return ret; 1859 1860 return 0; 1861 } 1862 1863 static int qcom_qmp_phy_pcie_power_on(struct phy *phy) 1864 { 1865 struct qmp_phy *qphy = phy_get_drvdata(phy); 1866 struct qcom_qmp *qmp = qphy->qmp; 1867 const struct qmp_phy_cfg *cfg = qphy->cfg; 1868 void __iomem *tx = qphy->tx; 1869 void __iomem *rx = qphy->rx; 1870 void __iomem *pcs = qphy->pcs; 1871 void __iomem *pcs_misc = qphy->pcs_misc; 1872 void __iomem *status; 1873 unsigned int mask, val, ready; 1874 int ret; 1875 1876 qcom_qmp_phy_pcie_serdes_init(qphy); 1877 1878 ret = clk_prepare_enable(qphy->pipe_clk); 1879 if (ret) { 1880 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1881 return ret; 1882 } 1883 1884 /* Tx, Rx, and PCS configurations */ 1885 qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, 1886 cfg->tx_tbl, cfg->tx_tbl_num, 1); 1887 if (cfg->tx_tbl_sec) 1888 qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 1889 cfg->tx_tbl_num_sec, 1); 1890 1891 /* Configuration for other LANE for USB-DP combo PHY */ 1892 if (cfg->is_dual_lane_phy) { 1893 qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, 1894 cfg->tx_tbl, cfg->tx_tbl_num, 2); 1895 if (cfg->tx_tbl_sec) 1896 qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs, 1897 cfg->tx_tbl_sec, 1898 cfg->tx_tbl_num_sec, 2); 1899 } 1900 1901 qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, 1902 cfg->rx_tbl, cfg->rx_tbl_num, 1); 1903 if (cfg->rx_tbl_sec) 1904 qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs, 1905 cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 1906 1907 if (cfg->is_dual_lane_phy) { 1908 qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, 1909 cfg->rx_tbl, cfg->rx_tbl_num, 2); 1910 if (cfg->rx_tbl_sec) 1911 qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs, 1912 cfg->rx_tbl_sec, 1913 cfg->rx_tbl_num_sec, 2); 1914 } 1915 1916 qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1917 if (cfg->pcs_tbl_sec) 1918 qcom_qmp_phy_pcie_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 1919 cfg->pcs_tbl_num_sec); 1920 1921 qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 1922 cfg->pcs_misc_tbl_num); 1923 if (cfg->pcs_misc_tbl_sec) 1924 qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 1925 cfg->pcs_misc_tbl_num_sec); 1926 1927 /* 1928 * Pull out PHY from POWER DOWN state. 1929 * This is active low enable signal to power-down PHY. 1930 */ 1931 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 1932 1933 if (cfg->has_pwrdn_delay) 1934 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1935 1936 /* Pull PHY out of reset state */ 1937 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1938 1939 /* start SerDes and Phy-Coding-Sublayer */ 1940 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1941 1942 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1943 mask = cfg->phy_status; 1944 ready = 0; 1945 1946 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 1947 PHY_INIT_COMPLETE_TIMEOUT); 1948 if (ret) { 1949 dev_err(qmp->dev, "phy initialization timed-out\n"); 1950 goto err_disable_pipe_clk; 1951 } 1952 1953 return 0; 1954 1955 err_disable_pipe_clk: 1956 clk_disable_unprepare(qphy->pipe_clk); 1957 1958 return ret; 1959 } 1960 1961 static int qcom_qmp_phy_pcie_power_off(struct phy *phy) 1962 { 1963 struct qmp_phy *qphy = phy_get_drvdata(phy); 1964 const struct qmp_phy_cfg *cfg = qphy->cfg; 1965 1966 clk_disable_unprepare(qphy->pipe_clk); 1967 1968 /* PHY reset */ 1969 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1970 1971 /* stop SerDes and Phy-Coding-Sublayer */ 1972 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1973 1974 /* Put PHY into POWER DOWN state: active low */ 1975 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 1976 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1977 cfg->pwrdn_ctrl); 1978 } else { 1979 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 1980 cfg->pwrdn_ctrl); 1981 } 1982 1983 return 0; 1984 } 1985 1986 static int qcom_qmp_phy_pcie_exit(struct phy *phy) 1987 { 1988 struct qmp_phy *qphy = phy_get_drvdata(phy); 1989 1990 qcom_qmp_phy_pcie_com_exit(qphy); 1991 1992 return 0; 1993 } 1994 1995 static int qcom_qmp_phy_pcie_enable(struct phy *phy) 1996 { 1997 int ret; 1998 1999 ret = qcom_qmp_phy_pcie_init(phy); 2000 if (ret) 2001 return ret; 2002 2003 ret = qcom_qmp_phy_pcie_power_on(phy); 2004 if (ret) 2005 qcom_qmp_phy_pcie_exit(phy); 2006 2007 return ret; 2008 } 2009 2010 static int qcom_qmp_phy_pcie_disable(struct phy *phy) 2011 { 2012 int ret; 2013 2014 ret = qcom_qmp_phy_pcie_power_off(phy); 2015 if (ret) 2016 return ret; 2017 return qcom_qmp_phy_pcie_exit(phy); 2018 } 2019 2020 static int qcom_qmp_phy_pcie_set_mode(struct phy *phy, 2021 enum phy_mode mode, int submode) 2022 { 2023 struct qmp_phy *qphy = phy_get_drvdata(phy); 2024 2025 qphy->mode = mode; 2026 2027 return 0; 2028 } 2029 2030 static int qcom_qmp_phy_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2031 { 2032 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2033 int num = cfg->num_vregs; 2034 int i; 2035 2036 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2037 if (!qmp->vregs) 2038 return -ENOMEM; 2039 2040 for (i = 0; i < num; i++) 2041 qmp->vregs[i].supply = cfg->vreg_list[i]; 2042 2043 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2044 } 2045 2046 static int qcom_qmp_phy_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2047 { 2048 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2049 int i; 2050 int ret; 2051 2052 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2053 sizeof(*qmp->resets), GFP_KERNEL); 2054 if (!qmp->resets) 2055 return -ENOMEM; 2056 2057 for (i = 0; i < cfg->num_resets; i++) 2058 qmp->resets[i].id = cfg->reset_list[i]; 2059 2060 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2061 if (ret) 2062 return dev_err_probe(dev, ret, "failed to get resets\n"); 2063 2064 return 0; 2065 } 2066 2067 static int qcom_qmp_phy_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2068 { 2069 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2070 int num = cfg->num_clks; 2071 int i; 2072 2073 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2074 if (!qmp->clks) 2075 return -ENOMEM; 2076 2077 for (i = 0; i < num; i++) 2078 qmp->clks[i].id = cfg->clk_list[i]; 2079 2080 return devm_clk_bulk_get(dev, num, qmp->clks); 2081 } 2082 2083 static void phy_clk_release_provider(void *res) 2084 { 2085 of_clk_del_provider(res); 2086 } 2087 2088 /* 2089 * Register a fixed rate pipe clock. 2090 * 2091 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2092 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2093 * by the PHY driver for its operations. 2094 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2095 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2096 * Below picture shows this relationship. 2097 * 2098 * +---------------+ 2099 * | PHY block |<<---------------------------------------+ 2100 * | | | 2101 * | +-------+ | +-----+ | 2102 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2103 * clk | +-------+ | +-----+ 2104 * +---------------+ 2105 */ 2106 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2107 { 2108 struct clk_fixed_rate *fixed; 2109 struct clk_init_data init = { }; 2110 int ret; 2111 2112 ret = of_property_read_string(np, "clock-output-names", &init.name); 2113 if (ret) { 2114 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2115 return ret; 2116 } 2117 2118 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2119 if (!fixed) 2120 return -ENOMEM; 2121 2122 init.ops = &clk_fixed_rate_ops; 2123 2124 /* controllers using QMP phys use 125MHz pipe clock interface */ 2125 fixed->fixed_rate = 125000000; 2126 fixed->hw.init = &init; 2127 2128 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2129 if (ret) 2130 return ret; 2131 2132 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2133 if (ret) 2134 return ret; 2135 2136 /* 2137 * Roll a devm action because the clock provider is the child node, but 2138 * the child node is not actually a device. 2139 */ 2140 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2141 } 2142 2143 static const struct phy_ops qcom_qmp_phy_pcie_ops = { 2144 .power_on = qcom_qmp_phy_pcie_enable, 2145 .power_off = qcom_qmp_phy_pcie_disable, 2146 .set_mode = qcom_qmp_phy_pcie_set_mode, 2147 .owner = THIS_MODULE, 2148 }; 2149 2150 static 2151 int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id, 2152 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2153 { 2154 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2155 struct phy *generic_phy; 2156 struct qmp_phy *qphy; 2157 char prop_name[MAX_PROP_NAME]; 2158 int ret; 2159 2160 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2161 if (!qphy) 2162 return -ENOMEM; 2163 2164 qphy->cfg = cfg; 2165 qphy->serdes = serdes; 2166 /* 2167 * Get memory resources for each phy lane: 2168 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2169 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2170 * For single lane PHYs: pcs_misc (optional) -> 3. 2171 */ 2172 qphy->tx = of_iomap(np, 0); 2173 if (!qphy->tx) 2174 return -ENOMEM; 2175 2176 qphy->rx = of_iomap(np, 1); 2177 if (!qphy->rx) 2178 return -ENOMEM; 2179 2180 qphy->pcs = of_iomap(np, 2); 2181 if (!qphy->pcs) 2182 return -ENOMEM; 2183 2184 /* 2185 * If this is a dual-lane PHY, then there should be registers for the 2186 * second lane. Some old device trees did not specify this, so fall 2187 * back to old legacy behavior of assuming they can be reached at an 2188 * offset from the first lane. 2189 */ 2190 if (cfg->is_dual_lane_phy) { 2191 qphy->tx2 = of_iomap(np, 3); 2192 qphy->rx2 = of_iomap(np, 4); 2193 if (!qphy->tx2 || !qphy->rx2) { 2194 dev_warn(dev, 2195 "Underspecified device tree, falling back to legacy register regions\n"); 2196 2197 /* In the old version, pcs_misc is at index 3. */ 2198 qphy->pcs_misc = qphy->tx2; 2199 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; 2200 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; 2201 2202 } else { 2203 qphy->pcs_misc = of_iomap(np, 5); 2204 } 2205 2206 } else { 2207 qphy->pcs_misc = of_iomap(np, 3); 2208 } 2209 2210 if (!qphy->pcs_misc) 2211 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2212 2213 /* 2214 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 2215 * based phys, so they essentially have pipe clock. So, 2216 * we return error in case phy is USB3 or PIPE type. 2217 * Otherwise, we initialize pipe clock to NULL for 2218 * all phys that don't need this. 2219 */ 2220 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 2221 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 2222 if (IS_ERR(qphy->pipe_clk)) { 2223 if (cfg->type == PHY_TYPE_PCIE || 2224 cfg->type == PHY_TYPE_USB3) { 2225 ret = PTR_ERR(qphy->pipe_clk); 2226 if (ret != -EPROBE_DEFER) 2227 dev_err(dev, 2228 "failed to get lane%d pipe_clk, %d\n", 2229 id, ret); 2230 return ret; 2231 } 2232 qphy->pipe_clk = NULL; 2233 } 2234 2235 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_ops); 2236 if (IS_ERR(generic_phy)) { 2237 ret = PTR_ERR(generic_phy); 2238 dev_err(dev, "failed to create qphy %d\n", ret); 2239 return ret; 2240 } 2241 2242 qphy->phy = generic_phy; 2243 qphy->index = id; 2244 qphy->qmp = qmp; 2245 qmp->phys[id] = qphy; 2246 phy_set_drvdata(generic_phy, qphy); 2247 2248 return 0; 2249 } 2250 2251 static const struct of_device_id qcom_qmp_phy_pcie_of_match_table[] = { 2252 { 2253 .compatible = "qcom,msm8998-qmp-pcie-phy", 2254 .data = &msm8998_pciephy_cfg, 2255 }, { 2256 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2257 .data = &ipq8074_pciephy_cfg, 2258 }, { 2259 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2260 .data = &ipq6018_pciephy_cfg, 2261 }, { 2262 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2263 .data = &sc8180x_pciephy_cfg, 2264 }, { 2265 .compatible = "qcom,sdm845-qhp-pcie-phy", 2266 .data = &sdm845_qhp_pciephy_cfg, 2267 }, { 2268 .compatible = "qcom,sdm845-qmp-pcie-phy", 2269 .data = &sdm845_qmp_pciephy_cfg, 2270 }, { 2271 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2272 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2273 }, { 2274 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2275 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2276 }, { 2277 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2278 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2279 }, { 2280 .compatible = "qcom,sdx55-qmp-pcie-phy", 2281 .data = &sdx55_qmp_pciephy_cfg, 2282 }, { 2283 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2284 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2285 }, { 2286 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2287 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2288 }, 2289 { }, 2290 }; 2291 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_of_match_table); 2292 2293 static int qcom_qmp_phy_pcie_probe(struct platform_device *pdev) 2294 { 2295 struct qcom_qmp *qmp; 2296 struct device *dev = &pdev->dev; 2297 struct device_node *child; 2298 struct phy_provider *phy_provider; 2299 void __iomem *serdes; 2300 const struct qmp_phy_cfg *cfg = NULL; 2301 int num, id; 2302 int ret; 2303 2304 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2305 if (!qmp) 2306 return -ENOMEM; 2307 2308 qmp->dev = dev; 2309 dev_set_drvdata(dev, qmp); 2310 2311 /* Get the specific init parameters of QMP phy */ 2312 cfg = of_device_get_match_data(dev); 2313 if (!cfg) 2314 return -EINVAL; 2315 2316 /* per PHY serdes; usually located at base address */ 2317 serdes = devm_platform_ioremap_resource(pdev, 0); 2318 if (IS_ERR(serdes)) 2319 return PTR_ERR(serdes); 2320 2321 ret = qcom_qmp_phy_pcie_clk_init(dev, cfg); 2322 if (ret) 2323 return ret; 2324 2325 ret = qcom_qmp_phy_pcie_reset_init(dev, cfg); 2326 if (ret) 2327 return ret; 2328 2329 ret = qcom_qmp_phy_pcie_vreg_init(dev, cfg); 2330 if (ret) { 2331 if (ret != -EPROBE_DEFER) 2332 dev_err(dev, "failed to get regulator supplies: %d\n", 2333 ret); 2334 return ret; 2335 } 2336 2337 num = of_get_available_child_count(dev->of_node); 2338 /* do we have a rogue child node ? */ 2339 if (num > 1) 2340 return -EINVAL; 2341 2342 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2343 if (!qmp->phys) 2344 return -ENOMEM; 2345 2346 pm_runtime_set_active(dev); 2347 pm_runtime_enable(dev); 2348 /* 2349 * Prevent runtime pm from being ON by default. Users can enable 2350 * it using power/control in sysfs. 2351 */ 2352 pm_runtime_forbid(dev); 2353 2354 id = 0; 2355 for_each_available_child_of_node(dev->of_node, child) { 2356 /* Create per-lane phy */ 2357 ret = qcom_qmp_phy_pcie_create(dev, child, id, serdes, cfg); 2358 if (ret) { 2359 dev_err(dev, "failed to create lane%d phy, %d\n", 2360 id, ret); 2361 goto err_node_put; 2362 } 2363 2364 /* 2365 * Register the pipe clock provided by phy. 2366 * See function description to see details of this pipe clock. 2367 */ 2368 ret = phy_pipe_clk_register(qmp, child); 2369 if (ret) { 2370 dev_err(qmp->dev, 2371 "failed to register pipe clock source\n"); 2372 goto err_node_put; 2373 } 2374 2375 id++; 2376 } 2377 2378 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2379 if (!IS_ERR(phy_provider)) 2380 dev_info(dev, "Registered Qcom-QMP phy\n"); 2381 else 2382 pm_runtime_disable(dev); 2383 2384 return PTR_ERR_OR_ZERO(phy_provider); 2385 2386 err_node_put: 2387 pm_runtime_disable(dev); 2388 of_node_put(child); 2389 return ret; 2390 } 2391 2392 static struct platform_driver qcom_qmp_phy_pcie_driver = { 2393 .probe = qcom_qmp_phy_pcie_probe, 2394 .driver = { 2395 .name = "qcom-qmp-pcie-phy", 2396 .of_match_table = qcom_qmp_phy_pcie_of_match_table, 2397 }, 2398 }; 2399 2400 module_platform_driver(qcom_qmp_phy_pcie_driver); 2401 2402 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2403 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2404 MODULE_LICENSE("GPL v2"); 2405