1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include <dt-bindings/phy/phy-qcom-qmp.h> 26 27 #include "phy-qcom-qmp-common.h" 28 29 #include "phy-qcom-qmp.h" 30 #include "phy-qcom-qmp-pcs-misc-v3.h" 31 #include "phy-qcom-qmp-pcs-pcie-v4.h" 32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 33 #include "phy-qcom-qmp-pcs-pcie-v5.h" 34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 35 #include "phy-qcom-qmp-pcs-pcie-v6.h" 36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h" 37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h" 38 #include "phy-qcom-qmp-pcs-v6_30.h" 39 #include "phy-qcom-qmp-pcie-qhp.h" 40 41 #define PHY_INIT_COMPLETE_TIMEOUT 10000 42 43 /* set of registers with offsets different per-PHY */ 44 enum qphy_reg_layout { 45 /* PCS registers */ 46 QPHY_SW_RESET, 47 QPHY_START_CTRL, 48 QPHY_PCS_STATUS, 49 QPHY_PCS_POWER_DOWN_CONTROL, 50 /* Keep last to ensure regs_layout arrays are properly initialized */ 51 QPHY_LAYOUT_SIZE 52 }; 53 54 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 55 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 56 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 57 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 59 }; 60 61 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 65 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 66 }; 67 68 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 69 [QPHY_SW_RESET] = 0x00, 70 [QPHY_START_CTRL] = 0x08, 71 [QPHY_PCS_STATUS] = 0x2ac, 72 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 73 }; 74 75 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 76 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 77 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 78 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 79 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 80 }; 81 82 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 83 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 84 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 85 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 86 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 87 }; 88 89 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 90 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 91 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 92 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 93 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 94 }; 95 96 static const unsigned int pciephy_v7_regs_layout[QPHY_LAYOUT_SIZE] = { 97 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET, 98 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL, 99 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1, 100 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL, 101 }; 102 103 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 146 }; 147 148 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 149 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 150 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 151 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 152 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 153 }; 154 155 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 161 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 163 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 164 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 165 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 170 }; 171 172 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 183 }; 184 185 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 186 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 187 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 188 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 189 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 190 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 191 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 192 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 193 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 194 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 195 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 232 }; 233 234 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 235 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 236 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 237 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 238 }; 239 240 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 271 }; 272 273 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 274 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 275 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 276 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 281 }; 282 283 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 290 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 292 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 293 }; 294 295 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 296 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 297 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 298 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 299 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 300 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 301 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 302 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 303 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 304 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 305 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 306 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 307 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 308 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 309 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 310 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 311 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 312 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 313 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 314 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 315 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 316 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 317 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 318 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 319 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 320 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 321 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 322 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 323 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 324 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 325 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 326 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 327 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 328 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 331 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 332 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 334 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 335 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 336 }; 337 338 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 339 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 340 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 341 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 342 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 343 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 344 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 345 }; 346 347 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 348 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 349 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 350 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 351 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 352 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 353 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 354 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 355 }; 356 357 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 361 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 362 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 363 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 364 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 365 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 366 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 368 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 369 }; 370 371 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 372 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 373 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 374 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 375 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 376 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 377 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 378 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 379 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 380 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 381 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 429 }; 430 431 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 433 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 434 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 435 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 436 }; 437 438 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 469 }; 470 471 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 472 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 473 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 474 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 475 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 476 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 477 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 483 }; 484 485 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 499 }; 500 501 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { 502 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 503 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 504 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 505 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 506 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 507 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 508 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 509 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 510 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 511 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 512 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 513 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 514 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 515 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 516 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 517 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 518 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 519 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 520 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 521 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 522 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 523 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 524 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 525 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 526 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 528 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 529 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 530 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 531 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 532 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 533 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 534 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 535 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 536 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 537 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 538 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 539 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 540 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 541 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 542 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 543 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 544 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 545 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 546 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 547 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 548 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 549 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 550 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 551 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 552 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 553 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 554 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 555 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 556 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 557 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 558 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 559 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 560 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 561 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 562 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 563 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 564 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 565 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 566 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 567 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 568 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 569 }; 570 571 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { 572 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 573 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 574 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 575 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 576 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 577 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 578 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 579 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 580 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 581 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 582 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 583 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 584 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 585 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 586 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 587 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 588 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 589 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 590 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 591 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 592 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 593 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 594 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 595 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 596 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 597 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 598 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 599 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 600 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 601 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 602 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 603 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 604 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 605 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 606 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 607 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 608 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 609 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 610 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 611 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 612 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 613 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 614 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 615 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 616 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 617 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 618 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 619 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 620 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 621 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 622 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 623 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 624 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 625 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 626 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 627 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 628 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 629 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 630 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 631 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 632 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 633 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 634 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 635 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 636 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 637 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 638 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 639 }; 640 641 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = { 642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73), 654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80), 655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00), 661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02), 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 672 }; 673 674 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = { 675 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 676 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 681 }; 682 683 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = { 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 696 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06), 701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 703 }; 704 705 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = { 706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 712 }; 713 714 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { 715 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 716 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 717 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 718 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 719 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 720 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), 722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), 724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), 725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), 726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), 730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 731 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), 732 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), 733 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), 734 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 735 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 736 }; 737 738 static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] = { 739 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 740 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 741 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 742 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 743 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 744 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 745 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 746 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 747 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 748 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 749 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 750 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 751 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 752 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 753 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x9), 754 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x4), 755 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 756 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 757 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 758 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 759 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 760 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xd), 761 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x04), 762 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x35), 763 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 764 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 765 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x4), 766 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 767 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x30), 768 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 769 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 770 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 771 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 772 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 773 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 774 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 775 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 776 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 777 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 778 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 779 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 780 }; 781 782 static const struct qmp_phy_init_tbl qcs615_pcie_rx_tbl[] = { 783 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 784 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 785 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 786 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 787 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 788 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 789 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 790 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4), 791 }; 792 793 static const struct qmp_phy_init_tbl qcs615_pcie_tx_tbl[] = { 794 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 795 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 796 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 797 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 798 }; 799 800 static const struct qmp_phy_init_tbl qcs615_pcie_pcs_tbl[] = { 801 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 802 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 803 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 804 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 805 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 806 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 807 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 808 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 809 QMP_PHY_INIT_CFG(QPHY_V2_PCS_SIGDET_CNTRL, 0x7), 810 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 811 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 812 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 813 }; 814 815 static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = { 816 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 817 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 818 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), 819 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 820 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2), 821 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 822 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 823 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 824 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 825 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), 826 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 827 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2), 828 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 829 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 830 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 831 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 832 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 833 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 834 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec), 835 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6), 836 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 837 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5), 838 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e), 839 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 840 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 841 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 842 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 843 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 844 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 845 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 846 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 847 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 848 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 849 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 850 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 851 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 852 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 853 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 854 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 855 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 856 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 857 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 858 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 859 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 860 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 861 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 862 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 863 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 864 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 865 }; 866 867 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 868 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 869 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 870 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 871 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 872 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 873 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 874 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 875 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 876 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 877 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 878 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 879 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 880 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 881 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 882 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 883 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 884 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 885 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 886 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 887 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 888 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 889 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 890 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 891 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 892 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 893 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 894 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 895 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 896 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 897 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 898 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 899 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 900 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 901 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 902 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 903 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 904 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 905 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 906 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 907 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 908 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 909 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 910 }; 911 912 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 913 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 914 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 915 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 916 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 917 }; 918 919 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 920 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 921 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 922 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 923 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 924 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 925 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 926 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 927 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 928 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 929 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 930 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 931 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 932 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 933 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 934 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 935 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 936 }; 937 938 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 939 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 940 941 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 942 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 943 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 944 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 945 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 946 947 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 948 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 949 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 950 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 951 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 952 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 953 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 954 955 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 956 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 957 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 958 959 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 960 }; 961 962 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 963 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 964 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 965 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 966 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 967 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 968 }; 969 970 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 971 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 972 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 973 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 974 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 975 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 976 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 977 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 978 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 979 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 980 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 981 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 982 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 983 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 984 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 985 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 986 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 987 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 988 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 989 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 990 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 991 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 992 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 993 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 994 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 995 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 996 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 997 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 998 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 999 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 1000 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 1001 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1002 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 1003 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 1004 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 1005 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 1006 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 1007 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 1008 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 1009 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 1010 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 1011 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 1012 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 1013 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 1014 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 1015 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 1016 }; 1017 1018 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 1019 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 1020 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 1021 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 1022 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 1023 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 1024 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 1025 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 1026 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 1027 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 1028 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 1029 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 1030 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 1031 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 1032 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 1033 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 1034 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 1035 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 1036 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 1037 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 1038 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 1039 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 1040 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 1041 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 1042 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 1043 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 1044 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 1045 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 1046 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 1047 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 1048 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 1049 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 1050 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 1051 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 1052 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 1053 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 1054 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 1055 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 1056 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 1057 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 1058 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 1059 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 1060 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 1061 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 1062 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 1063 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 1064 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 1065 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 1066 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 1067 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 1068 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 1069 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 1070 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 1071 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 1072 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 1073 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 1074 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 1075 }; 1076 1077 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 1078 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 1079 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 1080 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 1081 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 1082 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 1083 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 1084 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 1085 }; 1086 1087 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 1088 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1089 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1090 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1091 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1092 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1093 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1094 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1095 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1096 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1097 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1098 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1099 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1100 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1101 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1102 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1103 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1104 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1105 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1106 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1107 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1108 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1109 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1110 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1111 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1112 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1113 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1114 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1115 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1116 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1117 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1118 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1119 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1120 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1121 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1122 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1123 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1124 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1130 }; 1131 1132 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 1133 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 1135 }; 1136 1137 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 1138 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1139 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1140 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1141 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 1142 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 1143 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 1144 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 1145 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1146 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1147 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1148 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1149 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1150 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 1151 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1152 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1157 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1158 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1159 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 1160 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1164 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 1165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 1166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1169 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 1172 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1173 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1174 }; 1175 1176 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 1177 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1178 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1179 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1180 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1181 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 1182 }; 1183 1184 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 1185 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1186 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1187 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1188 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1189 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1190 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1191 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1192 }; 1193 1194 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1236 }; 1237 1238 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1240 }; 1241 1242 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 1243 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1244 }; 1245 1246 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1248 }; 1249 1250 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 1251 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1256 }; 1257 1258 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 1259 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1277 }; 1278 1279 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 1280 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1281 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1282 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1283 }; 1284 1285 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1286 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1287 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1288 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1289 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1290 }; 1291 1292 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 1293 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1294 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1299 }; 1300 1301 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 1302 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1319 }; 1320 1321 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 1322 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1323 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 1324 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1325 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 1326 }; 1327 1328 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1329 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1330 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1331 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1332 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1333 }; 1334 1335 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 1336 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1337 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1338 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1339 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1340 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1341 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1380 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1381 }; 1382 1383 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = { 1384 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1385 }; 1386 1387 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1388 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1389 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1390 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1391 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1392 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), 1393 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1394 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1395 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1396 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), 1397 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1398 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1399 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1400 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1401 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1402 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1403 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1404 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1405 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1406 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1407 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1408 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1409 }; 1410 1411 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { 1412 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1413 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1414 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1415 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1416 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1417 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1418 }; 1419 1420 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 1421 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1422 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1423 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1424 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1425 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1432 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1), 1433 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1435 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1439 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1), 1440 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1443 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1444 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1445 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1446 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1447 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1448 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), 1451 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1452 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1453 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), 1454 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1455 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1456 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1457 }; 1458 1459 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { 1460 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1461 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 1462 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1463 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1464 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 1465 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 1466 }; 1467 1468 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1469 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1470 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1471 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1472 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1473 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1474 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1475 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1476 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 1477 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 1478 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1479 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1480 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18), 1481 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1482 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1483 }; 1484 1485 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = { 1486 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1487 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1488 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1489 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1490 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1491 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08), 1492 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04), 1493 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d), 1494 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1495 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1496 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1497 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1498 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1499 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1500 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1501 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1502 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1503 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1504 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1505 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1506 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1507 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1508 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1509 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1510 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1511 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1512 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1513 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1514 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1515 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1516 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1517 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1518 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1519 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1520 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1521 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1522 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1523 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1524 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1525 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1526 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 1527 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1528 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1529 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1530 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1531 }; 1532 1533 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = { 1534 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1535 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1536 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1537 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1538 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1539 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1540 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1541 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1542 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1543 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1544 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1545 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1546 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1547 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1548 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1549 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1550 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1551 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1552 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1553 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1554 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1555 }; 1556 1557 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = { 1558 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1559 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05), 1560 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1561 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1562 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1563 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1564 }; 1565 1566 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = { 1567 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1568 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1569 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1570 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1571 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1572 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1573 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1574 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1575 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1576 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c), 1577 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1578 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1579 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1580 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1581 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1582 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1583 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1584 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4), 1585 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23), 1586 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1587 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1588 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38), 1589 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1590 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1591 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c), 1592 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4), 1593 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1594 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1595 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69), 1596 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1597 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1598 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1599 }; 1600 1601 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = { 1602 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)), 1603 }; 1604 1605 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = { 1606 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00), 1607 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e), 1608 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99), 1609 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00), 1610 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00), 1611 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22), 1612 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04), 1613 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02), 1614 }; 1615 1616 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = { 1617 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1618 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00), 1619 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16), 1620 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02), 1621 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e), 1622 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03), 1623 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28), 1624 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18), 1625 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1626 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1627 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27), 1628 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27), 1629 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0), 1630 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d), 1631 }; 1632 1633 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 1634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1667 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1668 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1669 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1670 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1671 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1672 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1673 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1674 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1675 }; 1676 1677 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1678 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1679 }; 1680 1681 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1682 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1683 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1684 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1685 }; 1686 1687 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1718 }; 1719 1720 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1723 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1724 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1725 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1726 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1727 }; 1728 1729 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1730 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1731 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1732 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1733 }; 1734 1735 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1736 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1737 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1738 }; 1739 1740 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1741 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1742 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1743 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1744 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1745 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1746 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1747 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1748 }; 1749 1750 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1751 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1752 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1753 }; 1754 1755 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1756 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1757 }; 1758 1759 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1764 }; 1765 1766 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1767 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1769 }; 1770 1771 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1772 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1773 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1774 }; 1775 1776 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1791 }; 1792 1793 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1797 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1798 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1799 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1800 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1826 }; 1827 1828 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1854 }; 1855 1856 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1857 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1858 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1859 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1860 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1861 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1862 }; 1863 1864 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1865 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1866 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1867 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1868 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1869 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1870 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1871 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1872 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1873 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1874 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1875 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1876 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1877 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1878 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1879 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1880 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1881 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1882 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1883 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1884 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1885 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1886 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1887 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1888 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1889 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1890 }; 1891 1892 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1893 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1894 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1895 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1896 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1897 }; 1898 1899 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1900 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1901 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1902 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1903 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1904 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1905 }; 1906 1907 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1908 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1909 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1910 }; 1911 1912 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_lane1_tbl[] = { 1913 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1914 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1915 }; 1916 1917 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 1918 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1919 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1920 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1921 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1922 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1923 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1927 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1928 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1929 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1939 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1940 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1945 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1946 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1947 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 1951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1952 }; 1953 1954 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 1955 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1956 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1957 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 1958 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 1959 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 1960 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1961 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1962 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 1963 }; 1964 1965 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 1966 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1967 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 1968 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 1969 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 1970 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 1971 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1972 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1973 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 1974 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 1975 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 1976 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 1977 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 1978 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1979 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 1980 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1981 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 1982 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 1983 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1984 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 1985 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1986 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1987 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1988 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 1989 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1990 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1991 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1992 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 1993 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1994 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1995 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1996 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1997 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1998 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1999 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2000 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2001 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2002 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2003 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 2004 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2005 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2006 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2007 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 2008 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2009 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 2010 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2011 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 2012 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2013 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 2014 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 2015 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 2016 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 2017 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 2018 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 2019 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2020 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 2021 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 2022 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 2023 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 2024 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 2025 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 2026 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 2027 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 2028 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2029 }; 2030 2031 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 2032 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2033 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 2034 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 2035 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2036 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2037 }; 2038 2039 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 2040 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2041 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2042 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 2043 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 2044 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2045 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2046 }; 2047 2048 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_lane1_tbl[] = { 2049 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2050 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2051 }; 2052 2053 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 2054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 2057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 2059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 2060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 2061 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 2062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 2064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 2071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 2072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 2073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 2074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 2077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 2084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 2085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 2086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 2087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 2088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2095 }; 2096 2097 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 2098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 2099 }; 2100 2101 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 2102 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2103 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2104 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2105 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 2106 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 2107 }; 2108 2109 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 2110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 2111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 2112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 2113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 2114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 2115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 2116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 2117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 2118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 2119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 2120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 2121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 2122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 2124 }; 2125 2126 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2127 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2128 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2129 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 2130 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2131 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2132 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 2133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 2134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 2135 }; 2136 2137 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 2138 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 2139 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 2140 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 2141 }; 2142 2143 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 2144 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2145 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 2146 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 2147 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2148 }; 2149 2150 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 2151 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2152 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2153 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2154 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2155 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2156 }; 2157 2158 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2163 }; 2164 2165 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 2166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 2167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 2168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 2169 }; 2170 2171 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 2172 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 2173 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 2174 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 2175 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2176 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2177 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2178 }; 2179 2180 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 2181 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 2182 }; 2183 2184 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 2185 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2198 }; 2199 2200 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 2201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 2229 }; 2230 2231 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 2232 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2233 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2234 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 2235 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2236 }; 2237 2238 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 2239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 2242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 2243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 2244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 2245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 2247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 2248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 2249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 2250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 2251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 2252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 2253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 2254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 2255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 2256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 2257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 2258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 2259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 2260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2263 2264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 2265 2266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2267 2268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2269 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2273 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2276 2277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 2279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2280 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2281 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2282 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2283 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 2284 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2285 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2286 }; 2287 2288 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 2289 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2290 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2291 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2292 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 2293 }; 2294 2295 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2299 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2300 }; 2301 2302 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 2303 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2304 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2305 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 2306 }; 2307 2308 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 2309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2329 }; 2330 2331 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 2332 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 2333 }; 2334 2335 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 2336 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2337 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2338 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2339 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2340 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2341 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 2342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 2361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 2365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 2366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 2367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 2373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2374 }; 2375 2376 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 2377 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 2378 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 2379 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 2380 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 2381 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 2382 }; 2383 2384 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 2385 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2386 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 2387 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 2388 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 2389 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 2390 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 2391 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 2392 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 2393 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 2394 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 2395 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 2396 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 2397 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 2398 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 2399 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 2400 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 2401 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), 2402 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 2403 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 2404 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 2405 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 2406 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 2407 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 2408 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2409 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 2410 }; 2411 2412 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 2413 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 2414 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 2415 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 2416 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 2417 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 2418 }; 2419 2420 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 2421 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 2422 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 2423 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2424 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2425 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2426 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2427 }; 2428 2429 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 2430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 2431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 2432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 2433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 2441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 2442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 2443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 2446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 2449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 2456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 2461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 2462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 2465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 2467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 2468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 2472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 2473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 2474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 2475 }; 2476 2477 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 2478 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 2479 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 2480 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 2481 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 2482 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 2483 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 2484 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 2485 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 2486 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 2487 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 2488 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 2489 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2490 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2491 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2492 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2493 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2494 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2495 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2496 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2497 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2498 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 2499 }; 2500 2501 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 2502 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2503 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 2504 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 2505 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 2506 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 2507 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 2508 }; 2509 2510 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 2511 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 2512 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2513 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 2514 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2515 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2516 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 2517 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 2518 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2519 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 2520 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2521 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2522 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2523 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2524 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2525 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 2526 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2527 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 2528 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 2529 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 2530 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2531 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 2532 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2533 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2534 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 2535 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 2536 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 2537 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2538 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 2539 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2540 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2541 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 2542 }; 2543 2544 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 2545 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2546 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 2547 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 2548 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 2549 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 2550 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 2551 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 2552 }; 2553 2554 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2555 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 2556 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 2557 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 2558 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 2559 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 2560 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 2561 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 2562 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 2563 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 2564 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 2565 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 2566 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 2567 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 2568 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 2569 }; 2570 2571 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 2572 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 2573 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2574 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2575 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2576 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 2577 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2578 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2579 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2580 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2581 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2582 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2583 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2584 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 2585 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 2586 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 2587 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2588 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 2589 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2590 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2591 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 2592 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 2593 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 2594 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2595 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 2596 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2597 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2598 }; 2599 2600 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_serdes_tbl[] = { 2601 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x1), 2602 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62), 2603 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02), 2604 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2605 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2606 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0x93), 2607 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2608 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_ENABLE1, 0x90), 2609 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYS_CLK_CTRL, 0x82), 2610 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_IVCO, 0x07), 2611 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02), 2612 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02), 2613 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16), 2614 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16), 2615 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36), 2616 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36), 2617 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x08), 2618 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a), 2619 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_EN, 0x42), 2620 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x04), 2621 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x0d), 2622 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x0a), 2623 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x1a), 2624 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41), 2625 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x34), 2626 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0xab), 2627 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0xaa), 2628 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01), 2629 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55), 2630 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x55), 2631 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01), 2632 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x14), 2633 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_SELECT, 0x34), 2634 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01), 2635 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04), 2636 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16), 2637 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC_3, 0x0F), 2638 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0xA0), 2639 }; 2640 2641 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_rx_tbl[] = { 2642 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2643 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x11), 2644 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xBF), 2645 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xBF), 2646 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xB7), 2647 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xEA), 2648 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3F), 2649 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x09), 2650 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x49), 2651 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1B), 2652 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x9C), 2653 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xD1), 2654 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH, 0x09), 2655 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH2, 0x49), 2656 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH3, 0x1B), 2657 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH4, 0x9C), 2658 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_LOW, 0xD1), 2659 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1, 0x3E), 2660 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2, 0x1E), 2661 QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_POST_THRESH, 0xD2), 2662 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x09), 2663 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x05), 2664 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08), 2665 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08), 2666 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x09), 2667 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_ENABLES, 0x1C), 2668 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x60), 2669 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2670 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08), 2671 }; 2672 2673 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_tx_tbl[] = { 2674 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0x35), 2675 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x10), 2676 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x31), 2677 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x7F), 2678 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x02), 2679 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x08), 2680 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x14), 2681 }; 2682 2683 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_tbl[] = { 2684 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x05), 2685 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0x77), 2686 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RATE_SLEW_CNTRL1, 0x0B), 2687 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG2, 0x0F), 2688 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x8C), 2689 QMP_PHY_INIT_CFG(QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2690 QMP_PHY_INIT_CFG(QPHY_V7_PCS_G3S2_PRE_GAIN, 0x2E), 2691 }; 2692 2693 static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 2694 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1E), 2695 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 2696 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D), 2697 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2698 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1), 2699 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2700 }; 2701 2702 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 2703 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2704 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2705 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2706 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2707 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2708 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2709 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2710 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2711 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2712 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2713 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2714 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2715 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2716 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2717 }; 2718 2719 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = { 2720 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2721 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2722 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2723 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2724 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2725 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2726 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2727 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2728 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2729 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2730 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2731 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2732 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2733 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2734 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2735 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2736 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2737 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2738 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2739 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2740 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2741 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2742 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2743 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2744 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2745 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2746 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2747 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2748 }; 2749 2750 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = { 2751 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x07), 2752 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2753 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), 2754 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2755 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xe4), 2756 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2757 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2758 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 2759 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 2760 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), 2761 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 2762 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xe4), 2763 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 2764 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2765 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2766 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2767 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3), 2768 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 2769 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xed), 2770 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe5), 2771 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x8d), 2772 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6), 2773 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e), 2774 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2775 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2776 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2777 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2778 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2779 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2780 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2781 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2782 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2783 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2784 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2785 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2786 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2787 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2788 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2789 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2790 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2791 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2792 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03), 2793 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x08), 2794 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2795 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2796 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2797 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x01), 2798 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2799 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2800 }; 2801 2802 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = { 2803 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2804 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 2805 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2806 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2807 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f), 2808 }; 2809 2810 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = { 2811 QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME, 0x27), 2812 QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME, 0x27), 2813 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2814 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2815 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2816 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2817 }; 2818 2819 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = { 2820 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2821 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2822 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2823 }; 2824 2825 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_alt_tbl[] = { 2826 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2827 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2828 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2829 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2830 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1, 0xff), 2831 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2, 0x89), 2832 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1, 0x00), 2833 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2, 0x50), 2834 }; 2835 2836 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 2837 QMP_PHY_INIT_CFG(QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2, 0x00), 2838 }; 2839 2840 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = { 2841 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2842 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2843 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2844 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2845 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2846 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2847 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2848 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2849 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2850 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2851 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2852 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2853 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2854 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2855 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2856 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2857 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2858 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2859 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2860 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2861 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), 2862 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2863 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2), 2864 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2865 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2866 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 2867 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 2868 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), 2869 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), 2870 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2), 2871 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), 2872 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2873 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2874 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2875 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3), 2876 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), 2877 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xe4), 2878 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe6), 2879 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2880 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6), 2881 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e), 2882 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2883 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2884 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2885 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2886 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2887 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2888 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2889 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x06), 2890 }; 2891 2892 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = { 2893 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 2894 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2895 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2896 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2897 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2898 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2899 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2900 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2901 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2902 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2903 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2904 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2905 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2906 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2907 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2908 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2909 }; 2910 2911 2912 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = { 2913 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2914 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2915 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2916 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2917 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2918 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2919 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2920 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2921 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2922 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2923 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2927 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2928 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2929 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2939 }; 2940 2941 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { 2942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2945 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2946 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2947 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2956 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2957 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2958 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2959 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2960 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2961 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2962 }; 2963 2964 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { 2965 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00), 2966 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), 2967 }; 2968 2969 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 2970 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2971 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 2972 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 2973 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), 2974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), 2975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 2976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), 2977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 2988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 2990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 2991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), 2992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), 2993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 2994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2995 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2996 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), 2997 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), 2998 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2999 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 3000 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 3001 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 3002 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 3003 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 3004 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 3005 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 3006 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 3007 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 3008 }; 3009 3010 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = { 3011 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01), 3012 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01), 3013 }; 3014 3015 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = { 3016 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2), 3017 }; 3018 3019 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 3020 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3021 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e), 3022 }; 3023 3024 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = { 3025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00), 3026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06), 3027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07), 3028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 3029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28), 3030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28), 3031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d), 3032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d), 3033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00), 3034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00), 3035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 3036 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 3037 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 3038 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff), 3039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09), 3040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19), 3041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14), 3042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 3043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03), 3044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 3045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03), 3046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 3047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 3048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 3049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 3050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 3051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 3052 }; 3053 3054 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = { 3055 QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 3056 }; 3057 3058 static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = { 3059 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 3060 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14), 3061 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 3062 }; 3063 3064 struct qmp_pcie_offsets { 3065 u16 serdes; 3066 u16 pcs; 3067 u16 pcs_misc; 3068 u16 pcs_lane1; 3069 u16 tx; 3070 u16 rx; 3071 u16 tx2; 3072 u16 rx2; 3073 u16 txz; 3074 u16 rxz; 3075 u16 ln_shrd; 3076 }; 3077 3078 struct qmp_phy_cfg_tbls { 3079 const struct qmp_phy_init_tbl *serdes; 3080 int serdes_num; 3081 const struct qmp_phy_init_tbl *tx; 3082 int tx_num; 3083 const struct qmp_phy_init_tbl *rx; 3084 int rx_num; 3085 const struct qmp_phy_init_tbl *txz; 3086 int txz_num; 3087 const struct qmp_phy_init_tbl *rxz; 3088 int rxz_num; 3089 const struct qmp_phy_init_tbl *pcs; 3090 int pcs_num; 3091 const struct qmp_phy_init_tbl *pcs_misc; 3092 int pcs_misc_num; 3093 const struct qmp_phy_init_tbl *pcs_lane1; 3094 int pcs_lane1_num; 3095 const struct qmp_phy_init_tbl *ln_shrd; 3096 int ln_shrd_num; 3097 }; 3098 3099 /* struct qmp_phy_cfg - per-PHY initialization config */ 3100 struct qmp_phy_cfg { 3101 int lanes; 3102 3103 const struct qmp_pcie_offsets *offsets; 3104 3105 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 3106 const struct qmp_phy_cfg_tbls tbls; 3107 /* 3108 * Additional init sequences for PHY blocks, providing additional 3109 * register programming. They are used for providing separate sequences 3110 * for the Root Complex and End Point use cases. 3111 * 3112 * If EP mode is not supported, both tables can be left unset. 3113 */ 3114 const struct qmp_phy_cfg_tbls *tbls_rc; 3115 const struct qmp_phy_cfg_tbls *tbls_ep; 3116 3117 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 3118 int serdes_4ln_num; 3119 3120 /* resets to be requested */ 3121 const char * const *reset_list; 3122 int num_resets; 3123 /* regulators to be requested */ 3124 const char * const *vreg_list; 3125 int num_vregs; 3126 3127 /* array of registers with different offsets */ 3128 const unsigned int *regs; 3129 3130 unsigned int pwrdn_ctrl; 3131 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 3132 unsigned int phy_status; 3133 3134 bool skip_start_delay; 3135 3136 /* QMP PHY pipe clock interface rate */ 3137 unsigned long pipe_clock_rate; 3138 3139 /* QMP PHY AUX clock interface rate */ 3140 unsigned long aux_clock_rate; 3141 }; 3142 3143 struct qmp_pcie { 3144 struct device *dev; 3145 3146 const struct qmp_phy_cfg *cfg; 3147 bool tcsr_4ln_config; 3148 bool skip_init; 3149 3150 void __iomem *serdes; 3151 void __iomem *pcs; 3152 void __iomem *pcs_misc; 3153 void __iomem *pcs_lane1; 3154 void __iomem *tx; 3155 void __iomem *rx; 3156 void __iomem *tx2; 3157 void __iomem *rx2; 3158 void __iomem *txz; 3159 void __iomem *rxz; 3160 void __iomem *ln_shrd; 3161 3162 void __iomem *port_b; 3163 3164 struct clk_bulk_data *clks; 3165 struct clk_bulk_data pipe_clks[2]; 3166 int num_pipe_clks; 3167 3168 struct reset_control_bulk_data *resets; 3169 struct reset_control *nocsr_reset; 3170 struct regulator_bulk_data *vregs; 3171 3172 struct phy *phy; 3173 int mode; 3174 3175 struct clk_fixed_rate pipe_clk_fixed; 3176 struct clk_fixed_rate aux_clk_fixed; 3177 }; 3178 3179 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 3180 { 3181 u32 reg; 3182 3183 reg = readl(base + offset); 3184 reg |= val; 3185 writel(reg, base + offset); 3186 3187 /* ensure that above write is through */ 3188 readl(base + offset); 3189 } 3190 3191 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 3192 { 3193 u32 reg; 3194 3195 reg = readl(base + offset); 3196 reg &= ~val; 3197 writel(reg, base + offset); 3198 3199 /* ensure that above write is through */ 3200 readl(base + offset); 3201 } 3202 3203 /* list of clocks required by phy */ 3204 static const char * const qmp_pciephy_clk_l[] = { 3205 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", 3206 }; 3207 3208 /* list of regulators */ 3209 static const char * const qmp_phy_vreg_l[] = { 3210 "vdda-phy", "vdda-pll", 3211 }; 3212 3213 static const char * const sm8550_qmp_phy_vreg_l[] = { 3214 "vdda-phy", "vdda-pll", "vdda-qref", 3215 }; 3216 3217 /* list of resets */ 3218 static const char * const ipq8074_pciephy_reset_l[] = { 3219 "phy", "common", 3220 }; 3221 3222 static const char * const sdm845_pciephy_reset_l[] = { 3223 "phy", 3224 }; 3225 3226 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { 3227 .serdes = 0, 3228 .pcs = 0x1800, 3229 .tx = 0x0800, 3230 /* no .rx for QHP */ 3231 }; 3232 3233 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { 3234 .serdes = 0, 3235 .pcs = 0x0800, 3236 .tx = 0x0200, 3237 .rx = 0x0400, 3238 }; 3239 3240 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { 3241 .serdes = 0, 3242 .pcs = 0x0800, 3243 .pcs_misc = 0x0600, 3244 .tx = 0x0200, 3245 .rx = 0x0400, 3246 }; 3247 3248 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { 3249 .serdes = 0, 3250 .pcs = 0x0800, 3251 .pcs_misc = 0x0c00, 3252 .tx = 0x0200, 3253 .rx = 0x0400, 3254 }; 3255 3256 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { 3257 .serdes = 0, 3258 .pcs = 0x0a00, 3259 .pcs_misc = 0x0e00, 3260 .tx = 0x0200, 3261 .rx = 0x0400, 3262 .tx2 = 0x0600, 3263 .rx2 = 0x0800, 3264 }; 3265 3266 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { 3267 .serdes = 0x1000, 3268 .pcs = 0x1200, 3269 .pcs_misc = 0x1600, 3270 .pcs_lane1 = 0x1e00, 3271 .tx = 0x0000, 3272 .rx = 0x0200, 3273 .tx2 = 0x0800, 3274 .rx2 = 0x0a00, 3275 }; 3276 3277 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 3278 .serdes = 0, 3279 .pcs = 0x0200, 3280 .pcs_misc = 0x0600, 3281 .tx = 0x0e00, 3282 .rx = 0x1000, 3283 .tx2 = 0x1600, 3284 .rx2 = 0x1800, 3285 }; 3286 3287 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { 3288 .serdes = 0, 3289 .pcs = 0x1000, 3290 .pcs_misc = 0x1400, 3291 .tx = 0x0200, 3292 .rx = 0x0400, 3293 .tx2 = 0x0600, 3294 .rx2 = 0x0800, 3295 }; 3296 3297 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { 3298 .serdes = 0x1000, 3299 .pcs = 0x1200, 3300 .pcs_misc = 0x1400, 3301 .pcs_lane1 = 0x1e00, 3302 .tx = 0x0000, 3303 .rx = 0x0200, 3304 .tx2 = 0x0800, 3305 .rx2 = 0x0a00, 3306 .ln_shrd = 0x0e00, 3307 }; 3308 3309 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { 3310 .serdes = 0x2000, 3311 .pcs = 0x2200, 3312 .pcs_misc = 0x2400, 3313 .tx = 0x0, 3314 .rx = 0x0200, 3315 .tx2 = 0x3800, 3316 .rx2 = 0x3a00, 3317 }; 3318 3319 static const struct qmp_pcie_offsets qmp_pcie_offsets_v7 = { 3320 .serdes = 0x0, 3321 .pcs = 0x400, 3322 .pcs_misc = 0x800, 3323 .tx = 0x1000, 3324 .rx = 0x1200, 3325 .tx2 = 0x1800, 3326 .rx2 = 0x1a00, 3327 }; 3328 3329 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 3330 .serdes = 0x1000, 3331 .pcs = 0x1200, 3332 .pcs_misc = 0x1400, 3333 .tx = 0x0000, 3334 .rx = 0x0200, 3335 .tx2 = 0x0800, 3336 .rx2 = 0x0a00, 3337 .ln_shrd = 0x0e00, 3338 }; 3339 3340 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = { 3341 .serdes = 0x8800, 3342 .pcs = 0x9000, 3343 .pcs_misc = 0x9800, 3344 .tx = 0x0000, 3345 .rx = 0x0200, 3346 .txz = 0xe000, 3347 .rxz = 0xe200, 3348 .ln_shrd = 0x8000, 3349 }; 3350 3351 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 3352 .lanes = 1, 3353 3354 .offsets = &qmp_pcie_offsets_v2, 3355 3356 .tbls = { 3357 .serdes = ipq8074_pcie_serdes_tbl, 3358 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 3359 .tx = ipq8074_pcie_tx_tbl, 3360 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 3361 .rx = ipq8074_pcie_rx_tbl, 3362 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 3363 .pcs = ipq8074_pcie_pcs_tbl, 3364 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 3365 }, 3366 .reset_list = ipq8074_pciephy_reset_l, 3367 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3368 .vreg_list = NULL, 3369 .num_vregs = 0, 3370 .regs = pciephy_v2_regs_layout, 3371 3372 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3373 .phy_status = PHYSTATUS, 3374 }; 3375 3376 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 3377 .lanes = 1, 3378 3379 .offsets = &qmp_pcie_offsets_v4x1, 3380 3381 .tbls = { 3382 .serdes = ipq8074_pcie_gen3_serdes_tbl, 3383 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 3384 .tx = ipq8074_pcie_gen3_tx_tbl, 3385 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3386 .rx = ipq8074_pcie_gen3_rx_tbl, 3387 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 3388 .pcs = ipq8074_pcie_gen3_pcs_tbl, 3389 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 3390 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 3391 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 3392 }, 3393 .reset_list = ipq8074_pciephy_reset_l, 3394 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3395 .vreg_list = NULL, 3396 .num_vregs = 0, 3397 .regs = pciephy_v4_regs_layout, 3398 3399 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3400 .phy_status = PHYSTATUS, 3401 3402 .pipe_clock_rate = 250000000, 3403 }; 3404 3405 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 3406 .lanes = 1, 3407 3408 .offsets = &qmp_pcie_offsets_v4x1, 3409 3410 .tbls = { 3411 .serdes = ipq6018_pcie_serdes_tbl, 3412 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 3413 .tx = ipq6018_pcie_tx_tbl, 3414 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 3415 .rx = ipq6018_pcie_rx_tbl, 3416 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 3417 .pcs = ipq6018_pcie_pcs_tbl, 3418 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 3419 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 3420 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 3421 }, 3422 .reset_list = ipq8074_pciephy_reset_l, 3423 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3424 .vreg_list = NULL, 3425 .num_vregs = 0, 3426 .regs = pciephy_v4_regs_layout, 3427 3428 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3429 .phy_status = PHYSTATUS, 3430 }; 3431 3432 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { 3433 .lanes = 1, 3434 3435 .offsets = &qmp_pcie_offsets_v4x1, 3436 3437 .tbls = { 3438 .serdes = ipq9574_gen3x1_pcie_serdes_tbl, 3439 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), 3440 .tx = ipq8074_pcie_gen3_tx_tbl, 3441 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3442 .rx = ipq9574_pcie_rx_tbl, 3443 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 3444 .pcs = ipq9574_gen3x1_pcie_pcs_tbl, 3445 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), 3446 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, 3447 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), 3448 }, 3449 .reset_list = ipq8074_pciephy_reset_l, 3450 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3451 .vreg_list = NULL, 3452 .num_vregs = 0, 3453 .regs = pciephy_v4_regs_layout, 3454 3455 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3456 .phy_status = PHYSTATUS, 3457 .pipe_clock_rate = 250000000, 3458 }; 3459 3460 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = { 3461 .lanes = 2, 3462 3463 .offsets = &qmp_pcie_offsets_ipq9574, 3464 3465 .tbls = { 3466 .serdes = ipq9574_gen3x2_pcie_serdes_tbl, 3467 .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), 3468 .tx = ipq8074_pcie_gen3_tx_tbl, 3469 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3470 .rx = ipq9574_pcie_rx_tbl, 3471 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 3472 .pcs = ipq9574_gen3x2_pcie_pcs_tbl, 3473 .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl), 3474 .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, 3475 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), 3476 }, 3477 .reset_list = ipq8074_pciephy_reset_l, 3478 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3479 .vreg_list = NULL, 3480 .num_vregs = 0, 3481 .regs = pciephy_v5_regs_layout, 3482 3483 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3484 .phy_status = PHYSTATUS, 3485 .pipe_clock_rate = 250000000, 3486 }; 3487 3488 static const struct qmp_phy_cfg qcs615_pciephy_cfg = { 3489 .lanes = 1, 3490 3491 .offsets = &qmp_pcie_offsets_v2, 3492 3493 .tbls = { 3494 .serdes = qcs615_pcie_serdes_tbl, 3495 .serdes_num = ARRAY_SIZE(qcs615_pcie_serdes_tbl), 3496 .tx = qcs615_pcie_tx_tbl, 3497 .tx_num = ARRAY_SIZE(qcs615_pcie_tx_tbl), 3498 .rx = qcs615_pcie_rx_tbl, 3499 .rx_num = ARRAY_SIZE(qcs615_pcie_rx_tbl), 3500 .pcs = qcs615_pcie_pcs_tbl, 3501 .pcs_num = ARRAY_SIZE(qcs615_pcie_pcs_tbl), 3502 }, 3503 .reset_list = sdm845_pciephy_reset_l, 3504 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3505 .vreg_list = qmp_phy_vreg_l, 3506 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3507 .regs = pciephy_v2_regs_layout, 3508 3509 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3510 .phy_status = PHYSTATUS, 3511 }; 3512 3513 static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = { 3514 .lanes = 2, 3515 .offsets = &qmp_pcie_offsets_v5_20, 3516 3517 .tbls = { 3518 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 3519 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 3520 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 3521 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 3522 .rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl, 3523 .rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl), 3524 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, 3525 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), 3526 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3527 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3528 }, 3529 3530 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3531 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 3532 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 3533 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 3534 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 3535 }, 3536 3537 .reset_list = sdm845_pciephy_reset_l, 3538 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3539 .vreg_list = qmp_phy_vreg_l, 3540 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3541 .regs = pciephy_v5_regs_layout, 3542 3543 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3544 .phy_status = PHYSTATUS_4_20, 3545 }; 3546 3547 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 3548 .lanes = 1, 3549 3550 .offsets = &qmp_pcie_offsets_v3, 3551 3552 .tbls = { 3553 .serdes = sdm845_qmp_pcie_serdes_tbl, 3554 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 3555 .tx = sdm845_qmp_pcie_tx_tbl, 3556 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 3557 .rx = sdm845_qmp_pcie_rx_tbl, 3558 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 3559 .pcs = sdm845_qmp_pcie_pcs_tbl, 3560 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 3561 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 3562 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 3563 }, 3564 .reset_list = sdm845_pciephy_reset_l, 3565 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3566 .vreg_list = qmp_phy_vreg_l, 3567 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3568 .regs = pciephy_v3_regs_layout, 3569 3570 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3571 .phy_status = PHYSTATUS, 3572 }; 3573 3574 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 3575 .lanes = 1, 3576 3577 .offsets = &qmp_pcie_offsets_qhp, 3578 3579 .tbls = { 3580 .serdes = sdm845_qhp_pcie_serdes_tbl, 3581 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 3582 .tx = sdm845_qhp_pcie_tx_tbl, 3583 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 3584 .pcs = sdm845_qhp_pcie_pcs_tbl, 3585 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 3586 }, 3587 .reset_list = sdm845_pciephy_reset_l, 3588 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3589 .vreg_list = qmp_phy_vreg_l, 3590 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3591 .regs = sdm845_qhp_pciephy_regs_layout, 3592 3593 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3594 .phy_status = PHYSTATUS, 3595 }; 3596 3597 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 3598 .lanes = 1, 3599 3600 .offsets = &qmp_pcie_offsets_v4x1, 3601 3602 .tbls = { 3603 .serdes = sm8250_qmp_pcie_serdes_tbl, 3604 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 3605 .tx = sm8250_qmp_pcie_tx_tbl, 3606 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 3607 .rx = sm8250_qmp_pcie_rx_tbl, 3608 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 3609 .pcs = sm8250_qmp_pcie_pcs_tbl, 3610 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 3611 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 3612 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 3613 }, 3614 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3615 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 3616 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 3617 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 3618 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 3619 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 3620 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 3621 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 3622 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 3623 }, 3624 .reset_list = sdm845_pciephy_reset_l, 3625 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3626 .vreg_list = qmp_phy_vreg_l, 3627 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3628 .regs = pciephy_v4_regs_layout, 3629 3630 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3631 .phy_status = PHYSTATUS, 3632 }; 3633 3634 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 3635 .lanes = 2, 3636 3637 .offsets = &qmp_pcie_offsets_v4x2, 3638 3639 .tbls = { 3640 .serdes = sm8250_qmp_pcie_serdes_tbl, 3641 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 3642 .tx = sm8250_qmp_pcie_tx_tbl, 3643 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 3644 .rx = sm8250_qmp_pcie_rx_tbl, 3645 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 3646 .pcs = sm8250_qmp_pcie_pcs_tbl, 3647 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 3648 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 3649 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 3650 }, 3651 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3652 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 3653 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 3654 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 3655 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 3656 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 3657 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 3658 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 3659 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 3660 }, 3661 .reset_list = sdm845_pciephy_reset_l, 3662 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3663 .vreg_list = qmp_phy_vreg_l, 3664 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3665 .regs = pciephy_v4_regs_layout, 3666 3667 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3668 .phy_status = PHYSTATUS, 3669 }; 3670 3671 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 3672 .lanes = 1, 3673 3674 .offsets = &qmp_pcie_offsets_v3, 3675 3676 .tbls = { 3677 .serdes = msm8998_pcie_serdes_tbl, 3678 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 3679 .tx = msm8998_pcie_tx_tbl, 3680 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 3681 .rx = msm8998_pcie_rx_tbl, 3682 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 3683 .pcs = msm8998_pcie_pcs_tbl, 3684 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 3685 }, 3686 .reset_list = ipq8074_pciephy_reset_l, 3687 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3688 .vreg_list = qmp_phy_vreg_l, 3689 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3690 .regs = pciephy_v3_regs_layout, 3691 3692 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3693 .phy_status = PHYSTATUS, 3694 3695 .skip_start_delay = true, 3696 }; 3697 3698 static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = { 3699 .lanes = 2, 3700 3701 .offsets = &qmp_pcie_offsets_v5, 3702 3703 .tbls = { 3704 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 3705 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 3706 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 3707 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 3708 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 3709 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 3710 .pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, 3711 .pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), 3712 }, 3713 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3714 .serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl, 3715 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl), 3716 .tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl, 3717 .tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl), 3718 .pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl, 3719 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl), 3720 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 3721 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 3722 }, 3723 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3724 .serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl, 3725 .serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl), 3726 .pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl, 3727 .pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl), 3728 .pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl, 3729 .pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl), 3730 }, 3731 .reset_list = sdm845_pciephy_reset_l, 3732 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3733 .vreg_list = qmp_phy_vreg_l, 3734 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3735 .regs = pciephy_v5_regs_layout, 3736 3737 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3738 .phy_status = PHYSTATUS, 3739 }; 3740 3741 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 3742 .lanes = 2, 3743 3744 .offsets = &qmp_pcie_offsets_v4x2, 3745 3746 .tbls = { 3747 .serdes = sc8180x_qmp_pcie_serdes_tbl, 3748 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 3749 .tx = sc8180x_qmp_pcie_tx_tbl, 3750 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 3751 .rx = sc8180x_qmp_pcie_rx_tbl, 3752 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 3753 .pcs = sc8180x_qmp_pcie_pcs_tbl, 3754 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 3755 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 3756 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 3757 }, 3758 .reset_list = sdm845_pciephy_reset_l, 3759 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3760 .vreg_list = qmp_phy_vreg_l, 3761 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3762 .regs = pciephy_v4_regs_layout, 3763 3764 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3765 .phy_status = PHYSTATUS, 3766 }; 3767 3768 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 3769 .lanes = 1, 3770 3771 .offsets = &qmp_pcie_offsets_v5, 3772 3773 .tbls = { 3774 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3775 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3776 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 3777 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 3778 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 3779 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 3780 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 3781 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 3782 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 3783 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 3784 }, 3785 3786 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3787 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 3788 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 3789 }, 3790 3791 .reset_list = sdm845_pciephy_reset_l, 3792 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3793 .vreg_list = qmp_phy_vreg_l, 3794 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3795 .regs = pciephy_v5_regs_layout, 3796 3797 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3798 .phy_status = PHYSTATUS, 3799 }; 3800 3801 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 3802 .lanes = 2, 3803 3804 .offsets = &qmp_pcie_offsets_v5, 3805 3806 .tbls = { 3807 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3808 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3809 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 3810 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 3811 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 3812 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 3813 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 3814 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 3815 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3816 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3817 }, 3818 3819 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3820 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 3821 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 3822 }, 3823 3824 .reset_list = sdm845_pciephy_reset_l, 3825 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3826 .vreg_list = qmp_phy_vreg_l, 3827 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3828 .regs = pciephy_v5_regs_layout, 3829 3830 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3831 .phy_status = PHYSTATUS, 3832 }; 3833 3834 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 3835 .lanes = 4, 3836 3837 .offsets = &qmp_pcie_offsets_v5, 3838 3839 .tbls = { 3840 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3841 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3842 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 3843 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 3844 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 3845 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 3846 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 3847 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 3848 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3849 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3850 }, 3851 3852 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3853 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 3854 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 3855 }, 3856 3857 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 3858 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 3859 3860 .reset_list = sdm845_pciephy_reset_l, 3861 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3862 .vreg_list = qmp_phy_vreg_l, 3863 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3864 .regs = pciephy_v5_regs_layout, 3865 3866 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3867 .phy_status = PHYSTATUS, 3868 }; 3869 3870 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 3871 .lanes = 2, 3872 3873 .offsets = &qmp_pcie_offsets_v4_20, 3874 3875 .tbls = { 3876 .serdes = sdx55_qmp_pcie_serdes_tbl, 3877 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 3878 .tx = sdx55_qmp_pcie_tx_tbl, 3879 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 3880 .rx = sdx55_qmp_pcie_rx_tbl, 3881 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 3882 .pcs = sdx55_qmp_pcie_pcs_tbl, 3883 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 3884 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 3885 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 3886 }, 3887 3888 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3889 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 3890 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 3891 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 3892 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 3893 }, 3894 3895 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3896 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 3897 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 3898 .pcs_lane1 = sdx55_qmp_pcie_ep_pcs_lane1_tbl, 3899 .pcs_lane1_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_lane1_tbl), 3900 }, 3901 3902 .reset_list = sdm845_pciephy_reset_l, 3903 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3904 .vreg_list = qmp_phy_vreg_l, 3905 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3906 .regs = pciephy_v4_regs_layout, 3907 3908 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3909 .phy_status = PHYSTATUS_4_20, 3910 }; 3911 3912 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 3913 .lanes = 1, 3914 3915 .offsets = &qmp_pcie_offsets_v5, 3916 3917 .tbls = { 3918 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3919 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3920 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 3921 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 3922 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3923 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3924 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3925 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3926 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 3927 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 3928 }, 3929 3930 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3931 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 3932 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 3933 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 3934 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 3935 }, 3936 3937 .reset_list = sdm845_pciephy_reset_l, 3938 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3939 .vreg_list = qmp_phy_vreg_l, 3940 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3941 .regs = pciephy_v5_regs_layout, 3942 3943 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3944 .phy_status = PHYSTATUS, 3945 }; 3946 3947 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 3948 .lanes = 2, 3949 3950 .offsets = &qmp_pcie_offsets_v5, 3951 3952 .tbls = { 3953 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3954 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3955 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 3956 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 3957 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3958 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3959 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3960 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3961 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3962 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3963 }, 3964 3965 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3966 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 3967 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 3968 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 3969 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 3970 }, 3971 3972 .reset_list = sdm845_pciephy_reset_l, 3973 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3974 .vreg_list = qmp_phy_vreg_l, 3975 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3976 .regs = pciephy_v5_regs_layout, 3977 3978 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3979 .phy_status = PHYSTATUS, 3980 }; 3981 3982 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 3983 .lanes = 2, 3984 3985 .offsets = &qmp_pcie_offsets_v6_20, 3986 3987 .tbls = { 3988 .serdes = sdx65_qmp_pcie_serdes_tbl, 3989 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 3990 .tx = sdx65_qmp_pcie_tx_tbl, 3991 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 3992 .rx = sdx65_qmp_pcie_rx_tbl, 3993 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 3994 .pcs = sdx65_qmp_pcie_pcs_tbl, 3995 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 3996 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 3997 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 3998 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 3999 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 4000 }, 4001 .reset_list = sdm845_pciephy_reset_l, 4002 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4003 .vreg_list = qmp_phy_vreg_l, 4004 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4005 .regs = pciephy_v6_regs_layout, 4006 4007 .pwrdn_ctrl = SW_PWRDN, 4008 .phy_status = PHYSTATUS_4_20, 4009 }; 4010 4011 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 4012 .lanes = 1, 4013 4014 .offsets = &qmp_pcie_offsets_v5, 4015 4016 .tbls = { 4017 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 4018 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 4019 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 4020 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 4021 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 4022 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 4023 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 4024 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 4025 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 4026 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 4027 }, 4028 4029 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4030 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 4031 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 4032 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 4033 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 4034 }, 4035 4036 .reset_list = sdm845_pciephy_reset_l, 4037 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4038 .vreg_list = qmp_phy_vreg_l, 4039 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4040 .regs = pciephy_v5_regs_layout, 4041 4042 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4043 .phy_status = PHYSTATUS, 4044 }; 4045 4046 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 4047 .lanes = 2, 4048 4049 .offsets = &qmp_pcie_offsets_v5_20, 4050 4051 .tbls = { 4052 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 4053 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 4054 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 4055 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 4056 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 4057 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 4058 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 4059 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 4060 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 4061 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 4062 }, 4063 4064 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4065 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 4066 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 4067 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 4068 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 4069 }, 4070 4071 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4072 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 4073 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 4074 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 4075 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 4076 }, 4077 4078 .reset_list = sdm845_pciephy_reset_l, 4079 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4080 .vreg_list = qmp_phy_vreg_l, 4081 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4082 .regs = pciephy_v5_regs_layout, 4083 4084 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4085 .phy_status = PHYSTATUS_4_20, 4086 4087 /* 20MHz PHY AUX Clock */ 4088 .aux_clock_rate = 20000000, 4089 }; 4090 4091 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 4092 .lanes = 2, 4093 4094 .offsets = &qmp_pcie_offsets_v5, 4095 4096 .tbls = { 4097 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 4098 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 4099 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 4100 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 4101 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 4102 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 4103 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 4104 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 4105 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 4106 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 4107 }, 4108 .reset_list = sdm845_pciephy_reset_l, 4109 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4110 .vreg_list = qmp_phy_vreg_l, 4111 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4112 .regs = pciephy_v5_regs_layout, 4113 4114 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4115 .phy_status = PHYSTATUS, 4116 }; 4117 4118 static const struct qmp_phy_cfg sm8750_qmp_gen3x2_pciephy_cfg = { 4119 .lanes = 2, 4120 4121 .offsets = &qmp_pcie_offsets_v7, 4122 4123 .tbls = { 4124 .serdes = sm8750_qmp_gen3x2_pcie_serdes_tbl, 4125 .serdes_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_serdes_tbl), 4126 .tx = sm8750_qmp_gen3x2_pcie_tx_tbl, 4127 .tx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_tx_tbl), 4128 .rx = sm8750_qmp_gen3x2_pcie_rx_tbl, 4129 .rx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_rx_tbl), 4130 .pcs = sm8750_qmp_gen3x2_pcie_pcs_tbl, 4131 .pcs_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_tbl), 4132 .pcs_misc = sm8750_qmp_gen3x2_pcie_pcs_misc_tbl, 4133 .pcs_misc_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_misc_tbl), 4134 }, 4135 .reset_list = sdm845_pciephy_reset_l, 4136 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4137 .vreg_list = qmp_phy_vreg_l, 4138 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4139 .regs = pciephy_v7_regs_layout, 4140 4141 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4142 .phy_status = PHYSTATUS, 4143 }; 4144 4145 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 4146 .lanes = 2, 4147 4148 .offsets = &qmp_pcie_offsets_v6_20, 4149 4150 .tbls = { 4151 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 4152 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 4153 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 4154 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 4155 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 4156 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 4157 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 4158 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 4159 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 4160 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 4161 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 4162 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 4163 }, 4164 .reset_list = sdm845_pciephy_reset_l, 4165 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4166 .vreg_list = sm8550_qmp_phy_vreg_l, 4167 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 4168 .regs = pciephy_v6_regs_layout, 4169 4170 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4171 .phy_status = PHYSTATUS_4_20, 4172 4173 /* 20MHz PHY AUX Clock */ 4174 .aux_clock_rate = 20000000, 4175 }; 4176 4177 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 4178 .lanes = 2, 4179 4180 .offsets = &qmp_pcie_offsets_v6_20, 4181 4182 .tbls = { 4183 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 4184 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 4185 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 4186 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 4187 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 4188 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 4189 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 4190 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 4191 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 4192 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 4193 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 4194 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 4195 }, 4196 .reset_list = sdm845_pciephy_reset_l, 4197 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4198 .vreg_list = sm8550_qmp_phy_vreg_l, 4199 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 4200 .regs = pciephy_v6_regs_layout, 4201 4202 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4203 .phy_status = PHYSTATUS_4_20, 4204 4205 /* 20MHz PHY AUX Clock */ 4206 .aux_clock_rate = 20000000, 4207 }; 4208 4209 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 4210 .lanes = 2, 4211 .offsets = &qmp_pcie_offsets_v5_20, 4212 4213 .tbls = { 4214 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 4215 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 4216 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 4217 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 4218 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl, 4219 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl), 4220 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, 4221 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), 4222 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 4223 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 4224 .pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl, 4225 .pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl), 4226 .ln_shrd = sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl, 4227 .ln_shrd_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl), 4228 4229 }, 4230 4231 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4232 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 4233 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 4234 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 4235 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 4236 }, 4237 4238 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4239 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 4240 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 4241 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 4242 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 4243 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, 4244 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), 4245 }, 4246 4247 .reset_list = sdm845_pciephy_reset_l, 4248 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4249 .vreg_list = qmp_phy_vreg_l, 4250 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4251 .regs = pciephy_v5_regs_layout, 4252 4253 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4254 .phy_status = PHYSTATUS_4_20, 4255 }; 4256 4257 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { 4258 .lanes = 4, 4259 .offsets = &qmp_pcie_offsets_v5_30, 4260 4261 .tbls = { 4262 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, 4263 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), 4264 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 4265 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 4266 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl, 4267 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl), 4268 .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, 4269 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), 4270 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 4271 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 4272 }, 4273 4274 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 4275 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, 4276 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), 4277 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 4278 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 4279 }, 4280 4281 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 4282 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 4283 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 4284 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 4285 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 4286 }, 4287 4288 .reset_list = sdm845_pciephy_reset_l, 4289 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4290 .vreg_list = qmp_phy_vreg_l, 4291 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4292 .regs = pciephy_v5_regs_layout, 4293 4294 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4295 .phy_status = PHYSTATUS_4_20, 4296 }; 4297 4298 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { 4299 .lanes = 2, 4300 4301 .offsets = &qmp_pcie_offsets_v6_20, 4302 4303 .tbls = { 4304 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 4305 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 4306 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 4307 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 4308 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 4309 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 4310 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 4311 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 4312 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 4313 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 4314 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 4315 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 4316 }, 4317 4318 .reset_list = sdm845_pciephy_reset_l, 4319 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4320 .vreg_list = qmp_phy_vreg_l, 4321 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4322 .regs = pciephy_v6_regs_layout, 4323 4324 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4325 .phy_status = PHYSTATUS_4_20, 4326 }; 4327 4328 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { 4329 .lanes = 4, 4330 4331 .offsets = &qmp_pcie_offsets_v6_20, 4332 4333 .tbls = { 4334 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 4335 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 4336 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 4337 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 4338 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 4339 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 4340 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 4341 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 4342 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 4343 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 4344 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 4345 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 4346 }, 4347 4348 .serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl, 4349 .serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl), 4350 4351 .reset_list = sdm845_pciephy_reset_l, 4352 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4353 .vreg_list = qmp_phy_vreg_l, 4354 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4355 .regs = pciephy_v6_regs_layout, 4356 4357 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4358 .phy_status = PHYSTATUS_4_20, 4359 }; 4360 4361 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { 4362 .lanes = 8, 4363 4364 .offsets = &qmp_pcie_offsets_v6_30, 4365 .tbls = { 4366 .serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl, 4367 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl), 4368 .rx = x1e80100_qmp_gen4x8_pcie_rx_tbl, 4369 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl), 4370 .txz = x1e80100_qmp_gen4x8_pcie_txz_tbl, 4371 .txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl), 4372 .rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl, 4373 .rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl), 4374 .pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl, 4375 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl), 4376 .pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl, 4377 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl), 4378 .ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl, 4379 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl), 4380 }, 4381 4382 .reset_list = sdm845_pciephy_reset_l, 4383 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4384 .vreg_list = qmp_phy_vreg_l, 4385 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4386 .regs = pciephy_v6_regs_layout, 4387 4388 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4389 .phy_status = PHYSTATUS_4_20, 4390 }; 4391 4392 static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = { 4393 .lanes = 4, 4394 4395 .offsets = &qmp_pcie_offsets_v6_20, 4396 4397 .reset_list = sdm845_pciephy_reset_l, 4398 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 4399 .vreg_list = qmp_phy_vreg_l, 4400 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 4401 .regs = pciephy_v6_regs_layout, 4402 4403 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 4404 .phy_status = PHYSTATUS_4_20, 4405 }; 4406 4407 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 4408 { 4409 const struct qmp_phy_cfg *cfg = qmp->cfg; 4410 const struct qmp_pcie_offsets *offs = cfg->offsets; 4411 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; 4412 4413 serdes = qmp->port_b + offs->serdes; 4414 tx3 = qmp->port_b + offs->tx; 4415 rx3 = qmp->port_b + offs->rx; 4416 tx4 = qmp->port_b + offs->tx2; 4417 rx4 = qmp->port_b + offs->rx2; 4418 pcs = qmp->port_b + offs->pcs; 4419 pcs_misc = qmp->port_b + offs->pcs_misc; 4420 ln_shrd = qmp->port_b + offs->ln_shrd; 4421 4422 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 4423 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 4424 4425 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); 4426 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); 4427 4428 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); 4429 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); 4430 4431 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 4432 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 4433 4434 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 4435 } 4436 4437 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 4438 { 4439 const struct qmp_phy_cfg *cfg = qmp->cfg; 4440 void __iomem *serdes = qmp->serdes; 4441 void __iomem *tx = qmp->tx; 4442 void __iomem *rx = qmp->rx; 4443 void __iomem *tx2 = qmp->tx2; 4444 void __iomem *rx2 = qmp->rx2; 4445 void __iomem *pcs = qmp->pcs; 4446 void __iomem *pcs_misc = qmp->pcs_misc; 4447 void __iomem *pcs_lane1 = qmp->pcs_lane1; 4448 void __iomem *ln_shrd = qmp->ln_shrd; 4449 4450 if (!tbls) 4451 return; 4452 4453 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 4454 4455 /* 4456 * Tx/Rx registers that require different settings than 4457 * txz/rxz must be programmed after txz/rxz. 4458 */ 4459 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); 4460 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); 4461 4462 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 4463 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 4464 4465 if (cfg->lanes >= 2) { 4466 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); 4467 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); 4468 } 4469 4470 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 4471 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 4472 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); 4473 4474 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 4475 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, 4476 cfg->serdes_4ln_num); 4477 qmp_pcie_init_port_b(qmp, tbls); 4478 } 4479 4480 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 4481 } 4482 4483 static int qmp_pcie_init(struct phy *phy) 4484 { 4485 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4486 const struct qmp_phy_cfg *cfg = qmp->cfg; 4487 void __iomem *pcs = qmp->pcs; 4488 bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL])); 4489 int ret; 4490 4491 qmp->skip_init = qmp->nocsr_reset && phy_initialized; 4492 /* 4493 * We need to check the existence of init sequences in two cases: 4494 * 1. The PHY doesn't support no_csr reset. 4495 * 2. The PHY supports no_csr reset but isn't initialized by bootloader. 4496 * As we can't skip init in these two cases. 4497 */ 4498 if (!qmp->skip_init && !cfg->tbls.serdes_num) { 4499 dev_err(qmp->dev, "Init sequence not available\n"); 4500 return -ENODATA; 4501 } 4502 4503 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 4504 if (ret) { 4505 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 4506 return ret; 4507 } 4508 4509 /* 4510 * Toggle BCR reset for PHY that doesn't support no_csr reset or has not 4511 * been initialized. 4512 */ 4513 if (!qmp->skip_init) { 4514 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4515 if (ret) { 4516 dev_err(qmp->dev, "reset assert failed\n"); 4517 goto err_disable_regulators; 4518 } 4519 } 4520 4521 ret = reset_control_assert(qmp->nocsr_reset); 4522 if (ret) { 4523 dev_err(qmp->dev, "no-csr reset assert failed\n"); 4524 goto err_assert_reset; 4525 } 4526 4527 usleep_range(200, 300); 4528 4529 if (!qmp->skip_init) { 4530 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 4531 if (ret) { 4532 dev_err(qmp->dev, "reset deassert failed\n"); 4533 goto err_assert_reset; 4534 } 4535 } 4536 4537 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 4538 if (ret) 4539 goto err_assert_reset; 4540 4541 return 0; 4542 4543 err_assert_reset: 4544 if (!qmp->skip_init) 4545 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4546 err_disable_regulators: 4547 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4548 4549 return ret; 4550 } 4551 4552 static int qmp_pcie_exit(struct phy *phy) 4553 { 4554 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4555 const struct qmp_phy_cfg *cfg = qmp->cfg; 4556 4557 if (qmp->nocsr_reset) 4558 reset_control_assert(qmp->nocsr_reset); 4559 else 4560 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4561 4562 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 4563 4564 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4565 4566 return 0; 4567 } 4568 4569 static int qmp_pcie_power_on(struct phy *phy) 4570 { 4571 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4572 const struct qmp_phy_cfg *cfg = qmp->cfg; 4573 const struct qmp_phy_cfg_tbls *mode_tbls; 4574 void __iomem *pcs = qmp->pcs; 4575 void __iomem *status; 4576 unsigned int mask, val; 4577 int ret; 4578 4579 /* 4580 * Write CSR register for PHY that doesn't support no_csr reset or has not 4581 * been initialized. 4582 */ 4583 if (qmp->skip_init) 4584 goto skip_tbls_init; 4585 4586 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4587 cfg->pwrdn_ctrl); 4588 4589 if (qmp->mode == PHY_MODE_PCIE_RC) 4590 mode_tbls = cfg->tbls_rc; 4591 else 4592 mode_tbls = cfg->tbls_ep; 4593 4594 qmp_pcie_init_registers(qmp, &cfg->tbls); 4595 qmp_pcie_init_registers(qmp, mode_tbls); 4596 4597 skip_tbls_init: 4598 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 4599 if (ret) 4600 return ret; 4601 4602 ret = reset_control_deassert(qmp->nocsr_reset); 4603 if (ret) { 4604 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 4605 goto err_disable_pipe_clk; 4606 } 4607 4608 if (qmp->skip_init) 4609 goto skip_serdes_start; 4610 4611 /* Pull PHY out of reset state */ 4612 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4613 4614 /* start SerDes and Phy-Coding-Sublayer */ 4615 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 4616 4617 if (!cfg->skip_start_delay) 4618 usleep_range(1000, 1200); 4619 4620 skip_serdes_start: 4621 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 4622 mask = cfg->phy_status; 4623 ret = readl_poll_timeout(status, val, !(val & mask), 200, 4624 PHY_INIT_COMPLETE_TIMEOUT); 4625 if (ret) { 4626 dev_err(qmp->dev, "phy initialization timed-out\n"); 4627 goto err_disable_pipe_clk; 4628 } 4629 4630 return 0; 4631 4632 err_disable_pipe_clk: 4633 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 4634 4635 return ret; 4636 } 4637 4638 static int qmp_pcie_power_off(struct phy *phy) 4639 { 4640 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4641 const struct qmp_phy_cfg *cfg = qmp->cfg; 4642 4643 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 4644 4645 /* 4646 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In 4647 * this way, no matter whether the PHY settings were initially programmed by 4648 * bootloader or PHY driver itself, we can reuse them when PHY is powered on 4649 * next time. 4650 */ 4651 if (qmp->nocsr_reset) 4652 goto skip_phy_deinit; 4653 4654 /* PHY reset */ 4655 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4656 4657 /* stop SerDes and Phy-Coding-Sublayer */ 4658 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 4659 SERDES_START | PCS_START); 4660 4661 /* Put PHY into POWER DOWN state: active low */ 4662 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4663 cfg->pwrdn_ctrl); 4664 4665 skip_phy_deinit: 4666 return 0; 4667 } 4668 4669 static int qmp_pcie_enable(struct phy *phy) 4670 { 4671 int ret; 4672 4673 ret = qmp_pcie_init(phy); 4674 if (ret) 4675 return ret; 4676 4677 ret = qmp_pcie_power_on(phy); 4678 if (ret) 4679 qmp_pcie_exit(phy); 4680 4681 return ret; 4682 } 4683 4684 static int qmp_pcie_disable(struct phy *phy) 4685 { 4686 int ret; 4687 4688 ret = qmp_pcie_power_off(phy); 4689 if (ret) 4690 return ret; 4691 4692 return qmp_pcie_exit(phy); 4693 } 4694 4695 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 4696 { 4697 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4698 4699 switch (submode) { 4700 case PHY_MODE_PCIE_RC: 4701 case PHY_MODE_PCIE_EP: 4702 qmp->mode = submode; 4703 break; 4704 default: 4705 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 4706 return -EINVAL; 4707 } 4708 4709 return 0; 4710 } 4711 4712 static const struct phy_ops qmp_pcie_phy_ops = { 4713 .power_on = qmp_pcie_enable, 4714 .power_off = qmp_pcie_disable, 4715 .set_mode = qmp_pcie_set_mode, 4716 .owner = THIS_MODULE, 4717 }; 4718 4719 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 4720 { 4721 const struct qmp_phy_cfg *cfg = qmp->cfg; 4722 struct device *dev = qmp->dev; 4723 int num = cfg->num_vregs; 4724 int i; 4725 4726 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 4727 if (!qmp->vregs) 4728 return -ENOMEM; 4729 4730 for (i = 0; i < num; i++) 4731 qmp->vregs[i].supply = cfg->vreg_list[i]; 4732 4733 return devm_regulator_bulk_get(dev, num, qmp->vregs); 4734 } 4735 4736 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 4737 { 4738 const struct qmp_phy_cfg *cfg = qmp->cfg; 4739 struct device *dev = qmp->dev; 4740 int i; 4741 int ret; 4742 4743 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 4744 sizeof(*qmp->resets), GFP_KERNEL); 4745 if (!qmp->resets) 4746 return -ENOMEM; 4747 4748 for (i = 0; i < cfg->num_resets; i++) 4749 qmp->resets[i].id = cfg->reset_list[i]; 4750 4751 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 4752 if (ret) 4753 return dev_err_probe(dev, ret, "failed to get resets\n"); 4754 4755 qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr"); 4756 if (IS_ERR(qmp->nocsr_reset)) 4757 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 4758 "failed to get no-csr reset\n"); 4759 4760 return 0; 4761 } 4762 4763 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 4764 { 4765 struct device *dev = qmp->dev; 4766 int num = ARRAY_SIZE(qmp_pciephy_clk_l); 4767 int i; 4768 4769 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 4770 if (!qmp->clks) 4771 return -ENOMEM; 4772 4773 for (i = 0; i < num; i++) 4774 qmp->clks[i].id = qmp_pciephy_clk_l[i]; 4775 4776 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 4777 } 4778 4779 static void phy_clk_release_provider(void *res) 4780 { 4781 of_clk_del_provider(res); 4782 } 4783 4784 /* 4785 * Register a fixed rate pipe clock. 4786 * 4787 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 4788 * controls it. The <s>_pipe_clk coming out of the GCC is requested 4789 * by the PHY driver for its operations. 4790 * We register the <s>_pipe_clksrc here. The gcc driver takes care 4791 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 4792 * Below picture shows this relationship. 4793 * 4794 * +---------------+ 4795 * | PHY block |<<---------------------------------------+ 4796 * | | | 4797 * | +-------+ | +-----+ | 4798 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 4799 * clk | +-------+ | +-----+ 4800 * +---------------+ 4801 */ 4802 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 4803 { 4804 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 4805 struct clk_init_data init = { }; 4806 int ret; 4807 4808 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); 4809 if (ret) { 4810 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 4811 return ret; 4812 } 4813 4814 init.ops = &clk_fixed_rate_ops; 4815 4816 /* 4817 * Controllers using QMP PHY-s use 125MHz pipe clock interface 4818 * unless other frequency is specified in the PHY config. 4819 */ 4820 if (qmp->cfg->pipe_clock_rate) 4821 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 4822 else 4823 fixed->fixed_rate = 125000000; 4824 4825 fixed->hw.init = &init; 4826 4827 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4828 } 4829 4830 /* 4831 * Register a fixed rate PHY aux clock. 4832 * 4833 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate 4834 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested 4835 * by the PHY driver for its operations. 4836 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care 4837 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk. 4838 * Below picture shows this relationship. 4839 * 4840 * +---------------+ 4841 * | PHY block |<<---------------------------------------------+ 4842 * | | | 4843 * | +-------+ | +-----+ | 4844 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ 4845 * clk | +-------+ | +-----+ 4846 * +---------------+ 4847 */ 4848 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) 4849 { 4850 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; 4851 struct clk_init_data init = { }; 4852 char name[64]; 4853 4854 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); 4855 4856 init.name = name; 4857 init.ops = &clk_fixed_rate_ops; 4858 4859 fixed->fixed_rate = qmp->cfg->aux_clock_rate; 4860 fixed->hw.init = &init; 4861 4862 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4863 } 4864 4865 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) 4866 { 4867 struct qmp_pcie *qmp = data; 4868 4869 /* Support legacy bindings */ 4870 if (!clkspec->args_count) 4871 return &qmp->pipe_clk_fixed.hw; 4872 4873 switch (clkspec->args[0]) { 4874 case QMP_PCIE_PIPE_CLK: 4875 return &qmp->pipe_clk_fixed.hw; 4876 case QMP_PCIE_PHY_AUX_CLK: 4877 return &qmp->aux_clk_fixed.hw; 4878 } 4879 4880 return ERR_PTR(-EINVAL); 4881 } 4882 4883 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) 4884 { 4885 int ret; 4886 4887 ret = phy_pipe_clk_register(qmp, np); 4888 if (ret) 4889 return ret; 4890 4891 if (qmp->cfg->aux_clock_rate) { 4892 ret = phy_aux_clk_register(qmp, np); 4893 if (ret) 4894 return ret; 4895 4896 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp); 4897 if (ret) 4898 return ret; 4899 } else { 4900 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); 4901 if (ret) 4902 return ret; 4903 } 4904 4905 /* 4906 * Roll a devm action because the clock provider is the child node, but 4907 * the child node is not actually a device. 4908 */ 4909 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 4910 } 4911 4912 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 4913 { 4914 struct platform_device *pdev = to_platform_device(qmp->dev); 4915 const struct qmp_phy_cfg *cfg = qmp->cfg; 4916 struct device *dev = qmp->dev; 4917 struct clk *clk; 4918 4919 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 4920 if (IS_ERR(qmp->serdes)) 4921 return PTR_ERR(qmp->serdes); 4922 4923 /* 4924 * Get memory resources for the PHY: 4925 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 4926 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 4927 * For single lane PHYs: pcs_misc (optional) -> 3. 4928 */ 4929 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 4930 if (IS_ERR(qmp->tx)) 4931 return PTR_ERR(qmp->tx); 4932 4933 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 4934 qmp->rx = qmp->tx; 4935 else 4936 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 4937 if (IS_ERR(qmp->rx)) 4938 return PTR_ERR(qmp->rx); 4939 4940 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 4941 if (IS_ERR(qmp->pcs)) 4942 return PTR_ERR(qmp->pcs); 4943 4944 if (cfg->lanes >= 2) { 4945 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 4946 if (IS_ERR(qmp->tx2)) 4947 return PTR_ERR(qmp->tx2); 4948 4949 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 4950 if (IS_ERR(qmp->rx2)) 4951 return PTR_ERR(qmp->rx2); 4952 4953 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 4954 } else { 4955 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 4956 } 4957 4958 if (IS_ERR(qmp->pcs_misc) && 4959 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 4960 qmp->pcs_misc = qmp->pcs + 0x400; 4961 4962 if (IS_ERR(qmp->pcs_misc)) { 4963 if (cfg->tbls.pcs_misc || 4964 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 4965 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 4966 return PTR_ERR(qmp->pcs_misc); 4967 } 4968 } 4969 4970 /* 4971 * For all platforms where legacy bindings existed, PCS_LANE1 was 4972 * mapped as a part of the PCS_MISC region. 4973 */ 4974 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) 4975 qmp->pcs_lane1 = qmp->pcs_misc + 4976 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); 4977 4978 clk = devm_get_clk_from_child(dev, np, NULL); 4979 if (IS_ERR(clk)) { 4980 return dev_err_probe(dev, PTR_ERR(clk), 4981 "failed to get pipe clock\n"); 4982 } 4983 4984 qmp->num_pipe_clks = 1; 4985 qmp->pipe_clks[0].id = "pipe"; 4986 qmp->pipe_clks[0].clk = clk; 4987 4988 return 0; 4989 } 4990 4991 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 4992 { 4993 struct regmap *tcsr; 4994 unsigned int args[2]; 4995 int ret; 4996 4997 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 4998 "qcom,4ln-config-sel", 4999 ARRAY_SIZE(args), args); 5000 if (IS_ERR(tcsr)) { 5001 ret = PTR_ERR(tcsr); 5002 if (ret == -ENOENT) 5003 return 0; 5004 5005 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 5006 return ret; 5007 } 5008 5009 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 5010 if (ret < 0) { 5011 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 5012 return ret; 5013 } 5014 5015 qmp->tcsr_4ln_config = ret; 5016 5017 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 5018 5019 return 0; 5020 } 5021 5022 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 5023 { 5024 struct platform_device *pdev = to_platform_device(qmp->dev); 5025 const struct qmp_phy_cfg *cfg = qmp->cfg; 5026 const struct qmp_pcie_offsets *offs = cfg->offsets; 5027 struct device *dev = qmp->dev; 5028 void __iomem *base; 5029 int ret; 5030 5031 if (!offs) 5032 return -EINVAL; 5033 5034 ret = qmp_pcie_get_4ln_config(qmp); 5035 if (ret) 5036 return ret; 5037 5038 base = devm_platform_ioremap_resource(pdev, 0); 5039 if (IS_ERR(base)) 5040 return PTR_ERR(base); 5041 5042 qmp->serdes = base + offs->serdes; 5043 qmp->pcs = base + offs->pcs; 5044 qmp->pcs_misc = base + offs->pcs_misc; 5045 qmp->pcs_lane1 = base + offs->pcs_lane1; 5046 qmp->tx = base + offs->tx; 5047 qmp->rx = base + offs->rx; 5048 5049 if (cfg->lanes >= 2) { 5050 qmp->tx2 = base + offs->tx2; 5051 qmp->rx2 = base + offs->rx2; 5052 } 5053 5054 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 5055 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 5056 if (IS_ERR(qmp->port_b)) 5057 return PTR_ERR(qmp->port_b); 5058 } 5059 5060 qmp->txz = base + offs->txz; 5061 qmp->rxz = base + offs->rxz; 5062 5063 if (cfg->tbls.ln_shrd) 5064 qmp->ln_shrd = base + offs->ln_shrd; 5065 5066 qmp->num_pipe_clks = 2; 5067 qmp->pipe_clks[0].id = "pipe"; 5068 qmp->pipe_clks[1].id = "pipediv2"; 5069 5070 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 5071 if (ret) 5072 return ret; 5073 5074 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 5075 if (ret) 5076 return ret; 5077 5078 return 0; 5079 } 5080 5081 static int qmp_pcie_probe(struct platform_device *pdev) 5082 { 5083 struct device *dev = &pdev->dev; 5084 struct phy_provider *phy_provider; 5085 struct device_node *np; 5086 struct qmp_pcie *qmp; 5087 int ret; 5088 5089 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 5090 if (!qmp) 5091 return -ENOMEM; 5092 5093 qmp->dev = dev; 5094 5095 qmp->cfg = of_device_get_match_data(dev); 5096 if (!qmp->cfg) 5097 return -EINVAL; 5098 5099 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 5100 WARN_ON_ONCE(!qmp->cfg->phy_status); 5101 5102 ret = qmp_pcie_clk_init(qmp); 5103 if (ret) 5104 return ret; 5105 5106 ret = qmp_pcie_reset_init(qmp); 5107 if (ret) 5108 return ret; 5109 5110 ret = qmp_pcie_vreg_init(qmp); 5111 if (ret) 5112 return ret; 5113 5114 /* Check for legacy binding with child node. */ 5115 np = of_get_next_available_child(dev->of_node, NULL); 5116 if (np) { 5117 ret = qmp_pcie_parse_dt_legacy(qmp, np); 5118 } else { 5119 np = of_node_get(dev->of_node); 5120 ret = qmp_pcie_parse_dt(qmp); 5121 } 5122 if (ret) 5123 goto err_node_put; 5124 5125 ret = qmp_pcie_register_clocks(qmp, np); 5126 if (ret) 5127 goto err_node_put; 5128 5129 qmp->mode = PHY_MODE_PCIE_RC; 5130 5131 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 5132 if (IS_ERR(qmp->phy)) { 5133 ret = PTR_ERR(qmp->phy); 5134 dev_err(dev, "failed to create PHY: %d\n", ret); 5135 goto err_node_put; 5136 } 5137 5138 phy_set_drvdata(qmp->phy, qmp); 5139 5140 of_node_put(np); 5141 5142 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 5143 5144 return PTR_ERR_OR_ZERO(phy_provider); 5145 5146 err_node_put: 5147 of_node_put(np); 5148 return ret; 5149 } 5150 5151 static const struct of_device_id qmp_pcie_of_match_table[] = { 5152 { 5153 .compatible = "qcom,ipq6018-qmp-pcie-phy", 5154 .data = &ipq6018_pciephy_cfg, 5155 }, { 5156 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 5157 .data = &ipq8074_pciephy_gen3_cfg, 5158 }, { 5159 .compatible = "qcom,ipq8074-qmp-pcie-phy", 5160 .data = &ipq8074_pciephy_cfg, 5161 }, { 5162 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy", 5163 .data = &ipq9574_gen3x1_pciephy_cfg, 5164 }, { 5165 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", 5166 .data = &ipq9574_gen3x2_pciephy_cfg, 5167 }, { 5168 .compatible = "qcom,msm8998-qmp-pcie-phy", 5169 .data = &msm8998_pciephy_cfg, 5170 }, { 5171 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy", 5172 .data = &qcs615_pciephy_cfg, 5173 }, { 5174 .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy", 5175 .data = &qcs8300_qmp_gen4x2_pciephy_cfg, 5176 }, { 5177 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", 5178 .data = &sa8775p_qmp_gen4x2_pciephy_cfg, 5179 }, { 5180 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy", 5181 .data = &sa8775p_qmp_gen4x4_pciephy_cfg, 5182 }, { 5183 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy", 5184 .data = &sar2130p_qmp_gen3x2_pciephy_cfg, 5185 }, { 5186 .compatible = "qcom,sc8180x-qmp-pcie-phy", 5187 .data = &sc8180x_pciephy_cfg, 5188 }, { 5189 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 5190 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 5191 }, { 5192 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 5193 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 5194 }, { 5195 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 5196 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 5197 }, { 5198 .compatible = "qcom,sdm845-qhp-pcie-phy", 5199 .data = &sdm845_qhp_pciephy_cfg, 5200 }, { 5201 .compatible = "qcom,sdm845-qmp-pcie-phy", 5202 .data = &sdm845_qmp_pciephy_cfg, 5203 }, { 5204 .compatible = "qcom,sdx55-qmp-pcie-phy", 5205 .data = &sdx55_qmp_pciephy_cfg, 5206 }, { 5207 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 5208 .data = &sdx65_qmp_pciephy_cfg, 5209 }, { 5210 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy", 5211 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 5212 }, { 5213 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy", 5214 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 5215 }, { 5216 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 5217 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 5218 }, { 5219 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 5220 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 5221 }, { 5222 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 5223 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 5224 }, { 5225 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 5226 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 5227 }, { 5228 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 5229 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 5230 }, { 5231 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 5232 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 5233 }, { 5234 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 5235 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 5236 }, { 5237 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 5238 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 5239 }, { 5240 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 5241 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 5242 }, { 5243 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 5244 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 5245 }, { 5246 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 5247 .data = &sm8650_qmp_gen4x2_pciephy_cfg, 5248 }, { 5249 .compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy", 5250 .data = &sm8750_qmp_gen3x2_pciephy_cfg, 5251 }, { 5252 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", 5253 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 5254 }, { 5255 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", 5256 .data = &x1e80100_qmp_gen4x2_pciephy_cfg, 5257 }, { 5258 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy", 5259 .data = &x1e80100_qmp_gen4x4_pciephy_cfg, 5260 }, { 5261 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy", 5262 .data = &x1e80100_qmp_gen4x8_pciephy_cfg, 5263 }, { 5264 .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy", 5265 .data = &qmp_v6_gen4x4_pciephy_cfg, 5266 }, 5267 { }, 5268 }; 5269 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 5270 5271 static struct platform_driver qmp_pcie_driver = { 5272 .probe = qmp_pcie_probe, 5273 .driver = { 5274 .name = "qcom-qmp-pcie-phy", 5275 .of_match_table = qmp_pcie_of_match_table, 5276 }, 5277 }; 5278 5279 module_platform_driver(qmp_pcie_driver); 5280 5281 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 5282 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 5283 MODULE_LICENSE("GPL v2"); 5284