1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include "phy-qcom-qmp.h" 27 #include "phy-qcom-qmp-pcs-misc-v3.h" 28 #include "phy-qcom-qmp-pcs-pcie-v4.h" 29 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 30 #include "phy-qcom-qmp-pcs-pcie-v5.h" 31 #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 32 #include "phy-qcom-qmp-pcs-pcie-v6.h" 33 #include "phy-qcom-qmp-pcs-pcie-v6_20.h" 34 #include "phy-qcom-qmp-pcie-qhp.h" 35 36 /* QPHY_SW_RESET bit */ 37 #define SW_RESET BIT(0) 38 /* QPHY_POWER_DOWN_CONTROL */ 39 #define SW_PWRDN BIT(0) 40 #define REFCLK_DRV_DSBL BIT(1) 41 /* QPHY_START_CONTROL bits */ 42 #define SERDES_START BIT(0) 43 #define PCS_START BIT(1) 44 /* QPHY_PCS_STATUS bit */ 45 #define PHYSTATUS BIT(6) 46 #define PHYSTATUS_4_20 BIT(7) 47 48 #define PHY_INIT_COMPLETE_TIMEOUT 10000 49 50 struct qmp_phy_init_tbl { 51 unsigned int offset; 52 unsigned int val; 53 /* 54 * mask of lanes for which this register is written 55 * for cases when second lane needs different values 56 */ 57 u8 lane_mask; 58 }; 59 60 #define QMP_PHY_INIT_CFG(o, v) \ 61 { \ 62 .offset = o, \ 63 .val = v, \ 64 .lane_mask = 0xff, \ 65 } 66 67 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 68 { \ 69 .offset = o, \ 70 .val = v, \ 71 .lane_mask = l, \ 72 } 73 74 /* set of registers with offsets different per-PHY */ 75 enum qphy_reg_layout { 76 /* PCS registers */ 77 QPHY_SW_RESET, 78 QPHY_START_CTRL, 79 QPHY_PCS_STATUS, 80 QPHY_PCS_POWER_DOWN_CONTROL, 81 /* Keep last to ensure regs_layout arrays are properly initialized */ 82 QPHY_LAYOUT_SIZE 83 }; 84 85 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 86 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 87 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 88 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 89 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 90 }; 91 92 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 93 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 94 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 95 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 96 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 97 }; 98 99 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 100 [QPHY_SW_RESET] = 0x00, 101 [QPHY_START_CTRL] = 0x08, 102 [QPHY_PCS_STATUS] = 0x2ac, 103 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 104 }; 105 106 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 107 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 108 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 109 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 110 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 111 }; 112 113 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 114 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 115 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 116 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 118 }; 119 120 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 163 }; 164 165 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 170 }; 171 172 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 181 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 182 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 187 }; 188 189 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 200 }; 201 202 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 203 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 243 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 244 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 245 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 247 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 248 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 249 }; 250 251 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 252 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 253 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 254 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 255 }; 256 257 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 288 }; 289 290 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 292 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 298 }; 299 300 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 304 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 305 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 308 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 309 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 310 }; 311 312 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 313 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 314 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 315 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 316 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 317 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 318 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 319 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 320 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 321 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 322 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 323 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 324 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 325 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 326 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 327 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 328 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 329 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 330 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 331 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 332 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 333 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 334 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 335 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 336 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 337 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 339 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 340 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 341 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 342 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 343 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 344 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 346 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 349 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 352 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 353 }; 354 355 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 356 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 357 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 358 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 359 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 360 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 361 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 362 }; 363 364 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 365 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 366 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 367 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 368 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 369 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 370 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 371 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 372 }; 373 374 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 378 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 379 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 380 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 381 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 382 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 383 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 384 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 385 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 386 }; 387 388 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 389 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 440 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 441 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 442 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 443 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 444 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 445 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 446 }; 447 448 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 449 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 450 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 451 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 452 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 453 }; 454 455 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 486 }; 487 488 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 500 }; 501 502 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 516 }; 517 518 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 561 }; 562 563 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 564 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 565 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 566 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 567 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 568 }; 569 570 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 587 }; 588 589 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 591 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 597 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 605 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 609 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 611 }; 612 613 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 619 }; 620 621 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 667 }; 668 669 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 726 }; 727 728 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 729 }; 730 731 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 735 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 736 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 737 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 738 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 739 }; 740 741 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 784 }; 785 786 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 787 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 788 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 789 }; 790 791 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 828 }; 829 830 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 836 }; 837 838 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 842 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 843 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 844 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 845 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 846 }; 847 848 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 883 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 884 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 885 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 886 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 887 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 888 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 889 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 890 }; 891 892 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 893 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 894 }; 895 896 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 897 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 898 }; 899 900 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 901 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 902 }; 903 904 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 905 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 906 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 907 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 908 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 909 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 910 }; 911 912 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 923 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 924 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 925 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 926 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 928 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 929 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 930 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 931 }; 932 933 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 934 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 935 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 936 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 937 }; 938 939 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 940 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 941 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 942 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 943 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 944 }; 945 946 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 947 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 948 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 949 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 950 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 951 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 952 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 953 }; 954 955 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 958 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 959 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 960 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 961 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 962 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 963 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 964 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 965 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 966 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 967 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 968 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 969 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 970 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 971 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 972 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 973 }; 974 975 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 976 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 977 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 978 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 979 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 980 }; 981 982 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 983 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 984 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 985 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 986 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 987 }; 988 989 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1031 }; 1032 1033 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1035 }; 1036 1037 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1038 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1041 }; 1042 1043 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1074 }; 1075 1076 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1077 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1078 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1079 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1080 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1081 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1082 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1083 }; 1084 1085 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1086 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1087 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1088 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1089 }; 1090 1091 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1092 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1094 }; 1095 1096 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1097 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1098 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1100 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1101 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1102 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1103 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1104 }; 1105 1106 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1107 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1108 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1109 }; 1110 1111 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1112 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1113 }; 1114 1115 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1116 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1117 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1118 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1119 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1120 }; 1121 1122 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1123 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1124 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1125 }; 1126 1127 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1128 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1129 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1130 }; 1131 1132 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1147 }; 1148 1149 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1166 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1167 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1168 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1169 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1172 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1173 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1174 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1175 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1176 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1177 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1178 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1179 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1180 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1181 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1182 }; 1183 1184 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1185 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1186 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1187 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1188 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1189 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1190 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1191 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1192 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1193 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1194 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1195 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1196 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1197 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1198 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1199 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1200 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1201 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1202 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1203 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1204 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1205 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1206 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1207 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1208 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1209 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1210 }; 1211 1212 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1213 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1214 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1215 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1216 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1217 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1218 }; 1219 1220 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1221 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1222 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1223 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1224 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1225 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1226 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1227 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1228 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1229 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1230 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1231 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1232 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1233 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1234 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1235 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1236 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1237 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1238 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1239 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1240 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1241 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1242 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1243 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1244 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1245 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1246 }; 1247 1248 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1249 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1250 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1251 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1252 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1253 }; 1254 1255 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1256 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1257 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1258 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1259 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1260 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1261 }; 1262 1263 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1264 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1265 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1266 }; 1267 1268 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { 1269 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1270 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1271 }; 1272 1273 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 1274 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1315 }; 1316 1317 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1319 }; 1320 1321 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1322 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1327 }; 1328 1329 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 1330 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1344 }; 1345 1346 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1347 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1355 }; 1356 1357 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 1358 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1359 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1360 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1361 }; 1362 1363 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1364 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1365 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1366 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1367 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1368 }; 1369 1370 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 1371 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1376 }; 1377 1378 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1383 }; 1384 1385 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 1386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1388 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1389 }; 1390 1391 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 1392 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1393 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1394 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1395 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1396 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1398 }; 1399 1400 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 1401 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 1402 }; 1403 1404 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1405 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1409 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1410 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1412 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1413 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1414 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1415 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1416 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1417 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1418 }; 1419 1420 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1421 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1422 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1423 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1424 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1425 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1426 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1427 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1428 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1429 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1430 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1431 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1432 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1433 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1434 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1445 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1446 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1447 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1448 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1449 }; 1450 1451 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1452 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1453 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1454 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1455 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1456 }; 1457 1458 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1459 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1460 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1461 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1462 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1463 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1464 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1465 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1466 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1467 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1468 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1469 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1470 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1471 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1472 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1473 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1474 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1475 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1476 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1477 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1478 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1479 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1480 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1481 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1482 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1483 1484 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1485 1486 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1487 1488 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1489 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1490 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1491 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1492 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1493 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1494 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1495 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1496 1497 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1498 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1499 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1500 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1501 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1502 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1503 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1504 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1505 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1506 }; 1507 1508 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1509 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1510 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1511 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1512 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 1513 }; 1514 1515 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1516 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1517 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1518 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1519 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1520 }; 1521 1522 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1523 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1524 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1525 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1526 }; 1527 1528 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1529 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1530 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1531 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1532 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1533 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1534 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1535 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1536 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1537 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1538 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1539 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1540 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1541 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1547 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1548 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1549 }; 1550 1551 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1552 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1553 }; 1554 1555 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 1556 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1557 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1558 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1559 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1560 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1561 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 1562 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1563 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1564 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1565 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1566 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1567 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1568 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1569 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1570 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1571 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1572 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1573 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1574 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 1575 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1576 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1577 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1578 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1579 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1580 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 1581 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1582 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1583 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1584 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1585 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1586 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 1587 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1588 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1589 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1590 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1591 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 1592 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 1593 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1594 }; 1595 1596 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 1597 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 1598 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 1599 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 1600 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 1601 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 1602 }; 1603 1604 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 1605 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1606 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 1607 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 1608 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 1609 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 1610 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 1611 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 1612 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 1613 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 1614 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 1615 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 1616 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 1617 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 1618 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 1619 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 1620 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 1621 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), 1622 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 1623 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 1624 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 1625 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 1626 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 1627 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 1628 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1629 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1630 }; 1631 1632 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 1633 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 1634 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 1635 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 1636 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 1637 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 1638 }; 1639 1640 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1641 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1642 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1643 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1644 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1645 }; 1646 1647 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 1648 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1649 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1650 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1651 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1652 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1653 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1654 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1655 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1656 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1657 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1658 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1659 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1660 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1661 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1662 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1663 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1664 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1665 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1666 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1667 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1668 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1669 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1670 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1671 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1672 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1673 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1674 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1675 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1676 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1677 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1678 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1679 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1680 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1681 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1682 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1683 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1684 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1685 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1686 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1687 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1688 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1689 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1690 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1691 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1692 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1693 }; 1694 1695 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1696 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1697 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe), 1698 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 1699 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), 1700 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), 1701 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1702 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1703 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1704 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1705 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1706 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1707 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1708 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1709 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1710 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1711 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1712 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1713 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1714 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1715 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1716 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1717 }; 1718 1719 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 1720 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1721 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1722 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1723 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 1724 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1725 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1726 }; 1727 1728 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 1729 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 1730 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1731 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1732 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1733 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1734 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1735 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 1736 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1737 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1738 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1739 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1740 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1741 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1742 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 1743 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1744 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1745 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1746 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1747 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1748 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1749 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1750 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 1751 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 1752 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 1753 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1754 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 1755 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1756 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1757 }; 1758 1759 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 1760 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1761 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25), 1762 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1763 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1764 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 1765 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 1766 }; 1767 1768 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1769 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1770 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1771 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1772 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1773 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1774 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1775 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1776 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1777 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1778 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 1779 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 1780 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 1781 }; 1782 1783 struct qmp_pcie_offsets { 1784 u16 serdes; 1785 u16 pcs; 1786 u16 pcs_misc; 1787 u16 tx; 1788 u16 rx; 1789 u16 tx2; 1790 u16 rx2; 1791 u16 ln_shrd; 1792 }; 1793 1794 struct qmp_phy_cfg_tbls { 1795 const struct qmp_phy_init_tbl *serdes; 1796 int serdes_num; 1797 const struct qmp_phy_init_tbl *tx; 1798 int tx_num; 1799 const struct qmp_phy_init_tbl *rx; 1800 int rx_num; 1801 const struct qmp_phy_init_tbl *pcs; 1802 int pcs_num; 1803 const struct qmp_phy_init_tbl *pcs_misc; 1804 int pcs_misc_num; 1805 const struct qmp_phy_init_tbl *ln_shrd; 1806 int ln_shrd_num; 1807 }; 1808 1809 /* struct qmp_phy_cfg - per-PHY initialization config */ 1810 struct qmp_phy_cfg { 1811 int lanes; 1812 1813 const struct qmp_pcie_offsets *offsets; 1814 1815 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1816 const struct qmp_phy_cfg_tbls tbls; 1817 /* 1818 * Additional init sequences for PHY blocks, providing additional 1819 * register programming. They are used for providing separate sequences 1820 * for the Root Complex and End Point use cases. 1821 * 1822 * If EP mode is not supported, both tables can be left unset. 1823 */ 1824 const struct qmp_phy_cfg_tbls *tbls_rc; 1825 const struct qmp_phy_cfg_tbls *tbls_ep; 1826 1827 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 1828 int serdes_4ln_num; 1829 1830 /* clock ids to be requested */ 1831 const char * const *clk_list; 1832 int num_clks; 1833 /* resets to be requested */ 1834 const char * const *reset_list; 1835 int num_resets; 1836 /* regulators to be requested */ 1837 const char * const *vreg_list; 1838 int num_vregs; 1839 1840 /* array of registers with different offsets */ 1841 const unsigned int *regs; 1842 1843 unsigned int pwrdn_ctrl; 1844 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1845 unsigned int phy_status; 1846 1847 bool skip_start_delay; 1848 1849 bool has_nocsr_reset; 1850 1851 /* QMP PHY pipe clock interface rate */ 1852 unsigned long pipe_clock_rate; 1853 }; 1854 1855 struct qmp_pcie { 1856 struct device *dev; 1857 1858 const struct qmp_phy_cfg *cfg; 1859 bool tcsr_4ln_config; 1860 1861 void __iomem *serdes; 1862 void __iomem *pcs; 1863 void __iomem *pcs_misc; 1864 void __iomem *tx; 1865 void __iomem *rx; 1866 void __iomem *tx2; 1867 void __iomem *rx2; 1868 void __iomem *ln_shrd; 1869 1870 void __iomem *port_b; 1871 1872 struct clk_bulk_data *clks; 1873 struct clk_bulk_data pipe_clks[2]; 1874 int num_pipe_clks; 1875 1876 struct reset_control_bulk_data *resets; 1877 struct reset_control *nocsr_reset; 1878 struct regulator_bulk_data *vregs; 1879 1880 struct phy *phy; 1881 int mode; 1882 1883 struct clk_fixed_rate pipe_clk_fixed; 1884 }; 1885 1886 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1887 { 1888 u32 reg; 1889 1890 reg = readl(base + offset); 1891 reg |= val; 1892 writel(reg, base + offset); 1893 1894 /* ensure that above write is through */ 1895 readl(base + offset); 1896 } 1897 1898 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1899 { 1900 u32 reg; 1901 1902 reg = readl(base + offset); 1903 reg &= ~val; 1904 writel(reg, base + offset); 1905 1906 /* ensure that above write is through */ 1907 readl(base + offset); 1908 } 1909 1910 /* list of clocks required by phy */ 1911 static const char * const ipq8074_pciephy_clk_l[] = { 1912 "aux", "cfg_ahb", 1913 }; 1914 1915 static const char * const msm8996_phy_clk_l[] = { 1916 "aux", "cfg_ahb", "ref", 1917 }; 1918 1919 static const char * const sc8280xp_pciephy_clk_l[] = { 1920 "aux", "cfg_ahb", "ref", "rchng", 1921 }; 1922 1923 static const char * const sdm845_pciephy_clk_l[] = { 1924 "aux", "cfg_ahb", "ref", "refgen", 1925 }; 1926 1927 /* list of regulators */ 1928 static const char * const qmp_phy_vreg_l[] = { 1929 "vdda-phy", "vdda-pll", 1930 }; 1931 1932 static const char * const sm8550_qmp_phy_vreg_l[] = { 1933 "vdda-phy", "vdda-pll", "vdda-qref", 1934 }; 1935 1936 /* list of resets */ 1937 static const char * const ipq8074_pciephy_reset_l[] = { 1938 "phy", "common", 1939 }; 1940 1941 static const char * const sdm845_pciephy_reset_l[] = { 1942 "phy", 1943 }; 1944 1945 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 1946 .serdes = 0, 1947 .pcs = 0x0200, 1948 .pcs_misc = 0x0600, 1949 .tx = 0x0e00, 1950 .rx = 0x1000, 1951 .tx2 = 0x1600, 1952 .rx2 = 0x1800, 1953 }; 1954 1955 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 1956 .serdes = 0x1000, 1957 .pcs = 0x1200, 1958 .pcs_misc = 0x1400, 1959 .tx = 0x0000, 1960 .rx = 0x0200, 1961 .tx2 = 0x0800, 1962 .rx2 = 0x0a00, 1963 .ln_shrd = 0x0e00, 1964 }; 1965 1966 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1967 .lanes = 1, 1968 1969 .tbls = { 1970 .serdes = ipq8074_pcie_serdes_tbl, 1971 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1972 .tx = ipq8074_pcie_tx_tbl, 1973 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1974 .rx = ipq8074_pcie_rx_tbl, 1975 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1976 .pcs = ipq8074_pcie_pcs_tbl, 1977 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1978 }, 1979 .clk_list = ipq8074_pciephy_clk_l, 1980 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1981 .reset_list = ipq8074_pciephy_reset_l, 1982 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1983 .vreg_list = NULL, 1984 .num_vregs = 0, 1985 .regs = pciephy_v2_regs_layout, 1986 1987 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1988 .phy_status = PHYSTATUS, 1989 }; 1990 1991 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1992 .lanes = 1, 1993 1994 .tbls = { 1995 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1996 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1997 .tx = ipq8074_pcie_gen3_tx_tbl, 1998 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1999 .rx = ipq8074_pcie_gen3_rx_tbl, 2000 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 2001 .pcs = ipq8074_pcie_gen3_pcs_tbl, 2002 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 2003 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 2004 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 2005 }, 2006 .clk_list = ipq8074_pciephy_clk_l, 2007 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 2008 .reset_list = ipq8074_pciephy_reset_l, 2009 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2010 .vreg_list = NULL, 2011 .num_vregs = 0, 2012 .regs = pciephy_v4_regs_layout, 2013 2014 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2015 .phy_status = PHYSTATUS, 2016 2017 .pipe_clock_rate = 250000000, 2018 }; 2019 2020 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 2021 .lanes = 1, 2022 2023 .tbls = { 2024 .serdes = ipq6018_pcie_serdes_tbl, 2025 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 2026 .tx = ipq6018_pcie_tx_tbl, 2027 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 2028 .rx = ipq6018_pcie_rx_tbl, 2029 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 2030 .pcs = ipq6018_pcie_pcs_tbl, 2031 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 2032 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 2033 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 2034 }, 2035 .clk_list = ipq8074_pciephy_clk_l, 2036 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 2037 .reset_list = ipq8074_pciephy_reset_l, 2038 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2039 .vreg_list = NULL, 2040 .num_vregs = 0, 2041 .regs = pciephy_v4_regs_layout, 2042 2043 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2044 .phy_status = PHYSTATUS, 2045 }; 2046 2047 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 2048 .lanes = 1, 2049 2050 .tbls = { 2051 .serdes = sdm845_qmp_pcie_serdes_tbl, 2052 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 2053 .tx = sdm845_qmp_pcie_tx_tbl, 2054 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 2055 .rx = sdm845_qmp_pcie_rx_tbl, 2056 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 2057 .pcs = sdm845_qmp_pcie_pcs_tbl, 2058 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 2059 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 2060 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 2061 }, 2062 .clk_list = sdm845_pciephy_clk_l, 2063 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2064 .reset_list = sdm845_pciephy_reset_l, 2065 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2066 .vreg_list = qmp_phy_vreg_l, 2067 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2068 .regs = pciephy_v3_regs_layout, 2069 2070 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2071 .phy_status = PHYSTATUS, 2072 }; 2073 2074 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 2075 .lanes = 1, 2076 2077 .tbls = { 2078 .serdes = sdm845_qhp_pcie_serdes_tbl, 2079 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 2080 .tx = sdm845_qhp_pcie_tx_tbl, 2081 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 2082 .rx = sdm845_qhp_pcie_rx_tbl, 2083 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 2084 .pcs = sdm845_qhp_pcie_pcs_tbl, 2085 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 2086 }, 2087 .clk_list = sdm845_pciephy_clk_l, 2088 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2089 .reset_list = sdm845_pciephy_reset_l, 2090 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2091 .vreg_list = qmp_phy_vreg_l, 2092 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2093 .regs = sdm845_qhp_pciephy_regs_layout, 2094 2095 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2096 .phy_status = PHYSTATUS, 2097 }; 2098 2099 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 2100 .lanes = 1, 2101 2102 .tbls = { 2103 .serdes = sm8250_qmp_pcie_serdes_tbl, 2104 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2105 .tx = sm8250_qmp_pcie_tx_tbl, 2106 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2107 .rx = sm8250_qmp_pcie_rx_tbl, 2108 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2109 .pcs = sm8250_qmp_pcie_pcs_tbl, 2110 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2111 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 2112 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2113 }, 2114 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2115 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 2116 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 2117 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 2118 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 2119 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 2120 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 2121 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 2122 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 2123 }, 2124 .clk_list = sdm845_pciephy_clk_l, 2125 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2126 .reset_list = sdm845_pciephy_reset_l, 2127 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2128 .vreg_list = qmp_phy_vreg_l, 2129 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2130 .regs = pciephy_v4_regs_layout, 2131 2132 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2133 .phy_status = PHYSTATUS, 2134 }; 2135 2136 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 2137 .lanes = 2, 2138 2139 .tbls = { 2140 .serdes = sm8250_qmp_pcie_serdes_tbl, 2141 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2142 .tx = sm8250_qmp_pcie_tx_tbl, 2143 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2144 .rx = sm8250_qmp_pcie_rx_tbl, 2145 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2146 .pcs = sm8250_qmp_pcie_pcs_tbl, 2147 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2148 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 2149 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2150 }, 2151 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2152 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 2153 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 2154 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 2155 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 2156 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 2157 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 2158 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 2159 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 2160 }, 2161 .clk_list = sdm845_pciephy_clk_l, 2162 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2163 .reset_list = sdm845_pciephy_reset_l, 2164 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2165 .vreg_list = qmp_phy_vreg_l, 2166 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2167 .regs = pciephy_v4_regs_layout, 2168 2169 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2170 .phy_status = PHYSTATUS, 2171 }; 2172 2173 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 2174 .lanes = 1, 2175 2176 .tbls = { 2177 .serdes = msm8998_pcie_serdes_tbl, 2178 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 2179 .tx = msm8998_pcie_tx_tbl, 2180 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 2181 .rx = msm8998_pcie_rx_tbl, 2182 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 2183 .pcs = msm8998_pcie_pcs_tbl, 2184 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 2185 }, 2186 .clk_list = msm8996_phy_clk_l, 2187 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2188 .reset_list = ipq8074_pciephy_reset_l, 2189 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2190 .vreg_list = qmp_phy_vreg_l, 2191 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2192 .regs = pciephy_v3_regs_layout, 2193 2194 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2195 .phy_status = PHYSTATUS, 2196 2197 .skip_start_delay = true, 2198 }; 2199 2200 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 2201 .lanes = 1, 2202 2203 .tbls = { 2204 .serdes = sc8180x_qmp_pcie_serdes_tbl, 2205 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 2206 .tx = sc8180x_qmp_pcie_tx_tbl, 2207 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 2208 .rx = sc8180x_qmp_pcie_rx_tbl, 2209 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 2210 .pcs = sc8180x_qmp_pcie_pcs_tbl, 2211 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 2212 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 2213 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 2214 }, 2215 .clk_list = sdm845_pciephy_clk_l, 2216 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2217 .reset_list = sdm845_pciephy_reset_l, 2218 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2219 .vreg_list = qmp_phy_vreg_l, 2220 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2221 .regs = pciephy_v4_regs_layout, 2222 2223 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2224 .phy_status = PHYSTATUS, 2225 }; 2226 2227 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 2228 .lanes = 1, 2229 2230 .offsets = &qmp_pcie_offsets_v5, 2231 2232 .tbls = { 2233 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2234 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2235 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 2236 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 2237 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 2238 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 2239 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 2240 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 2241 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 2242 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 2243 }, 2244 2245 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2246 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 2247 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 2248 }, 2249 2250 .clk_list = sc8280xp_pciephy_clk_l, 2251 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2252 .reset_list = sdm845_pciephy_reset_l, 2253 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2254 .vreg_list = qmp_phy_vreg_l, 2255 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2256 .regs = pciephy_v5_regs_layout, 2257 2258 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2259 .phy_status = PHYSTATUS, 2260 }; 2261 2262 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 2263 .lanes = 2, 2264 2265 .offsets = &qmp_pcie_offsets_v5, 2266 2267 .tbls = { 2268 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2269 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2270 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 2271 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 2272 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 2273 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 2274 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 2275 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 2276 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2277 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2278 }, 2279 2280 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2281 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 2282 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 2283 }, 2284 2285 .clk_list = sc8280xp_pciephy_clk_l, 2286 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2287 .reset_list = sdm845_pciephy_reset_l, 2288 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2289 .vreg_list = qmp_phy_vreg_l, 2290 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2291 .regs = pciephy_v5_regs_layout, 2292 2293 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2294 .phy_status = PHYSTATUS, 2295 }; 2296 2297 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 2298 .lanes = 4, 2299 2300 .offsets = &qmp_pcie_offsets_v5, 2301 2302 .tbls = { 2303 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2304 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2305 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 2306 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 2307 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 2308 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 2309 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 2310 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 2311 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2312 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2313 }, 2314 2315 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2316 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 2317 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 2318 }, 2319 2320 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 2321 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 2322 2323 .clk_list = sc8280xp_pciephy_clk_l, 2324 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2325 .reset_list = sdm845_pciephy_reset_l, 2326 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2327 .vreg_list = qmp_phy_vreg_l, 2328 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2329 .regs = pciephy_v5_regs_layout, 2330 2331 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2332 .phy_status = PHYSTATUS, 2333 }; 2334 2335 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 2336 .lanes = 2, 2337 2338 .tbls = { 2339 .serdes = sdx55_qmp_pcie_serdes_tbl, 2340 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 2341 .tx = sdx55_qmp_pcie_tx_tbl, 2342 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 2343 .rx = sdx55_qmp_pcie_rx_tbl, 2344 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 2345 .pcs = sdx55_qmp_pcie_pcs_tbl, 2346 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 2347 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 2348 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 2349 }, 2350 2351 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2352 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 2353 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 2354 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 2355 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 2356 }, 2357 2358 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2359 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 2360 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 2361 .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, 2362 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), 2363 }, 2364 2365 .clk_list = sdm845_pciephy_clk_l, 2366 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2367 .reset_list = sdm845_pciephy_reset_l, 2368 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2369 .vreg_list = qmp_phy_vreg_l, 2370 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2371 .regs = pciephy_v4_regs_layout, 2372 2373 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2374 .phy_status = PHYSTATUS_4_20, 2375 }; 2376 2377 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 2378 .lanes = 1, 2379 2380 .offsets = &qmp_pcie_offsets_v5, 2381 2382 .tbls = { 2383 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2384 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2385 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 2386 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 2387 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2388 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2389 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2390 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2391 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2392 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2393 }, 2394 2395 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2396 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 2397 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 2398 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 2399 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 2400 }, 2401 2402 .clk_list = sc8280xp_pciephy_clk_l, 2403 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2404 .reset_list = sdm845_pciephy_reset_l, 2405 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2406 .vreg_list = qmp_phy_vreg_l, 2407 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2408 .regs = pciephy_v5_regs_layout, 2409 2410 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2411 .phy_status = PHYSTATUS, 2412 }; 2413 2414 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 2415 .lanes = 2, 2416 2417 .offsets = &qmp_pcie_offsets_v5, 2418 2419 .tbls = { 2420 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2421 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2422 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 2423 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 2424 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2425 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2426 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2427 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2428 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2429 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2430 }, 2431 2432 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2433 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 2434 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 2435 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 2436 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 2437 }, 2438 2439 .clk_list = sc8280xp_pciephy_clk_l, 2440 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2441 .reset_list = sdm845_pciephy_reset_l, 2442 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2443 .vreg_list = qmp_phy_vreg_l, 2444 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2445 .regs = pciephy_v5_regs_layout, 2446 2447 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2448 .phy_status = PHYSTATUS, 2449 }; 2450 2451 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 2452 .lanes = 1, 2453 2454 .tbls = { 2455 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2456 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2457 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 2458 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 2459 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2460 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2461 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2462 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2463 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2464 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2465 }, 2466 2467 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2468 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 2469 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 2470 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 2471 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 2472 }, 2473 2474 .clk_list = sdm845_pciephy_clk_l, 2475 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2476 .reset_list = sdm845_pciephy_reset_l, 2477 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2478 .vreg_list = qmp_phy_vreg_l, 2479 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2480 .regs = pciephy_v5_regs_layout, 2481 2482 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2483 .phy_status = PHYSTATUS, 2484 }; 2485 2486 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 2487 .lanes = 2, 2488 2489 .tbls = { 2490 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 2491 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 2492 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 2493 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 2494 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 2495 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 2496 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 2497 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 2498 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 2499 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 2500 }, 2501 2502 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2503 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 2504 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 2505 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 2506 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 2507 }, 2508 2509 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2510 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 2511 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 2512 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 2513 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 2514 }, 2515 2516 .clk_list = sdm845_pciephy_clk_l, 2517 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2518 .reset_list = sdm845_pciephy_reset_l, 2519 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2520 .vreg_list = qmp_phy_vreg_l, 2521 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2522 .regs = pciephy_v5_regs_layout, 2523 2524 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2525 .phy_status = PHYSTATUS_4_20, 2526 }; 2527 2528 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 2529 .lanes = 2, 2530 2531 .offsets = &qmp_pcie_offsets_v5, 2532 2533 .tbls = { 2534 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 2535 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 2536 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 2537 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 2538 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 2539 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 2540 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 2541 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 2542 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 2543 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 2544 }, 2545 .clk_list = sc8280xp_pciephy_clk_l, 2546 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2547 .reset_list = sdm845_pciephy_reset_l, 2548 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2549 .vreg_list = qmp_phy_vreg_l, 2550 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2551 .regs = pciephy_v5_regs_layout, 2552 2553 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2554 .phy_status = PHYSTATUS, 2555 }; 2556 2557 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 2558 .lanes = 2, 2559 2560 .offsets = &qmp_pcie_offsets_v6_20, 2561 2562 .tbls = { 2563 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 2564 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 2565 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 2566 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 2567 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 2568 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 2569 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 2570 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 2571 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 2572 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 2573 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 2574 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 2575 }, 2576 .clk_list = sc8280xp_pciephy_clk_l, 2577 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2578 .reset_list = sdm845_pciephy_reset_l, 2579 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2580 .vreg_list = sm8550_qmp_phy_vreg_l, 2581 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 2582 .regs = pciephy_v5_regs_layout, 2583 2584 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2585 .phy_status = PHYSTATUS_4_20, 2586 .has_nocsr_reset = true, 2587 }; 2588 2589 static void qmp_pcie_configure_lane(void __iomem *base, 2590 const struct qmp_phy_init_tbl tbl[], 2591 int num, 2592 u8 lane_mask) 2593 { 2594 int i; 2595 const struct qmp_phy_init_tbl *t = tbl; 2596 2597 if (!t) 2598 return; 2599 2600 for (i = 0; i < num; i++, t++) { 2601 if (!(t->lane_mask & lane_mask)) 2602 continue; 2603 2604 writel(t->val, base + t->offset); 2605 } 2606 } 2607 2608 static void qmp_pcie_configure(void __iomem *base, 2609 const struct qmp_phy_init_tbl tbl[], 2610 int num) 2611 { 2612 qmp_pcie_configure_lane(base, tbl, num, 0xff); 2613 } 2614 2615 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2616 { 2617 const struct qmp_phy_cfg *cfg = qmp->cfg; 2618 const struct qmp_pcie_offsets *offs = cfg->offsets; 2619 void __iomem *tx3, *rx3, *tx4, *rx4; 2620 2621 tx3 = qmp->port_b + offs->tx; 2622 rx3 = qmp->port_b + offs->rx; 2623 tx4 = qmp->port_b + offs->tx2; 2624 rx4 = qmp->port_b + offs->rx2; 2625 2626 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); 2627 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); 2628 2629 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); 2630 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); 2631 } 2632 2633 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2634 { 2635 const struct qmp_phy_cfg *cfg = qmp->cfg; 2636 void __iomem *serdes = qmp->serdes; 2637 void __iomem *tx = qmp->tx; 2638 void __iomem *rx = qmp->rx; 2639 void __iomem *tx2 = qmp->tx2; 2640 void __iomem *rx2 = qmp->rx2; 2641 void __iomem *pcs = qmp->pcs; 2642 void __iomem *pcs_misc = qmp->pcs_misc; 2643 void __iomem *ln_shrd = qmp->ln_shrd; 2644 2645 if (!tbls) 2646 return; 2647 2648 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 2649 2650 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 2651 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 2652 2653 if (cfg->lanes >= 2) { 2654 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 2655 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 2656 } 2657 2658 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 2659 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 2660 2661 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2662 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 2663 qmp_pcie_init_port_b(qmp, tbls); 2664 } 2665 2666 qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 2667 } 2668 2669 static int qmp_pcie_init(struct phy *phy) 2670 { 2671 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2672 const struct qmp_phy_cfg *cfg = qmp->cfg; 2673 int ret; 2674 2675 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2676 if (ret) { 2677 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2678 return ret; 2679 } 2680 2681 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2682 if (ret) { 2683 dev_err(qmp->dev, "reset assert failed\n"); 2684 goto err_disable_regulators; 2685 } 2686 2687 ret = reset_control_assert(qmp->nocsr_reset); 2688 if (ret) { 2689 dev_err(qmp->dev, "no-csr reset assert failed\n"); 2690 goto err_assert_reset; 2691 } 2692 2693 usleep_range(200, 300); 2694 2695 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2696 if (ret) { 2697 dev_err(qmp->dev, "reset deassert failed\n"); 2698 goto err_assert_reset; 2699 } 2700 2701 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2702 if (ret) 2703 goto err_assert_reset; 2704 2705 return 0; 2706 2707 err_assert_reset: 2708 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2709 err_disable_regulators: 2710 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2711 2712 return ret; 2713 } 2714 2715 static int qmp_pcie_exit(struct phy *phy) 2716 { 2717 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2718 const struct qmp_phy_cfg *cfg = qmp->cfg; 2719 2720 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2721 2722 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2723 2724 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2725 2726 return 0; 2727 } 2728 2729 static int qmp_pcie_power_on(struct phy *phy) 2730 { 2731 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2732 const struct qmp_phy_cfg *cfg = qmp->cfg; 2733 const struct qmp_phy_cfg_tbls *mode_tbls; 2734 void __iomem *pcs = qmp->pcs; 2735 void __iomem *status; 2736 unsigned int mask, val; 2737 int ret; 2738 2739 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2740 cfg->pwrdn_ctrl); 2741 2742 if (qmp->mode == PHY_MODE_PCIE_RC) 2743 mode_tbls = cfg->tbls_rc; 2744 else 2745 mode_tbls = cfg->tbls_ep; 2746 2747 qmp_pcie_init_registers(qmp, &cfg->tbls); 2748 qmp_pcie_init_registers(qmp, mode_tbls); 2749 2750 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 2751 if (ret) 2752 return ret; 2753 2754 ret = reset_control_deassert(qmp->nocsr_reset); 2755 if (ret) { 2756 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 2757 goto err_disable_pipe_clk; 2758 } 2759 2760 /* Pull PHY out of reset state */ 2761 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2762 2763 /* start SerDes and Phy-Coding-Sublayer */ 2764 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2765 2766 if (!cfg->skip_start_delay) 2767 usleep_range(1000, 1200); 2768 2769 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2770 mask = cfg->phy_status; 2771 ret = readl_poll_timeout(status, val, !(val & mask), 200, 2772 PHY_INIT_COMPLETE_TIMEOUT); 2773 if (ret) { 2774 dev_err(qmp->dev, "phy initialization timed-out\n"); 2775 goto err_disable_pipe_clk; 2776 } 2777 2778 return 0; 2779 2780 err_disable_pipe_clk: 2781 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2782 2783 return ret; 2784 } 2785 2786 static int qmp_pcie_power_off(struct phy *phy) 2787 { 2788 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2789 const struct qmp_phy_cfg *cfg = qmp->cfg; 2790 2791 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2792 2793 /* PHY reset */ 2794 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2795 2796 /* stop SerDes and Phy-Coding-Sublayer */ 2797 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2798 SERDES_START | PCS_START); 2799 2800 /* Put PHY into POWER DOWN state: active low */ 2801 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2802 cfg->pwrdn_ctrl); 2803 2804 return 0; 2805 } 2806 2807 static int qmp_pcie_enable(struct phy *phy) 2808 { 2809 int ret; 2810 2811 ret = qmp_pcie_init(phy); 2812 if (ret) 2813 return ret; 2814 2815 ret = qmp_pcie_power_on(phy); 2816 if (ret) 2817 qmp_pcie_exit(phy); 2818 2819 return ret; 2820 } 2821 2822 static int qmp_pcie_disable(struct phy *phy) 2823 { 2824 int ret; 2825 2826 ret = qmp_pcie_power_off(phy); 2827 if (ret) 2828 return ret; 2829 2830 return qmp_pcie_exit(phy); 2831 } 2832 2833 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2834 { 2835 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2836 2837 switch (submode) { 2838 case PHY_MODE_PCIE_RC: 2839 case PHY_MODE_PCIE_EP: 2840 qmp->mode = submode; 2841 break; 2842 default: 2843 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2844 return -EINVAL; 2845 } 2846 2847 return 0; 2848 } 2849 2850 static const struct phy_ops qmp_pcie_phy_ops = { 2851 .power_on = qmp_pcie_enable, 2852 .power_off = qmp_pcie_disable, 2853 .set_mode = qmp_pcie_set_mode, 2854 .owner = THIS_MODULE, 2855 }; 2856 2857 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 2858 { 2859 const struct qmp_phy_cfg *cfg = qmp->cfg; 2860 struct device *dev = qmp->dev; 2861 int num = cfg->num_vregs; 2862 int i; 2863 2864 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2865 if (!qmp->vregs) 2866 return -ENOMEM; 2867 2868 for (i = 0; i < num; i++) 2869 qmp->vregs[i].supply = cfg->vreg_list[i]; 2870 2871 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2872 } 2873 2874 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 2875 { 2876 const struct qmp_phy_cfg *cfg = qmp->cfg; 2877 struct device *dev = qmp->dev; 2878 int i; 2879 int ret; 2880 2881 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2882 sizeof(*qmp->resets), GFP_KERNEL); 2883 if (!qmp->resets) 2884 return -ENOMEM; 2885 2886 for (i = 0; i < cfg->num_resets; i++) 2887 qmp->resets[i].id = cfg->reset_list[i]; 2888 2889 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2890 if (ret) 2891 return dev_err_probe(dev, ret, "failed to get resets\n"); 2892 2893 if (cfg->has_nocsr_reset) { 2894 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); 2895 if (IS_ERR(qmp->nocsr_reset)) 2896 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 2897 "failed to get no-csr reset\n"); 2898 } 2899 2900 return 0; 2901 } 2902 2903 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 2904 { 2905 const struct qmp_phy_cfg *cfg = qmp->cfg; 2906 struct device *dev = qmp->dev; 2907 int num = cfg->num_clks; 2908 int i; 2909 2910 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2911 if (!qmp->clks) 2912 return -ENOMEM; 2913 2914 for (i = 0; i < num; i++) 2915 qmp->clks[i].id = cfg->clk_list[i]; 2916 2917 return devm_clk_bulk_get(dev, num, qmp->clks); 2918 } 2919 2920 static void phy_clk_release_provider(void *res) 2921 { 2922 of_clk_del_provider(res); 2923 } 2924 2925 /* 2926 * Register a fixed rate pipe clock. 2927 * 2928 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2929 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2930 * by the PHY driver for its operations. 2931 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2932 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2933 * Below picture shows this relationship. 2934 * 2935 * +---------------+ 2936 * | PHY block |<<---------------------------------------+ 2937 * | | | 2938 * | +-------+ | +-----+ | 2939 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2940 * clk | +-------+ | +-----+ 2941 * +---------------+ 2942 */ 2943 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 2944 { 2945 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2946 struct clk_init_data init = { }; 2947 int ret; 2948 2949 ret = of_property_read_string(np, "clock-output-names", &init.name); 2950 if (ret) { 2951 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2952 return ret; 2953 } 2954 2955 init.ops = &clk_fixed_rate_ops; 2956 2957 /* 2958 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2959 * unless other frequency is specified in the PHY config. 2960 */ 2961 if (qmp->cfg->pipe_clock_rate) 2962 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 2963 else 2964 fixed->fixed_rate = 125000000; 2965 2966 fixed->hw.init = &init; 2967 2968 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2969 if (ret) 2970 return ret; 2971 2972 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2973 if (ret) 2974 return ret; 2975 2976 /* 2977 * Roll a devm action because the clock provider is the child node, but 2978 * the child node is not actually a device. 2979 */ 2980 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2981 } 2982 2983 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 2984 { 2985 struct platform_device *pdev = to_platform_device(qmp->dev); 2986 const struct qmp_phy_cfg *cfg = qmp->cfg; 2987 struct device *dev = qmp->dev; 2988 struct clk *clk; 2989 2990 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2991 if (IS_ERR(qmp->serdes)) 2992 return PTR_ERR(qmp->serdes); 2993 2994 /* 2995 * Get memory resources for the PHY: 2996 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2997 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2998 * For single lane PHYs: pcs_misc (optional) -> 3. 2999 */ 3000 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3001 if (IS_ERR(qmp->tx)) 3002 return PTR_ERR(qmp->tx); 3003 3004 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 3005 qmp->rx = qmp->tx; 3006 else 3007 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3008 if (IS_ERR(qmp->rx)) 3009 return PTR_ERR(qmp->rx); 3010 3011 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3012 if (IS_ERR(qmp->pcs)) 3013 return PTR_ERR(qmp->pcs); 3014 3015 if (cfg->lanes >= 2) { 3016 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3017 if (IS_ERR(qmp->tx2)) 3018 return PTR_ERR(qmp->tx2); 3019 3020 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3021 if (IS_ERR(qmp->rx2)) 3022 return PTR_ERR(qmp->rx2); 3023 3024 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3025 } else { 3026 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 3027 } 3028 3029 if (IS_ERR(qmp->pcs_misc) && 3030 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 3031 qmp->pcs_misc = qmp->pcs + 0x400; 3032 3033 if (IS_ERR(qmp->pcs_misc)) { 3034 if (cfg->tbls.pcs_misc || 3035 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 3036 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 3037 return PTR_ERR(qmp->pcs_misc); 3038 } 3039 } 3040 3041 clk = devm_get_clk_from_child(dev, np, NULL); 3042 if (IS_ERR(clk)) { 3043 return dev_err_probe(dev, PTR_ERR(clk), 3044 "failed to get pipe clock\n"); 3045 } 3046 3047 qmp->num_pipe_clks = 1; 3048 qmp->pipe_clks[0].id = "pipe"; 3049 qmp->pipe_clks[0].clk = clk; 3050 3051 return 0; 3052 } 3053 3054 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 3055 { 3056 struct regmap *tcsr; 3057 unsigned int args[2]; 3058 int ret; 3059 3060 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 3061 "qcom,4ln-config-sel", 3062 ARRAY_SIZE(args), args); 3063 if (IS_ERR(tcsr)) { 3064 ret = PTR_ERR(tcsr); 3065 if (ret == -ENOENT) 3066 return 0; 3067 3068 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 3069 return ret; 3070 } 3071 3072 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 3073 if (ret < 0) { 3074 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 3075 return ret; 3076 } 3077 3078 qmp->tcsr_4ln_config = ret; 3079 3080 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 3081 3082 return 0; 3083 } 3084 3085 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 3086 { 3087 struct platform_device *pdev = to_platform_device(qmp->dev); 3088 const struct qmp_phy_cfg *cfg = qmp->cfg; 3089 const struct qmp_pcie_offsets *offs = cfg->offsets; 3090 struct device *dev = qmp->dev; 3091 void __iomem *base; 3092 int ret; 3093 3094 if (!offs) 3095 return -EINVAL; 3096 3097 ret = qmp_pcie_get_4ln_config(qmp); 3098 if (ret) 3099 return ret; 3100 3101 base = devm_platform_ioremap_resource(pdev, 0); 3102 if (IS_ERR(base)) 3103 return PTR_ERR(base); 3104 3105 qmp->serdes = base + offs->serdes; 3106 qmp->pcs = base + offs->pcs; 3107 qmp->pcs_misc = base + offs->pcs_misc; 3108 qmp->tx = base + offs->tx; 3109 qmp->rx = base + offs->rx; 3110 3111 if (cfg->lanes >= 2) { 3112 qmp->tx2 = base + offs->tx2; 3113 qmp->rx2 = base + offs->rx2; 3114 } 3115 3116 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 3117 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 3118 if (IS_ERR(qmp->port_b)) 3119 return PTR_ERR(qmp->port_b); 3120 } 3121 3122 if (cfg->tbls.ln_shrd) 3123 qmp->ln_shrd = base + offs->ln_shrd; 3124 3125 qmp->num_pipe_clks = 2; 3126 qmp->pipe_clks[0].id = "pipe"; 3127 qmp->pipe_clks[1].id = "pipediv2"; 3128 3129 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 3130 if (ret) 3131 return ret; 3132 3133 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 3134 if (ret) 3135 return ret; 3136 3137 return 0; 3138 } 3139 3140 static int qmp_pcie_probe(struct platform_device *pdev) 3141 { 3142 struct device *dev = &pdev->dev; 3143 struct phy_provider *phy_provider; 3144 struct device_node *np; 3145 struct qmp_pcie *qmp; 3146 int ret; 3147 3148 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3149 if (!qmp) 3150 return -ENOMEM; 3151 3152 qmp->dev = dev; 3153 3154 qmp->cfg = of_device_get_match_data(dev); 3155 if (!qmp->cfg) 3156 return -EINVAL; 3157 3158 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 3159 WARN_ON_ONCE(!qmp->cfg->phy_status); 3160 3161 ret = qmp_pcie_clk_init(qmp); 3162 if (ret) 3163 return ret; 3164 3165 ret = qmp_pcie_reset_init(qmp); 3166 if (ret) 3167 return ret; 3168 3169 ret = qmp_pcie_vreg_init(qmp); 3170 if (ret) 3171 return ret; 3172 3173 /* Check for legacy binding with child node. */ 3174 np = of_get_next_available_child(dev->of_node, NULL); 3175 if (np) { 3176 ret = qmp_pcie_parse_dt_legacy(qmp, np); 3177 } else { 3178 np = of_node_get(dev->of_node); 3179 ret = qmp_pcie_parse_dt(qmp); 3180 } 3181 if (ret) 3182 goto err_node_put; 3183 3184 ret = phy_pipe_clk_register(qmp, np); 3185 if (ret) 3186 goto err_node_put; 3187 3188 qmp->mode = PHY_MODE_PCIE_RC; 3189 3190 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 3191 if (IS_ERR(qmp->phy)) { 3192 ret = PTR_ERR(qmp->phy); 3193 dev_err(dev, "failed to create PHY: %d\n", ret); 3194 goto err_node_put; 3195 } 3196 3197 phy_set_drvdata(qmp->phy, qmp); 3198 3199 of_node_put(np); 3200 3201 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3202 3203 return PTR_ERR_OR_ZERO(phy_provider); 3204 3205 err_node_put: 3206 of_node_put(np); 3207 return ret; 3208 } 3209 3210 static const struct of_device_id qmp_pcie_of_match_table[] = { 3211 { 3212 .compatible = "qcom,ipq6018-qmp-pcie-phy", 3213 .data = &ipq6018_pciephy_cfg, 3214 }, { 3215 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 3216 .data = &ipq8074_pciephy_gen3_cfg, 3217 }, { 3218 .compatible = "qcom,ipq8074-qmp-pcie-phy", 3219 .data = &ipq8074_pciephy_cfg, 3220 }, { 3221 .compatible = "qcom,msm8998-qmp-pcie-phy", 3222 .data = &msm8998_pciephy_cfg, 3223 }, { 3224 .compatible = "qcom,sc8180x-qmp-pcie-phy", 3225 .data = &sc8180x_pciephy_cfg, 3226 }, { 3227 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 3228 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 3229 }, { 3230 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 3231 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 3232 }, { 3233 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 3234 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 3235 }, { 3236 .compatible = "qcom,sdm845-qhp-pcie-phy", 3237 .data = &sdm845_qhp_pciephy_cfg, 3238 }, { 3239 .compatible = "qcom,sdm845-qmp-pcie-phy", 3240 .data = &sdm845_qmp_pciephy_cfg, 3241 }, { 3242 .compatible = "qcom,sdx55-qmp-pcie-phy", 3243 .data = &sdx55_qmp_pciephy_cfg, 3244 }, { 3245 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 3246 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 3247 }, { 3248 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 3249 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 3250 }, { 3251 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 3252 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 3253 }, { 3254 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 3255 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 3256 }, { 3257 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 3258 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 3259 }, { 3260 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 3261 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 3262 }, { 3263 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 3264 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 3265 }, { 3266 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 3267 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 3268 }, { 3269 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 3270 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 3271 }, 3272 { }, 3273 }; 3274 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 3275 3276 static struct platform_driver qmp_pcie_driver = { 3277 .probe = qmp_pcie_probe, 3278 .driver = { 3279 .name = "qcom-qmp-pcie-phy", 3280 .of_match_table = qmp_pcie_of_match_table, 3281 }, 3282 }; 3283 3284 module_platform_driver(qmp_pcie_driver); 3285 3286 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3287 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 3288 MODULE_LICENSE("GPL v2"); 3289