1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include "phy-qcom-qmp.h" 27 #include "phy-qcom-qmp-pcs-misc-v3.h" 28 #include "phy-qcom-qmp-pcs-pcie-v4.h" 29 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 30 #include "phy-qcom-qmp-pcs-pcie-v5.h" 31 #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 32 #include "phy-qcom-qmp-pcs-pcie-v6.h" 33 #include "phy-qcom-qmp-pcs-pcie-v6_20.h" 34 #include "phy-qcom-qmp-pcie-qhp.h" 35 36 /* QPHY_SW_RESET bit */ 37 #define SW_RESET BIT(0) 38 /* QPHY_POWER_DOWN_CONTROL */ 39 #define SW_PWRDN BIT(0) 40 #define REFCLK_DRV_DSBL BIT(1) 41 /* QPHY_START_CONTROL bits */ 42 #define SERDES_START BIT(0) 43 #define PCS_START BIT(1) 44 /* QPHY_PCS_STATUS bit */ 45 #define PHYSTATUS BIT(6) 46 #define PHYSTATUS_4_20 BIT(7) 47 48 #define PHY_INIT_COMPLETE_TIMEOUT 10000 49 50 struct qmp_phy_init_tbl { 51 unsigned int offset; 52 unsigned int val; 53 /* 54 * mask of lanes for which this register is written 55 * for cases when second lane needs different values 56 */ 57 u8 lane_mask; 58 }; 59 60 #define QMP_PHY_INIT_CFG(o, v) \ 61 { \ 62 .offset = o, \ 63 .val = v, \ 64 .lane_mask = 0xff, \ 65 } 66 67 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 68 { \ 69 .offset = o, \ 70 .val = v, \ 71 .lane_mask = l, \ 72 } 73 74 /* set of registers with offsets different per-PHY */ 75 enum qphy_reg_layout { 76 /* PCS registers */ 77 QPHY_SW_RESET, 78 QPHY_START_CTRL, 79 QPHY_PCS_STATUS, 80 QPHY_PCS_POWER_DOWN_CONTROL, 81 /* Keep last to ensure regs_layout arrays are properly initialized */ 82 QPHY_LAYOUT_SIZE 83 }; 84 85 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 86 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 87 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 88 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 89 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 90 }; 91 92 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 93 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 94 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 95 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 96 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 97 }; 98 99 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 100 [QPHY_SW_RESET] = 0x00, 101 [QPHY_START_CTRL] = 0x08, 102 [QPHY_PCS_STATUS] = 0x2ac, 103 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 104 }; 105 106 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 107 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 108 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 109 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 110 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 111 }; 112 113 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 114 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 115 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 116 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 118 }; 119 120 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 163 }; 164 165 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 170 }; 171 172 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 181 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 182 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 187 }; 188 189 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 200 }; 201 202 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 203 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 243 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 244 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 245 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 247 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 248 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 249 }; 250 251 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 252 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 253 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 254 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 255 }; 256 257 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 288 }; 289 290 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 292 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 298 }; 299 300 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 304 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 305 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 308 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 309 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 310 }; 311 312 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 313 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 314 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 315 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 316 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 317 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 318 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 319 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 320 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 321 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 322 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 323 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 324 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 325 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 326 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 327 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 328 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 329 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 330 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 331 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 332 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 333 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 334 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 335 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 336 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 337 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 339 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 340 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 341 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 342 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 343 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 344 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 346 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 349 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 352 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 353 }; 354 355 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 356 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 357 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 358 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 359 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 360 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 361 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 362 }; 363 364 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 365 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 366 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 367 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 368 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 369 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 370 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 371 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 372 }; 373 374 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 378 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 379 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 380 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 381 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 382 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 383 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 384 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 385 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 386 }; 387 388 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 389 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 440 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 441 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 442 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 443 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 444 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 445 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 446 }; 447 448 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 449 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 450 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 451 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 452 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 453 }; 454 455 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 486 }; 487 488 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 500 }; 501 502 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 516 }; 517 518 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 561 }; 562 563 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 564 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 565 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 566 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 567 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 568 }; 569 570 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 587 }; 588 589 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 591 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 597 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 605 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 609 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 611 }; 612 613 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 619 }; 620 621 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 667 }; 668 669 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 726 }; 727 728 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 731 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 735 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 736 }; 737 738 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 781 }; 782 783 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 784 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 785 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 786 }; 787 788 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 825 }; 826 827 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 833 }; 834 835 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 842 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 843 }; 844 845 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 883 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 884 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 885 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 886 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 887 }; 888 889 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 890 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 891 }; 892 893 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 894 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 895 }; 896 897 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 898 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 899 }; 900 901 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 902 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 903 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 904 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 905 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 906 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 907 }; 908 909 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 923 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 924 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 925 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 926 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 927 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 928 }; 929 930 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 931 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 932 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 933 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 934 }; 935 936 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 937 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 938 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 939 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 940 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 941 }; 942 943 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 944 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 945 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 946 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 947 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 948 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 949 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 950 }; 951 952 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 953 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 954 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 955 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 958 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 959 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 960 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 961 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 962 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 963 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 964 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 965 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 966 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 967 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 968 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 969 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 970 }; 971 972 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 973 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 974 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 975 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 976 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 977 }; 978 979 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 980 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 981 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 982 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 983 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 984 }; 985 986 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1028 }; 1029 1030 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1032 }; 1033 1034 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1035 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1038 }; 1039 1040 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1071 }; 1072 1073 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1076 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1077 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1078 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1079 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1080 }; 1081 1082 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1085 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1086 }; 1087 1088 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1089 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1090 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1091 }; 1092 1093 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1094 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1095 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1096 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1097 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1098 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1100 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1101 }; 1102 1103 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1104 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1105 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1106 }; 1107 1108 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1109 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1110 }; 1111 1112 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1113 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1114 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1115 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1116 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1117 }; 1118 1119 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1120 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1121 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1122 }; 1123 1124 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1125 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1126 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1127 }; 1128 1129 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1144 }; 1145 1146 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1166 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1167 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1168 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1169 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1172 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1173 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1174 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1175 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1176 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1177 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1178 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1179 }; 1180 1181 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1182 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1183 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1184 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1185 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1186 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1187 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1188 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1189 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1190 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1191 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1192 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1193 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1194 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1195 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1196 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1197 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1198 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1199 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1200 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1201 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1202 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1203 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1204 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1205 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1206 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1207 }; 1208 1209 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1210 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1211 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1212 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1213 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1214 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1215 }; 1216 1217 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1218 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1219 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1220 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1221 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1222 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1223 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1224 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1225 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1226 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1227 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1228 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1229 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1230 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1231 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1232 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1233 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1234 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1235 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1236 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1237 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1238 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1239 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1240 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1241 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1242 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1243 }; 1244 1245 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1246 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1247 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1248 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1249 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1250 }; 1251 1252 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1253 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1254 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1255 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1256 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1257 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1258 }; 1259 1260 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1261 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1262 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1263 }; 1264 1265 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { 1266 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1267 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1268 }; 1269 1270 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 1271 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1305 }; 1306 1307 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 1308 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 1316 }; 1317 1318 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 1319 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 1346 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1347 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1355 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1356 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1357 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1358 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1359 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 1363 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1364 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 1371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1382 }; 1383 1384 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 1385 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1386 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 1387 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 1388 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1389 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1390 }; 1391 1392 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 1393 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1394 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1395 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1396 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 1397 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1398 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1399 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1400 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1401 }; 1402 1403 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 1404 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1405 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1409 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1410 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1412 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1413 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1414 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1415 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1416 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1417 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1418 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1419 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1420 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1421 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1422 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1423 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1424 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1425 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1426 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1427 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1428 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1429 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1430 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1431 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1432 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1433 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1434 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1445 }; 1446 1447 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1448 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1449 }; 1450 1451 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1452 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1453 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1454 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1455 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1456 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1457 }; 1458 1459 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 1460 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1461 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1462 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1463 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1464 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1465 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1466 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1467 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1468 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1469 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1470 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1471 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1472 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1473 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1474 }; 1475 1476 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1477 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1478 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1479 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1480 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1481 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1482 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1483 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1484 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1485 }; 1486 1487 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 1488 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1489 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1490 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1491 }; 1492 1493 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1494 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1495 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1496 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1497 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1498 }; 1499 1500 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 1501 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1502 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1503 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1504 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1505 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1506 }; 1507 1508 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1509 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1510 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1511 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1512 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1513 }; 1514 1515 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 1516 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1517 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1518 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1519 }; 1520 1521 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 1522 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1523 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1524 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1525 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1526 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1527 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1528 }; 1529 1530 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 1531 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 1532 }; 1533 1534 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1535 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1536 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1537 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1538 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1539 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1540 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1541 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1547 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1548 }; 1549 1550 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1551 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1552 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1553 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1554 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1555 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1556 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1557 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1558 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1559 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1560 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1561 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1562 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1563 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1564 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1565 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1566 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1567 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1568 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1569 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1570 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1571 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1572 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1573 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1574 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1575 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1576 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1577 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1578 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1579 }; 1580 1581 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1582 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1583 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1584 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1585 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1586 }; 1587 1588 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1589 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1590 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1591 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1592 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1593 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1594 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1595 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1596 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1597 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1598 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1599 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1600 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1601 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1602 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1603 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1604 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1605 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1606 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1607 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1608 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1609 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1610 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1611 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1612 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1613 1614 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1615 1616 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1617 1618 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1619 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1620 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1621 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1622 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1623 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1624 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1625 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1626 1627 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1628 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1629 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1630 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1631 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1632 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1633 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1634 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1635 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1636 }; 1637 1638 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1639 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1640 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1641 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1642 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 1643 }; 1644 1645 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1646 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1647 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1648 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1649 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1650 }; 1651 1652 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1653 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1654 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1655 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1656 }; 1657 1658 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1659 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1660 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1661 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1666 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1667 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1668 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1669 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1670 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1679 }; 1680 1681 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1682 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1683 }; 1684 1685 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 1686 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1687 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1688 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1689 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1690 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1691 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 1692 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1693 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1694 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1695 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1696 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1697 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1698 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1699 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1700 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1701 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1702 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1703 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 1705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 1711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 1717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 1722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 1723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1724 }; 1725 1726 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 1727 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 1728 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 1729 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 1730 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 1731 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 1732 }; 1733 1734 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 1735 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1736 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 1737 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 1738 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 1739 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 1740 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 1741 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 1742 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 1743 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 1744 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 1745 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 1746 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 1747 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 1748 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 1749 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 1750 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 1751 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), 1752 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 1753 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 1754 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 1755 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 1756 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 1757 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 1758 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1759 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1760 }; 1761 1762 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 1763 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 1764 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 1765 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 1766 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 1767 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 1768 }; 1769 1770 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1771 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1772 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1773 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1774 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1775 }; 1776 1777 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 1778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1787 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1793 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1794 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1795 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1796 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1800 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1801 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1802 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1823 }; 1824 1825 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1826 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1827 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe), 1828 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 1829 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00), 1830 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f), 1831 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1832 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1833 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1834 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1835 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1836 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1837 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1838 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1839 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1840 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1841 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1842 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1843 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1844 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1845 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1846 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1847 }; 1848 1849 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 1850 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1851 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1852 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1853 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 1854 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1855 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1856 }; 1857 1858 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 1859 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 1860 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1861 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1862 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1863 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1864 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1865 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 1866 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1867 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1868 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1869 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1870 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1871 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1872 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 1873 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1874 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1875 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1876 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1877 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1878 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1879 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1880 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 1881 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 1882 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 1883 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1884 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 1885 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1886 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1887 }; 1888 1889 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 1890 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1891 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25), 1892 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1893 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1894 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 1895 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 1896 }; 1897 1898 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1899 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1900 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1901 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1902 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1903 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1904 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1905 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1906 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1907 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1908 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 1909 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 1910 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 1911 }; 1912 1913 struct qmp_pcie_offsets { 1914 u16 serdes; 1915 u16 pcs; 1916 u16 pcs_misc; 1917 u16 tx; 1918 u16 rx; 1919 u16 tx2; 1920 u16 rx2; 1921 u16 ln_shrd; 1922 }; 1923 1924 struct qmp_phy_cfg_tbls { 1925 const struct qmp_phy_init_tbl *serdes; 1926 int serdes_num; 1927 const struct qmp_phy_init_tbl *tx; 1928 int tx_num; 1929 const struct qmp_phy_init_tbl *rx; 1930 int rx_num; 1931 const struct qmp_phy_init_tbl *pcs; 1932 int pcs_num; 1933 const struct qmp_phy_init_tbl *pcs_misc; 1934 int pcs_misc_num; 1935 const struct qmp_phy_init_tbl *ln_shrd; 1936 int ln_shrd_num; 1937 }; 1938 1939 /* struct qmp_phy_cfg - per-PHY initialization config */ 1940 struct qmp_phy_cfg { 1941 int lanes; 1942 1943 const struct qmp_pcie_offsets *offsets; 1944 1945 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1946 const struct qmp_phy_cfg_tbls tbls; 1947 /* 1948 * Additional init sequences for PHY blocks, providing additional 1949 * register programming. They are used for providing separate sequences 1950 * for the Root Complex and End Point use cases. 1951 * 1952 * If EP mode is not supported, both tables can be left unset. 1953 */ 1954 const struct qmp_phy_cfg_tbls *tbls_rc; 1955 const struct qmp_phy_cfg_tbls *tbls_ep; 1956 1957 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 1958 int serdes_4ln_num; 1959 1960 /* clock ids to be requested */ 1961 const char * const *clk_list; 1962 int num_clks; 1963 /* resets to be requested */ 1964 const char * const *reset_list; 1965 int num_resets; 1966 /* regulators to be requested */ 1967 const char * const *vreg_list; 1968 int num_vregs; 1969 1970 /* array of registers with different offsets */ 1971 const unsigned int *regs; 1972 1973 unsigned int pwrdn_ctrl; 1974 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1975 unsigned int phy_status; 1976 1977 bool skip_start_delay; 1978 1979 bool has_nocsr_reset; 1980 1981 /* QMP PHY pipe clock interface rate */ 1982 unsigned long pipe_clock_rate; 1983 }; 1984 1985 struct qmp_pcie { 1986 struct device *dev; 1987 1988 const struct qmp_phy_cfg *cfg; 1989 bool tcsr_4ln_config; 1990 1991 void __iomem *serdes; 1992 void __iomem *pcs; 1993 void __iomem *pcs_misc; 1994 void __iomem *tx; 1995 void __iomem *rx; 1996 void __iomem *tx2; 1997 void __iomem *rx2; 1998 void __iomem *ln_shrd; 1999 2000 void __iomem *port_b; 2001 2002 struct clk_bulk_data *clks; 2003 struct clk_bulk_data pipe_clks[2]; 2004 int num_pipe_clks; 2005 2006 struct reset_control_bulk_data *resets; 2007 struct reset_control *nocsr_reset; 2008 struct regulator_bulk_data *vregs; 2009 2010 struct phy *phy; 2011 int mode; 2012 2013 struct clk_fixed_rate pipe_clk_fixed; 2014 }; 2015 2016 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 2017 { 2018 u32 reg; 2019 2020 reg = readl(base + offset); 2021 reg |= val; 2022 writel(reg, base + offset); 2023 2024 /* ensure that above write is through */ 2025 readl(base + offset); 2026 } 2027 2028 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 2029 { 2030 u32 reg; 2031 2032 reg = readl(base + offset); 2033 reg &= ~val; 2034 writel(reg, base + offset); 2035 2036 /* ensure that above write is through */ 2037 readl(base + offset); 2038 } 2039 2040 /* list of clocks required by phy */ 2041 static const char * const ipq8074_pciephy_clk_l[] = { 2042 "aux", "cfg_ahb", 2043 }; 2044 2045 static const char * const msm8996_phy_clk_l[] = { 2046 "aux", "cfg_ahb", "ref", 2047 }; 2048 2049 static const char * const sc8280xp_pciephy_clk_l[] = { 2050 "aux", "cfg_ahb", "ref", "rchng", 2051 }; 2052 2053 static const char * const sdm845_pciephy_clk_l[] = { 2054 "aux", "cfg_ahb", "ref", "refgen", 2055 }; 2056 2057 /* list of regulators */ 2058 static const char * const qmp_phy_vreg_l[] = { 2059 "vdda-phy", "vdda-pll", 2060 }; 2061 2062 static const char * const sm8550_qmp_phy_vreg_l[] = { 2063 "vdda-phy", "vdda-pll", "vdda-qref", 2064 }; 2065 2066 /* list of resets */ 2067 static const char * const ipq8074_pciephy_reset_l[] = { 2068 "phy", "common", 2069 }; 2070 2071 static const char * const sdm845_pciephy_reset_l[] = { 2072 "phy", 2073 }; 2074 2075 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 2076 .serdes = 0, 2077 .pcs = 0x0200, 2078 .pcs_misc = 0x0600, 2079 .tx = 0x0e00, 2080 .rx = 0x1000, 2081 .tx2 = 0x1600, 2082 .rx2 = 0x1800, 2083 }; 2084 2085 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 2086 .serdes = 0x1000, 2087 .pcs = 0x1200, 2088 .pcs_misc = 0x1400, 2089 .tx = 0x0000, 2090 .rx = 0x0200, 2091 .tx2 = 0x0800, 2092 .rx2 = 0x0a00, 2093 .ln_shrd = 0x0e00, 2094 }; 2095 2096 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 2097 .lanes = 1, 2098 2099 .tbls = { 2100 .serdes = ipq8074_pcie_serdes_tbl, 2101 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 2102 .tx = ipq8074_pcie_tx_tbl, 2103 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 2104 .rx = ipq8074_pcie_rx_tbl, 2105 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 2106 .pcs = ipq8074_pcie_pcs_tbl, 2107 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 2108 }, 2109 .clk_list = ipq8074_pciephy_clk_l, 2110 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 2111 .reset_list = ipq8074_pciephy_reset_l, 2112 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2113 .vreg_list = NULL, 2114 .num_vregs = 0, 2115 .regs = pciephy_v2_regs_layout, 2116 2117 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2118 .phy_status = PHYSTATUS, 2119 }; 2120 2121 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 2122 .lanes = 1, 2123 2124 .tbls = { 2125 .serdes = ipq8074_pcie_gen3_serdes_tbl, 2126 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 2127 .tx = ipq8074_pcie_gen3_tx_tbl, 2128 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 2129 .rx = ipq8074_pcie_gen3_rx_tbl, 2130 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 2131 .pcs = ipq8074_pcie_gen3_pcs_tbl, 2132 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 2133 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 2134 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 2135 }, 2136 .clk_list = ipq8074_pciephy_clk_l, 2137 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 2138 .reset_list = ipq8074_pciephy_reset_l, 2139 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2140 .vreg_list = NULL, 2141 .num_vregs = 0, 2142 .regs = pciephy_v4_regs_layout, 2143 2144 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2145 .phy_status = PHYSTATUS, 2146 2147 .pipe_clock_rate = 250000000, 2148 }; 2149 2150 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 2151 .lanes = 1, 2152 2153 .tbls = { 2154 .serdes = ipq6018_pcie_serdes_tbl, 2155 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 2156 .tx = ipq6018_pcie_tx_tbl, 2157 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 2158 .rx = ipq6018_pcie_rx_tbl, 2159 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 2160 .pcs = ipq6018_pcie_pcs_tbl, 2161 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 2162 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 2163 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 2164 }, 2165 .clk_list = ipq8074_pciephy_clk_l, 2166 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 2167 .reset_list = ipq8074_pciephy_reset_l, 2168 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2169 .vreg_list = NULL, 2170 .num_vregs = 0, 2171 .regs = pciephy_v4_regs_layout, 2172 2173 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2174 .phy_status = PHYSTATUS, 2175 }; 2176 2177 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 2178 .lanes = 1, 2179 2180 .tbls = { 2181 .serdes = sdm845_qmp_pcie_serdes_tbl, 2182 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 2183 .tx = sdm845_qmp_pcie_tx_tbl, 2184 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 2185 .rx = sdm845_qmp_pcie_rx_tbl, 2186 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 2187 .pcs = sdm845_qmp_pcie_pcs_tbl, 2188 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 2189 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 2190 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 2191 }, 2192 .clk_list = sdm845_pciephy_clk_l, 2193 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2194 .reset_list = sdm845_pciephy_reset_l, 2195 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2196 .vreg_list = qmp_phy_vreg_l, 2197 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2198 .regs = pciephy_v3_regs_layout, 2199 2200 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2201 .phy_status = PHYSTATUS, 2202 }; 2203 2204 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 2205 .lanes = 1, 2206 2207 .tbls = { 2208 .serdes = sdm845_qhp_pcie_serdes_tbl, 2209 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 2210 .tx = sdm845_qhp_pcie_tx_tbl, 2211 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 2212 .pcs = sdm845_qhp_pcie_pcs_tbl, 2213 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 2214 }, 2215 .clk_list = sdm845_pciephy_clk_l, 2216 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2217 .reset_list = sdm845_pciephy_reset_l, 2218 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2219 .vreg_list = qmp_phy_vreg_l, 2220 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2221 .regs = sdm845_qhp_pciephy_regs_layout, 2222 2223 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2224 .phy_status = PHYSTATUS, 2225 }; 2226 2227 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 2228 .lanes = 1, 2229 2230 .tbls = { 2231 .serdes = sm8250_qmp_pcie_serdes_tbl, 2232 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2233 .tx = sm8250_qmp_pcie_tx_tbl, 2234 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2235 .rx = sm8250_qmp_pcie_rx_tbl, 2236 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2237 .pcs = sm8250_qmp_pcie_pcs_tbl, 2238 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2239 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 2240 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2241 }, 2242 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2243 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 2244 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 2245 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 2246 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 2247 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 2248 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 2249 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 2250 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 2251 }, 2252 .clk_list = sdm845_pciephy_clk_l, 2253 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2254 .reset_list = sdm845_pciephy_reset_l, 2255 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2256 .vreg_list = qmp_phy_vreg_l, 2257 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2258 .regs = pciephy_v4_regs_layout, 2259 2260 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2261 .phy_status = PHYSTATUS, 2262 }; 2263 2264 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 2265 .lanes = 2, 2266 2267 .tbls = { 2268 .serdes = sm8250_qmp_pcie_serdes_tbl, 2269 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 2270 .tx = sm8250_qmp_pcie_tx_tbl, 2271 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 2272 .rx = sm8250_qmp_pcie_rx_tbl, 2273 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 2274 .pcs = sm8250_qmp_pcie_pcs_tbl, 2275 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 2276 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 2277 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 2278 }, 2279 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2280 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 2281 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 2282 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 2283 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 2284 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 2285 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 2286 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 2287 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 2288 }, 2289 .clk_list = sdm845_pciephy_clk_l, 2290 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2291 .reset_list = sdm845_pciephy_reset_l, 2292 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2293 .vreg_list = qmp_phy_vreg_l, 2294 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2295 .regs = pciephy_v4_regs_layout, 2296 2297 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2298 .phy_status = PHYSTATUS, 2299 }; 2300 2301 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 2302 .lanes = 1, 2303 2304 .tbls = { 2305 .serdes = msm8998_pcie_serdes_tbl, 2306 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 2307 .tx = msm8998_pcie_tx_tbl, 2308 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 2309 .rx = msm8998_pcie_rx_tbl, 2310 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 2311 .pcs = msm8998_pcie_pcs_tbl, 2312 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 2313 }, 2314 .clk_list = msm8996_phy_clk_l, 2315 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 2316 .reset_list = ipq8074_pciephy_reset_l, 2317 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 2318 .vreg_list = qmp_phy_vreg_l, 2319 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2320 .regs = pciephy_v3_regs_layout, 2321 2322 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2323 .phy_status = PHYSTATUS, 2324 2325 .skip_start_delay = true, 2326 }; 2327 2328 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 2329 .lanes = 2, 2330 2331 .tbls = { 2332 .serdes = sc8180x_qmp_pcie_serdes_tbl, 2333 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 2334 .tx = sc8180x_qmp_pcie_tx_tbl, 2335 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 2336 .rx = sc8180x_qmp_pcie_rx_tbl, 2337 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 2338 .pcs = sc8180x_qmp_pcie_pcs_tbl, 2339 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 2340 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 2341 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 2342 }, 2343 .clk_list = sdm845_pciephy_clk_l, 2344 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2345 .reset_list = sdm845_pciephy_reset_l, 2346 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2347 .vreg_list = qmp_phy_vreg_l, 2348 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2349 .regs = pciephy_v4_regs_layout, 2350 2351 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2352 .phy_status = PHYSTATUS, 2353 }; 2354 2355 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 2356 .lanes = 1, 2357 2358 .offsets = &qmp_pcie_offsets_v5, 2359 2360 .tbls = { 2361 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2362 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2363 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 2364 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 2365 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 2366 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 2367 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 2368 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 2369 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 2370 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 2371 }, 2372 2373 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2374 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 2375 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 2376 }, 2377 2378 .clk_list = sc8280xp_pciephy_clk_l, 2379 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2380 .reset_list = sdm845_pciephy_reset_l, 2381 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2382 .vreg_list = qmp_phy_vreg_l, 2383 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2384 .regs = pciephy_v5_regs_layout, 2385 2386 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2387 .phy_status = PHYSTATUS, 2388 }; 2389 2390 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 2391 .lanes = 2, 2392 2393 .offsets = &qmp_pcie_offsets_v5, 2394 2395 .tbls = { 2396 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2397 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2398 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 2399 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 2400 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 2401 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 2402 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 2403 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 2404 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2405 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2406 }, 2407 2408 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2409 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 2410 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 2411 }, 2412 2413 .clk_list = sc8280xp_pciephy_clk_l, 2414 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2415 .reset_list = sdm845_pciephy_reset_l, 2416 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2417 .vreg_list = qmp_phy_vreg_l, 2418 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2419 .regs = pciephy_v5_regs_layout, 2420 2421 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2422 .phy_status = PHYSTATUS, 2423 }; 2424 2425 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 2426 .lanes = 4, 2427 2428 .offsets = &qmp_pcie_offsets_v5, 2429 2430 .tbls = { 2431 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 2432 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 2433 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 2434 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 2435 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 2436 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 2437 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 2438 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 2439 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2440 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2441 }, 2442 2443 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2444 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 2445 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 2446 }, 2447 2448 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 2449 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 2450 2451 .clk_list = sc8280xp_pciephy_clk_l, 2452 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2453 .reset_list = sdm845_pciephy_reset_l, 2454 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2455 .vreg_list = qmp_phy_vreg_l, 2456 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2457 .regs = pciephy_v5_regs_layout, 2458 2459 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2460 .phy_status = PHYSTATUS, 2461 }; 2462 2463 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 2464 .lanes = 2, 2465 2466 .tbls = { 2467 .serdes = sdx55_qmp_pcie_serdes_tbl, 2468 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 2469 .tx = sdx55_qmp_pcie_tx_tbl, 2470 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 2471 .rx = sdx55_qmp_pcie_rx_tbl, 2472 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 2473 .pcs = sdx55_qmp_pcie_pcs_tbl, 2474 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 2475 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 2476 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 2477 }, 2478 2479 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2480 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 2481 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 2482 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 2483 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 2484 }, 2485 2486 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2487 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 2488 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 2489 .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, 2490 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), 2491 }, 2492 2493 .clk_list = sdm845_pciephy_clk_l, 2494 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2495 .reset_list = sdm845_pciephy_reset_l, 2496 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2497 .vreg_list = qmp_phy_vreg_l, 2498 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2499 .regs = pciephy_v4_regs_layout, 2500 2501 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2502 .phy_status = PHYSTATUS_4_20, 2503 }; 2504 2505 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 2506 .lanes = 1, 2507 2508 .offsets = &qmp_pcie_offsets_v5, 2509 2510 .tbls = { 2511 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2512 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2513 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 2514 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 2515 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2516 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2517 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2518 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2519 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2520 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2521 }, 2522 2523 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2524 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 2525 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 2526 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 2527 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 2528 }, 2529 2530 .clk_list = sc8280xp_pciephy_clk_l, 2531 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2532 .reset_list = sdm845_pciephy_reset_l, 2533 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2534 .vreg_list = qmp_phy_vreg_l, 2535 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2536 .regs = pciephy_v5_regs_layout, 2537 2538 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2539 .phy_status = PHYSTATUS, 2540 }; 2541 2542 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 2543 .lanes = 2, 2544 2545 .offsets = &qmp_pcie_offsets_v5, 2546 2547 .tbls = { 2548 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2549 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2550 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 2551 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 2552 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2553 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2554 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2555 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2556 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 2557 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 2558 }, 2559 2560 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2561 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 2562 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 2563 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 2564 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 2565 }, 2566 2567 .clk_list = sc8280xp_pciephy_clk_l, 2568 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2569 .reset_list = sdm845_pciephy_reset_l, 2570 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2571 .vreg_list = qmp_phy_vreg_l, 2572 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2573 .regs = pciephy_v5_regs_layout, 2574 2575 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2576 .phy_status = PHYSTATUS, 2577 }; 2578 2579 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 2580 .lanes = 2, 2581 2582 .offsets = &qmp_pcie_offsets_v6_20, 2583 2584 .tbls = { 2585 .serdes = sdx65_qmp_pcie_serdes_tbl, 2586 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 2587 .tx = sdx65_qmp_pcie_tx_tbl, 2588 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 2589 .rx = sdx65_qmp_pcie_rx_tbl, 2590 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 2591 .pcs = sdx65_qmp_pcie_pcs_tbl, 2592 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 2593 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 2594 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 2595 }, 2596 .clk_list = sdm845_pciephy_clk_l, 2597 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2598 .reset_list = sdm845_pciephy_reset_l, 2599 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2600 .vreg_list = qmp_phy_vreg_l, 2601 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2602 .regs = pciephy_v5_regs_layout, 2603 2604 .pwrdn_ctrl = SW_PWRDN, 2605 .phy_status = PHYSTATUS_4_20, 2606 }; 2607 2608 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 2609 .lanes = 1, 2610 2611 .tbls = { 2612 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 2613 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 2614 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 2615 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 2616 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 2617 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 2618 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 2619 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 2620 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2621 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2622 }, 2623 2624 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2625 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 2626 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 2627 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 2628 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 2629 }, 2630 2631 .clk_list = sdm845_pciephy_clk_l, 2632 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2633 .reset_list = sdm845_pciephy_reset_l, 2634 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2635 .vreg_list = qmp_phy_vreg_l, 2636 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2637 .regs = pciephy_v5_regs_layout, 2638 2639 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2640 .phy_status = PHYSTATUS, 2641 }; 2642 2643 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 2644 .lanes = 2, 2645 2646 .tbls = { 2647 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 2648 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 2649 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 2650 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 2651 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 2652 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 2653 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 2654 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 2655 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 2656 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 2657 }, 2658 2659 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2660 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 2661 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 2662 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 2663 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 2664 }, 2665 2666 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2667 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 2668 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 2669 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 2670 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 2671 }, 2672 2673 .clk_list = sdm845_pciephy_clk_l, 2674 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2675 .reset_list = sdm845_pciephy_reset_l, 2676 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2677 .vreg_list = qmp_phy_vreg_l, 2678 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2679 .regs = pciephy_v5_regs_layout, 2680 2681 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2682 .phy_status = PHYSTATUS_4_20, 2683 }; 2684 2685 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 2686 .lanes = 2, 2687 2688 .offsets = &qmp_pcie_offsets_v5, 2689 2690 .tbls = { 2691 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 2692 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 2693 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 2694 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 2695 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 2696 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 2697 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 2698 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 2699 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 2700 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 2701 }, 2702 .clk_list = sc8280xp_pciephy_clk_l, 2703 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2704 .reset_list = sdm845_pciephy_reset_l, 2705 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2706 .vreg_list = qmp_phy_vreg_l, 2707 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2708 .regs = pciephy_v5_regs_layout, 2709 2710 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2711 .phy_status = PHYSTATUS, 2712 }; 2713 2714 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 2715 .lanes = 2, 2716 2717 .offsets = &qmp_pcie_offsets_v6_20, 2718 2719 .tbls = { 2720 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 2721 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 2722 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 2723 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 2724 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 2725 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 2726 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 2727 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 2728 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 2729 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 2730 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 2731 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 2732 }, 2733 .clk_list = sc8280xp_pciephy_clk_l, 2734 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 2735 .reset_list = sdm845_pciephy_reset_l, 2736 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2737 .vreg_list = sm8550_qmp_phy_vreg_l, 2738 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 2739 .regs = pciephy_v5_regs_layout, 2740 2741 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2742 .phy_status = PHYSTATUS_4_20, 2743 .has_nocsr_reset = true, 2744 }; 2745 2746 static void qmp_pcie_configure_lane(void __iomem *base, 2747 const struct qmp_phy_init_tbl tbl[], 2748 int num, 2749 u8 lane_mask) 2750 { 2751 int i; 2752 const struct qmp_phy_init_tbl *t = tbl; 2753 2754 if (!t) 2755 return; 2756 2757 for (i = 0; i < num; i++, t++) { 2758 if (!(t->lane_mask & lane_mask)) 2759 continue; 2760 2761 writel(t->val, base + t->offset); 2762 } 2763 } 2764 2765 static void qmp_pcie_configure(void __iomem *base, 2766 const struct qmp_phy_init_tbl tbl[], 2767 int num) 2768 { 2769 qmp_pcie_configure_lane(base, tbl, num, 0xff); 2770 } 2771 2772 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2773 { 2774 const struct qmp_phy_cfg *cfg = qmp->cfg; 2775 const struct qmp_pcie_offsets *offs = cfg->offsets; 2776 void __iomem *tx3, *rx3, *tx4, *rx4; 2777 2778 tx3 = qmp->port_b + offs->tx; 2779 rx3 = qmp->port_b + offs->rx; 2780 tx4 = qmp->port_b + offs->tx2; 2781 rx4 = qmp->port_b + offs->rx2; 2782 2783 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); 2784 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); 2785 2786 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); 2787 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); 2788 } 2789 2790 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2791 { 2792 const struct qmp_phy_cfg *cfg = qmp->cfg; 2793 void __iomem *serdes = qmp->serdes; 2794 void __iomem *tx = qmp->tx; 2795 void __iomem *rx = qmp->rx; 2796 void __iomem *tx2 = qmp->tx2; 2797 void __iomem *rx2 = qmp->rx2; 2798 void __iomem *pcs = qmp->pcs; 2799 void __iomem *pcs_misc = qmp->pcs_misc; 2800 void __iomem *ln_shrd = qmp->ln_shrd; 2801 2802 if (!tbls) 2803 return; 2804 2805 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 2806 2807 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 2808 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 2809 2810 if (cfg->lanes >= 2) { 2811 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 2812 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 2813 } 2814 2815 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 2816 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 2817 2818 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2819 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 2820 qmp_pcie_init_port_b(qmp, tbls); 2821 } 2822 2823 qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 2824 } 2825 2826 static int qmp_pcie_init(struct phy *phy) 2827 { 2828 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2829 const struct qmp_phy_cfg *cfg = qmp->cfg; 2830 int ret; 2831 2832 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2833 if (ret) { 2834 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2835 return ret; 2836 } 2837 2838 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2839 if (ret) { 2840 dev_err(qmp->dev, "reset assert failed\n"); 2841 goto err_disable_regulators; 2842 } 2843 2844 ret = reset_control_assert(qmp->nocsr_reset); 2845 if (ret) { 2846 dev_err(qmp->dev, "no-csr reset assert failed\n"); 2847 goto err_assert_reset; 2848 } 2849 2850 usleep_range(200, 300); 2851 2852 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2853 if (ret) { 2854 dev_err(qmp->dev, "reset deassert failed\n"); 2855 goto err_assert_reset; 2856 } 2857 2858 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2859 if (ret) 2860 goto err_assert_reset; 2861 2862 return 0; 2863 2864 err_assert_reset: 2865 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2866 err_disable_regulators: 2867 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2868 2869 return ret; 2870 } 2871 2872 static int qmp_pcie_exit(struct phy *phy) 2873 { 2874 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2875 const struct qmp_phy_cfg *cfg = qmp->cfg; 2876 2877 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2878 2879 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2880 2881 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2882 2883 return 0; 2884 } 2885 2886 static int qmp_pcie_power_on(struct phy *phy) 2887 { 2888 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2889 const struct qmp_phy_cfg *cfg = qmp->cfg; 2890 const struct qmp_phy_cfg_tbls *mode_tbls; 2891 void __iomem *pcs = qmp->pcs; 2892 void __iomem *status; 2893 unsigned int mask, val; 2894 int ret; 2895 2896 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2897 cfg->pwrdn_ctrl); 2898 2899 if (qmp->mode == PHY_MODE_PCIE_RC) 2900 mode_tbls = cfg->tbls_rc; 2901 else 2902 mode_tbls = cfg->tbls_ep; 2903 2904 qmp_pcie_init_registers(qmp, &cfg->tbls); 2905 qmp_pcie_init_registers(qmp, mode_tbls); 2906 2907 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 2908 if (ret) 2909 return ret; 2910 2911 ret = reset_control_deassert(qmp->nocsr_reset); 2912 if (ret) { 2913 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 2914 goto err_disable_pipe_clk; 2915 } 2916 2917 /* Pull PHY out of reset state */ 2918 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2919 2920 /* start SerDes and Phy-Coding-Sublayer */ 2921 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2922 2923 if (!cfg->skip_start_delay) 2924 usleep_range(1000, 1200); 2925 2926 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2927 mask = cfg->phy_status; 2928 ret = readl_poll_timeout(status, val, !(val & mask), 200, 2929 PHY_INIT_COMPLETE_TIMEOUT); 2930 if (ret) { 2931 dev_err(qmp->dev, "phy initialization timed-out\n"); 2932 goto err_disable_pipe_clk; 2933 } 2934 2935 return 0; 2936 2937 err_disable_pipe_clk: 2938 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2939 2940 return ret; 2941 } 2942 2943 static int qmp_pcie_power_off(struct phy *phy) 2944 { 2945 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2946 const struct qmp_phy_cfg *cfg = qmp->cfg; 2947 2948 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2949 2950 /* PHY reset */ 2951 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2952 2953 /* stop SerDes and Phy-Coding-Sublayer */ 2954 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2955 SERDES_START | PCS_START); 2956 2957 /* Put PHY into POWER DOWN state: active low */ 2958 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2959 cfg->pwrdn_ctrl); 2960 2961 return 0; 2962 } 2963 2964 static int qmp_pcie_enable(struct phy *phy) 2965 { 2966 int ret; 2967 2968 ret = qmp_pcie_init(phy); 2969 if (ret) 2970 return ret; 2971 2972 ret = qmp_pcie_power_on(phy); 2973 if (ret) 2974 qmp_pcie_exit(phy); 2975 2976 return ret; 2977 } 2978 2979 static int qmp_pcie_disable(struct phy *phy) 2980 { 2981 int ret; 2982 2983 ret = qmp_pcie_power_off(phy); 2984 if (ret) 2985 return ret; 2986 2987 return qmp_pcie_exit(phy); 2988 } 2989 2990 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2991 { 2992 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2993 2994 switch (submode) { 2995 case PHY_MODE_PCIE_RC: 2996 case PHY_MODE_PCIE_EP: 2997 qmp->mode = submode; 2998 break; 2999 default: 3000 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 3001 return -EINVAL; 3002 } 3003 3004 return 0; 3005 } 3006 3007 static const struct phy_ops qmp_pcie_phy_ops = { 3008 .power_on = qmp_pcie_enable, 3009 .power_off = qmp_pcie_disable, 3010 .set_mode = qmp_pcie_set_mode, 3011 .owner = THIS_MODULE, 3012 }; 3013 3014 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 3015 { 3016 const struct qmp_phy_cfg *cfg = qmp->cfg; 3017 struct device *dev = qmp->dev; 3018 int num = cfg->num_vregs; 3019 int i; 3020 3021 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 3022 if (!qmp->vregs) 3023 return -ENOMEM; 3024 3025 for (i = 0; i < num; i++) 3026 qmp->vregs[i].supply = cfg->vreg_list[i]; 3027 3028 return devm_regulator_bulk_get(dev, num, qmp->vregs); 3029 } 3030 3031 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 3032 { 3033 const struct qmp_phy_cfg *cfg = qmp->cfg; 3034 struct device *dev = qmp->dev; 3035 int i; 3036 int ret; 3037 3038 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 3039 sizeof(*qmp->resets), GFP_KERNEL); 3040 if (!qmp->resets) 3041 return -ENOMEM; 3042 3043 for (i = 0; i < cfg->num_resets; i++) 3044 qmp->resets[i].id = cfg->reset_list[i]; 3045 3046 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 3047 if (ret) 3048 return dev_err_probe(dev, ret, "failed to get resets\n"); 3049 3050 if (cfg->has_nocsr_reset) { 3051 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); 3052 if (IS_ERR(qmp->nocsr_reset)) 3053 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 3054 "failed to get no-csr reset\n"); 3055 } 3056 3057 return 0; 3058 } 3059 3060 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 3061 { 3062 const struct qmp_phy_cfg *cfg = qmp->cfg; 3063 struct device *dev = qmp->dev; 3064 int num = cfg->num_clks; 3065 int i; 3066 3067 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3068 if (!qmp->clks) 3069 return -ENOMEM; 3070 3071 for (i = 0; i < num; i++) 3072 qmp->clks[i].id = cfg->clk_list[i]; 3073 3074 return devm_clk_bulk_get(dev, num, qmp->clks); 3075 } 3076 3077 static void phy_clk_release_provider(void *res) 3078 { 3079 of_clk_del_provider(res); 3080 } 3081 3082 /* 3083 * Register a fixed rate pipe clock. 3084 * 3085 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3086 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3087 * by the PHY driver for its operations. 3088 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3089 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3090 * Below picture shows this relationship. 3091 * 3092 * +---------------+ 3093 * | PHY block |<<---------------------------------------+ 3094 * | | | 3095 * | +-------+ | +-----+ | 3096 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3097 * clk | +-------+ | +-----+ 3098 * +---------------+ 3099 */ 3100 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 3101 { 3102 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3103 struct clk_init_data init = { }; 3104 int ret; 3105 3106 ret = of_property_read_string(np, "clock-output-names", &init.name); 3107 if (ret) { 3108 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 3109 return ret; 3110 } 3111 3112 init.ops = &clk_fixed_rate_ops; 3113 3114 /* 3115 * Controllers using QMP PHY-s use 125MHz pipe clock interface 3116 * unless other frequency is specified in the PHY config. 3117 */ 3118 if (qmp->cfg->pipe_clock_rate) 3119 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 3120 else 3121 fixed->fixed_rate = 125000000; 3122 3123 fixed->hw.init = &init; 3124 3125 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 3126 if (ret) 3127 return ret; 3128 3129 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 3130 if (ret) 3131 return ret; 3132 3133 /* 3134 * Roll a devm action because the clock provider is the child node, but 3135 * the child node is not actually a device. 3136 */ 3137 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 3138 } 3139 3140 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 3141 { 3142 struct platform_device *pdev = to_platform_device(qmp->dev); 3143 const struct qmp_phy_cfg *cfg = qmp->cfg; 3144 struct device *dev = qmp->dev; 3145 struct clk *clk; 3146 3147 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3148 if (IS_ERR(qmp->serdes)) 3149 return PTR_ERR(qmp->serdes); 3150 3151 /* 3152 * Get memory resources for the PHY: 3153 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 3154 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 3155 * For single lane PHYs: pcs_misc (optional) -> 3. 3156 */ 3157 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3158 if (IS_ERR(qmp->tx)) 3159 return PTR_ERR(qmp->tx); 3160 3161 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 3162 qmp->rx = qmp->tx; 3163 else 3164 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3165 if (IS_ERR(qmp->rx)) 3166 return PTR_ERR(qmp->rx); 3167 3168 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3169 if (IS_ERR(qmp->pcs)) 3170 return PTR_ERR(qmp->pcs); 3171 3172 if (cfg->lanes >= 2) { 3173 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3174 if (IS_ERR(qmp->tx2)) 3175 return PTR_ERR(qmp->tx2); 3176 3177 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3178 if (IS_ERR(qmp->rx2)) 3179 return PTR_ERR(qmp->rx2); 3180 3181 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3182 } else { 3183 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 3184 } 3185 3186 if (IS_ERR(qmp->pcs_misc) && 3187 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 3188 qmp->pcs_misc = qmp->pcs + 0x400; 3189 3190 if (IS_ERR(qmp->pcs_misc)) { 3191 if (cfg->tbls.pcs_misc || 3192 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 3193 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 3194 return PTR_ERR(qmp->pcs_misc); 3195 } 3196 } 3197 3198 clk = devm_get_clk_from_child(dev, np, NULL); 3199 if (IS_ERR(clk)) { 3200 return dev_err_probe(dev, PTR_ERR(clk), 3201 "failed to get pipe clock\n"); 3202 } 3203 3204 qmp->num_pipe_clks = 1; 3205 qmp->pipe_clks[0].id = "pipe"; 3206 qmp->pipe_clks[0].clk = clk; 3207 3208 return 0; 3209 } 3210 3211 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 3212 { 3213 struct regmap *tcsr; 3214 unsigned int args[2]; 3215 int ret; 3216 3217 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 3218 "qcom,4ln-config-sel", 3219 ARRAY_SIZE(args), args); 3220 if (IS_ERR(tcsr)) { 3221 ret = PTR_ERR(tcsr); 3222 if (ret == -ENOENT) 3223 return 0; 3224 3225 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 3226 return ret; 3227 } 3228 3229 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 3230 if (ret < 0) { 3231 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 3232 return ret; 3233 } 3234 3235 qmp->tcsr_4ln_config = ret; 3236 3237 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 3238 3239 return 0; 3240 } 3241 3242 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 3243 { 3244 struct platform_device *pdev = to_platform_device(qmp->dev); 3245 const struct qmp_phy_cfg *cfg = qmp->cfg; 3246 const struct qmp_pcie_offsets *offs = cfg->offsets; 3247 struct device *dev = qmp->dev; 3248 void __iomem *base; 3249 int ret; 3250 3251 if (!offs) 3252 return -EINVAL; 3253 3254 ret = qmp_pcie_get_4ln_config(qmp); 3255 if (ret) 3256 return ret; 3257 3258 base = devm_platform_ioremap_resource(pdev, 0); 3259 if (IS_ERR(base)) 3260 return PTR_ERR(base); 3261 3262 qmp->serdes = base + offs->serdes; 3263 qmp->pcs = base + offs->pcs; 3264 qmp->pcs_misc = base + offs->pcs_misc; 3265 qmp->tx = base + offs->tx; 3266 qmp->rx = base + offs->rx; 3267 3268 if (cfg->lanes >= 2) { 3269 qmp->tx2 = base + offs->tx2; 3270 qmp->rx2 = base + offs->rx2; 3271 } 3272 3273 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 3274 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 3275 if (IS_ERR(qmp->port_b)) 3276 return PTR_ERR(qmp->port_b); 3277 } 3278 3279 if (cfg->tbls.ln_shrd) 3280 qmp->ln_shrd = base + offs->ln_shrd; 3281 3282 qmp->num_pipe_clks = 2; 3283 qmp->pipe_clks[0].id = "pipe"; 3284 qmp->pipe_clks[1].id = "pipediv2"; 3285 3286 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 3287 if (ret) 3288 return ret; 3289 3290 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 3291 if (ret) 3292 return ret; 3293 3294 return 0; 3295 } 3296 3297 static int qmp_pcie_probe(struct platform_device *pdev) 3298 { 3299 struct device *dev = &pdev->dev; 3300 struct phy_provider *phy_provider; 3301 struct device_node *np; 3302 struct qmp_pcie *qmp; 3303 int ret; 3304 3305 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3306 if (!qmp) 3307 return -ENOMEM; 3308 3309 qmp->dev = dev; 3310 3311 qmp->cfg = of_device_get_match_data(dev); 3312 if (!qmp->cfg) 3313 return -EINVAL; 3314 3315 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 3316 WARN_ON_ONCE(!qmp->cfg->phy_status); 3317 3318 ret = qmp_pcie_clk_init(qmp); 3319 if (ret) 3320 return ret; 3321 3322 ret = qmp_pcie_reset_init(qmp); 3323 if (ret) 3324 return ret; 3325 3326 ret = qmp_pcie_vreg_init(qmp); 3327 if (ret) 3328 return ret; 3329 3330 /* Check for legacy binding with child node. */ 3331 np = of_get_next_available_child(dev->of_node, NULL); 3332 if (np) { 3333 ret = qmp_pcie_parse_dt_legacy(qmp, np); 3334 } else { 3335 np = of_node_get(dev->of_node); 3336 ret = qmp_pcie_parse_dt(qmp); 3337 } 3338 if (ret) 3339 goto err_node_put; 3340 3341 ret = phy_pipe_clk_register(qmp, np); 3342 if (ret) 3343 goto err_node_put; 3344 3345 qmp->mode = PHY_MODE_PCIE_RC; 3346 3347 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 3348 if (IS_ERR(qmp->phy)) { 3349 ret = PTR_ERR(qmp->phy); 3350 dev_err(dev, "failed to create PHY: %d\n", ret); 3351 goto err_node_put; 3352 } 3353 3354 phy_set_drvdata(qmp->phy, qmp); 3355 3356 of_node_put(np); 3357 3358 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3359 3360 return PTR_ERR_OR_ZERO(phy_provider); 3361 3362 err_node_put: 3363 of_node_put(np); 3364 return ret; 3365 } 3366 3367 static const struct of_device_id qmp_pcie_of_match_table[] = { 3368 { 3369 .compatible = "qcom,ipq6018-qmp-pcie-phy", 3370 .data = &ipq6018_pciephy_cfg, 3371 }, { 3372 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 3373 .data = &ipq8074_pciephy_gen3_cfg, 3374 }, { 3375 .compatible = "qcom,ipq8074-qmp-pcie-phy", 3376 .data = &ipq8074_pciephy_cfg, 3377 }, { 3378 .compatible = "qcom,msm8998-qmp-pcie-phy", 3379 .data = &msm8998_pciephy_cfg, 3380 }, { 3381 .compatible = "qcom,sc8180x-qmp-pcie-phy", 3382 .data = &sc8180x_pciephy_cfg, 3383 }, { 3384 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 3385 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 3386 }, { 3387 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 3388 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 3389 }, { 3390 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 3391 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 3392 }, { 3393 .compatible = "qcom,sdm845-qhp-pcie-phy", 3394 .data = &sdm845_qhp_pciephy_cfg, 3395 }, { 3396 .compatible = "qcom,sdm845-qmp-pcie-phy", 3397 .data = &sdm845_qmp_pciephy_cfg, 3398 }, { 3399 .compatible = "qcom,sdx55-qmp-pcie-phy", 3400 .data = &sdx55_qmp_pciephy_cfg, 3401 }, { 3402 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 3403 .data = &sdx65_qmp_pciephy_cfg, 3404 }, { 3405 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 3406 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 3407 }, { 3408 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 3409 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 3410 }, { 3411 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 3412 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 3413 }, { 3414 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 3415 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 3416 }, { 3417 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 3418 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 3419 }, { 3420 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 3421 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 3422 }, { 3423 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 3424 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 3425 }, { 3426 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 3427 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 3428 }, { 3429 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 3430 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 3431 }, 3432 { }, 3433 }; 3434 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 3435 3436 static struct platform_driver qmp_pcie_driver = { 3437 .probe = qmp_pcie_probe, 3438 .driver = { 3439 .name = "qcom-qmp-pcie-phy", 3440 .of_match_table = qmp_pcie_of_match_table, 3441 }, 3442 }; 3443 3444 module_platform_driver(qmp_pcie_driver); 3445 3446 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3447 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 3448 MODULE_LICENSE("GPL v2"); 3449