1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/reset.h> 23 #include <linux/slab.h> 24 25 #include <dt-bindings/phy/phy-qcom-qmp.h> 26 27 #include "phy-qcom-qmp-common.h" 28 29 #include "phy-qcom-qmp.h" 30 #include "phy-qcom-qmp-pcs-misc-v3.h" 31 #include "phy-qcom-qmp-pcs-pcie-v4.h" 32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 33 #include "phy-qcom-qmp-pcs-pcie-v5.h" 34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 35 #include "phy-qcom-qmp-pcs-pcie-v6.h" 36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h" 37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h" 38 #include "phy-qcom-qmp-pcs-v6_30.h" 39 #include "phy-qcom-qmp-pcie-qhp.h" 40 41 #define PHY_INIT_COMPLETE_TIMEOUT 10000 42 43 /* set of registers with offsets different per-PHY */ 44 enum qphy_reg_layout { 45 /* PCS registers */ 46 QPHY_SW_RESET, 47 QPHY_START_CTRL, 48 QPHY_PCS_STATUS, 49 QPHY_PCS_POWER_DOWN_CONTROL, 50 /* Keep last to ensure regs_layout arrays are properly initialized */ 51 QPHY_LAYOUT_SIZE 52 }; 53 54 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 55 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 56 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 57 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, 58 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 59 }; 60 61 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 62 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 63 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 64 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 65 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 66 }; 67 68 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 69 [QPHY_SW_RESET] = 0x00, 70 [QPHY_START_CTRL] = 0x08, 71 [QPHY_PCS_STATUS] = 0x2ac, 72 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 73 }; 74 75 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 76 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 77 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 78 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 79 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 80 }; 81 82 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 83 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 84 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 85 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 86 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 87 }; 88 89 static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 90 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 91 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 92 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 93 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 94 }; 95 96 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 97 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 98 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 99 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 100 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 101 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 102 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 103 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 104 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 105 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 106 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 107 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 108 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 109 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 110 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 111 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 112 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 139 }; 140 141 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 142 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 144 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 145 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 146 }; 147 148 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 159 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 160 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 161 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 162 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 163 }; 164 165 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 176 }; 177 178 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 179 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 180 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 181 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 182 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 183 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 184 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 185 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 186 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 187 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 188 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 189 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 190 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 191 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 192 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 193 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 194 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 195 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 225 }; 226 227 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 228 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 229 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 230 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 231 }; 232 233 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 264 }; 265 266 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 267 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 268 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 269 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 270 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 271 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 272 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 273 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 274 }; 275 276 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 286 }; 287 288 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 289 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 290 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 291 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 292 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 293 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 294 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 295 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 296 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 297 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 298 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 299 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 300 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 301 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 302 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 303 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 304 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 305 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 306 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 307 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 308 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 309 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 310 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 311 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 312 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 313 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 314 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 315 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 316 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 317 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 318 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 319 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 320 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 321 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 322 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 323 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 324 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 325 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 326 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 329 }; 330 331 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 332 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 333 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 334 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 335 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 336 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 337 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 338 }; 339 340 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 341 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 342 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 343 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 344 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 345 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 346 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 347 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 348 }; 349 350 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 351 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 352 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 353 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 354 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 355 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 356 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 361 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 362 }; 363 364 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 365 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 366 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 367 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 368 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 369 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 370 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 371 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 372 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 373 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 374 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 375 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 376 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 377 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 378 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 379 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 380 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 381 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 422 }; 423 424 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 425 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 426 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 427 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 428 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 429 }; 430 431 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 462 }; 463 464 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 465 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 466 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 467 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 468 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 469 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 470 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 471 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 472 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 473 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 474 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 475 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 476 }; 477 478 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 492 }; 493 494 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { 495 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 496 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 497 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 498 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 499 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 500 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 501 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 502 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 503 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 504 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 505 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 506 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 507 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 508 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 509 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 510 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 511 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 512 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 513 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 514 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 515 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 516 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 517 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 518 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 519 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 521 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 522 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 523 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 524 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 525 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 526 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 527 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 528 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 529 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 530 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 531 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 532 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 533 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 534 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 535 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 536 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 537 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 538 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 539 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 540 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 541 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 542 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 543 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 544 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 545 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 546 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 547 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 548 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 549 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 550 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 551 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 554 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 555 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 556 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 557 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 558 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 559 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 560 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 561 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 562 }; 563 564 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = { 565 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 566 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 567 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 568 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 569 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 570 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 571 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 572 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 573 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 574 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 575 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 576 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 577 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 578 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 579 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 580 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 581 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 582 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 583 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 584 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 585 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 586 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 587 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 588 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 589 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00), 590 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 591 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 592 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 593 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 594 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 595 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a), 596 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 597 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 598 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 599 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 600 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a), 601 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 602 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 603 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 604 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 605 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 606 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 607 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 608 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 609 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 610 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 611 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 613 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 614 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 615 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 616 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 617 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 618 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01), 619 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 620 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 621 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00), 622 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00), 623 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 624 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 625 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 626 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 627 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 628 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 629 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 630 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89), 631 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10), 632 }; 633 634 static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = { 635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 640 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73), 647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80), 648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00), 654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 665 }; 666 667 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = { 668 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 669 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 670 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 671 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 672 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 673 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 674 }; 675 676 static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = { 677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14), 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06), 694 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 695 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 696 }; 697 698 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = { 699 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 700 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 701 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 702 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 703 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 705 }; 706 707 static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = { 708 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 709 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 710 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 711 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 712 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 713 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 714 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14), 715 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10), 716 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b), 717 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00), 718 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58), 719 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 720 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00), 721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19), 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49), 725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a), 726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02), 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 729 }; 730 731 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 732 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 733 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 734 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 735 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 736 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 737 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 738 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 739 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 740 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 741 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 742 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 743 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 744 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 745 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 746 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 747 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 748 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 749 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 750 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 751 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 752 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 753 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 754 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 755 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 756 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 757 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 758 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 759 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 760 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 761 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 762 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 763 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 764 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 765 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 766 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 767 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 768 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 769 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 770 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 771 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 772 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 773 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 774 }; 775 776 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 777 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 778 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 779 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 780 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 781 }; 782 783 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 784 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 785 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 786 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 787 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 788 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 789 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 790 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 791 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 792 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 793 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 794 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 795 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 796 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 797 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 798 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 799 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 800 }; 801 802 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 803 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 804 805 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 806 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 807 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 808 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 809 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 810 811 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 812 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 813 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 814 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 815 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 816 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 817 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 818 819 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 820 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 821 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 822 823 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 824 }; 825 826 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 827 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 828 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 829 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 830 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 831 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 832 }; 833 834 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 835 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 836 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 837 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 838 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 839 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 840 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 841 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 842 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 843 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 844 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 845 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 846 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 847 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 848 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 849 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 850 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 851 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 852 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 853 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 854 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 855 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 856 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 857 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 858 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 859 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 860 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 861 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 862 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 863 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 864 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 865 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 866 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 867 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 868 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 869 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 870 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 871 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 872 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 873 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 874 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 875 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 876 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 877 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 878 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 879 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 880 }; 881 882 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 883 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 884 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 885 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 886 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 887 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 888 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 889 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 890 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 891 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 892 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 893 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 894 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 895 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 896 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 897 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 898 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 899 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 900 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 901 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 902 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 903 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 904 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 905 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 906 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 907 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 908 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 909 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 910 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 911 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 912 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 913 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 914 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 915 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 916 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 917 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 918 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 919 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 920 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 921 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 922 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 923 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 924 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 925 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 926 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 927 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 928 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 929 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 930 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 931 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 932 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 933 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 934 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 935 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 936 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 937 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 938 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 939 }; 940 941 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 942 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 943 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 944 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 945 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 946 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 947 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 948 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 949 }; 950 951 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 952 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 994 }; 995 996 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 997 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 998 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 999 }; 1000 1001 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1038 }; 1039 1040 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 1041 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1042 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1043 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1044 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1045 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 1046 }; 1047 1048 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 1049 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1050 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1051 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1052 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1053 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1054 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1055 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1056 }; 1057 1058 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 1059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1100 }; 1101 1102 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1104 }; 1105 1106 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1108 }; 1109 1110 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1112 }; 1113 1114 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 1115 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1120 }; 1121 1122 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 1123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1141 }; 1142 1143 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 1144 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1145 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1146 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1147 }; 1148 1149 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1150 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1151 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1152 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1153 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1154 }; 1155 1156 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 1157 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 1158 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1163 }; 1164 1165 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1183 }; 1184 1185 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 1186 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1187 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 1188 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1189 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 1190 }; 1191 1192 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1193 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 1194 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1195 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1196 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1197 }; 1198 1199 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = { 1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 1208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1227 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1235 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1236 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1242 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1243 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1244 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1245 }; 1246 1247 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = { 1248 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1249 }; 1250 1251 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 1252 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1253 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1254 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1255 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1256 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4), 1257 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1258 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1259 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1260 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32), 1261 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1262 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1263 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1264 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1265 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1266 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1267 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1268 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1269 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1270 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1271 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1272 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1273 }; 1274 1275 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = { 1276 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 1277 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 1278 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1279 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1280 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1281 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1282 }; 1283 1284 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = { 1285 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1286 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1287 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1288 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1289 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1290 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1291 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1292 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1293 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01), 1294 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01), 1295 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1296 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1), 1297 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2), 1298 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1299 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1300 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1301 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1302 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1303 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1), 1304 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2), 1305 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1306 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 1307 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 1308 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1309 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1310 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 1311 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1312 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1313 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4), 1314 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4), 1315 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1316 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1317 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b), 1318 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1319 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1320 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1321 }; 1322 1323 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = { 1324 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 1325 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 1326 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 1327 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 1328 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 1329 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 1330 }; 1331 1332 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1333 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1334 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 1335 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 1336 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 1337 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 1338 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 1339 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 1340 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 1341 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 1342 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 1343 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 1344 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18), 1345 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1346 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1347 }; 1348 1349 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_serdes_tbl[] = { 1350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 1351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 1353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x08), 1356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x04), 1357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0d), 1358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 1359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 1360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 1361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 1362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 1363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 1364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 1370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 1371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 1373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 1374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1380 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 1381 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c), 1382 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 1383 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 1384 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1385 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 1386 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 1387 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1388 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1389 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 1390 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 1391 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 1392 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 1393 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 1394 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 1395 }; 1396 1397 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl[] = { 1398 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 1399 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 1400 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88), 1401 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 1402 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 1403 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 1404 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 1405 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 1406 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 1407 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 1408 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 1409 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 1410 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1411 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1412 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1413 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1414 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1415 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1416 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1417 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1418 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1419 }; 1420 1421 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_txz_tbl[] = { 1422 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1423 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x05), 1424 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 1425 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 1428 }; 1429 1430 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rxz_tbl[] = { 1431 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 1432 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 1433 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 1435 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0c), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 1443 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1444 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 1445 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 1446 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1447 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39), 1448 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd4), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0x23), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 1451 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 1452 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x38), 1453 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 1454 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 1455 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x1c), 1456 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xe4), 1457 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 1458 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 1459 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x69), 1460 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 1461 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 1462 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 1463 }; 1464 1465 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_rx_tbl[] = { 1466 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, BIT(0)), 1467 }; 1468 1469 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_tbl[] = { 1470 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_LOCK_DETECT_CONFIG2, 0x00), 1471 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_G3S2_PRE_GAIN, 0x2e), 1472 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_RX_SIGDET_LVL, 0x99), 1473 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_ALIGN_DETECT_CONFIG7, 0x00), 1474 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG4, 0x00), 1475 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_EQ_CONFIG5, 0x22), 1476 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG, 0x04), 1477 QMP_PHY_INIT_CFG(QPHY_V6_30_PCS_TX_RX_CONFIG2, 0x02), 1478 }; 1479 1480 static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl[] = { 1481 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 1482 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS, 0x00), 1483 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_EQ_CONFIG1, 0x16), 1484 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5, 0x02), 1485 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN, 0x2e), 1486 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1, 0x03), 1487 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3, 0x28), 1488 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5, 0x18), 1489 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5, 0x7a), 1490 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5, 0x8a), 1491 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME, 0x27), 1492 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME, 0x27), 1493 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG, 0xc0), 1494 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2, 0x1d), 1495 }; 1496 1497 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 1498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 1501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 1503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 1504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 1505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 1506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 1509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 1510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 1511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 1512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 1513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1518 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1519 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1520 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1539 }; 1540 1541 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1543 }; 1544 1545 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1546 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1547 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1548 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1549 }; 1550 1551 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1563 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1564 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1582 }; 1583 1584 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1591 }; 1592 1593 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1594 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1595 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1596 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1597 }; 1598 1599 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1600 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1601 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1602 }; 1603 1604 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1605 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1606 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1607 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1608 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1609 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1612 }; 1613 1614 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1617 }; 1618 1619 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1620 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1621 }; 1622 1623 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1628 }; 1629 1630 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1631 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1632 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1633 }; 1634 1635 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1638 }; 1639 1640 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1655 }; 1656 1657 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = { 1658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce), 1662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b), 1663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a), 1667 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10), 1668 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1669 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1670 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1671 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1672 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1673 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1674 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 1675 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04), 1676 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d), 1677 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a), 1678 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a), 1679 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3), 1680 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0), 1681 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05), 1682 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), 1683 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), 1684 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), 1685 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 1686 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1687 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1688 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8), 1689 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20), 1690 }; 1691 1692 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = { 1693 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1694 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1695 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1696 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1697 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1698 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1699 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1700 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1701 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1702 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1703 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1704 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1705 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1706 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1707 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1708 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1709 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1710 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1711 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1712 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1713 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1714 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1718 }; 1719 1720 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1721 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1722 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1723 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1724 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1725 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1726 }; 1727 1728 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1729 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1730 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1731 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1732 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1733 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1734 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1735 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1736 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1737 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1738 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1739 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1740 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1741 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1742 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1743 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1744 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1745 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1746 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1747 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1748 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1749 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1750 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1751 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1752 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1753 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1754 }; 1755 1756 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1757 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1758 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1759 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1760 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1761 }; 1762 1763 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1764 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1765 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1766 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1767 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1768 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1769 }; 1770 1771 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = { 1772 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1773 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1774 }; 1775 1776 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = { 1777 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1778 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1779 }; 1780 1781 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = { 1782 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1783 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1784 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1785 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1786 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1787 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1788 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1789 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1790 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1791 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1792 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1793 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1794 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1795 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1796 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1797 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1798 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1799 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1800 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1801 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1802 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1803 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1804 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1805 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1806 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1807 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1808 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1809 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1810 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1811 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1812 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1813 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1814 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00), 1815 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1816 }; 1817 1818 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = { 1819 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1820 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1821 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00), 1822 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00), 1823 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00), 1824 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1825 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1826 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12), 1827 }; 1828 1829 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = { 1830 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1831 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06), 1832 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06), 1833 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e), 1834 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e), 1835 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1836 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1837 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02), 1838 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d), 1839 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44), 1840 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00), 1841 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 1842 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1843 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74), 1844 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 1845 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c), 1846 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03), 1847 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 1848 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04), 1849 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1850 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1851 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1852 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64), 1853 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1854 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1855 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1856 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c), 1857 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1858 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1859 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1860 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1861 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1862 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1863 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1864 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1865 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1866 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1867 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1868 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1869 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1870 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1871 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1872 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1873 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00), 1874 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1875 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1876 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1877 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1878 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac), 1879 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1880 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1881 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07), 1882 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1883 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 1884 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5), 1885 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee), 1886 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1887 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1888 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1889 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1890 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1891 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28), 1892 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1893 }; 1894 1895 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = { 1896 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 1897 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa), 1898 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d), 1899 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 1900 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 1901 }; 1902 1903 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = { 1904 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1905 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1906 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1907 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d), 1908 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1909 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1910 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1911 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1912 }; 1913 1914 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = { 1915 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1916 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1917 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1918 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1919 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1920 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1921 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1922 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1923 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1927 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1928 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1929 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1939 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1940 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1945 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1946 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1947 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1956 }; 1957 1958 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 1959 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1960 }; 1961 1962 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1963 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1964 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1965 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1966 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1967 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1968 }; 1969 1970 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = { 1971 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1972 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1973 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1974 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1975 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1976 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1977 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1978 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1979 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1980 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1981 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1982 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1983 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1984 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1985 }; 1986 1987 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = { 1988 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1989 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1990 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1991 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1992 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1993 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1994 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1995 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1996 }; 1997 1998 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = { 1999 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 2000 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 2001 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 2002 }; 2003 2004 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 2005 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2006 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 2007 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 2008 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2009 }; 2010 2011 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = { 2012 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 2013 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 2014 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2015 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2016 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2017 }; 2018 2019 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = { 2020 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 2021 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 2022 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 2023 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 2024 }; 2025 2026 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = { 2027 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 2028 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 2029 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 2030 }; 2031 2032 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = { 2033 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 2034 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 2035 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 2036 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 2037 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2038 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2039 }; 2040 2041 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = { 2042 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f), 2043 }; 2044 2045 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 2046 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2047 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2048 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2049 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2050 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2051 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2052 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2053 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2059 }; 2060 2061 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 2062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 2090 }; 2091 2092 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 2093 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2094 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2095 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 2096 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 2097 }; 2098 2099 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 2100 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2101 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2102 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 2103 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 2104 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 2105 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 2106 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2107 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 2108 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 2109 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 2110 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 2111 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 2112 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 2113 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 2114 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 2115 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 2116 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 2117 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 2118 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 2119 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 2120 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 2121 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2122 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2123 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2124 2125 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 2126 2127 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2128 2129 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2130 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2131 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2132 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2133 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2134 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2135 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2136 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2137 2138 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2139 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 2140 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2141 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2142 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2143 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2144 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 2145 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2146 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2147 }; 2148 2149 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 2150 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2151 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2152 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2153 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99), 2154 }; 2155 2156 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2157 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2158 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2159 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2160 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2161 }; 2162 2163 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 2164 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2165 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2166 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 2167 }; 2168 2169 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 2170 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2171 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2172 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2173 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2174 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2175 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2176 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2177 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2178 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2179 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2180 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2181 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2182 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2183 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2184 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2185 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2190 }; 2191 2192 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 2193 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 2194 }; 2195 2196 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = { 2197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93), 2203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 2207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 2208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 2209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), 2216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34), 2222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 2226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 2227 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 2228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 2231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 2233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), 2234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2235 }; 2236 2237 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = { 2238 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15), 2239 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 2240 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02), 2241 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 2242 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18), 2243 }; 2244 2245 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = { 2246 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2247 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), 2248 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), 2249 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), 2250 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), 2251 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), 2252 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 2253 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 2254 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 2255 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), 2256 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), 2257 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 2258 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), 2259 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), 2260 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), 2261 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), 2262 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00), 2263 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), 2264 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), 2265 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 2266 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 2267 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 2268 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), 2269 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2270 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 2271 }; 2272 2273 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = { 2274 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05), 2275 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77), 2276 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b), 2277 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f), 2278 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c), 2279 }; 2280 2281 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 2282 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e), 2283 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27), 2284 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2285 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 2286 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2287 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2288 }; 2289 2290 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = { 2291 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26), 2292 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 2293 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 2294 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 2295 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 2296 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2297 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a), 2298 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a), 2299 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), 2300 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), 2301 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), 2302 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), 2303 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12), 2304 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8), 2305 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2306 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 2307 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 2308 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 2309 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 2310 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04), 2311 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d), 2312 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 2313 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), 2314 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa), 2315 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 2316 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 2317 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2318 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 2319 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 2320 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 2321 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40), 2322 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14), 2323 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), 2324 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), 2325 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 2326 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), 2327 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46), 2328 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 2329 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 2330 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), 2331 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2332 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06), 2333 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88), 2334 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14), 2335 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f), 2336 }; 2337 2338 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = { 2339 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01), 2340 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00), 2341 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02), 2342 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d), 2343 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12), 2344 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12), 2345 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb), 2346 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a), 2347 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38), 2348 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6), 2349 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64), 2350 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2351 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2352 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2353 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2354 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2355 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2356 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2357 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2358 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2359 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b), 2360 }; 2361 2362 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = { 2363 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 2364 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03), 2365 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01), 2366 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00), 2367 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51), 2368 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34), 2369 }; 2370 2371 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = { 2372 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c), 2373 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2374 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04), 2375 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2376 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2377 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80), 2378 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c), 2379 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2380 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10), 2381 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2382 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2383 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2384 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2385 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2386 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 2387 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2388 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14), 2389 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3), 2390 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58), 2391 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2392 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26), 2393 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2394 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2395 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb), 2396 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb), 2397 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0), 2398 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2399 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78), 2400 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2401 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2402 QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00), 2403 }; 2404 2405 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = { 2406 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17), 2407 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e), 2408 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc), 2409 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00), 2410 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22), 2411 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04), 2412 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02), 2413 }; 2414 2415 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 2416 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), 2417 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00), 2418 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16), 2419 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27), 2420 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27), 2421 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02), 2422 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e), 2423 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03), 2424 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28), 2425 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0), 2426 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d), 2427 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f), 2428 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2), 2429 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2), 2430 }; 2431 2432 static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = { 2433 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a), 2434 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a), 2435 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16), 2436 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00), 2437 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82), 2438 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05), 2439 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a), 2440 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d), 2441 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2442 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c), 2443 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20), 2444 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2445 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3), 2446 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3), 2447 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00), 2448 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a), 2449 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06), 2450 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6), 2451 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee), 2452 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23), 2453 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b), 2454 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60), 2455 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf), 2456 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43), 2457 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76), 2458 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff), 2459 }; 2460 2461 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = { 2462 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 2463 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2464 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2465 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2466 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2467 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2468 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2469 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2470 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2471 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2472 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2473 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2474 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2475 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2476 }; 2477 2478 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = { 2479 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2480 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2481 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2482 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2483 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2484 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2485 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2486 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2487 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2488 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2489 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2490 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2491 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2492 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2493 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2494 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2495 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2496 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2497 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2498 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2499 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2500 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2501 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2502 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2503 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2504 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2505 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2506 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2507 }; 2508 2509 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = { 2510 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2511 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2512 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a), 2513 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2514 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), 2515 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2516 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2517 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99), 2518 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 2519 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), 2520 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb), 2521 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), 2522 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec), 2523 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2524 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2525 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2526 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 2527 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8), 2528 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec), 2529 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6), 2530 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2531 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5), 2532 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e), 2533 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2534 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2535 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2536 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2537 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2538 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2539 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2540 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2541 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2542 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2543 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2544 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2545 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2546 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2547 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2548 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2549 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2550 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2551 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 2552 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2553 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2554 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2555 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2556 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2557 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2558 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2559 }; 2560 2561 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = { 2562 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2563 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 2564 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 2565 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 2566 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f), 2567 }; 2568 2569 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = { 2570 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 2571 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 2572 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 2573 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 2574 }; 2575 2576 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = { 2577 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 2578 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 2579 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 2580 }; 2581 2582 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = { 2583 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2584 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2585 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 2586 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 2587 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2588 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2589 }; 2590 2591 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = { 2592 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 2593 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 2594 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), 2595 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2596 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 2597 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), 2598 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 2599 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 2600 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), 2601 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 2602 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 2603 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 2604 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 2605 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 2606 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 2607 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 2608 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 2609 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 2610 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 2611 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), 2612 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99), 2613 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), 2614 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92), 2615 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), 2616 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), 2617 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), 2618 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), 2619 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a), 2620 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), 2621 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92), 2622 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), 2623 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), 2624 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), 2625 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), 2626 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), 2627 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), 2628 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee), 2629 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2), 2630 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), 2631 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9), 2632 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d), 2633 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 2634 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 2635 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 2636 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), 2637 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), 2638 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 2639 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), 2640 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), 2641 }; 2642 2643 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = { 2644 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16), 2645 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22), 2646 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e), 2647 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66), 2648 }; 2649 2650 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = { 2651 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 2652 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 2653 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 2654 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 2655 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 2656 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 2657 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 2658 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 2659 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 2660 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 2661 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 2662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 2663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 2664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 2665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2666 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 2667 }; 2668 2669 2670 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = { 2671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 2672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 2673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 2674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 2675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 2676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 2677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 2678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 2679 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 2680 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 2681 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 2682 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 2683 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 2684 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 2685 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 2686 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 2687 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 2688 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 2689 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 2690 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 2691 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 2692 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 2693 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 2694 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 2695 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 2696 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 2697 }; 2698 2699 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = { 2700 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 2701 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 2702 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 2703 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 2704 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 2705 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 2706 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 2707 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 2708 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 2709 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 2710 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 2711 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 2712 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 2713 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 2714 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 2715 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 2716 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 2717 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 2718 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 2719 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 2720 }; 2721 2722 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = { 2723 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00), 2724 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00), 2725 }; 2726 2727 struct qmp_pcie_offsets { 2728 u16 serdes; 2729 u16 pcs; 2730 u16 pcs_misc; 2731 u16 tx; 2732 u16 rx; 2733 u16 tx2; 2734 u16 rx2; 2735 u16 txz; 2736 u16 rxz; 2737 u16 ln_shrd; 2738 }; 2739 2740 struct qmp_phy_cfg_tbls { 2741 const struct qmp_phy_init_tbl *serdes; 2742 int serdes_num; 2743 const struct qmp_phy_init_tbl *tx; 2744 int tx_num; 2745 const struct qmp_phy_init_tbl *rx; 2746 int rx_num; 2747 const struct qmp_phy_init_tbl *txz; 2748 int txz_num; 2749 const struct qmp_phy_init_tbl *rxz; 2750 int rxz_num; 2751 const struct qmp_phy_init_tbl *pcs; 2752 int pcs_num; 2753 const struct qmp_phy_init_tbl *pcs_misc; 2754 int pcs_misc_num; 2755 const struct qmp_phy_init_tbl *ln_shrd; 2756 int ln_shrd_num; 2757 }; 2758 2759 /* struct qmp_phy_cfg - per-PHY initialization config */ 2760 struct qmp_phy_cfg { 2761 int lanes; 2762 2763 const struct qmp_pcie_offsets *offsets; 2764 2765 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 2766 const struct qmp_phy_cfg_tbls tbls; 2767 /* 2768 * Additional init sequences for PHY blocks, providing additional 2769 * register programming. They are used for providing separate sequences 2770 * for the Root Complex and End Point use cases. 2771 * 2772 * If EP mode is not supported, both tables can be left unset. 2773 */ 2774 const struct qmp_phy_cfg_tbls *tbls_rc; 2775 const struct qmp_phy_cfg_tbls *tbls_ep; 2776 2777 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 2778 int serdes_4ln_num; 2779 2780 /* resets to be requested */ 2781 const char * const *reset_list; 2782 int num_resets; 2783 /* regulators to be requested */ 2784 const char * const *vreg_list; 2785 int num_vregs; 2786 2787 /* array of registers with different offsets */ 2788 const unsigned int *regs; 2789 2790 unsigned int pwrdn_ctrl; 2791 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 2792 unsigned int phy_status; 2793 2794 bool skip_start_delay; 2795 2796 bool has_nocsr_reset; 2797 2798 /* QMP PHY pipe clock interface rate */ 2799 unsigned long pipe_clock_rate; 2800 2801 /* QMP PHY AUX clock interface rate */ 2802 unsigned long aux_clock_rate; 2803 }; 2804 2805 struct qmp_pcie { 2806 struct device *dev; 2807 2808 const struct qmp_phy_cfg *cfg; 2809 bool tcsr_4ln_config; 2810 2811 void __iomem *serdes; 2812 void __iomem *pcs; 2813 void __iomem *pcs_misc; 2814 void __iomem *tx; 2815 void __iomem *rx; 2816 void __iomem *tx2; 2817 void __iomem *rx2; 2818 void __iomem *txz; 2819 void __iomem *rxz; 2820 void __iomem *ln_shrd; 2821 2822 void __iomem *port_b; 2823 2824 struct clk_bulk_data *clks; 2825 struct clk_bulk_data pipe_clks[2]; 2826 int num_pipe_clks; 2827 2828 struct reset_control_bulk_data *resets; 2829 struct reset_control *nocsr_reset; 2830 struct regulator_bulk_data *vregs; 2831 2832 struct phy *phy; 2833 int mode; 2834 2835 struct clk_fixed_rate pipe_clk_fixed; 2836 struct clk_fixed_rate aux_clk_fixed; 2837 }; 2838 2839 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 2840 { 2841 u32 reg; 2842 2843 reg = readl(base + offset); 2844 reg |= val; 2845 writel(reg, base + offset); 2846 2847 /* ensure that above write is through */ 2848 readl(base + offset); 2849 } 2850 2851 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 2852 { 2853 u32 reg; 2854 2855 reg = readl(base + offset); 2856 reg &= ~val; 2857 writel(reg, base + offset); 2858 2859 /* ensure that above write is through */ 2860 readl(base + offset); 2861 } 2862 2863 /* list of clocks required by phy */ 2864 static const char * const qmp_pciephy_clk_l[] = { 2865 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", 2866 }; 2867 2868 /* list of regulators */ 2869 static const char * const qmp_phy_vreg_l[] = { 2870 "vdda-phy", "vdda-pll", 2871 }; 2872 2873 static const char * const sm8550_qmp_phy_vreg_l[] = { 2874 "vdda-phy", "vdda-pll", "vdda-qref", 2875 }; 2876 2877 /* list of resets */ 2878 static const char * const ipq8074_pciephy_reset_l[] = { 2879 "phy", "common", 2880 }; 2881 2882 static const char * const sdm845_pciephy_reset_l[] = { 2883 "phy", 2884 }; 2885 2886 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { 2887 .serdes = 0, 2888 .pcs = 0x1800, 2889 .tx = 0x0800, 2890 /* no .rx for QHP */ 2891 }; 2892 2893 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { 2894 .serdes = 0, 2895 .pcs = 0x0800, 2896 .tx = 0x0200, 2897 .rx = 0x0400, 2898 }; 2899 2900 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { 2901 .serdes = 0, 2902 .pcs = 0x0800, 2903 .pcs_misc = 0x0600, 2904 .tx = 0x0200, 2905 .rx = 0x0400, 2906 }; 2907 2908 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { 2909 .serdes = 0, 2910 .pcs = 0x0800, 2911 .pcs_misc = 0x0c00, 2912 .tx = 0x0200, 2913 .rx = 0x0400, 2914 }; 2915 2916 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { 2917 .serdes = 0, 2918 .pcs = 0x0a00, 2919 .pcs_misc = 0x0e00, 2920 .tx = 0x0200, 2921 .rx = 0x0400, 2922 .tx2 = 0x0600, 2923 .rx2 = 0x0800, 2924 }; 2925 2926 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { 2927 .serdes = 0x1000, 2928 .pcs = 0x1200, 2929 .pcs_misc = 0x1600, 2930 .tx = 0x0000, 2931 .rx = 0x0200, 2932 .tx2 = 0x0800, 2933 .rx2 = 0x0a00, 2934 }; 2935 2936 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 2937 .serdes = 0, 2938 .pcs = 0x0200, 2939 .pcs_misc = 0x0600, 2940 .tx = 0x0e00, 2941 .rx = 0x1000, 2942 .tx2 = 0x1600, 2943 .rx2 = 0x1800, 2944 }; 2945 2946 static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = { 2947 .serdes = 0, 2948 .pcs = 0x1000, 2949 .pcs_misc = 0x1400, 2950 .tx = 0x0200, 2951 .rx = 0x0400, 2952 .tx2 = 0x0600, 2953 .rx2 = 0x0800, 2954 }; 2955 2956 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { 2957 .serdes = 0x1000, 2958 .pcs = 0x1200, 2959 .pcs_misc = 0x1400, 2960 .tx = 0x0000, 2961 .rx = 0x0200, 2962 .tx2 = 0x0800, 2963 .rx2 = 0x0a00, 2964 }; 2965 2966 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { 2967 .serdes = 0x2000, 2968 .pcs = 0x2200, 2969 .pcs_misc = 0x2400, 2970 .tx = 0x0, 2971 .rx = 0x0200, 2972 .tx2 = 0x3800, 2973 .rx2 = 0x3a00, 2974 }; 2975 2976 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { 2977 .serdes = 0x1000, 2978 .pcs = 0x1200, 2979 .pcs_misc = 0x1400, 2980 .tx = 0x0000, 2981 .rx = 0x0200, 2982 .tx2 = 0x0800, 2983 .rx2 = 0x0a00, 2984 .ln_shrd = 0x0e00, 2985 }; 2986 2987 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = { 2988 .serdes = 0x8800, 2989 .pcs = 0x9000, 2990 .pcs_misc = 0x9800, 2991 .tx = 0x0000, 2992 .rx = 0x0200, 2993 .txz = 0xe000, 2994 .rxz = 0xe200, 2995 .ln_shrd = 0x8000, 2996 }; 2997 2998 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 2999 .lanes = 1, 3000 3001 .offsets = &qmp_pcie_offsets_v2, 3002 3003 .tbls = { 3004 .serdes = ipq8074_pcie_serdes_tbl, 3005 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 3006 .tx = ipq8074_pcie_tx_tbl, 3007 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 3008 .rx = ipq8074_pcie_rx_tbl, 3009 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 3010 .pcs = ipq8074_pcie_pcs_tbl, 3011 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 3012 }, 3013 .reset_list = ipq8074_pciephy_reset_l, 3014 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3015 .vreg_list = NULL, 3016 .num_vregs = 0, 3017 .regs = pciephy_v2_regs_layout, 3018 3019 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3020 .phy_status = PHYSTATUS, 3021 }; 3022 3023 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 3024 .lanes = 1, 3025 3026 .offsets = &qmp_pcie_offsets_v4x1, 3027 3028 .tbls = { 3029 .serdes = ipq8074_pcie_gen3_serdes_tbl, 3030 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 3031 .tx = ipq8074_pcie_gen3_tx_tbl, 3032 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3033 .rx = ipq8074_pcie_gen3_rx_tbl, 3034 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 3035 .pcs = ipq8074_pcie_gen3_pcs_tbl, 3036 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 3037 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 3038 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 3039 }, 3040 .reset_list = ipq8074_pciephy_reset_l, 3041 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3042 .vreg_list = NULL, 3043 .num_vregs = 0, 3044 .regs = pciephy_v4_regs_layout, 3045 3046 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3047 .phy_status = PHYSTATUS, 3048 3049 .pipe_clock_rate = 250000000, 3050 }; 3051 3052 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 3053 .lanes = 1, 3054 3055 .offsets = &qmp_pcie_offsets_v4x1, 3056 3057 .tbls = { 3058 .serdes = ipq6018_pcie_serdes_tbl, 3059 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 3060 .tx = ipq6018_pcie_tx_tbl, 3061 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 3062 .rx = ipq6018_pcie_rx_tbl, 3063 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 3064 .pcs = ipq6018_pcie_pcs_tbl, 3065 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 3066 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 3067 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 3068 }, 3069 .reset_list = ipq8074_pciephy_reset_l, 3070 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3071 .vreg_list = NULL, 3072 .num_vregs = 0, 3073 .regs = pciephy_v4_regs_layout, 3074 3075 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3076 .phy_status = PHYSTATUS, 3077 }; 3078 3079 static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { 3080 .lanes = 1, 3081 3082 .offsets = &qmp_pcie_offsets_v4x1, 3083 3084 .tbls = { 3085 .serdes = ipq9574_gen3x1_pcie_serdes_tbl, 3086 .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), 3087 .tx = ipq8074_pcie_gen3_tx_tbl, 3088 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3089 .rx = ipq9574_pcie_rx_tbl, 3090 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 3091 .pcs = ipq9574_gen3x1_pcie_pcs_tbl, 3092 .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), 3093 .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, 3094 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), 3095 }, 3096 .reset_list = ipq8074_pciephy_reset_l, 3097 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3098 .vreg_list = NULL, 3099 .num_vregs = 0, 3100 .regs = pciephy_v4_regs_layout, 3101 3102 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3103 .phy_status = PHYSTATUS, 3104 .pipe_clock_rate = 250000000, 3105 }; 3106 3107 static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = { 3108 .lanes = 2, 3109 3110 .offsets = &qmp_pcie_offsets_ipq9574, 3111 3112 .tbls = { 3113 .serdes = ipq9574_gen3x2_pcie_serdes_tbl, 3114 .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl), 3115 .tx = ipq8074_pcie_gen3_tx_tbl, 3116 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 3117 .rx = ipq9574_pcie_rx_tbl, 3118 .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), 3119 .pcs = ipq9574_gen3x2_pcie_pcs_tbl, 3120 .pcs_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl), 3121 .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl, 3122 .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl), 3123 }, 3124 .reset_list = ipq8074_pciephy_reset_l, 3125 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3126 .vreg_list = NULL, 3127 .num_vregs = 0, 3128 .regs = pciephy_v5_regs_layout, 3129 3130 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3131 .phy_status = PHYSTATUS, 3132 .pipe_clock_rate = 250000000, 3133 }; 3134 3135 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 3136 .lanes = 1, 3137 3138 .offsets = &qmp_pcie_offsets_v3, 3139 3140 .tbls = { 3141 .serdes = sdm845_qmp_pcie_serdes_tbl, 3142 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 3143 .tx = sdm845_qmp_pcie_tx_tbl, 3144 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 3145 .rx = sdm845_qmp_pcie_rx_tbl, 3146 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 3147 .pcs = sdm845_qmp_pcie_pcs_tbl, 3148 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 3149 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 3150 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 3151 }, 3152 .reset_list = sdm845_pciephy_reset_l, 3153 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3154 .vreg_list = qmp_phy_vreg_l, 3155 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3156 .regs = pciephy_v3_regs_layout, 3157 3158 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3159 .phy_status = PHYSTATUS, 3160 }; 3161 3162 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 3163 .lanes = 1, 3164 3165 .offsets = &qmp_pcie_offsets_qhp, 3166 3167 .tbls = { 3168 .serdes = sdm845_qhp_pcie_serdes_tbl, 3169 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 3170 .tx = sdm845_qhp_pcie_tx_tbl, 3171 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 3172 .pcs = sdm845_qhp_pcie_pcs_tbl, 3173 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 3174 }, 3175 .reset_list = sdm845_pciephy_reset_l, 3176 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3177 .vreg_list = qmp_phy_vreg_l, 3178 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3179 .regs = sdm845_qhp_pciephy_regs_layout, 3180 3181 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3182 .phy_status = PHYSTATUS, 3183 }; 3184 3185 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 3186 .lanes = 1, 3187 3188 .offsets = &qmp_pcie_offsets_v4x1, 3189 3190 .tbls = { 3191 .serdes = sm8250_qmp_pcie_serdes_tbl, 3192 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 3193 .tx = sm8250_qmp_pcie_tx_tbl, 3194 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 3195 .rx = sm8250_qmp_pcie_rx_tbl, 3196 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 3197 .pcs = sm8250_qmp_pcie_pcs_tbl, 3198 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 3199 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 3200 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 3201 }, 3202 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3203 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 3204 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 3205 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 3206 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 3207 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 3208 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 3209 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 3210 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 3211 }, 3212 .reset_list = sdm845_pciephy_reset_l, 3213 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3214 .vreg_list = qmp_phy_vreg_l, 3215 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3216 .regs = pciephy_v4_regs_layout, 3217 3218 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3219 .phy_status = PHYSTATUS, 3220 }; 3221 3222 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 3223 .lanes = 2, 3224 3225 .offsets = &qmp_pcie_offsets_v4x2, 3226 3227 .tbls = { 3228 .serdes = sm8250_qmp_pcie_serdes_tbl, 3229 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 3230 .tx = sm8250_qmp_pcie_tx_tbl, 3231 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 3232 .rx = sm8250_qmp_pcie_rx_tbl, 3233 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 3234 .pcs = sm8250_qmp_pcie_pcs_tbl, 3235 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 3236 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 3237 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 3238 }, 3239 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3240 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 3241 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 3242 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 3243 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 3244 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 3245 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 3246 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 3247 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 3248 }, 3249 .reset_list = sdm845_pciephy_reset_l, 3250 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3251 .vreg_list = qmp_phy_vreg_l, 3252 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3253 .regs = pciephy_v4_regs_layout, 3254 3255 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3256 .phy_status = PHYSTATUS, 3257 }; 3258 3259 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 3260 .lanes = 1, 3261 3262 .offsets = &qmp_pcie_offsets_v3, 3263 3264 .tbls = { 3265 .serdes = msm8998_pcie_serdes_tbl, 3266 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 3267 .tx = msm8998_pcie_tx_tbl, 3268 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 3269 .rx = msm8998_pcie_rx_tbl, 3270 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 3271 .pcs = msm8998_pcie_pcs_tbl, 3272 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 3273 }, 3274 .reset_list = ipq8074_pciephy_reset_l, 3275 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 3276 .vreg_list = qmp_phy_vreg_l, 3277 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3278 .regs = pciephy_v3_regs_layout, 3279 3280 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3281 .phy_status = PHYSTATUS, 3282 3283 .skip_start_delay = true, 3284 }; 3285 3286 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 3287 .lanes = 2, 3288 3289 .offsets = &qmp_pcie_offsets_v4x2, 3290 3291 .tbls = { 3292 .serdes = sc8180x_qmp_pcie_serdes_tbl, 3293 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 3294 .tx = sc8180x_qmp_pcie_tx_tbl, 3295 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 3296 .rx = sc8180x_qmp_pcie_rx_tbl, 3297 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 3298 .pcs = sc8180x_qmp_pcie_pcs_tbl, 3299 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 3300 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 3301 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 3302 }, 3303 .reset_list = sdm845_pciephy_reset_l, 3304 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3305 .vreg_list = qmp_phy_vreg_l, 3306 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3307 .regs = pciephy_v4_regs_layout, 3308 3309 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3310 .phy_status = PHYSTATUS, 3311 }; 3312 3313 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 3314 .lanes = 1, 3315 3316 .offsets = &qmp_pcie_offsets_v5, 3317 3318 .tbls = { 3319 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3320 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3321 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 3322 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 3323 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 3324 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 3325 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 3326 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 3327 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 3328 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 3329 }, 3330 3331 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3332 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 3333 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 3334 }, 3335 3336 .reset_list = sdm845_pciephy_reset_l, 3337 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3338 .vreg_list = qmp_phy_vreg_l, 3339 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3340 .regs = pciephy_v5_regs_layout, 3341 3342 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3343 .phy_status = PHYSTATUS, 3344 }; 3345 3346 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 3347 .lanes = 2, 3348 3349 .offsets = &qmp_pcie_offsets_v5, 3350 3351 .tbls = { 3352 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3353 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3354 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 3355 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 3356 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 3357 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 3358 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 3359 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 3360 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3361 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3362 }, 3363 3364 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3365 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 3366 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 3367 }, 3368 3369 .reset_list = sdm845_pciephy_reset_l, 3370 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3371 .vreg_list = qmp_phy_vreg_l, 3372 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3373 .regs = pciephy_v5_regs_layout, 3374 3375 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3376 .phy_status = PHYSTATUS, 3377 }; 3378 3379 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 3380 .lanes = 4, 3381 3382 .offsets = &qmp_pcie_offsets_v5, 3383 3384 .tbls = { 3385 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 3386 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 3387 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 3388 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 3389 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 3390 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 3391 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 3392 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 3393 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3394 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3395 }, 3396 3397 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3398 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 3399 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 3400 }, 3401 3402 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 3403 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 3404 3405 .reset_list = sdm845_pciephy_reset_l, 3406 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3407 .vreg_list = qmp_phy_vreg_l, 3408 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3409 .regs = pciephy_v5_regs_layout, 3410 3411 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3412 .phy_status = PHYSTATUS, 3413 }; 3414 3415 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 3416 .lanes = 2, 3417 3418 .offsets = &qmp_pcie_offsets_v4_20, 3419 3420 .tbls = { 3421 .serdes = sdx55_qmp_pcie_serdes_tbl, 3422 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 3423 .tx = sdx55_qmp_pcie_tx_tbl, 3424 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 3425 .rx = sdx55_qmp_pcie_rx_tbl, 3426 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 3427 .pcs = sdx55_qmp_pcie_pcs_tbl, 3428 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 3429 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 3430 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 3431 }, 3432 3433 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3434 .serdes = sdx55_qmp_pcie_rc_serdes_tbl, 3435 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl), 3436 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl, 3437 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl), 3438 }, 3439 3440 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3441 .serdes = sdx55_qmp_pcie_ep_serdes_tbl, 3442 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl), 3443 .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl, 3444 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), 3445 }, 3446 3447 .reset_list = sdm845_pciephy_reset_l, 3448 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3449 .vreg_list = qmp_phy_vreg_l, 3450 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3451 .regs = pciephy_v4_regs_layout, 3452 3453 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3454 .phy_status = PHYSTATUS_4_20, 3455 }; 3456 3457 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { 3458 .lanes = 1, 3459 3460 .offsets = &qmp_pcie_offsets_v5, 3461 3462 .tbls = { 3463 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3464 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3465 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl, 3466 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl), 3467 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3468 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3469 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3470 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3471 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 3472 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 3473 }, 3474 3475 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3476 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 3477 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 3478 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl, 3479 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), 3480 }, 3481 3482 .reset_list = sdm845_pciephy_reset_l, 3483 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3484 .vreg_list = qmp_phy_vreg_l, 3485 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3486 .regs = pciephy_v5_regs_layout, 3487 3488 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3489 .phy_status = PHYSTATUS, 3490 }; 3491 3492 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { 3493 .lanes = 2, 3494 3495 .offsets = &qmp_pcie_offsets_v5, 3496 3497 .tbls = { 3498 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3499 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3500 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl, 3501 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl), 3502 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3503 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3504 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3505 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3506 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 3507 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 3508 }, 3509 3510 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3511 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl, 3512 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl), 3513 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl, 3514 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), 3515 }, 3516 3517 .reset_list = sdm845_pciephy_reset_l, 3518 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3519 .vreg_list = qmp_phy_vreg_l, 3520 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3521 .regs = pciephy_v5_regs_layout, 3522 3523 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3524 .phy_status = PHYSTATUS, 3525 }; 3526 3527 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { 3528 .lanes = 2, 3529 3530 .offsets = &qmp_pcie_offsets_v6_20, 3531 3532 .tbls = { 3533 .serdes = sdx65_qmp_pcie_serdes_tbl, 3534 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl), 3535 .tx = sdx65_qmp_pcie_tx_tbl, 3536 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl), 3537 .rx = sdx65_qmp_pcie_rx_tbl, 3538 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl), 3539 .pcs = sdx65_qmp_pcie_pcs_tbl, 3540 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl), 3541 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, 3542 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), 3543 }, 3544 .reset_list = sdm845_pciephy_reset_l, 3545 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3546 .vreg_list = qmp_phy_vreg_l, 3547 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3548 .regs = pciephy_v6_regs_layout, 3549 3550 .pwrdn_ctrl = SW_PWRDN, 3551 .phy_status = PHYSTATUS_4_20, 3552 }; 3553 3554 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 3555 .lanes = 1, 3556 3557 .offsets = &qmp_pcie_offsets_v5, 3558 3559 .tbls = { 3560 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, 3561 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), 3562 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 3563 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 3564 .rx = sm8450_qmp_gen3_pcie_rx_tbl, 3565 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl), 3566 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl, 3567 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl), 3568 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 3569 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 3570 }, 3571 3572 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3573 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl, 3574 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl), 3575 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl, 3576 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), 3577 }, 3578 3579 .reset_list = sdm845_pciephy_reset_l, 3580 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3581 .vreg_list = qmp_phy_vreg_l, 3582 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3583 .regs = pciephy_v5_regs_layout, 3584 3585 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3586 .phy_status = PHYSTATUS, 3587 }; 3588 3589 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 3590 .lanes = 2, 3591 3592 .offsets = &qmp_pcie_offsets_v5_20, 3593 3594 .tbls = { 3595 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 3596 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 3597 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 3598 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 3599 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 3600 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 3601 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 3602 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 3603 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 3604 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 3605 }, 3606 3607 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3608 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 3609 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 3610 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 3611 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 3612 }, 3613 3614 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3615 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 3616 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 3617 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3618 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3619 }, 3620 3621 .reset_list = sdm845_pciephy_reset_l, 3622 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3623 .vreg_list = qmp_phy_vreg_l, 3624 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3625 .regs = pciephy_v5_regs_layout, 3626 3627 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3628 .phy_status = PHYSTATUS_4_20, 3629 3630 /* 20MHz PHY AUX Clock */ 3631 .aux_clock_rate = 20000000, 3632 }; 3633 3634 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { 3635 .lanes = 2, 3636 3637 .offsets = &qmp_pcie_offsets_v5, 3638 3639 .tbls = { 3640 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl, 3641 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl), 3642 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl, 3643 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), 3644 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl, 3645 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl), 3646 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl, 3647 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), 3648 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, 3649 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), 3650 }, 3651 .reset_list = sdm845_pciephy_reset_l, 3652 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3653 .vreg_list = qmp_phy_vreg_l, 3654 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3655 .regs = pciephy_v5_regs_layout, 3656 3657 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3658 .phy_status = PHYSTATUS, 3659 }; 3660 3661 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { 3662 .lanes = 2, 3663 3664 .offsets = &qmp_pcie_offsets_v6_20, 3665 3666 .tbls = { 3667 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3668 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3669 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3670 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3671 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl, 3672 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl), 3673 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3674 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3675 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3676 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3677 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3678 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3679 }, 3680 .reset_list = sdm845_pciephy_reset_l, 3681 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3682 .vreg_list = sm8550_qmp_phy_vreg_l, 3683 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3684 .regs = pciephy_v6_regs_layout, 3685 3686 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3687 .phy_status = PHYSTATUS_4_20, 3688 .has_nocsr_reset = true, 3689 3690 /* 20MHz PHY AUX Clock */ 3691 .aux_clock_rate = 20000000, 3692 }; 3693 3694 static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = { 3695 .lanes = 2, 3696 3697 .offsets = &qmp_pcie_offsets_v6_20, 3698 3699 .tbls = { 3700 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl, 3701 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl), 3702 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl, 3703 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl), 3704 .rx = sm8650_qmp_gen4x2_pcie_rx_tbl, 3705 .rx_num = ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl), 3706 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl, 3707 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl), 3708 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl, 3709 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl), 3710 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, 3711 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), 3712 }, 3713 .reset_list = sdm845_pciephy_reset_l, 3714 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3715 .vreg_list = sm8550_qmp_phy_vreg_l, 3716 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3717 .regs = pciephy_v6_regs_layout, 3718 3719 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3720 .phy_status = PHYSTATUS_4_20, 3721 .has_nocsr_reset = true, 3722 3723 /* 20MHz PHY AUX Clock */ 3724 .aux_clock_rate = 20000000, 3725 }; 3726 3727 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { 3728 .lanes = 2, 3729 .offsets = &qmp_pcie_offsets_v5_20, 3730 3731 .tbls = { 3732 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl, 3733 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl), 3734 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 3735 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 3736 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl, 3737 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl), 3738 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl, 3739 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl), 3740 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3741 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3742 }, 3743 3744 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3745 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl, 3746 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl), 3747 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 3748 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 3749 }, 3750 3751 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3752 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 3753 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 3754 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3755 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3756 .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, 3757 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), 3758 }, 3759 3760 .reset_list = sdm845_pciephy_reset_l, 3761 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3762 .vreg_list = qmp_phy_vreg_l, 3763 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3764 .regs = pciephy_v5_regs_layout, 3765 3766 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3767 .phy_status = PHYSTATUS_4_20, 3768 }; 3769 3770 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { 3771 .lanes = 4, 3772 .offsets = &qmp_pcie_offsets_v5_30, 3773 3774 .tbls = { 3775 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, 3776 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), 3777 .tx = sa8775p_qmp_gen4_pcie_tx_tbl, 3778 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), 3779 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl, 3780 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl), 3781 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl, 3782 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl), 3783 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, 3784 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), 3785 }, 3786 3787 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 3788 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, 3789 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), 3790 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, 3791 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), 3792 }, 3793 3794 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 3795 .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, 3796 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), 3797 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 3798 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 3799 }, 3800 3801 .reset_list = sdm845_pciephy_reset_l, 3802 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3803 .vreg_list = qmp_phy_vreg_l, 3804 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3805 .regs = pciephy_v5_regs_layout, 3806 3807 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3808 .phy_status = PHYSTATUS_4_20, 3809 }; 3810 3811 static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = { 3812 .lanes = 2, 3813 3814 .offsets = &qmp_pcie_offsets_v6_20, 3815 3816 .tbls = { 3817 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 3818 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 3819 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 3820 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 3821 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 3822 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 3823 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 3824 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 3825 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 3826 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 3827 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 3828 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 3829 }, 3830 3831 .reset_list = sdm845_pciephy_reset_l, 3832 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3833 .vreg_list = qmp_phy_vreg_l, 3834 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3835 .regs = pciephy_v6_regs_layout, 3836 3837 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3838 .phy_status = PHYSTATUS_4_20, 3839 .has_nocsr_reset = true, 3840 }; 3841 3842 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = { 3843 .lanes = 4, 3844 3845 .offsets = &qmp_pcie_offsets_v6_20, 3846 3847 .tbls = { 3848 .serdes = x1e80100_qmp_gen4x2_pcie_serdes_tbl, 3849 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl), 3850 .tx = x1e80100_qmp_gen4x2_pcie_tx_tbl, 3851 .tx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl), 3852 .rx = x1e80100_qmp_gen4x2_pcie_rx_tbl, 3853 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl), 3854 .pcs = x1e80100_qmp_gen4x2_pcie_pcs_tbl, 3855 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl), 3856 .pcs_misc = x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl, 3857 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl), 3858 .ln_shrd = x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl, 3859 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl), 3860 }, 3861 3862 .serdes_4ln_tbl = x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl, 3863 .serdes_4ln_num = ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl), 3864 3865 .reset_list = sdm845_pciephy_reset_l, 3866 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3867 .vreg_list = qmp_phy_vreg_l, 3868 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3869 .regs = pciephy_v6_regs_layout, 3870 3871 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3872 .phy_status = PHYSTATUS_4_20, 3873 .has_nocsr_reset = true, 3874 }; 3875 3876 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = { 3877 .lanes = 8, 3878 3879 .offsets = &qmp_pcie_offsets_v6_30, 3880 .tbls = { 3881 .serdes = x1e80100_qmp_gen4x8_pcie_serdes_tbl, 3882 .serdes_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_serdes_tbl), 3883 .rx = x1e80100_qmp_gen4x8_pcie_rx_tbl, 3884 .rx_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rx_tbl), 3885 .txz = x1e80100_qmp_gen4x8_pcie_txz_tbl, 3886 .txz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_txz_tbl), 3887 .rxz = x1e80100_qmp_gen4x8_pcie_rxz_tbl, 3888 .rxz_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_rxz_tbl), 3889 .pcs = x1e80100_qmp_gen4x8_pcie_pcs_tbl, 3890 .pcs_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_tbl), 3891 .pcs_misc = x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl, 3892 .pcs_misc_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_pcs_misc_tbl), 3893 .ln_shrd = x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl, 3894 .ln_shrd_num = ARRAY_SIZE(x1e80100_qmp_gen4x8_pcie_ln_shrd_tbl), 3895 }, 3896 3897 .reset_list = sdm845_pciephy_reset_l, 3898 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 3899 .vreg_list = sm8550_qmp_phy_vreg_l, 3900 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), 3901 .regs = pciephy_v6_regs_layout, 3902 3903 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 3904 .phy_status = PHYSTATUS_4_20, 3905 .has_nocsr_reset = true, 3906 }; 3907 3908 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 3909 { 3910 const struct qmp_phy_cfg *cfg = qmp->cfg; 3911 const struct qmp_pcie_offsets *offs = cfg->offsets; 3912 void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd; 3913 3914 serdes = qmp->port_b + offs->serdes; 3915 tx3 = qmp->port_b + offs->tx; 3916 rx3 = qmp->port_b + offs->rx; 3917 tx4 = qmp->port_b + offs->tx2; 3918 rx4 = qmp->port_b + offs->rx2; 3919 pcs = qmp->port_b + offs->pcs; 3920 pcs_misc = qmp->port_b + offs->pcs_misc; 3921 ln_shrd = qmp->port_b + offs->ln_shrd; 3922 3923 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 3924 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 3925 3926 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); 3927 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); 3928 3929 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); 3930 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); 3931 3932 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 3933 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 3934 3935 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 3936 } 3937 3938 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 3939 { 3940 const struct qmp_phy_cfg *cfg = qmp->cfg; 3941 void __iomem *serdes = qmp->serdes; 3942 void __iomem *tx = qmp->tx; 3943 void __iomem *rx = qmp->rx; 3944 void __iomem *tx2 = qmp->tx2; 3945 void __iomem *rx2 = qmp->rx2; 3946 void __iomem *pcs = qmp->pcs; 3947 void __iomem *pcs_misc = qmp->pcs_misc; 3948 void __iomem *ln_shrd = qmp->ln_shrd; 3949 3950 if (!tbls) 3951 return; 3952 3953 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 3954 3955 /* 3956 * Tx/Rx registers that require different settings than 3957 * txz/rxz must be programmed after txz/rxz. 3958 */ 3959 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); 3960 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); 3961 3962 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 3963 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 3964 3965 if (cfg->lanes >= 2) { 3966 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); 3967 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); 3968 } 3969 3970 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 3971 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 3972 3973 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 3974 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, 3975 cfg->serdes_4ln_num); 3976 qmp_pcie_init_port_b(qmp, tbls); 3977 } 3978 3979 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); 3980 } 3981 3982 static int qmp_pcie_init(struct phy *phy) 3983 { 3984 struct qmp_pcie *qmp = phy_get_drvdata(phy); 3985 const struct qmp_phy_cfg *cfg = qmp->cfg; 3986 int ret; 3987 3988 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 3989 if (ret) { 3990 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 3991 return ret; 3992 } 3993 3994 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3995 if (ret) { 3996 dev_err(qmp->dev, "reset assert failed\n"); 3997 goto err_disable_regulators; 3998 } 3999 4000 ret = reset_control_assert(qmp->nocsr_reset); 4001 if (ret) { 4002 dev_err(qmp->dev, "no-csr reset assert failed\n"); 4003 goto err_assert_reset; 4004 } 4005 4006 usleep_range(200, 300); 4007 4008 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 4009 if (ret) { 4010 dev_err(qmp->dev, "reset deassert failed\n"); 4011 goto err_assert_reset; 4012 } 4013 4014 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 4015 if (ret) 4016 goto err_assert_reset; 4017 4018 return 0; 4019 4020 err_assert_reset: 4021 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4022 err_disable_regulators: 4023 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4024 4025 return ret; 4026 } 4027 4028 static int qmp_pcie_exit(struct phy *phy) 4029 { 4030 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4031 const struct qmp_phy_cfg *cfg = qmp->cfg; 4032 4033 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4034 4035 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); 4036 4037 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4038 4039 return 0; 4040 } 4041 4042 static int qmp_pcie_power_on(struct phy *phy) 4043 { 4044 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4045 const struct qmp_phy_cfg *cfg = qmp->cfg; 4046 const struct qmp_phy_cfg_tbls *mode_tbls; 4047 void __iomem *pcs = qmp->pcs; 4048 void __iomem *status; 4049 unsigned int mask, val; 4050 int ret; 4051 4052 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4053 cfg->pwrdn_ctrl); 4054 4055 if (qmp->mode == PHY_MODE_PCIE_RC) 4056 mode_tbls = cfg->tbls_rc; 4057 else 4058 mode_tbls = cfg->tbls_ep; 4059 4060 qmp_pcie_init_registers(qmp, &cfg->tbls); 4061 qmp_pcie_init_registers(qmp, mode_tbls); 4062 4063 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 4064 if (ret) 4065 return ret; 4066 4067 ret = reset_control_deassert(qmp->nocsr_reset); 4068 if (ret) { 4069 dev_err(qmp->dev, "no-csr reset deassert failed\n"); 4070 goto err_disable_pipe_clk; 4071 } 4072 4073 /* Pull PHY out of reset state */ 4074 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4075 4076 /* start SerDes and Phy-Coding-Sublayer */ 4077 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 4078 4079 if (!cfg->skip_start_delay) 4080 usleep_range(1000, 1200); 4081 4082 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 4083 mask = cfg->phy_status; 4084 ret = readl_poll_timeout(status, val, !(val & mask), 200, 4085 PHY_INIT_COMPLETE_TIMEOUT); 4086 if (ret) { 4087 dev_err(qmp->dev, "phy initialization timed-out\n"); 4088 goto err_disable_pipe_clk; 4089 } 4090 4091 return 0; 4092 4093 err_disable_pipe_clk: 4094 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 4095 4096 return ret; 4097 } 4098 4099 static int qmp_pcie_power_off(struct phy *phy) 4100 { 4101 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4102 const struct qmp_phy_cfg *cfg = qmp->cfg; 4103 4104 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 4105 4106 /* PHY reset */ 4107 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4108 4109 /* stop SerDes and Phy-Coding-Sublayer */ 4110 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 4111 SERDES_START | PCS_START); 4112 4113 /* Put PHY into POWER DOWN state: active low */ 4114 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4115 cfg->pwrdn_ctrl); 4116 4117 return 0; 4118 } 4119 4120 static int qmp_pcie_enable(struct phy *phy) 4121 { 4122 int ret; 4123 4124 ret = qmp_pcie_init(phy); 4125 if (ret) 4126 return ret; 4127 4128 ret = qmp_pcie_power_on(phy); 4129 if (ret) 4130 qmp_pcie_exit(phy); 4131 4132 return ret; 4133 } 4134 4135 static int qmp_pcie_disable(struct phy *phy) 4136 { 4137 int ret; 4138 4139 ret = qmp_pcie_power_off(phy); 4140 if (ret) 4141 return ret; 4142 4143 return qmp_pcie_exit(phy); 4144 } 4145 4146 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 4147 { 4148 struct qmp_pcie *qmp = phy_get_drvdata(phy); 4149 4150 switch (submode) { 4151 case PHY_MODE_PCIE_RC: 4152 case PHY_MODE_PCIE_EP: 4153 qmp->mode = submode; 4154 break; 4155 default: 4156 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 4157 return -EINVAL; 4158 } 4159 4160 return 0; 4161 } 4162 4163 static const struct phy_ops qmp_pcie_phy_ops = { 4164 .power_on = qmp_pcie_enable, 4165 .power_off = qmp_pcie_disable, 4166 .set_mode = qmp_pcie_set_mode, 4167 .owner = THIS_MODULE, 4168 }; 4169 4170 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 4171 { 4172 const struct qmp_phy_cfg *cfg = qmp->cfg; 4173 struct device *dev = qmp->dev; 4174 int num = cfg->num_vregs; 4175 int i; 4176 4177 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 4178 if (!qmp->vregs) 4179 return -ENOMEM; 4180 4181 for (i = 0; i < num; i++) 4182 qmp->vregs[i].supply = cfg->vreg_list[i]; 4183 4184 return devm_regulator_bulk_get(dev, num, qmp->vregs); 4185 } 4186 4187 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 4188 { 4189 const struct qmp_phy_cfg *cfg = qmp->cfg; 4190 struct device *dev = qmp->dev; 4191 int i; 4192 int ret; 4193 4194 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 4195 sizeof(*qmp->resets), GFP_KERNEL); 4196 if (!qmp->resets) 4197 return -ENOMEM; 4198 4199 for (i = 0; i < cfg->num_resets; i++) 4200 qmp->resets[i].id = cfg->reset_list[i]; 4201 4202 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 4203 if (ret) 4204 return dev_err_probe(dev, ret, "failed to get resets\n"); 4205 4206 if (cfg->has_nocsr_reset) { 4207 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); 4208 if (IS_ERR(qmp->nocsr_reset)) 4209 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), 4210 "failed to get no-csr reset\n"); 4211 } 4212 4213 return 0; 4214 } 4215 4216 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 4217 { 4218 struct device *dev = qmp->dev; 4219 int num = ARRAY_SIZE(qmp_pciephy_clk_l); 4220 int i; 4221 4222 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 4223 if (!qmp->clks) 4224 return -ENOMEM; 4225 4226 for (i = 0; i < num; i++) 4227 qmp->clks[i].id = qmp_pciephy_clk_l[i]; 4228 4229 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 4230 } 4231 4232 static void phy_clk_release_provider(void *res) 4233 { 4234 of_clk_del_provider(res); 4235 } 4236 4237 /* 4238 * Register a fixed rate pipe clock. 4239 * 4240 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 4241 * controls it. The <s>_pipe_clk coming out of the GCC is requested 4242 * by the PHY driver for its operations. 4243 * We register the <s>_pipe_clksrc here. The gcc driver takes care 4244 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 4245 * Below picture shows this relationship. 4246 * 4247 * +---------------+ 4248 * | PHY block |<<---------------------------------------+ 4249 * | | | 4250 * | +-------+ | +-----+ | 4251 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 4252 * clk | +-------+ | +-----+ 4253 * +---------------+ 4254 */ 4255 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 4256 { 4257 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 4258 struct clk_init_data init = { }; 4259 int ret; 4260 4261 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); 4262 if (ret) { 4263 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 4264 return ret; 4265 } 4266 4267 init.ops = &clk_fixed_rate_ops; 4268 4269 /* 4270 * Controllers using QMP PHY-s use 125MHz pipe clock interface 4271 * unless other frequency is specified in the PHY config. 4272 */ 4273 if (qmp->cfg->pipe_clock_rate) 4274 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 4275 else 4276 fixed->fixed_rate = 125000000; 4277 4278 fixed->hw.init = &init; 4279 4280 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4281 } 4282 4283 /* 4284 * Register a fixed rate PHY aux clock. 4285 * 4286 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate 4287 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested 4288 * by the PHY driver for its operations. 4289 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care 4290 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk. 4291 * Below picture shows this relationship. 4292 * 4293 * +---------------+ 4294 * | PHY block |<<---------------------------------------------+ 4295 * | | | 4296 * | +-------+ | +-----+ | 4297 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ 4298 * clk | +-------+ | +-----+ 4299 * +---------------+ 4300 */ 4301 static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) 4302 { 4303 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; 4304 struct clk_init_data init = { }; 4305 char name[64]; 4306 4307 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); 4308 4309 init.name = name; 4310 init.ops = &clk_fixed_rate_ops; 4311 4312 fixed->fixed_rate = qmp->cfg->aux_clock_rate; 4313 fixed->hw.init = &init; 4314 4315 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4316 } 4317 4318 static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) 4319 { 4320 struct qmp_pcie *qmp = data; 4321 4322 /* Support legacy bindings */ 4323 if (!clkspec->args_count) 4324 return &qmp->pipe_clk_fixed.hw; 4325 4326 switch (clkspec->args[0]) { 4327 case QMP_PCIE_PIPE_CLK: 4328 return &qmp->pipe_clk_fixed.hw; 4329 case QMP_PCIE_PHY_AUX_CLK: 4330 return &qmp->aux_clk_fixed.hw; 4331 } 4332 4333 return ERR_PTR(-EINVAL); 4334 } 4335 4336 static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) 4337 { 4338 int ret; 4339 4340 ret = phy_pipe_clk_register(qmp, np); 4341 if (ret) 4342 return ret; 4343 4344 if (qmp->cfg->aux_clock_rate) { 4345 ret = phy_aux_clk_register(qmp, np); 4346 if (ret) 4347 return ret; 4348 4349 ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp); 4350 if (ret) 4351 return ret; 4352 } else { 4353 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); 4354 if (ret) 4355 return ret; 4356 } 4357 4358 /* 4359 * Roll a devm action because the clock provider is the child node, but 4360 * the child node is not actually a device. 4361 */ 4362 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 4363 } 4364 4365 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 4366 { 4367 struct platform_device *pdev = to_platform_device(qmp->dev); 4368 const struct qmp_phy_cfg *cfg = qmp->cfg; 4369 struct device *dev = qmp->dev; 4370 struct clk *clk; 4371 4372 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 4373 if (IS_ERR(qmp->serdes)) 4374 return PTR_ERR(qmp->serdes); 4375 4376 /* 4377 * Get memory resources for the PHY: 4378 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 4379 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 4380 * For single lane PHYs: pcs_misc (optional) -> 3. 4381 */ 4382 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 4383 if (IS_ERR(qmp->tx)) 4384 return PTR_ERR(qmp->tx); 4385 4386 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 4387 qmp->rx = qmp->tx; 4388 else 4389 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 4390 if (IS_ERR(qmp->rx)) 4391 return PTR_ERR(qmp->rx); 4392 4393 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 4394 if (IS_ERR(qmp->pcs)) 4395 return PTR_ERR(qmp->pcs); 4396 4397 if (cfg->lanes >= 2) { 4398 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 4399 if (IS_ERR(qmp->tx2)) 4400 return PTR_ERR(qmp->tx2); 4401 4402 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 4403 if (IS_ERR(qmp->rx2)) 4404 return PTR_ERR(qmp->rx2); 4405 4406 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 4407 } else { 4408 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 4409 } 4410 4411 if (IS_ERR(qmp->pcs_misc) && 4412 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 4413 qmp->pcs_misc = qmp->pcs + 0x400; 4414 4415 if (IS_ERR(qmp->pcs_misc)) { 4416 if (cfg->tbls.pcs_misc || 4417 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 4418 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 4419 return PTR_ERR(qmp->pcs_misc); 4420 } 4421 } 4422 4423 clk = devm_get_clk_from_child(dev, np, NULL); 4424 if (IS_ERR(clk)) { 4425 return dev_err_probe(dev, PTR_ERR(clk), 4426 "failed to get pipe clock\n"); 4427 } 4428 4429 qmp->num_pipe_clks = 1; 4430 qmp->pipe_clks[0].id = "pipe"; 4431 qmp->pipe_clks[0].clk = clk; 4432 4433 return 0; 4434 } 4435 4436 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 4437 { 4438 struct regmap *tcsr; 4439 unsigned int args[2]; 4440 int ret; 4441 4442 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 4443 "qcom,4ln-config-sel", 4444 ARRAY_SIZE(args), args); 4445 if (IS_ERR(tcsr)) { 4446 ret = PTR_ERR(tcsr); 4447 if (ret == -ENOENT) 4448 return 0; 4449 4450 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 4451 return ret; 4452 } 4453 4454 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 4455 if (ret < 0) { 4456 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 4457 return ret; 4458 } 4459 4460 qmp->tcsr_4ln_config = ret; 4461 4462 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 4463 4464 return 0; 4465 } 4466 4467 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 4468 { 4469 struct platform_device *pdev = to_platform_device(qmp->dev); 4470 const struct qmp_phy_cfg *cfg = qmp->cfg; 4471 const struct qmp_pcie_offsets *offs = cfg->offsets; 4472 struct device *dev = qmp->dev; 4473 void __iomem *base; 4474 int ret; 4475 4476 if (!offs) 4477 return -EINVAL; 4478 4479 ret = qmp_pcie_get_4ln_config(qmp); 4480 if (ret) 4481 return ret; 4482 4483 base = devm_platform_ioremap_resource(pdev, 0); 4484 if (IS_ERR(base)) 4485 return PTR_ERR(base); 4486 4487 qmp->serdes = base + offs->serdes; 4488 qmp->pcs = base + offs->pcs; 4489 qmp->pcs_misc = base + offs->pcs_misc; 4490 qmp->tx = base + offs->tx; 4491 qmp->rx = base + offs->rx; 4492 4493 if (cfg->lanes >= 2) { 4494 qmp->tx2 = base + offs->tx2; 4495 qmp->rx2 = base + offs->rx2; 4496 } 4497 4498 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 4499 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 4500 if (IS_ERR(qmp->port_b)) 4501 return PTR_ERR(qmp->port_b); 4502 } 4503 4504 qmp->txz = base + offs->txz; 4505 qmp->rxz = base + offs->rxz; 4506 4507 if (cfg->tbls.ln_shrd) 4508 qmp->ln_shrd = base + offs->ln_shrd; 4509 4510 qmp->num_pipe_clks = 2; 4511 qmp->pipe_clks[0].id = "pipe"; 4512 qmp->pipe_clks[1].id = "pipediv2"; 4513 4514 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); 4515 if (ret) 4516 return ret; 4517 4518 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); 4519 if (ret) 4520 return ret; 4521 4522 return 0; 4523 } 4524 4525 static int qmp_pcie_probe(struct platform_device *pdev) 4526 { 4527 struct device *dev = &pdev->dev; 4528 struct phy_provider *phy_provider; 4529 struct device_node *np; 4530 struct qmp_pcie *qmp; 4531 int ret; 4532 4533 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 4534 if (!qmp) 4535 return -ENOMEM; 4536 4537 qmp->dev = dev; 4538 4539 qmp->cfg = of_device_get_match_data(dev); 4540 if (!qmp->cfg) 4541 return -EINVAL; 4542 4543 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 4544 WARN_ON_ONCE(!qmp->cfg->phy_status); 4545 4546 ret = qmp_pcie_clk_init(qmp); 4547 if (ret) 4548 return ret; 4549 4550 ret = qmp_pcie_reset_init(qmp); 4551 if (ret) 4552 return ret; 4553 4554 ret = qmp_pcie_vreg_init(qmp); 4555 if (ret) 4556 return ret; 4557 4558 /* Check for legacy binding with child node. */ 4559 np = of_get_next_available_child(dev->of_node, NULL); 4560 if (np) { 4561 ret = qmp_pcie_parse_dt_legacy(qmp, np); 4562 } else { 4563 np = of_node_get(dev->of_node); 4564 ret = qmp_pcie_parse_dt(qmp); 4565 } 4566 if (ret) 4567 goto err_node_put; 4568 4569 ret = qmp_pcie_register_clocks(qmp, np); 4570 if (ret) 4571 goto err_node_put; 4572 4573 qmp->mode = PHY_MODE_PCIE_RC; 4574 4575 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 4576 if (IS_ERR(qmp->phy)) { 4577 ret = PTR_ERR(qmp->phy); 4578 dev_err(dev, "failed to create PHY: %d\n", ret); 4579 goto err_node_put; 4580 } 4581 4582 phy_set_drvdata(qmp->phy, qmp); 4583 4584 of_node_put(np); 4585 4586 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4587 4588 return PTR_ERR_OR_ZERO(phy_provider); 4589 4590 err_node_put: 4591 of_node_put(np); 4592 return ret; 4593 } 4594 4595 static const struct of_device_id qmp_pcie_of_match_table[] = { 4596 { 4597 .compatible = "qcom,ipq6018-qmp-pcie-phy", 4598 .data = &ipq6018_pciephy_cfg, 4599 }, { 4600 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 4601 .data = &ipq8074_pciephy_gen3_cfg, 4602 }, { 4603 .compatible = "qcom,ipq8074-qmp-pcie-phy", 4604 .data = &ipq8074_pciephy_cfg, 4605 }, { 4606 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy", 4607 .data = &ipq9574_gen3x1_pciephy_cfg, 4608 }, { 4609 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy", 4610 .data = &ipq9574_gen3x2_pciephy_cfg, 4611 }, { 4612 .compatible = "qcom,msm8998-qmp-pcie-phy", 4613 .data = &msm8998_pciephy_cfg, 4614 }, { 4615 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", 4616 .data = &sa8775p_qmp_gen4x2_pciephy_cfg, 4617 }, { 4618 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy", 4619 .data = &sa8775p_qmp_gen4x4_pciephy_cfg, 4620 }, { 4621 .compatible = "qcom,sc8180x-qmp-pcie-phy", 4622 .data = &sc8180x_pciephy_cfg, 4623 }, { 4624 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 4625 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 4626 }, { 4627 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 4628 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 4629 }, { 4630 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 4631 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 4632 }, { 4633 .compatible = "qcom,sdm845-qhp-pcie-phy", 4634 .data = &sdm845_qhp_pciephy_cfg, 4635 }, { 4636 .compatible = "qcom,sdm845-qmp-pcie-phy", 4637 .data = &sdm845_qmp_pciephy_cfg, 4638 }, { 4639 .compatible = "qcom,sdx55-qmp-pcie-phy", 4640 .data = &sdx55_qmp_pciephy_cfg, 4641 }, { 4642 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy", 4643 .data = &sdx65_qmp_pciephy_cfg, 4644 }, { 4645 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy", 4646 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 4647 }, { 4648 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy", 4649 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4650 }, { 4651 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 4652 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 4653 }, { 4654 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 4655 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4656 }, { 4657 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 4658 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 4659 }, { 4660 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy", 4661 .data = &sm8350_qmp_gen3x1_pciephy_cfg, 4662 }, { 4663 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy", 4664 .data = &sm8350_qmp_gen3x2_pciephy_cfg, 4665 }, { 4666 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 4667 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 4668 }, { 4669 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 4670 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 4671 }, { 4672 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy", 4673 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4674 }, { 4675 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy", 4676 .data = &sm8550_qmp_gen4x2_pciephy_cfg, 4677 }, { 4678 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy", 4679 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4680 }, { 4681 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy", 4682 .data = &sm8650_qmp_gen4x2_pciephy_cfg, 4683 }, { 4684 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy", 4685 .data = &sm8550_qmp_gen3x2_pciephy_cfg, 4686 }, { 4687 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy", 4688 .data = &x1e80100_qmp_gen4x2_pciephy_cfg, 4689 }, { 4690 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy", 4691 .data = &x1e80100_qmp_gen4x4_pciephy_cfg, 4692 }, { 4693 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy", 4694 .data = &x1e80100_qmp_gen4x8_pciephy_cfg, 4695 }, 4696 { }, 4697 }; 4698 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 4699 4700 static struct platform_driver qmp_pcie_driver = { 4701 .probe = qmp_pcie_probe, 4702 .driver = { 4703 .name = "qcom-qmp-pcie-phy", 4704 .of_match_table = qmp_pcie_of_match_table, 4705 }, 4706 }; 4707 4708 module_platform_driver(qmp_pcie_driver); 4709 4710 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 4711 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 4712 MODULE_LICENSE("GPL v2"); 4713