1*c1282d5fSXiangxu Yin /* SPDX-License-Identifier: GPL-2.0 */ 2*c1282d5fSXiangxu Yin /* 3*c1282d5fSXiangxu Yin * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4*c1282d5fSXiangxu Yin */ 5*c1282d5fSXiangxu Yin 6*c1282d5fSXiangxu Yin #ifndef QCOM_PHY_QMP_DP_PHY_V2_H_ 7*c1282d5fSXiangxu Yin #define QCOM_PHY_QMP_DP_PHY_V2_H_ 8*c1282d5fSXiangxu Yin 9*c1282d5fSXiangxu Yin // /* Only for QMP V2 PHY - DP PHY registers */ 10*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK 0x048 11*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 12*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_AUX_BIST_CFG 0x050 13*c1282d5fSXiangxu Yin 14*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_VCO_DIV 0x068 15*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL 0x06c 16*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL 0x088 17*c1282d5fSXiangxu Yin 18*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_SPARE0 0x0ac 19*c1282d5fSXiangxu Yin #define QSERDES_V2_DP_PHY_STATUS 0x0c0 20*c1282d5fSXiangxu Yin 21*c1282d5fSXiangxu Yin #endif 22