xref: /linux/drivers/phy/qualcomm/phy-qcom-qmp-common.h (revision 2cd86f02c017bf9733e5cd891381b7d40f6f37ad)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef QCOM_PHY_QMP_COMMON_H_
7 #define QCOM_PHY_QMP_COMMON_H_
8 
9 struct qmp_phy_init_tbl {
10 	unsigned int offset;
11 	unsigned int val;
12 	char *name;
13 	/*
14 	 * mask of lanes for which this register is written
15 	 * for cases when second lane needs different values
16 	 */
17 	u8 lane_mask;
18 };
19 
20 #define QMP_PHY_INIT_CFG(o, v)		\
21 	{				\
22 		.offset = o,		\
23 		.val = v,		\
24 		.name = #o,		\
25 		.lane_mask = 0xff,	\
26 	}
27 
28 #define QMP_PHY_INIT_CFG_LANE(o, v, l)	\
29 	{				\
30 		.offset = o,		\
31 		.val = v,		\
32 		.name = #o,		\
33 		.lane_mask = l,		\
34 	}
35 
36 static inline void qmp_configure_lane(struct device *dev, void __iomem *base,
37 				      const struct qmp_phy_init_tbl tbl[],
38 				      int num, u8 lane_mask)
39 {
40 	int i;
41 	const struct qmp_phy_init_tbl *t = tbl;
42 
43 	if (!t)
44 		return;
45 
46 	for (i = 0; i < num; i++, t++) {
47 		if (!(t->lane_mask & lane_mask))
48 			continue;
49 
50 		dev_dbg(dev, "Writing Reg: %s Offset: 0x%04x Val: 0x%02x\n",
51 			t->name, t->offset, t->val);
52 		writel(t->val, base + t->offset);
53 	}
54 }
55 
56 static inline void qmp_configure(struct device *dev, void __iomem *base,
57 				 const struct qmp_phy_init_tbl tbl[], int num)
58 {
59 	qmp_configure_lane(dev, base, tbl, num, 0xff);
60 }
61 
62 #endif
63