1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 #define PLL_READY_GATE_EN BIT(3) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */ 40 #define PCS_READY BIT(0) 41 42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 43 /* DP PHY soft reset */ 44 #define SW_DPPHY_RESET BIT(0) 45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_DPPHY_RESET_MUX BIT(1) 47 /* USB3 PHY soft reset */ 48 #define SW_USB3PHY_RESET BIT(2) 49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 50 #define SW_USB3PHY_RESET_MUX BIT(3) 51 52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 53 #define USB3_MODE BIT(0) /* enables USB3 mode */ 54 #define DP_MODE BIT(1) /* enables DP mode */ 55 56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 57 #define ARCVR_DTCT_EN BIT(0) 58 #define ALFPS_DTCT_EN BIT(1) 59 #define ARCVR_DTCT_EVENT_SEL BIT(4) 60 61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 62 #define IRQ_CLEAR BIT(0) 63 64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 65 #define RCVR_DETECT BIT(0) 66 67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 68 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 69 70 #define PHY_INIT_COMPLETE_TIMEOUT 10000 71 #define POWER_DOWN_DELAY_US_MIN 10 72 #define POWER_DOWN_DELAY_US_MAX 11 73 74 #define MAX_PROP_NAME 32 75 76 /* Define the assumed distance between lanes for underspecified device trees. */ 77 #define QMP_PHY_LEGACY_LANE_STRIDE 0x400 78 79 struct qmp_phy_init_tbl { 80 unsigned int offset; 81 unsigned int val; 82 /* 83 * register part of layout ? 84 * if yes, then offset gives index in the reg-layout 85 */ 86 bool in_layout; 87 /* 88 * mask of lanes for which this register is written 89 * for cases when second lane needs different values 90 */ 91 u8 lane_mask; 92 }; 93 94 #define QMP_PHY_INIT_CFG(o, v) \ 95 { \ 96 .offset = o, \ 97 .val = v, \ 98 .lane_mask = 0xff, \ 99 } 100 101 #define QMP_PHY_INIT_CFG_L(o, v) \ 102 { \ 103 .offset = o, \ 104 .val = v, \ 105 .in_layout = true, \ 106 .lane_mask = 0xff, \ 107 } 108 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 110 { \ 111 .offset = o, \ 112 .val = v, \ 113 .lane_mask = l, \ 114 } 115 116 /* set of registers with offsets different per-PHY */ 117 enum qphy_reg_layout { 118 /* Common block control registers */ 119 QPHY_COM_SW_RESET, 120 QPHY_COM_POWER_DOWN_CONTROL, 121 QPHY_COM_START_CONTROL, 122 QPHY_COM_PCS_READY_STATUS, 123 /* PCS registers */ 124 QPHY_PLL_LOCK_CHK_DLY_TIME, 125 QPHY_FLL_CNTRL1, 126 QPHY_FLL_CNTRL2, 127 QPHY_FLL_CNT_VAL_L, 128 QPHY_FLL_CNT_VAL_H_TOL, 129 QPHY_FLL_MAN_CODE, 130 QPHY_SW_RESET, 131 QPHY_START_CTRL, 132 QPHY_PCS_READY_STATUS, 133 QPHY_PCS_STATUS, 134 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 135 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 136 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 137 QPHY_PCS_POWER_DOWN_CONTROL, 138 /* PCS_MISC registers */ 139 QPHY_PCS_MISC_TYPEC_CTRL, 140 /* Keep last to ensure regs_layout arrays are properly initialized */ 141 QPHY_LAYOUT_SIZE 142 }; 143 144 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 145 [QPHY_SW_RESET] = 0x00, 146 [QPHY_START_CTRL] = 0x08, 147 [QPHY_PCS_STATUS] = 0x174, 148 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 149 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 150 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 151 }; 152 153 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 154 [QPHY_SW_RESET] = 0x00, 155 [QPHY_START_CTRL] = 0x44, 156 [QPHY_PCS_STATUS] = 0x14, 157 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 158 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308, 159 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314, 160 }; 161 162 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 165 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 166 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 167 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 168 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 169 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 170 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 171 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 172 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 173 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 174 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 177 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 178 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 179 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 180 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 181 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 182 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 183 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 184 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 186 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 199 }; 200 201 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 202 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 203 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 204 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 205 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 206 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 207 }; 208 209 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 231 }; 232 233 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 241 }; 242 243 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 251 }; 252 253 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 261 }; 262 263 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 271 }; 272 273 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 274 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 275 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 276 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 277 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 278 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 279 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 280 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 281 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 282 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 284 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 285 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 286 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 287 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 288 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 289 }; 290 291 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 292 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 293 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 294 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 295 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 296 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 297 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 298 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 299 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 300 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 301 }; 302 303 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 304 /* FLL settings */ 305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 310 311 /* Lock Det settings */ 312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 316 317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 336 337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 338 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 339 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 344 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 348 }; 349 350 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 351 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 352 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 353 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 354 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 355 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 356 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 357 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 358 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 359 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 360 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 361 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 362 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 363 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 364 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 365 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 366 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 367 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 368 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 369 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 370 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 371 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 372 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 373 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 374 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 375 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 376 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 377 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 378 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 379 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 380 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 381 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 382 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 383 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 384 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 385 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 386 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 387 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 388 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 389 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 390 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 391 }; 392 393 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 394 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 395 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 396 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 397 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 398 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 399 }; 400 401 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 402 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 403 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 404 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 405 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 406 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 407 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 408 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 409 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 410 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 411 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 412 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 413 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 414 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 415 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 416 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 417 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 418 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 419 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 420 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 421 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 422 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 423 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 424 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 425 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 426 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 427 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 428 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 429 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 431 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 438 }; 439 440 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 441 /* Lock Det settings */ 442 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 443 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 444 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 445 446 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 447 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 448 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 449 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 450 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 451 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 452 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 453 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 454 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 455 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 456 }; 457 458 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 459 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 460 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 461 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 462 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 463 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 464 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 465 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 466 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 467 }; 468 469 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 490 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 491 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 492 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 493 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 494 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 495 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 496 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 497 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 498 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 499 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 500 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 501 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 502 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 503 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 504 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 508 }; 509 510 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 516 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 517 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 518 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 519 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 520 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 521 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 522 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 523 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 524 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 525 }; 526 527 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 548 }; 549 550 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 558 }; 559 560 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 561 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 562 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 563 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 564 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 565 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 566 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 567 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 568 }; 569 570 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 571 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 572 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 573 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 574 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 575 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 576 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 577 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 578 }; 579 580 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 588 }; 589 590 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 591 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 592 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 593 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 594 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 595 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 596 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 597 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 598 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 599 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 600 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 601 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 602 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 603 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 604 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 605 }; 606 607 struct qmp_phy; 608 609 /* struct qmp_phy_cfg - per-PHY initialization config */ 610 struct qmp_phy_cfg { 611 /* phy-type - PCIE/UFS/USB */ 612 unsigned int type; 613 /* number of lanes provided by phy */ 614 int nlanes; 615 616 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 617 const struct qmp_phy_init_tbl *serdes_tbl; 618 int serdes_tbl_num; 619 const struct qmp_phy_init_tbl *tx_tbl; 620 int tx_tbl_num; 621 const struct qmp_phy_init_tbl *rx_tbl; 622 int rx_tbl_num; 623 const struct qmp_phy_init_tbl *pcs_tbl; 624 int pcs_tbl_num; 625 626 /* Init sequence for DP PHY block link rates */ 627 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 628 int serdes_tbl_rbr_num; 629 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 630 int serdes_tbl_hbr_num; 631 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 632 int serdes_tbl_hbr2_num; 633 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 634 int serdes_tbl_hbr3_num; 635 636 /* DP PHY callbacks */ 637 int (*configure_dp_phy)(struct qmp_phy *qphy); 638 void (*configure_dp_tx)(struct qmp_phy *qphy); 639 int (*calibrate_dp_phy)(struct qmp_phy *qphy); 640 void (*dp_aux_init)(struct qmp_phy *qphy); 641 642 /* clock ids to be requested */ 643 const char * const *clk_list; 644 int num_clks; 645 /* resets to be requested */ 646 const char * const *reset_list; 647 int num_resets; 648 /* regulators to be requested */ 649 const char * const *vreg_list; 650 int num_vregs; 651 652 /* array of registers with different offsets */ 653 const unsigned int *regs; 654 655 unsigned int start_ctrl; 656 unsigned int pwrdn_ctrl; 657 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 658 unsigned int phy_status; 659 660 /* true, if PHY needs delay after POWER_DOWN */ 661 bool has_pwrdn_delay; 662 /* power_down delay in usec */ 663 int pwrdn_delay_min; 664 int pwrdn_delay_max; 665 666 /* true, if PHY has a separate DP_COM control block */ 667 bool has_phy_dp_com_ctrl; 668 /* true, if PHY has secondary tx/rx lanes to be configured */ 669 bool is_dual_lane_phy; 670 }; 671 672 struct qmp_phy_combo_cfg { 673 const struct qmp_phy_cfg *usb_cfg; 674 const struct qmp_phy_cfg *dp_cfg; 675 }; 676 677 /** 678 * struct qmp_phy - per-lane phy descriptor 679 * 680 * @phy: generic phy 681 * @cfg: phy specific configuration 682 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 683 * @tx: iomapped memory space for lane's tx 684 * @rx: iomapped memory space for lane's rx 685 * @pcs: iomapped memory space for lane's pcs 686 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 687 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 688 * @pcs_misc: iomapped memory space for lane's pcs_misc 689 * @pipe_clk: pipe clock 690 * @index: lane index 691 * @qmp: QMP phy to which this lane belongs 692 * @lane_rst: lane's reset controller 693 * @mode: current PHY mode 694 * @dp_aux_cfg: Display port aux config 695 * @dp_opts: Display port optional config 696 * @dp_clks: Display port clocks 697 */ 698 struct qmp_phy { 699 struct phy *phy; 700 const struct qmp_phy_cfg *cfg; 701 void __iomem *serdes; 702 void __iomem *tx; 703 void __iomem *rx; 704 void __iomem *pcs; 705 void __iomem *tx2; 706 void __iomem *rx2; 707 void __iomem *pcs_misc; 708 struct clk *pipe_clk; 709 unsigned int index; 710 struct qcom_qmp *qmp; 711 struct reset_control *lane_rst; 712 enum phy_mode mode; 713 unsigned int dp_aux_cfg; 714 struct phy_configure_opts_dp dp_opts; 715 struct qmp_phy_dp_clks *dp_clks; 716 }; 717 718 struct qmp_phy_dp_clks { 719 struct qmp_phy *qphy; 720 struct clk_hw dp_link_hw; 721 struct clk_hw dp_pixel_hw; 722 }; 723 724 /** 725 * struct qcom_qmp - structure holding QMP phy block attributes 726 * 727 * @dev: device 728 * @dp_com: iomapped memory space for phy's dp_com control block 729 * 730 * @clks: array of clocks required by phy 731 * @resets: array of resets required by phy 732 * @vregs: regulator supplies bulk data 733 * 734 * @phys: array of per-lane phy descriptors 735 * @phy_mutex: mutex lock for PHY common block initialization 736 * @init_count: phy common block initialization count 737 * @ufs_reset: optional UFS PHY reset handle 738 */ 739 struct qcom_qmp { 740 struct device *dev; 741 void __iomem *dp_com; 742 743 struct clk_bulk_data *clks; 744 struct reset_control_bulk_data *resets; 745 struct regulator_bulk_data *vregs; 746 747 struct qmp_phy **phys; 748 749 struct mutex phy_mutex; 750 int init_count; 751 752 struct reset_control *ufs_reset; 753 }; 754 755 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); 756 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); 757 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); 758 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); 759 760 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); 761 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); 762 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); 763 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); 764 765 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 766 { 767 u32 reg; 768 769 reg = readl(base + offset); 770 reg |= val; 771 writel(reg, base + offset); 772 773 /* ensure that above write is through */ 774 readl(base + offset); 775 } 776 777 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 778 { 779 u32 reg; 780 781 reg = readl(base + offset); 782 reg &= ~val; 783 writel(reg, base + offset); 784 785 /* ensure that above write is through */ 786 readl(base + offset); 787 } 788 789 /* list of clocks required by phy */ 790 static const char * const qmp_v3_phy_clk_l[] = { 791 "aux", "cfg_ahb", "ref", "com_aux", 792 }; 793 794 static const char * const qmp_v4_phy_clk_l[] = { 795 "aux", "ref_clk_src", "ref", "com_aux", 796 }; 797 798 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 799 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 800 "aux", "ref_clk_src", "com_aux" 801 }; 802 803 /* list of resets */ 804 static const char * const msm8996_usb3phy_reset_l[] = { 805 "phy", "common", 806 }; 807 808 static const char * const sc7180_usb3phy_reset_l[] = { 809 "phy", 810 }; 811 812 /* list of regulators */ 813 static const char * const qmp_phy_vreg_l[] = { 814 "vdda-phy", "vdda-pll", 815 }; 816 817 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 818 .type = PHY_TYPE_USB3, 819 .nlanes = 1, 820 821 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 822 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 823 .tx_tbl = qmp_v3_usb3_tx_tbl, 824 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 825 .rx_tbl = qmp_v3_usb3_rx_tbl, 826 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 827 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 828 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 829 .clk_list = qmp_v3_phy_clk_l, 830 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 831 .reset_list = sc7180_usb3phy_reset_l, 832 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 833 .vreg_list = qmp_phy_vreg_l, 834 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 835 .regs = qmp_v3_usb3phy_regs_layout, 836 837 .start_ctrl = SERDES_START | PCS_START, 838 .pwrdn_ctrl = SW_PWRDN, 839 .phy_status = PHYSTATUS, 840 841 .has_pwrdn_delay = true, 842 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 843 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 844 845 .has_phy_dp_com_ctrl = true, 846 .is_dual_lane_phy = true, 847 }; 848 849 static const struct qmp_phy_cfg sc7180_dpphy_cfg = { 850 .type = PHY_TYPE_DP, 851 .nlanes = 1, 852 853 .serdes_tbl = qmp_v3_dp_serdes_tbl, 854 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 855 .tx_tbl = qmp_v3_dp_tx_tbl, 856 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 857 858 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 859 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 860 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 861 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 862 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 863 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 864 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 865 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 866 867 .clk_list = qmp_v3_phy_clk_l, 868 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 869 .reset_list = sc7180_usb3phy_reset_l, 870 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 871 .vreg_list = qmp_phy_vreg_l, 872 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 873 .regs = qmp_v3_usb3phy_regs_layout, 874 875 .has_phy_dp_com_ctrl = true, 876 .is_dual_lane_phy = true, 877 878 .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, 879 .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, 880 .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, 881 .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, 882 }; 883 884 static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { 885 .usb_cfg = &sc7180_usb3phy_cfg, 886 .dp_cfg = &sc7180_dpphy_cfg, 887 }; 888 889 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 890 .type = PHY_TYPE_USB3, 891 .nlanes = 1, 892 893 .serdes_tbl = sm8150_usb3_serdes_tbl, 894 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 895 .tx_tbl = sm8150_usb3_tx_tbl, 896 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 897 .rx_tbl = sm8150_usb3_rx_tbl, 898 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 899 .pcs_tbl = sm8150_usb3_pcs_tbl, 900 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 901 .clk_list = qmp_v4_phy_clk_l, 902 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 903 .reset_list = msm8996_usb3phy_reset_l, 904 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 905 .vreg_list = qmp_phy_vreg_l, 906 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 907 .regs = qmp_v4_usb3phy_regs_layout, 908 909 .start_ctrl = SERDES_START | PCS_START, 910 .pwrdn_ctrl = SW_PWRDN, 911 .phy_status = PHYSTATUS, 912 913 914 .has_pwrdn_delay = true, 915 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 916 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 917 918 .has_phy_dp_com_ctrl = true, 919 .is_dual_lane_phy = true, 920 }; 921 922 static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { 923 .type = PHY_TYPE_DP, 924 .nlanes = 1, 925 926 .serdes_tbl = qmp_v4_dp_serdes_tbl, 927 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 928 .tx_tbl = qmp_v4_dp_tx_tbl, 929 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 930 931 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 932 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 933 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 934 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 935 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 936 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 937 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 938 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 939 940 .clk_list = qmp_v3_phy_clk_l, 941 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 942 .reset_list = sc7180_usb3phy_reset_l, 943 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 944 .vreg_list = qmp_phy_vreg_l, 945 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 946 .regs = qmp_v3_usb3phy_regs_layout, 947 948 .has_phy_dp_com_ctrl = true, 949 .is_dual_lane_phy = true, 950 951 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 952 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 953 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 954 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 955 }; 956 957 static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { 958 .usb_cfg = &sm8150_usb3phy_cfg, 959 .dp_cfg = &sc8180x_dpphy_cfg, 960 }; 961 962 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 963 .type = PHY_TYPE_USB3, 964 .nlanes = 1, 965 966 .serdes_tbl = sm8150_usb3_serdes_tbl, 967 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 968 .tx_tbl = sm8250_usb3_tx_tbl, 969 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 970 .rx_tbl = sm8250_usb3_rx_tbl, 971 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 972 .pcs_tbl = sm8250_usb3_pcs_tbl, 973 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 974 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 975 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 976 .reset_list = msm8996_usb3phy_reset_l, 977 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 978 .vreg_list = qmp_phy_vreg_l, 979 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 980 .regs = qmp_v4_usb3phy_regs_layout, 981 982 .start_ctrl = SERDES_START | PCS_START, 983 .pwrdn_ctrl = SW_PWRDN, 984 .phy_status = PHYSTATUS, 985 986 .has_pwrdn_delay = true, 987 .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN, 988 .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX, 989 990 .has_phy_dp_com_ctrl = true, 991 .is_dual_lane_phy = true, 992 }; 993 994 static const struct qmp_phy_cfg sm8250_dpphy_cfg = { 995 .type = PHY_TYPE_DP, 996 .nlanes = 1, 997 998 .serdes_tbl = qmp_v4_dp_serdes_tbl, 999 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1000 .tx_tbl = qmp_v4_dp_tx_tbl, 1001 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1002 1003 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1004 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1005 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1006 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1007 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1008 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1009 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1010 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1011 1012 .clk_list = qmp_v4_phy_clk_l, 1013 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1014 .reset_list = msm8996_usb3phy_reset_l, 1015 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1016 .vreg_list = qmp_phy_vreg_l, 1017 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1018 .regs = qmp_v4_usb3phy_regs_layout, 1019 1020 .has_phy_dp_com_ctrl = true, 1021 .is_dual_lane_phy = true, 1022 1023 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1024 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1025 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1026 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1027 }; 1028 1029 static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { 1030 .usb_cfg = &sm8250_usb3phy_cfg, 1031 .dp_cfg = &sm8250_dpphy_cfg, 1032 }; 1033 1034 static void qcom_qmp_phy_combo_configure_lane(void __iomem *base, 1035 const unsigned int *regs, 1036 const struct qmp_phy_init_tbl tbl[], 1037 int num, 1038 u8 lane_mask) 1039 { 1040 int i; 1041 const struct qmp_phy_init_tbl *t = tbl; 1042 1043 if (!t) 1044 return; 1045 1046 for (i = 0; i < num; i++, t++) { 1047 if (!(t->lane_mask & lane_mask)) 1048 continue; 1049 1050 if (t->in_layout) 1051 writel(t->val, base + regs[t->offset]); 1052 else 1053 writel(t->val, base + t->offset); 1054 } 1055 } 1056 1057 static void qcom_qmp_phy_combo_configure(void __iomem *base, 1058 const unsigned int *regs, 1059 const struct qmp_phy_init_tbl tbl[], 1060 int num) 1061 { 1062 qcom_qmp_phy_combo_configure_lane(base, regs, tbl, num, 0xff); 1063 } 1064 1065 static int qcom_qmp_phy_combo_serdes_init(struct qmp_phy *qphy) 1066 { 1067 const struct qmp_phy_cfg *cfg = qphy->cfg; 1068 void __iomem *serdes = qphy->serdes; 1069 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1070 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1071 int serdes_tbl_num = cfg->serdes_tbl_num; 1072 1073 qcom_qmp_phy_combo_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 1074 1075 if (cfg->type == PHY_TYPE_DP) { 1076 switch (dp_opts->link_rate) { 1077 case 1620: 1078 qcom_qmp_phy_combo_configure(serdes, cfg->regs, 1079 cfg->serdes_tbl_rbr, 1080 cfg->serdes_tbl_rbr_num); 1081 break; 1082 case 2700: 1083 qcom_qmp_phy_combo_configure(serdes, cfg->regs, 1084 cfg->serdes_tbl_hbr, 1085 cfg->serdes_tbl_hbr_num); 1086 break; 1087 case 5400: 1088 qcom_qmp_phy_combo_configure(serdes, cfg->regs, 1089 cfg->serdes_tbl_hbr2, 1090 cfg->serdes_tbl_hbr2_num); 1091 break; 1092 case 8100: 1093 qcom_qmp_phy_combo_configure(serdes, cfg->regs, 1094 cfg->serdes_tbl_hbr3, 1095 cfg->serdes_tbl_hbr3_num); 1096 break; 1097 default: 1098 /* Other link rates aren't supported */ 1099 return -EINVAL; 1100 } 1101 } 1102 1103 return 0; 1104 } 1105 1106 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) 1107 { 1108 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1109 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1110 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1111 1112 /* Turn on BIAS current for PHY/PLL */ 1113 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1114 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1115 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1116 1117 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1118 1119 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1120 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1121 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1122 DP_PHY_PD_CTL_DP_CLAMP_EN, 1123 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1124 1125 writel(QSERDES_V3_COM_BIAS_EN | 1126 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1127 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1128 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1129 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1130 1131 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1132 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1133 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1134 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1135 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1136 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1137 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1138 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1139 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1140 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1141 qphy->dp_aux_cfg = 0; 1142 1143 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1144 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1145 PHY_AUX_REQ_ERR_MASK, 1146 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1147 } 1148 1149 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1150 { 0x00, 0x0c, 0x15, 0x1a }, 1151 { 0x02, 0x0e, 0x16, 0xff }, 1152 { 0x02, 0x11, 0xff, 0xff }, 1153 { 0x04, 0xff, 0xff, 0xff } 1154 }; 1155 1156 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1157 { 0x02, 0x12, 0x16, 0x1a }, 1158 { 0x09, 0x19, 0x1f, 0xff }, 1159 { 0x10, 0x1f, 0xff, 0xff }, 1160 { 0x1f, 0xff, 0xff, 0xff } 1161 }; 1162 1163 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1164 { 0x00, 0x0c, 0x14, 0x19 }, 1165 { 0x00, 0x0b, 0x12, 0xff }, 1166 { 0x00, 0x0b, 0xff, 0xff }, 1167 { 0x04, 0xff, 0xff, 0xff } 1168 }; 1169 1170 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1171 { 0x08, 0x0f, 0x16, 0x1f }, 1172 { 0x11, 0x1e, 0x1f, 0xff }, 1173 { 0x19, 0x1f, 0xff, 0xff }, 1174 { 0x1f, 0xff, 0xff, 0xff } 1175 }; 1176 1177 static int qcom_qmp_phy_combo_configure_dp_swing(struct qmp_phy *qphy, 1178 unsigned int drv_lvl_reg, unsigned int emp_post_reg) 1179 { 1180 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1181 unsigned int v_level = 0, p_level = 0; 1182 u8 voltage_swing_cfg, pre_emphasis_cfg; 1183 int i; 1184 1185 for (i = 0; i < dp_opts->lanes; i++) { 1186 v_level = max(v_level, dp_opts->voltage[i]); 1187 p_level = max(p_level, dp_opts->pre[i]); 1188 } 1189 1190 if (dp_opts->link_rate <= 2700) { 1191 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level]; 1192 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level]; 1193 } else { 1194 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level]; 1195 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level]; 1196 } 1197 1198 /* TODO: Move check to config check */ 1199 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1200 return -EINVAL; 1201 1202 /* Enable MUX to use Cursor values from these registers */ 1203 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1204 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 1205 1206 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); 1207 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); 1208 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); 1209 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); 1210 1211 return 0; 1212 } 1213 1214 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) 1215 { 1216 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1217 u32 bias_en, drvr_en; 1218 1219 if (qcom_qmp_phy_combo_configure_dp_swing(qphy, 1220 QSERDES_V3_TX_TX_DRV_LVL, 1221 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) 1222 return; 1223 1224 if (dp_opts->lanes == 1) { 1225 bias_en = 0x3e; 1226 drvr_en = 0x13; 1227 } else { 1228 bias_en = 0x3f; 1229 drvr_en = 0x10; 1230 } 1231 1232 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1233 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1234 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1235 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1236 } 1237 1238 static bool qcom_qmp_phy_combo_configure_dp_mode(struct qmp_phy *qphy) 1239 { 1240 u32 val; 1241 bool reverse = false; 1242 1243 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1244 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 1245 1246 /* 1247 * TODO: Assume orientation is CC1 for now and two lanes, need to 1248 * use type-c connector to understand orientation and lanes. 1249 * 1250 * Otherwise val changes to be like below if this code understood 1251 * the orientation of the type-c cable. 1252 * 1253 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) 1254 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 1255 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 1256 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1257 * if (orientation == ORIENTATION_CC2) 1258 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); 1259 */ 1260 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1261 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1262 1263 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); 1264 1265 return reverse; 1266 } 1267 1268 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) 1269 { 1270 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1271 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1272 u32 phy_vco_div, status; 1273 unsigned long pixel_freq; 1274 1275 qcom_qmp_phy_combo_configure_dp_mode(qphy); 1276 1277 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 1278 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 1279 1280 switch (dp_opts->link_rate) { 1281 case 1620: 1282 phy_vco_div = 0x1; 1283 pixel_freq = 1620000000UL / 2; 1284 break; 1285 case 2700: 1286 phy_vco_div = 0x1; 1287 pixel_freq = 2700000000UL / 2; 1288 break; 1289 case 5400: 1290 phy_vco_div = 0x2; 1291 pixel_freq = 5400000000UL / 4; 1292 break; 1293 case 8100: 1294 phy_vco_div = 0x0; 1295 pixel_freq = 8100000000UL / 6; 1296 break; 1297 default: 1298 /* Other link rates aren't supported */ 1299 return -EINVAL; 1300 } 1301 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); 1302 1303 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1304 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1305 1306 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1307 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1308 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1309 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1310 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1311 1312 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); 1313 1314 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, 1315 status, 1316 ((status & BIT(0)) > 0), 1317 500, 1318 10000)) 1319 return -ETIMEDOUT; 1320 1321 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1322 1323 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1324 status, 1325 ((status & BIT(1)) > 0), 1326 500, 1327 10000)) 1328 return -ETIMEDOUT; 1329 1330 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1331 udelay(2000); 1332 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1333 1334 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1335 status, 1336 ((status & BIT(1)) > 0), 1337 500, 1338 10000); 1339 } 1340 1341 /* 1342 * We need to calibrate the aux setting here as many times 1343 * as the caller tries 1344 */ 1345 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) 1346 { 1347 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 1348 u8 val; 1349 1350 qphy->dp_aux_cfg++; 1351 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1352 val = cfg1_settings[qphy->dp_aux_cfg]; 1353 1354 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1355 1356 return 0; 1357 } 1358 1359 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) 1360 { 1361 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1362 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1363 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1364 1365 /* Turn on BIAS current for PHY/PLL */ 1366 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 1367 1368 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1369 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1370 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1371 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1372 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1373 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1374 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1375 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1376 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1377 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1378 qphy->dp_aux_cfg = 0; 1379 1380 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1381 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1382 PHY_AUX_REQ_ERR_MASK, 1383 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 1384 } 1385 1386 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) 1387 { 1388 /* Program default values before writing proper values */ 1389 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1390 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1391 1392 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1393 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1394 1395 qcom_qmp_phy_combo_configure_dp_swing(qphy, 1396 QSERDES_V4_TX_TX_DRV_LVL, 1397 QSERDES_V4_TX_TX_EMP_POST1_LVL); 1398 } 1399 1400 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 1401 { 1402 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1403 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1404 u32 phy_vco_div, status; 1405 unsigned long pixel_freq; 1406 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1407 bool reverse; 1408 1409 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); 1410 1411 reverse = qcom_qmp_phy_combo_configure_dp_mode(qphy); 1412 1413 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1414 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1415 1416 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 1417 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 1418 1419 switch (dp_opts->link_rate) { 1420 case 1620: 1421 phy_vco_div = 0x1; 1422 pixel_freq = 1620000000UL / 2; 1423 break; 1424 case 2700: 1425 phy_vco_div = 0x1; 1426 pixel_freq = 2700000000UL / 2; 1427 break; 1428 case 5400: 1429 phy_vco_div = 0x2; 1430 pixel_freq = 5400000000UL / 4; 1431 break; 1432 case 8100: 1433 phy_vco_div = 0x0; 1434 pixel_freq = 8100000000UL / 6; 1435 break; 1436 default: 1437 /* Other link rates aren't supported */ 1438 return -EINVAL; 1439 } 1440 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); 1441 1442 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1443 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1444 1445 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1446 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1447 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1448 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1449 1450 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); 1451 1452 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, 1453 status, 1454 ((status & BIT(0)) > 0), 1455 500, 1456 10000)) 1457 return -ETIMEDOUT; 1458 1459 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1460 status, 1461 ((status & BIT(0)) > 0), 1462 500, 1463 10000)) 1464 return -ETIMEDOUT; 1465 1466 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1467 status, 1468 ((status & BIT(1)) > 0), 1469 500, 1470 10000)) 1471 return -ETIMEDOUT; 1472 1473 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1474 1475 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1476 status, 1477 ((status & BIT(0)) > 0), 1478 500, 1479 10000)) 1480 return -ETIMEDOUT; 1481 1482 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1483 status, 1484 ((status & BIT(1)) > 0), 1485 500, 1486 10000)) 1487 return -ETIMEDOUT; 1488 1489 /* 1490 * At least for 7nm DP PHY this has to be done after enabling link 1491 * clock. 1492 */ 1493 1494 if (dp_opts->lanes == 1) { 1495 bias0_en = reverse ? 0x3e : 0x15; 1496 bias1_en = reverse ? 0x15 : 0x3e; 1497 drvr0_en = reverse ? 0x13 : 0x10; 1498 drvr1_en = reverse ? 0x10 : 0x13; 1499 } else if (dp_opts->lanes == 2) { 1500 bias0_en = reverse ? 0x3f : 0x15; 1501 bias1_en = reverse ? 0x15 : 0x3f; 1502 drvr0_en = 0x10; 1503 drvr1_en = 0x10; 1504 } else { 1505 bias0_en = 0x3f; 1506 bias1_en = 0x3f; 1507 drvr0_en = 0x10; 1508 drvr1_en = 0x10; 1509 } 1510 1511 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1512 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1513 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1514 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1515 1516 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1517 udelay(2000); 1518 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1519 1520 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1521 status, 1522 ((status & BIT(1)) > 0), 1523 500, 1524 10000)) 1525 return -ETIMEDOUT; 1526 1527 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); 1528 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); 1529 1530 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1531 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1532 1533 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1534 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1535 1536 return 0; 1537 } 1538 1539 /* 1540 * We need to calibrate the aux setting here as many times 1541 * as the caller tries 1542 */ 1543 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) 1544 { 1545 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 1546 u8 val; 1547 1548 qphy->dp_aux_cfg++; 1549 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1550 val = cfg1_settings[qphy->dp_aux_cfg]; 1551 1552 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1553 1554 return 0; 1555 } 1556 1557 static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1558 { 1559 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1560 struct qmp_phy *qphy = phy_get_drvdata(phy); 1561 const struct qmp_phy_cfg *cfg = qphy->cfg; 1562 1563 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 1564 if (qphy->dp_opts.set_voltages) { 1565 cfg->configure_dp_tx(qphy); 1566 qphy->dp_opts.set_voltages = 0; 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 1573 { 1574 struct qmp_phy *qphy = phy_get_drvdata(phy); 1575 const struct qmp_phy_cfg *cfg = qphy->cfg; 1576 1577 if (cfg->calibrate_dp_phy) 1578 return cfg->calibrate_dp_phy(qphy); 1579 1580 return 0; 1581 } 1582 1583 static int qcom_qmp_phy_combo_com_init(struct qmp_phy *qphy) 1584 { 1585 struct qcom_qmp *qmp = qphy->qmp; 1586 const struct qmp_phy_cfg *cfg = qphy->cfg; 1587 void __iomem *pcs = qphy->pcs; 1588 void __iomem *dp_com = qmp->dp_com; 1589 int ret; 1590 1591 mutex_lock(&qmp->phy_mutex); 1592 if (qmp->init_count++) { 1593 mutex_unlock(&qmp->phy_mutex); 1594 return 0; 1595 } 1596 1597 /* turn on regulator supplies */ 1598 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1599 if (ret) { 1600 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1601 goto err_unlock; 1602 } 1603 1604 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1605 if (ret) { 1606 dev_err(qmp->dev, "reset assert failed\n"); 1607 goto err_disable_regulators; 1608 } 1609 1610 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1611 if (ret) { 1612 dev_err(qmp->dev, "reset deassert failed\n"); 1613 goto err_disable_regulators; 1614 } 1615 1616 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1617 if (ret) 1618 goto err_assert_reset; 1619 1620 if (cfg->has_phy_dp_com_ctrl) { 1621 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 1622 SW_PWRDN); 1623 /* override hardware control for reset of qmp phy */ 1624 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1625 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1626 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1627 1628 /* Default type-c orientation, i.e CC1 */ 1629 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1630 1631 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 1632 USB3_MODE | DP_MODE); 1633 1634 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1635 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1636 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1637 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1638 1639 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1640 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1641 } 1642 1643 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1644 qphy_setbits(pcs, 1645 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1646 cfg->pwrdn_ctrl); 1647 else 1648 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 1649 cfg->pwrdn_ctrl); 1650 1651 mutex_unlock(&qmp->phy_mutex); 1652 1653 return 0; 1654 1655 err_assert_reset: 1656 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1657 err_disable_regulators: 1658 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1659 err_unlock: 1660 mutex_unlock(&qmp->phy_mutex); 1661 1662 return ret; 1663 } 1664 1665 static int qcom_qmp_phy_combo_com_exit(struct qmp_phy *qphy) 1666 { 1667 struct qcom_qmp *qmp = qphy->qmp; 1668 const struct qmp_phy_cfg *cfg = qphy->cfg; 1669 1670 mutex_lock(&qmp->phy_mutex); 1671 if (--qmp->init_count) { 1672 mutex_unlock(&qmp->phy_mutex); 1673 return 0; 1674 } 1675 1676 reset_control_assert(qmp->ufs_reset); 1677 1678 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1679 1680 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1681 1682 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1683 1684 mutex_unlock(&qmp->phy_mutex); 1685 1686 return 0; 1687 } 1688 1689 static int qcom_qmp_phy_combo_init(struct phy *phy) 1690 { 1691 struct qmp_phy *qphy = phy_get_drvdata(phy); 1692 struct qcom_qmp *qmp = qphy->qmp; 1693 const struct qmp_phy_cfg *cfg = qphy->cfg; 1694 int ret; 1695 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1696 1697 ret = qcom_qmp_phy_combo_com_init(qphy); 1698 if (ret) 1699 return ret; 1700 1701 if (cfg->type == PHY_TYPE_DP) 1702 cfg->dp_aux_init(qphy); 1703 1704 return 0; 1705 } 1706 1707 static int qcom_qmp_phy_combo_power_on(struct phy *phy) 1708 { 1709 struct qmp_phy *qphy = phy_get_drvdata(phy); 1710 struct qcom_qmp *qmp = qphy->qmp; 1711 const struct qmp_phy_cfg *cfg = qphy->cfg; 1712 void __iomem *tx = qphy->tx; 1713 void __iomem *rx = qphy->rx; 1714 void __iomem *pcs = qphy->pcs; 1715 void __iomem *status; 1716 unsigned int mask, val, ready; 1717 int ret; 1718 1719 qcom_qmp_phy_combo_serdes_init(qphy); 1720 1721 ret = clk_prepare_enable(qphy->pipe_clk); 1722 if (ret) { 1723 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1724 return ret; 1725 } 1726 1727 /* Tx, Rx, and PCS configurations */ 1728 qcom_qmp_phy_combo_configure_lane(tx, cfg->regs, 1729 cfg->tx_tbl, cfg->tx_tbl_num, 1); 1730 1731 /* Configuration for other LANE for USB-DP combo PHY */ 1732 if (cfg->is_dual_lane_phy) { 1733 qcom_qmp_phy_combo_configure_lane(qphy->tx2, cfg->regs, 1734 cfg->tx_tbl, cfg->tx_tbl_num, 2); 1735 } 1736 1737 /* Configure special DP tx tunings */ 1738 if (cfg->type == PHY_TYPE_DP) 1739 cfg->configure_dp_tx(qphy); 1740 1741 qcom_qmp_phy_combo_configure_lane(rx, cfg->regs, 1742 cfg->rx_tbl, cfg->rx_tbl_num, 1); 1743 1744 if (cfg->is_dual_lane_phy) { 1745 qcom_qmp_phy_combo_configure_lane(qphy->rx2, cfg->regs, 1746 cfg->rx_tbl, cfg->rx_tbl_num, 2); 1747 } 1748 1749 /* Configure link rate, swing, etc. */ 1750 if (cfg->type == PHY_TYPE_DP) { 1751 cfg->configure_dp_phy(qphy); 1752 } else { 1753 qcom_qmp_phy_combo_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1754 } 1755 1756 ret = reset_control_deassert(qmp->ufs_reset); 1757 if (ret) 1758 goto err_disable_pipe_clk; 1759 1760 if (cfg->has_pwrdn_delay) 1761 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 1762 1763 if (cfg->type != PHY_TYPE_DP) { 1764 /* Pull PHY out of reset state */ 1765 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1766 /* start SerDes and Phy-Coding-Sublayer */ 1767 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1768 1769 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1770 mask = cfg->phy_status; 1771 ready = 0; 1772 1773 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 1774 PHY_INIT_COMPLETE_TIMEOUT); 1775 if (ret) { 1776 dev_err(qmp->dev, "phy initialization timed-out\n"); 1777 goto err_disable_pipe_clk; 1778 } 1779 } 1780 return 0; 1781 1782 err_disable_pipe_clk: 1783 clk_disable_unprepare(qphy->pipe_clk); 1784 1785 return ret; 1786 } 1787 1788 static int qcom_qmp_phy_combo_power_off(struct phy *phy) 1789 { 1790 struct qmp_phy *qphy = phy_get_drvdata(phy); 1791 const struct qmp_phy_cfg *cfg = qphy->cfg; 1792 1793 clk_disable_unprepare(qphy->pipe_clk); 1794 1795 if (cfg->type == PHY_TYPE_DP) { 1796 /* Assert DP PHY power down */ 1797 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1798 } else { 1799 /* PHY reset */ 1800 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1801 1802 /* stop SerDes and Phy-Coding-Sublayer */ 1803 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 1804 1805 /* Put PHY into POWER DOWN state: active low */ 1806 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 1807 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1808 cfg->pwrdn_ctrl); 1809 } else { 1810 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, 1811 cfg->pwrdn_ctrl); 1812 } 1813 } 1814 1815 return 0; 1816 } 1817 1818 static int qcom_qmp_phy_combo_exit(struct phy *phy) 1819 { 1820 struct qmp_phy *qphy = phy_get_drvdata(phy); 1821 1822 qcom_qmp_phy_combo_com_exit(qphy); 1823 1824 return 0; 1825 } 1826 1827 static int qcom_qmp_phy_combo_enable(struct phy *phy) 1828 { 1829 int ret; 1830 1831 ret = qcom_qmp_phy_combo_init(phy); 1832 if (ret) 1833 return ret; 1834 1835 ret = qcom_qmp_phy_combo_power_on(phy); 1836 if (ret) 1837 qcom_qmp_phy_combo_exit(phy); 1838 1839 return ret; 1840 } 1841 1842 static int qcom_qmp_phy_combo_disable(struct phy *phy) 1843 { 1844 int ret; 1845 1846 ret = qcom_qmp_phy_combo_power_off(phy); 1847 if (ret) 1848 return ret; 1849 return qcom_qmp_phy_combo_exit(phy); 1850 } 1851 1852 static int qcom_qmp_phy_combo_set_mode(struct phy *phy, 1853 enum phy_mode mode, int submode) 1854 { 1855 struct qmp_phy *qphy = phy_get_drvdata(phy); 1856 1857 qphy->mode = mode; 1858 1859 return 0; 1860 } 1861 1862 static void qcom_qmp_phy_combo_enable_autonomous_mode(struct qmp_phy *qphy) 1863 { 1864 const struct qmp_phy_cfg *cfg = qphy->cfg; 1865 void __iomem *pcs = qphy->pcs; 1866 void __iomem *pcs_misc = qphy->pcs_misc; 1867 u32 intr_mask; 1868 1869 if (qphy->mode == PHY_MODE_USB_HOST_SS || 1870 qphy->mode == PHY_MODE_USB_DEVICE_SS) 1871 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1872 else 1873 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1874 1875 /* Clear any pending interrupts status */ 1876 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1877 /* Writing 1 followed by 0 clears the interrupt */ 1878 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1879 1880 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1881 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1882 1883 /* Enable required PHY autonomous mode interrupts */ 1884 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1885 1886 /* Enable i/o clamp_n for autonomous mode */ 1887 if (pcs_misc) 1888 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1889 } 1890 1891 static void qcom_qmp_phy_combo_disable_autonomous_mode(struct qmp_phy *qphy) 1892 { 1893 const struct qmp_phy_cfg *cfg = qphy->cfg; 1894 void __iomem *pcs = qphy->pcs; 1895 void __iomem *pcs_misc = qphy->pcs_misc; 1896 1897 /* Disable i/o clamp_n on resume for normal mode */ 1898 if (pcs_misc) 1899 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1900 1901 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1902 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1903 1904 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1905 /* Writing 1 followed by 0 clears the interrupt */ 1906 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1907 } 1908 1909 static int __maybe_unused qcom_qmp_phy_combo_runtime_suspend(struct device *dev) 1910 { 1911 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1912 struct qmp_phy *qphy = qmp->phys[0]; 1913 const struct qmp_phy_cfg *cfg = qphy->cfg; 1914 1915 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 1916 1917 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 1918 if (cfg->type != PHY_TYPE_USB3) 1919 return 0; 1920 1921 if (!qmp->init_count) { 1922 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1923 return 0; 1924 } 1925 1926 qcom_qmp_phy_combo_enable_autonomous_mode(qphy); 1927 1928 clk_disable_unprepare(qphy->pipe_clk); 1929 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1930 1931 return 0; 1932 } 1933 1934 static int __maybe_unused qcom_qmp_phy_combo_runtime_resume(struct device *dev) 1935 { 1936 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1937 struct qmp_phy *qphy = qmp->phys[0]; 1938 const struct qmp_phy_cfg *cfg = qphy->cfg; 1939 int ret = 0; 1940 1941 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 1942 1943 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 1944 if (cfg->type != PHY_TYPE_USB3) 1945 return 0; 1946 1947 if (!qmp->init_count) { 1948 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1949 return 0; 1950 } 1951 1952 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1953 if (ret) 1954 return ret; 1955 1956 ret = clk_prepare_enable(qphy->pipe_clk); 1957 if (ret) { 1958 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1959 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1960 return ret; 1961 } 1962 1963 qcom_qmp_phy_combo_disable_autonomous_mode(qphy); 1964 1965 return 0; 1966 } 1967 1968 static int qcom_qmp_phy_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 1969 { 1970 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1971 int num = cfg->num_vregs; 1972 int i; 1973 1974 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 1975 if (!qmp->vregs) 1976 return -ENOMEM; 1977 1978 for (i = 0; i < num; i++) 1979 qmp->vregs[i].supply = cfg->vreg_list[i]; 1980 1981 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1982 } 1983 1984 static int qcom_qmp_phy_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 1985 { 1986 struct qcom_qmp *qmp = dev_get_drvdata(dev); 1987 int i; 1988 int ret; 1989 1990 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 1991 sizeof(*qmp->resets), GFP_KERNEL); 1992 if (!qmp->resets) 1993 return -ENOMEM; 1994 1995 for (i = 0; i < cfg->num_resets; i++) 1996 qmp->resets[i].id = cfg->reset_list[i]; 1997 1998 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 1999 if (ret) 2000 return dev_err_probe(dev, ret, "failed to get resets\n"); 2001 2002 return 0; 2003 } 2004 2005 static int qcom_qmp_phy_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2006 { 2007 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2008 int num = cfg->num_clks; 2009 int i; 2010 2011 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2012 if (!qmp->clks) 2013 return -ENOMEM; 2014 2015 for (i = 0; i < num; i++) 2016 qmp->clks[i].id = cfg->clk_list[i]; 2017 2018 return devm_clk_bulk_get(dev, num, qmp->clks); 2019 } 2020 2021 static void phy_clk_release_provider(void *res) 2022 { 2023 of_clk_del_provider(res); 2024 } 2025 2026 /* 2027 * Register a fixed rate pipe clock. 2028 * 2029 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2030 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2031 * by the PHY driver for its operations. 2032 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2033 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2034 * Below picture shows this relationship. 2035 * 2036 * +---------------+ 2037 * | PHY block |<<---------------------------------------+ 2038 * | | | 2039 * | +-------+ | +-----+ | 2040 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2041 * clk | +-------+ | +-----+ 2042 * +---------------+ 2043 */ 2044 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2045 { 2046 struct clk_fixed_rate *fixed; 2047 struct clk_init_data init = { }; 2048 int ret; 2049 2050 ret = of_property_read_string(np, "clock-output-names", &init.name); 2051 if (ret) { 2052 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2053 return ret; 2054 } 2055 2056 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2057 if (!fixed) 2058 return -ENOMEM; 2059 2060 init.ops = &clk_fixed_rate_ops; 2061 2062 /* controllers using QMP phys use 125MHz pipe clock interface */ 2063 fixed->fixed_rate = 125000000; 2064 fixed->hw.init = &init; 2065 2066 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2067 if (ret) 2068 return ret; 2069 2070 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2071 if (ret) 2072 return ret; 2073 2074 /* 2075 * Roll a devm action because the clock provider is the child node, but 2076 * the child node is not actually a device. 2077 */ 2078 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2079 } 2080 2081 /* 2082 * Display Port PLL driver block diagram for branch clocks 2083 * 2084 * +------------------------------+ 2085 * | DP_VCO_CLK | 2086 * | | 2087 * | +-------------------+ | 2088 * | | (DP PLL/VCO) | | 2089 * | +---------+---------+ | 2090 * | v | 2091 * | +----------+-----------+ | 2092 * | | hsclk_divsel_clk_src | | 2093 * | +----------+-----------+ | 2094 * +------------------------------+ 2095 * | 2096 * +---------<---------v------------>----------+ 2097 * | | 2098 * +--------v----------------+ | 2099 * | dp_phy_pll_link_clk | | 2100 * | link_clk | | 2101 * +--------+----------------+ | 2102 * | | 2103 * | | 2104 * v v 2105 * Input to DISPCC block | 2106 * for link clk, crypto clk | 2107 * and interface clock | 2108 * | 2109 * | 2110 * +--------<------------+-----------------+---<---+ 2111 * | | | 2112 * +----v---------+ +--------v-----+ +--------v------+ 2113 * | vco_divided | | vco_divided | | vco_divided | 2114 * | _clk_src | | _clk_src | | _clk_src | 2115 * | | | | | | 2116 * |divsel_six | | divsel_two | | divsel_four | 2117 * +-------+------+ +-----+--------+ +--------+------+ 2118 * | | | 2119 * v---->----------v-------------<------v 2120 * | 2121 * +----------+-----------------+ 2122 * | dp_phy_pll_vco_div_clk | 2123 * +---------+------------------+ 2124 * | 2125 * v 2126 * Input to DISPCC block 2127 * for DP pixel clock 2128 * 2129 */ 2130 static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 2131 struct clk_rate_request *req) 2132 { 2133 switch (req->rate) { 2134 case 1620000000UL / 2: 2135 case 2700000000UL / 2: 2136 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2137 return 0; 2138 default: 2139 return -EINVAL; 2140 } 2141 } 2142 2143 static unsigned long 2144 qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2145 { 2146 const struct qmp_phy_dp_clks *dp_clks; 2147 const struct qmp_phy *qphy; 2148 const struct phy_configure_opts_dp *dp_opts; 2149 2150 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 2151 qphy = dp_clks->qphy; 2152 dp_opts = &qphy->dp_opts; 2153 2154 switch (dp_opts->link_rate) { 2155 case 1620: 2156 return 1620000000UL / 2; 2157 case 2700: 2158 return 2700000000UL / 2; 2159 case 5400: 2160 return 5400000000UL / 4; 2161 case 8100: 2162 return 8100000000UL / 6; 2163 default: 2164 return 0; 2165 } 2166 } 2167 2168 static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 2169 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 2170 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 2171 }; 2172 2173 static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 2174 struct clk_rate_request *req) 2175 { 2176 switch (req->rate) { 2177 case 162000000: 2178 case 270000000: 2179 case 540000000: 2180 case 810000000: 2181 return 0; 2182 default: 2183 return -EINVAL; 2184 } 2185 } 2186 2187 static unsigned long 2188 qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2189 { 2190 const struct qmp_phy_dp_clks *dp_clks; 2191 const struct qmp_phy *qphy; 2192 const struct phy_configure_opts_dp *dp_opts; 2193 2194 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 2195 qphy = dp_clks->qphy; 2196 dp_opts = &qphy->dp_opts; 2197 2198 switch (dp_opts->link_rate) { 2199 case 1620: 2200 case 2700: 2201 case 5400: 2202 case 8100: 2203 return dp_opts->link_rate * 100000; 2204 default: 2205 return 0; 2206 } 2207 } 2208 2209 static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 2210 .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 2211 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 2212 }; 2213 2214 static struct clk_hw * 2215 qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2216 { 2217 struct qmp_phy_dp_clks *dp_clks = data; 2218 unsigned int idx = clkspec->args[0]; 2219 2220 if (idx >= 2) { 2221 pr_err("%s: invalid index %u\n", __func__, idx); 2222 return ERR_PTR(-EINVAL); 2223 } 2224 2225 if (idx == 0) 2226 return &dp_clks->dp_link_hw; 2227 2228 return &dp_clks->dp_pixel_hw; 2229 } 2230 2231 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 2232 struct device_node *np) 2233 { 2234 struct clk_init_data init = { }; 2235 struct qmp_phy_dp_clks *dp_clks; 2236 char name[64]; 2237 int ret; 2238 2239 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 2240 if (!dp_clks) 2241 return -ENOMEM; 2242 2243 dp_clks->qphy = qphy; 2244 qphy->dp_clks = dp_clks; 2245 2246 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 2247 init.ops = &qcom_qmp_dp_link_clk_ops; 2248 init.name = name; 2249 dp_clks->dp_link_hw.init = &init; 2250 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 2251 if (ret) 2252 return ret; 2253 2254 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 2255 init.ops = &qcom_qmp_dp_pixel_clk_ops; 2256 init.name = name; 2257 dp_clks->dp_pixel_hw.init = &init; 2258 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 2259 if (ret) 2260 return ret; 2261 2262 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 2263 if (ret) 2264 return ret; 2265 2266 /* 2267 * Roll a devm action because the clock provider is the child node, but 2268 * the child node is not actually a device. 2269 */ 2270 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2271 } 2272 2273 static const struct phy_ops qcom_qmp_phy_combo_usb_ops = { 2274 .init = qcom_qmp_phy_combo_enable, 2275 .exit = qcom_qmp_phy_combo_disable, 2276 .set_mode = qcom_qmp_phy_combo_set_mode, 2277 .owner = THIS_MODULE, 2278 }; 2279 2280 static const struct phy_ops qcom_qmp_phy_combo_dp_ops = { 2281 .init = qcom_qmp_phy_combo_init, 2282 .configure = qcom_qmp_dp_phy_configure, 2283 .power_on = qcom_qmp_phy_combo_power_on, 2284 .calibrate = qcom_qmp_dp_phy_calibrate, 2285 .power_off = qcom_qmp_phy_combo_power_off, 2286 .exit = qcom_qmp_phy_combo_exit, 2287 .set_mode = qcom_qmp_phy_combo_set_mode, 2288 .owner = THIS_MODULE, 2289 }; 2290 2291 static 2292 int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id, 2293 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2294 { 2295 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2296 struct phy *generic_phy; 2297 struct qmp_phy *qphy; 2298 const struct phy_ops *ops; 2299 char prop_name[MAX_PROP_NAME]; 2300 int ret; 2301 2302 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2303 if (!qphy) 2304 return -ENOMEM; 2305 2306 qphy->cfg = cfg; 2307 qphy->serdes = serdes; 2308 /* 2309 * Get memory resources for each phy lane: 2310 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2311 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2312 * For single lane PHYs: pcs_misc (optional) -> 3. 2313 */ 2314 qphy->tx = of_iomap(np, 0); 2315 if (!qphy->tx) 2316 return -ENOMEM; 2317 2318 qphy->rx = of_iomap(np, 1); 2319 if (!qphy->rx) 2320 return -ENOMEM; 2321 2322 qphy->pcs = of_iomap(np, 2); 2323 if (!qphy->pcs) 2324 return -ENOMEM; 2325 2326 /* 2327 * If this is a dual-lane PHY, then there should be registers for the 2328 * second lane. Some old device trees did not specify this, so fall 2329 * back to old legacy behavior of assuming they can be reached at an 2330 * offset from the first lane. 2331 */ 2332 if (cfg->is_dual_lane_phy) { 2333 qphy->tx2 = of_iomap(np, 3); 2334 qphy->rx2 = of_iomap(np, 4); 2335 if (!qphy->tx2 || !qphy->rx2) { 2336 dev_warn(dev, 2337 "Underspecified device tree, falling back to legacy register regions\n"); 2338 2339 /* In the old version, pcs_misc is at index 3. */ 2340 qphy->pcs_misc = qphy->tx2; 2341 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE; 2342 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE; 2343 2344 } else { 2345 qphy->pcs_misc = of_iomap(np, 5); 2346 } 2347 2348 } else { 2349 qphy->pcs_misc = of_iomap(np, 3); 2350 } 2351 2352 if (!qphy->pcs_misc) 2353 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2354 2355 /* 2356 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 2357 * based phys, so they essentially have pipe clock. So, 2358 * we return error in case phy is USB3 or PIPE type. 2359 * Otherwise, we initialize pipe clock to NULL for 2360 * all phys that don't need this. 2361 */ 2362 snprintf(prop_name, sizeof(prop_name), "pipe%d", id); 2363 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name); 2364 if (IS_ERR(qphy->pipe_clk)) { 2365 if (cfg->type == PHY_TYPE_USB3) { 2366 ret = PTR_ERR(qphy->pipe_clk); 2367 if (ret != -EPROBE_DEFER) 2368 dev_err(dev, 2369 "failed to get lane%d pipe_clk, %d\n", 2370 id, ret); 2371 return ret; 2372 } 2373 qphy->pipe_clk = NULL; 2374 } 2375 2376 if (cfg->type == PHY_TYPE_DP) 2377 ops = &qcom_qmp_phy_combo_dp_ops; 2378 else 2379 ops = &qcom_qmp_phy_combo_usb_ops; 2380 2381 generic_phy = devm_phy_create(dev, np, ops); 2382 if (IS_ERR(generic_phy)) { 2383 ret = PTR_ERR(generic_phy); 2384 dev_err(dev, "failed to create qphy %d\n", ret); 2385 return ret; 2386 } 2387 2388 qphy->phy = generic_phy; 2389 qphy->index = id; 2390 qphy->qmp = qmp; 2391 qmp->phys[id] = qphy; 2392 phy_set_drvdata(generic_phy, qphy); 2393 2394 return 0; 2395 } 2396 2397 static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { 2398 { 2399 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 2400 .data = &sc7180_usb3dpphy_cfg, 2401 }, 2402 { 2403 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 2404 .data = &sm8250_usb3dpphy_cfg, 2405 }, 2406 { 2407 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 2408 .data = &sc8180x_usb3dpphy_cfg, 2409 }, 2410 { } 2411 }; 2412 MODULE_DEVICE_TABLE(of, qcom_qmp_combo_phy_of_match_table); 2413 2414 static const struct dev_pm_ops qcom_qmp_phy_combo_pm_ops = { 2415 SET_RUNTIME_PM_OPS(qcom_qmp_phy_combo_runtime_suspend, 2416 qcom_qmp_phy_combo_runtime_resume, NULL) 2417 }; 2418 2419 static int qcom_qmp_phy_combo_probe(struct platform_device *pdev) 2420 { 2421 struct qcom_qmp *qmp; 2422 struct device *dev = &pdev->dev; 2423 struct device_node *child; 2424 struct phy_provider *phy_provider; 2425 void __iomem *serdes; 2426 void __iomem *usb_serdes; 2427 void __iomem *dp_serdes = NULL; 2428 const struct qmp_phy_combo_cfg *combo_cfg = NULL; 2429 const struct qmp_phy_cfg *cfg = NULL; 2430 const struct qmp_phy_cfg *usb_cfg = NULL; 2431 const struct qmp_phy_cfg *dp_cfg = NULL; 2432 int num, id, expected_phys; 2433 int ret; 2434 2435 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2436 if (!qmp) 2437 return -ENOMEM; 2438 2439 qmp->dev = dev; 2440 dev_set_drvdata(dev, qmp); 2441 2442 /* Get the specific init parameters of QMP phy */ 2443 combo_cfg = of_device_get_match_data(dev); 2444 if (!combo_cfg) 2445 return -EINVAL; 2446 2447 usb_cfg = combo_cfg->usb_cfg; 2448 cfg = usb_cfg; /* Setup clks and regulators */ 2449 2450 /* per PHY serdes; usually located at base address */ 2451 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 2452 if (IS_ERR(serdes)) 2453 return PTR_ERR(serdes); 2454 2455 /* per PHY dp_com; if PHY has dp_com control block */ 2456 if (cfg->has_phy_dp_com_ctrl) { 2457 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2458 if (IS_ERR(qmp->dp_com)) 2459 return PTR_ERR(qmp->dp_com); 2460 } 2461 2462 /* Only two serdes for combo PHY */ 2463 dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2464 if (IS_ERR(dp_serdes)) 2465 return PTR_ERR(dp_serdes); 2466 2467 dp_cfg = combo_cfg->dp_cfg; 2468 expected_phys = 2; 2469 2470 mutex_init(&qmp->phy_mutex); 2471 2472 ret = qcom_qmp_phy_combo_clk_init(dev, cfg); 2473 if (ret) 2474 return ret; 2475 2476 ret = qcom_qmp_phy_combo_reset_init(dev, cfg); 2477 if (ret) 2478 return ret; 2479 2480 ret = qcom_qmp_phy_combo_vreg_init(dev, cfg); 2481 if (ret) { 2482 if (ret != -EPROBE_DEFER) 2483 dev_err(dev, "failed to get regulator supplies: %d\n", 2484 ret); 2485 return ret; 2486 } 2487 2488 num = of_get_available_child_count(dev->of_node); 2489 /* do we have a rogue child node ? */ 2490 if (num > expected_phys) 2491 return -EINVAL; 2492 2493 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2494 if (!qmp->phys) 2495 return -ENOMEM; 2496 2497 pm_runtime_set_active(dev); 2498 pm_runtime_enable(dev); 2499 /* 2500 * Prevent runtime pm from being ON by default. Users can enable 2501 * it using power/control in sysfs. 2502 */ 2503 pm_runtime_forbid(dev); 2504 2505 id = 0; 2506 for_each_available_child_of_node(dev->of_node, child) { 2507 if (of_node_name_eq(child, "dp-phy")) { 2508 cfg = dp_cfg; 2509 serdes = dp_serdes; 2510 2511 /* Create per-lane phy */ 2512 ret = qcom_qmp_phy_combo_create(dev, child, id, serdes, cfg); 2513 if (ret) { 2514 dev_err(dev, "failed to create lane%d phy, %d\n", 2515 id, ret); 2516 goto err_node_put; 2517 } 2518 2519 ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 2520 if (ret) { 2521 dev_err(qmp->dev, 2522 "failed to register DP clock source\n"); 2523 goto err_node_put; 2524 } 2525 } else if (of_node_name_eq(child, "usb3-phy")) { 2526 cfg = usb_cfg; 2527 serdes = usb_serdes; 2528 2529 /* Create per-lane phy */ 2530 ret = qcom_qmp_phy_combo_create(dev, child, id, serdes, cfg); 2531 if (ret) { 2532 dev_err(dev, "failed to create lane%d phy, %d\n", 2533 id, ret); 2534 goto err_node_put; 2535 } 2536 2537 /* 2538 * Register the pipe clock provided by phy. 2539 * See function description to see details of this pipe clock. 2540 */ 2541 ret = phy_pipe_clk_register(qmp, child); 2542 if (ret) { 2543 dev_err(qmp->dev, 2544 "failed to register pipe clock source\n"); 2545 goto err_node_put; 2546 } 2547 } 2548 2549 id++; 2550 } 2551 2552 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2553 if (!IS_ERR(phy_provider)) 2554 dev_info(dev, "Registered Qcom-QMP phy\n"); 2555 else 2556 pm_runtime_disable(dev); 2557 2558 return PTR_ERR_OR_ZERO(phy_provider); 2559 2560 err_node_put: 2561 pm_runtime_disable(dev); 2562 of_node_put(child); 2563 return ret; 2564 } 2565 2566 static struct platform_driver qcom_qmp_phy_combo_driver = { 2567 .probe = qcom_qmp_phy_combo_probe, 2568 .driver = { 2569 .name = "qcom-qmp-combo-phy", 2570 .pm = &qcom_qmp_phy_combo_pm_ops, 2571 .of_match_table = qcom_qmp_combo_phy_of_match_table, 2572 }, 2573 }; 2574 2575 module_platform_driver(qcom_qmp_phy_combo_driver); 2576 2577 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2578 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 2579 MODULE_LICENSE("GPL v2"); 2580