1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_graph.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/usb/typec.h> 23 #include <linux/usb/typec_dp.h> 24 #include <linux/usb/typec_mux.h> 25 26 #include <drm/bridge/aux-bridge.h> 27 28 #include <dt-bindings/phy/phy-qcom-qmp.h> 29 30 #include "phy-qcom-qmp-common.h" 31 32 #include "phy-qcom-qmp.h" 33 #include "phy-qcom-qmp-pcs-misc-v3.h" 34 #include "phy-qcom-qmp-pcs-usb-v4.h" 35 #include "phy-qcom-qmp-pcs-usb-v5.h" 36 #include "phy-qcom-qmp-pcs-usb-v6.h" 37 #include "phy-qcom-qmp-pcs-usb-v8.h" 38 39 #include "phy-qcom-qmp-dp-com-v3.h" 40 41 #include "phy-qcom-qmp-dp-phy.h" 42 #include "phy-qcom-qmp-dp-phy-v3.h" 43 #include "phy-qcom-qmp-dp-phy-v4.h" 44 #include "phy-qcom-qmp-dp-phy-v5.h" 45 #include "phy-qcom-qmp-dp-phy-v6.h" 46 47 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 48 /* DP PHY soft reset */ 49 #define SW_DPPHY_RESET BIT(0) 50 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 51 #define SW_DPPHY_RESET_MUX BIT(1) 52 /* USB3 PHY soft reset */ 53 #define SW_USB3PHY_RESET BIT(2) 54 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 55 #define SW_USB3PHY_RESET_MUX BIT(3) 56 57 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 58 #define USB3_MODE BIT(0) /* enables USB3 mode */ 59 #define DP_MODE BIT(1) /* enables DP mode */ 60 61 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 62 #define SW_PORTSELECT_VAL BIT(0) 63 #define SW_PORTSELECT_MUX BIT(1) 64 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 66 67 enum qmpphy_mode { 68 QMPPHY_MODE_USB3DP = 0, 69 QMPPHY_MODE_DP_ONLY, 70 QMPPHY_MODE_USB3_ONLY, 71 }; 72 73 /* set of registers with offsets different per-PHY */ 74 enum qphy_reg_layout { 75 /* PCS registers */ 76 QPHY_SW_RESET, 77 QPHY_START_CTRL, 78 QPHY_PCS_STATUS, 79 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 80 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 81 QPHY_PCS_POWER_DOWN_CONTROL, 82 83 QPHY_COM_RESETSM_CNTRL, 84 QPHY_COM_C_READY_STATUS, 85 QPHY_COM_CMN_STATUS, 86 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 87 88 QPHY_DP_PHY_STATUS, 89 QPHY_DP_PHY_VCO_DIV, 90 91 QPHY_TX_TX_POL_INV, 92 QPHY_TX_TX_DRV_LVL, 93 QPHY_TX_TX_EMP_POST1_LVL, 94 QPHY_TX_HIGHZ_DRVR_EN, 95 QPHY_TX_TRANSCEIVER_BIAS_EN, 96 97 /* Keep last to ensure regs_layout arrays are properly initialized */ 98 QPHY_LAYOUT_SIZE 99 }; 100 101 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 102 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 103 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 104 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 105 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 106 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 107 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 108 109 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 110 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 111 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 112 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 113 114 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 115 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 116 117 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 118 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 119 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 120 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 121 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 122 }; 123 124 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 125 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 126 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 127 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 128 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 129 130 /* In PCS_USB */ 131 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 132 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 133 134 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 135 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 136 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 137 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 138 139 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 140 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 141 142 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 143 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 144 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 145 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 146 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 147 }; 148 149 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 150 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 151 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 152 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 153 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 154 155 /* In PCS_USB */ 156 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 157 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 158 159 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 160 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 161 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 162 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 163 164 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 165 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 166 167 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 168 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 169 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 170 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 171 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 172 }; 173 174 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 175 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 176 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 177 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 178 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 179 180 /* In PCS_USB */ 181 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 182 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 183 184 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 185 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 186 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 187 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 188 189 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 190 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 191 192 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 193 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 194 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 195 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 196 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 197 }; 198 199 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 200 [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET, 201 [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL, 202 [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1, 203 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL, 204 205 /* In PCS_USB */ 206 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 207 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 208 209 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 210 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 211 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 212 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 213 214 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 215 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 216 217 [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV, 218 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL, 219 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, 220 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, 221 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, 222 }; 223 224 static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 225 [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET, 226 [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL, 227 [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1, 228 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL, 229 230 /* In PCS_USB */ 231 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 232 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 233 234 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 235 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 236 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 237 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 238 239 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 240 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 241 242 [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV, 243 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL, 244 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL, 245 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN, 246 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, 247 }; 248 249 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 286 }; 287 288 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 289 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 290 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 291 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 292 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 293 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 294 }; 295 296 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 318 }; 319 320 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 328 }; 329 330 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 331 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 332 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 334 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 335 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 336 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 337 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 338 }; 339 340 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 341 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 342 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 343 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 344 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 345 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 346 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 347 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 348 }; 349 350 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 351 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 352 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 357 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 358 }; 359 360 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 361 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 362 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 363 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 364 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 365 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 366 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 367 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 368 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 369 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 370 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 371 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 372 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 373 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 374 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 375 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 376 }; 377 378 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 379 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 380 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 381 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 382 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 383 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 384 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 385 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 386 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 387 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 388 }; 389 390 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 391 /* FLL settings */ 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 397 398 /* Lock Det settings */ 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 403 404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 415 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 416 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 417 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 419 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 423 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 435 }; 436 437 static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = { 438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), 439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), 440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), 447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), 448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), 450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), 451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), 459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), 460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), 466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), 467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), 469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 478 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 481 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), 482 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 483 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 484 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 485 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 486 }; 487 488 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 489 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 490 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 491 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 492 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 493 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 494 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 495 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 496 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 497 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 498 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 499 }; 500 501 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 502 /* FLL settings */ 503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 508 509 /* Lock Det settings */ 510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 514 515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 517 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 518 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 519 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 521 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 522 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 523 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 524 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 525 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 526 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 527 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 528 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 529 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 530 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 531 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 532 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 533 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 534 535 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 536 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 537 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 538 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 539 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 540 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 541 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 542 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 543 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 544 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 545 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 546 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 547 548 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 549 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 550 }; 551 552 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 558 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 559 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 560 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 561 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 562 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 563 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 564 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 565 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 566 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 567 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 568 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 569 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 570 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 571 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 572 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 573 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 574 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 575 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 576 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 577 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 578 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 579 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 580 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 588 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 589 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 593 }; 594 595 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 596 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 597 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 598 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 599 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 600 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 601 }; 602 603 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 633 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 634 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 639 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 640 }; 641 642 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 643 /* Lock Det settings */ 644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 647 648 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 649 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 650 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 653 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 654 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 655 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 656 }; 657 658 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 659 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 660 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 661 }; 662 663 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 664 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 665 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 666 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 667 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 668 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 669 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 670 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 671 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 672 }; 673 674 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 695 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 696 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 697 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 698 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 713 }; 714 715 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 727 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 728 }; 729 730 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 731 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 732 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 733 }; 734 735 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 736 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 737 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 738 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 739 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 740 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 741 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 742 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 743 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 744 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 745 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 746 }; 747 748 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 753 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 754 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 755 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 756 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 757 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 758 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 759 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 760 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 761 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 762 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 763 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 764 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 765 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 766 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 767 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 768 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 769 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 770 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 771 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 772 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 773 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 774 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 778 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 779 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 780 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 781 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 782 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 783 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 784 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 785 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 786 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 787 }; 788 789 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 790 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 791 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 792 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 793 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 796 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 797 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 798 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 799 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 800 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 801 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 802 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 803 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 804 }; 805 806 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 807 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 808 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 809 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 810 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 811 }; 812 813 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 848 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 849 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 850 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 855 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 856 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 857 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 858 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 859 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 862 }; 863 864 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 865 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 866 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 867 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 868 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 869 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 870 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 871 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 872 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 873 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 874 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 875 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 876 }; 877 878 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 879 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 880 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 881 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 882 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 883 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 884 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 885 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 886 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 887 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 888 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 889 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 890 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 891 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 892 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 893 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 894 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 895 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 896 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 897 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 898 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 899 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 900 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 901 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 902 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 903 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 904 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 905 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 906 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 907 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 908 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 909 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 910 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 911 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 912 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 913 914 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 915 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 916 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 917 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 918 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 919 920 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 921 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 922 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 923 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 924 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 925 }; 926 927 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 929 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 930 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 931 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 932 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 933 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 934 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 935 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 936 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 937 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 938 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 939 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 940 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 941 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 942 }; 943 944 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 945 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 946 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 947 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 948 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 949 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 950 }; 951 952 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 973 }; 974 975 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 983 }; 984 985 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 993 }; 994 995 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1003 }; 1004 1005 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1013 }; 1014 1015 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 1016 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 1030 }; 1031 1032 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1056 }; 1057 1058 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 1059 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 1070 }; 1071 1072 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 1073 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1085 }; 1086 1087 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1090 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1091 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1092 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1093 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1094 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1095 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1096 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1097 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1098 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1099 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1100 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1101 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1102 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1107 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1108 }; 1109 1110 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = { 1111 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1112 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1113 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1114 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1115 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1116 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1117 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1118 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1119 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1120 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1121 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1122 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1123 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1124 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1125 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1126 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1127 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1128 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1129 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1130 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1131 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1132 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1133 }; 1134 1135 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1136 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1137 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1138 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1139 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1140 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1141 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1142 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1143 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1144 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1145 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1146 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1147 }; 1148 1149 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = { 1150 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40), 1151 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00), 1152 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff), 1153 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f), 1154 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03), 1155 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1156 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1157 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1158 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1159 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1), 1160 }; 1161 1162 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1163 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1164 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1165 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1166 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1167 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1168 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1169 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1170 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1171 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1172 }; 1173 1174 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1175 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1176 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1184 }; 1185 1186 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1196 }; 1197 1198 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1208 }; 1209 1210 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = { 1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1225 }; 1226 1227 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = { 1228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1235 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1236 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1242 }; 1243 1244 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = { 1245 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1246 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1247 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1248 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1249 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1250 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1251 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1252 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1253 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1254 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1255 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1256 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1257 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1258 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1259 }; 1260 1261 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = { 1262 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1263 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1264 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1265 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1266 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1267 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1268 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1269 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1270 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1271 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1272 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1273 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1274 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1275 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1276 }; 1277 1278 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1326 }; 1327 1328 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1329 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1334 }; 1335 1336 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1337 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1346 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1347 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1355 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1356 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1357 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1358 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1359 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1363 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1364 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1365 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1366 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1367 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1371 }; 1372 1373 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1374 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1375 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1376 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1377 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1378 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1379 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1380 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1381 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1382 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1383 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1384 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1385 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1386 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1387 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1388 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1389 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1390 }; 1391 1392 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1393 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1394 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1395 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1396 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1397 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1398 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1399 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1400 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1401 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1402 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1403 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1404 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1405 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1406 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1407 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1408 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1409 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1410 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1411 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1412 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1413 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1414 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1415 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1416 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1417 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1418 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1419 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1420 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1421 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1422 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1423 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1424 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1425 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1443 }; 1444 1445 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1446 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1447 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1448 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1451 }; 1452 1453 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1454 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1455 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1456 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1457 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1458 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1459 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1460 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1461 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1462 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1463 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1464 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1465 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1466 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1467 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1468 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1469 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1470 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1471 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1472 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1473 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1474 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1475 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1476 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1477 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1478 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1479 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1480 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1481 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1482 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1483 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1484 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1485 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1486 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1487 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1488 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1489 }; 1490 1491 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1492 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1493 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1494 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1495 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89), 1496 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1497 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1498 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1499 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55), 1500 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a), 1501 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1502 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1503 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1504 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b), 1505 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), 1506 }; 1507 1508 static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = { 1509 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1510 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1511 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), 1512 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 1513 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 1514 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 1515 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), 1516 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), 1517 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), 1518 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), 1519 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 1520 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), 1521 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 1522 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 1523 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), 1524 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), 1525 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1526 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1527 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1528 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1529 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1530 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1531 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), 1532 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 1533 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 1534 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), 1535 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), 1536 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 1537 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), 1538 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), 1539 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), 1540 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 1541 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), 1542 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), 1543 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 1544 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), 1545 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 1546 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 1547 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), 1548 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), 1549 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), 1550 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), 1551 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), 1552 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 1553 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1554 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 1555 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 1556 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), 1557 }; 1558 1559 static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = { 1560 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), 1561 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), 1562 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1563 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1564 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), 1565 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), 1566 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31), 1567 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), 1568 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), 1569 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1), 1570 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2), 1571 }; 1572 1573 static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = { 1574 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a), 1575 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06), 1576 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1577 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1578 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1579 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1580 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), 1581 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), 1582 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), 1583 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), 1584 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), 1585 QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 1586 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), 1587 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), 1588 QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13), 1589 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1590 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1591 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1592 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1593 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1594 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1595 1596 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), 1597 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), 1598 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1599 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f), 1600 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), 1601 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), 1602 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), 1603 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), 1604 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), 1605 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), 1606 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), 1607 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), 1608 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), 1609 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), 1610 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1611 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), 1612 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), 1613 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), 1614 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), 1615 }; 1616 1617 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = { 1618 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1619 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), 1620 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), 1621 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), 1622 QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), 1623 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), 1624 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1625 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1626 QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), 1627 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1628 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1629 QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), 1630 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), 1631 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), 1632 }; 1633 1634 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = { 1635 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1636 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 1637 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), 1638 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00), 1639 }; 1640 1641 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1642 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1643 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1644 }; 1645 1646 /* list of regulators */ 1647 static struct regulator_bulk_data qmp_phy_vreg_l[] = { 1648 { .supply = "vdda-phy", .init_load_uA = 21800, }, 1649 { .supply = "vdda-pll", .init_load_uA = 36000, }, 1650 }; 1651 1652 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1653 { 0x00, 0x0c, 0x15, 0x1a }, 1654 { 0x02, 0x0e, 0x16, 0xff }, 1655 { 0x02, 0x11, 0xff, 0xff }, 1656 { 0x04, 0xff, 0xff, 0xff } 1657 }; 1658 1659 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1660 { 0x02, 0x12, 0x16, 0x1a }, 1661 { 0x09, 0x19, 0x1f, 0xff }, 1662 { 0x10, 0x1f, 0xff, 0xff }, 1663 { 0x1f, 0xff, 0xff, 0xff } 1664 }; 1665 1666 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1667 { 0x00, 0x0c, 0x14, 0x19 }, 1668 { 0x00, 0x0b, 0x12, 0xff }, 1669 { 0x00, 0x0b, 0xff, 0xff }, 1670 { 0x04, 0xff, 0xff, 0xff } 1671 }; 1672 1673 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1674 { 0x08, 0x0f, 0x16, 0x1f }, 1675 { 0x11, 0x1e, 0x1f, 0xff }, 1676 { 0x19, 0x1f, 0xff, 0xff }, 1677 { 0x1f, 0xff, 0xff, 0xff } 1678 }; 1679 1680 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1681 { 0x00, 0x0c, 0x15, 0x1b }, 1682 { 0x02, 0x0e, 0x16, 0xff }, 1683 { 0x02, 0x11, 0xff, 0xff }, 1684 { 0x04, 0xff, 0xff, 0xff } 1685 }; 1686 1687 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1688 { 0x00, 0x0d, 0x14, 0x1a }, 1689 { 0x00, 0x0e, 0x15, 0xff }, 1690 { 0x00, 0x0d, 0xff, 0xff }, 1691 { 0x03, 0xff, 0xff, 0xff } 1692 }; 1693 1694 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1695 { 0x08, 0x0f, 0x16, 0x1f }, 1696 { 0x11, 0x1e, 0x1f, 0xff }, 1697 { 0x16, 0x1f, 0xff, 0xff }, 1698 { 0x1f, 0xff, 0xff, 0xff } 1699 }; 1700 1701 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1702 { 0x20, 0x2c, 0x35, 0x3b }, 1703 { 0x22, 0x2e, 0x36, 0xff }, 1704 { 0x22, 0x31, 0xff, 0xff }, 1705 { 0x24, 0xff, 0xff, 0xff } 1706 }; 1707 1708 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1709 { 0x22, 0x32, 0x36, 0x3a }, 1710 { 0x29, 0x39, 0x3f, 0xff }, 1711 { 0x30, 0x3f, 0xff, 0xff }, 1712 { 0x3f, 0xff, 0xff, 0xff } 1713 }; 1714 1715 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1716 { 0x20, 0x2d, 0x34, 0x3a }, 1717 { 0x20, 0x2e, 0x35, 0xff }, 1718 { 0x20, 0x2e, 0xff, 0xff }, 1719 { 0x24, 0xff, 0xff, 0xff } 1720 }; 1721 1722 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1723 { 0x28, 0x2f, 0x36, 0x3f }, 1724 { 0x31, 0x3e, 0x3f, 0xff }, 1725 { 0x36, 0x3f, 0xff, 0xff }, 1726 { 0x3f, 0xff, 0xff, 0xff } 1727 }; 1728 1729 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = { 1730 { 0x27, 0x2f, 0x36, 0x3f }, 1731 { 0x31, 0x3e, 0x3f, 0xff }, 1732 { 0x36, 0x3f, 0xff, 0xff }, 1733 { 0x3f, 0xff, 0xff, 0xff } 1734 }; 1735 1736 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1737 { 0x20, 0x2d, 0x34, 0x3a }, 1738 { 0x20, 0x2e, 0x35, 0xff }, 1739 { 0x20, 0x2e, 0xff, 0xff }, 1740 { 0x22, 0xff, 0xff, 0xff } 1741 }; 1742 1743 struct qmp_combo_lane_mapping { 1744 unsigned int lanes_count; 1745 enum typec_orientation orientation; 1746 u32 lanes[4]; 1747 }; 1748 1749 static const struct qmp_combo_lane_mapping usb3_data_lanes[] = { 1750 { 2, TYPEC_ORIENTATION_NORMAL, { 1, 0 }}, 1751 { 2, TYPEC_ORIENTATION_REVERSE, { 2, 3 }}, 1752 }; 1753 1754 static const struct qmp_combo_lane_mapping dp_data_lanes[] = { 1755 { 1, TYPEC_ORIENTATION_NORMAL, { 3 }}, 1756 { 1, TYPEC_ORIENTATION_REVERSE, { 0 }}, 1757 { 2, TYPEC_ORIENTATION_NORMAL, { 3, 2 }}, 1758 { 2, TYPEC_ORIENTATION_REVERSE, { 0, 1 }}, 1759 { 4, TYPEC_ORIENTATION_NORMAL, { 3, 2, 1, 0 }}, 1760 { 4, TYPEC_ORIENTATION_REVERSE, { 0, 1, 2, 3 }}, 1761 }; 1762 1763 struct qmp_combo; 1764 1765 struct qmp_combo_offsets { 1766 u16 com; 1767 u16 txa; 1768 u16 rxa; 1769 u16 txb; 1770 u16 rxb; 1771 u16 usb3_serdes; 1772 u16 usb3_pcs_misc; 1773 u16 usb3_pcs; 1774 u16 usb3_pcs_usb; 1775 u16 dp_serdes; 1776 u16 dp_txa; 1777 u16 dp_txb; 1778 u16 dp_dp_phy; 1779 }; 1780 1781 struct qmp_phy_cfg { 1782 const struct qmp_combo_offsets *offsets; 1783 1784 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1785 const struct qmp_phy_init_tbl *serdes_tbl; 1786 int serdes_tbl_num; 1787 const struct qmp_phy_init_tbl *tx_tbl; 1788 int tx_tbl_num; 1789 const struct qmp_phy_init_tbl *rx_tbl; 1790 int rx_tbl_num; 1791 const struct qmp_phy_init_tbl *pcs_tbl; 1792 int pcs_tbl_num; 1793 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1794 int pcs_usb_tbl_num; 1795 1796 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1797 int dp_serdes_tbl_num; 1798 const struct qmp_phy_init_tbl *dp_tx_tbl; 1799 int dp_tx_tbl_num; 1800 1801 /* Init sequence for DP PHY block link rates */ 1802 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1803 int serdes_tbl_rbr_num; 1804 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1805 int serdes_tbl_hbr_num; 1806 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1807 int serdes_tbl_hbr2_num; 1808 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1809 int serdes_tbl_hbr3_num; 1810 1811 /* DP PHY swing and pre_emphasis tables */ 1812 const u8 (*swing_hbr_rbr)[4][4]; 1813 const u8 (*swing_hbr3_hbr2)[4][4]; 1814 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1815 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1816 1817 /* DP PHY callbacks */ 1818 int (*configure_dp_phy)(struct qmp_combo *qmp); 1819 void (*configure_dp_tx)(struct qmp_combo *qmp); 1820 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1821 void (*dp_aux_init)(struct qmp_combo *qmp); 1822 1823 /* resets to be requested */ 1824 const char * const *reset_list; 1825 int num_resets; 1826 /* regulators to be requested */ 1827 const struct regulator_bulk_data *vreg_list; 1828 int num_vregs; 1829 1830 /* array of registers with different offsets */ 1831 const unsigned int *regs; 1832 1833 /* true, if PHY needs delay after POWER_DOWN */ 1834 bool has_pwrdn_delay; 1835 1836 /* Offset from PCS to PCS_USB region */ 1837 unsigned int pcs_usb_offset; 1838 1839 }; 1840 1841 struct qmp_combo { 1842 struct device *dev; 1843 1844 const struct qmp_phy_cfg *cfg; 1845 1846 void __iomem *com; 1847 1848 void __iomem *serdes; 1849 void __iomem *tx; 1850 void __iomem *rx; 1851 void __iomem *pcs; 1852 void __iomem *tx2; 1853 void __iomem *rx2; 1854 void __iomem *pcs_misc; 1855 void __iomem *pcs_usb; 1856 1857 void __iomem *dp_serdes; 1858 void __iomem *dp_tx; 1859 void __iomem *dp_tx2; 1860 void __iomem *dp_dp_phy; 1861 1862 struct clk *pipe_clk; 1863 struct clk_bulk_data *clks; 1864 int num_clks; 1865 struct reset_control_bulk_data *resets; 1866 struct regulator_bulk_data *vregs; 1867 1868 struct mutex phy_mutex; 1869 int init_count; 1870 enum qmpphy_mode qmpphy_mode; 1871 1872 struct phy *usb_phy; 1873 enum phy_mode phy_mode; 1874 unsigned int usb_init_count; 1875 1876 struct phy *dp_phy; 1877 unsigned int dp_aux_cfg; 1878 struct phy_configure_opts_dp dp_opts; 1879 unsigned int dp_init_count; 1880 bool dp_powered_on; 1881 1882 struct clk_fixed_rate pipe_clk_fixed; 1883 struct clk_hw dp_link_hw; 1884 struct clk_hw dp_pixel_hw; 1885 1886 struct typec_switch_dev *sw; 1887 enum typec_orientation orientation; 1888 1889 struct typec_mux_dev *mux; 1890 }; 1891 1892 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1893 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1894 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1895 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1896 1897 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1898 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1899 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1900 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1901 1902 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1903 { 1904 u32 reg; 1905 1906 reg = readl(base + offset); 1907 reg |= val; 1908 writel(reg, base + offset); 1909 1910 /* ensure that above write is through */ 1911 readl(base + offset); 1912 } 1913 1914 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1915 { 1916 u32 reg; 1917 1918 reg = readl(base + offset); 1919 reg &= ~val; 1920 writel(reg, base + offset); 1921 1922 /* ensure that above write is through */ 1923 readl(base + offset); 1924 } 1925 1926 /* list of clocks required by phy */ 1927 static const char * const qmp_combo_phy_clk_l[] = { 1928 "aux", "cfg_ahb", "ref", "com_aux", 1929 }; 1930 1931 /* list of resets */ 1932 static const char * const msm8996_usb3phy_reset_l[] = { 1933 "phy", "common", 1934 }; 1935 1936 static const char * const sc7180_usb3phy_reset_l[] = { 1937 "phy", 1938 }; 1939 1940 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1941 .com = 0x0000, 1942 .txa = 0x1200, 1943 .rxa = 0x1400, 1944 .txb = 0x1600, 1945 .rxb = 0x1800, 1946 .usb3_serdes = 0x1000, 1947 .usb3_pcs_misc = 0x1a00, 1948 .usb3_pcs = 0x1c00, 1949 .usb3_pcs_usb = 0x1f00, 1950 .dp_serdes = 0x2000, 1951 .dp_txa = 0x2200, 1952 .dp_txb = 0x2600, 1953 .dp_dp_phy = 0x2a00, 1954 }; 1955 1956 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1957 .com = 0x0000, 1958 .txa = 0x0400, 1959 .rxa = 0x0600, 1960 .txb = 0x0a00, 1961 .rxb = 0x0c00, 1962 .usb3_serdes = 0x1000, 1963 .usb3_pcs_misc = 0x1200, 1964 .usb3_pcs = 0x1400, 1965 .usb3_pcs_usb = 0x1700, 1966 .dp_serdes = 0x2000, 1967 .dp_dp_phy = 0x2200, 1968 }; 1969 1970 static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { 1971 .com = 0x0000, 1972 .txa = 0x1400, 1973 .rxa = 0x1600, 1974 .txb = 0x1800, 1975 .rxb = 0x1a00, 1976 .usb3_serdes = 0x1000, 1977 .usb3_pcs_misc = 0x1c00, 1978 .usb3_pcs = 0x1e00, 1979 .usb3_pcs_usb = 0x2100, 1980 .dp_serdes = 0x3000, 1981 .dp_txa = 0x3400, 1982 .dp_txb = 0x3800, 1983 .dp_dp_phy = 0x3c00, 1984 }; 1985 1986 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { 1987 .offsets = &qmp_combo_offsets_v3, 1988 1989 .serdes_tbl = sar2130p_usb3_serdes_tbl, 1990 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 1991 .tx_tbl = sm8550_usb3_tx_tbl, 1992 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1993 .rx_tbl = sm8550_usb3_rx_tbl, 1994 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1995 .pcs_tbl = sm8550_usb3_pcs_tbl, 1996 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1997 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1998 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1999 2000 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2001 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2002 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2003 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2004 2005 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2006 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2007 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2008 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2009 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2010 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2011 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2012 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2013 2014 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2015 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2016 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2017 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2018 2019 .dp_aux_init = qmp_v4_dp_aux_init, 2020 .configure_dp_tx = qmp_v4_configure_dp_tx, 2021 .configure_dp_phy = qmp_v4_configure_dp_phy, 2022 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2023 2024 .regs = qmp_v6_usb3phy_regs_layout, 2025 .reset_list = msm8996_usb3phy_reset_l, 2026 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2027 .vreg_list = qmp_phy_vreg_l, 2028 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2029 }; 2030 2031 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 2032 .offsets = &qmp_combo_offsets_v3, 2033 2034 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2035 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2036 .tx_tbl = qmp_v3_usb3_tx_tbl, 2037 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2038 .rx_tbl = qmp_v3_usb3_rx_tbl, 2039 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2040 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2041 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2042 2043 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2044 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2045 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2046 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2047 2048 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2049 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2050 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2051 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2052 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2053 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2054 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2055 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2056 2057 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2058 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2059 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2060 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2061 2062 .dp_aux_init = qmp_v3_dp_aux_init, 2063 .configure_dp_tx = qmp_v3_configure_dp_tx, 2064 .configure_dp_phy = qmp_v3_configure_dp_phy, 2065 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2066 2067 .reset_list = sc7180_usb3phy_reset_l, 2068 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 2069 .vreg_list = qmp_phy_vreg_l, 2070 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2071 .regs = qmp_v3_usb3phy_regs_layout, 2072 2073 .has_pwrdn_delay = true, 2074 }; 2075 2076 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 2077 .offsets = &qmp_combo_offsets_v3, 2078 2079 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2080 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2081 .tx_tbl = qmp_v3_usb3_tx_tbl, 2082 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2083 .rx_tbl = qmp_v3_usb3_rx_tbl, 2084 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2085 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2086 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2087 2088 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2089 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2090 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2091 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2092 2093 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2094 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2095 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2096 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2097 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2098 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2099 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2100 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2101 2102 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2103 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2104 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2105 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2106 2107 .dp_aux_init = qmp_v3_dp_aux_init, 2108 .configure_dp_tx = qmp_v3_configure_dp_tx, 2109 .configure_dp_phy = qmp_v3_configure_dp_phy, 2110 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2111 2112 .reset_list = msm8996_usb3phy_reset_l, 2113 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2114 .vreg_list = qmp_phy_vreg_l, 2115 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2116 .regs = qmp_v3_usb3phy_regs_layout, 2117 2118 .has_pwrdn_delay = true, 2119 }; 2120 2121 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 2122 .offsets = &qmp_combo_offsets_v3, 2123 2124 .serdes_tbl = sm8150_usb3_serdes_tbl, 2125 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2126 .tx_tbl = sm8150_usb3_tx_tbl, 2127 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 2128 .rx_tbl = sm8150_usb3_rx_tbl, 2129 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 2130 .pcs_tbl = sm8150_usb3_pcs_tbl, 2131 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 2132 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 2133 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 2134 2135 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2136 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2137 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2138 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2139 2140 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2141 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2142 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2143 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2144 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2145 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2146 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2147 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2148 2149 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2150 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2151 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2152 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2153 2154 .dp_aux_init = qmp_v4_dp_aux_init, 2155 .configure_dp_tx = qmp_v4_configure_dp_tx, 2156 .configure_dp_phy = qmp_v4_configure_dp_phy, 2157 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2158 2159 .reset_list = msm8996_usb3phy_reset_l, 2160 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2161 .vreg_list = qmp_phy_vreg_l, 2162 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2163 .regs = qmp_v45_usb3phy_regs_layout, 2164 .pcs_usb_offset = 0x300, 2165 2166 .has_pwrdn_delay = true, 2167 }; 2168 2169 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 2170 .offsets = &qmp_combo_offsets_v5, 2171 2172 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 2173 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 2174 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 2175 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 2176 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 2177 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 2178 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 2179 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 2180 2181 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 2182 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 2183 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 2184 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 2185 2186 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2187 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2188 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2189 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2190 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2191 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2192 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2193 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2194 2195 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2196 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 2197 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2198 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2199 2200 .dp_aux_init = qmp_v4_dp_aux_init, 2201 .configure_dp_tx = qmp_v4_configure_dp_tx, 2202 .configure_dp_phy = qmp_v4_configure_dp_phy, 2203 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2204 2205 .reset_list = msm8996_usb3phy_reset_l, 2206 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2207 .vreg_list = qmp_phy_vreg_l, 2208 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2209 .regs = qmp_v5_5nm_usb3phy_regs_layout, 2210 }; 2211 2212 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 2213 .offsets = &qmp_combo_offsets_v5, 2214 2215 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 2216 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 2217 .tx_tbl = x1e80100_usb43dp_tx_tbl, 2218 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 2219 .rx_tbl = x1e80100_usb43dp_rx_tbl, 2220 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 2221 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 2222 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 2223 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 2224 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 2225 2226 .dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl, 2227 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl), 2228 .dp_tx_tbl = qmp_v6_n4_dp_tx_tbl, 2229 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl), 2230 2231 .serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr, 2232 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr), 2233 .serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr, 2234 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr), 2235 .serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2, 2236 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2), 2237 .serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3, 2238 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3), 2239 2240 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2241 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2242 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2243 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2244 2245 .dp_aux_init = qmp_v4_dp_aux_init, 2246 .configure_dp_tx = qmp_v4_configure_dp_tx, 2247 .configure_dp_phy = qmp_v4_configure_dp_phy, 2248 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2249 2250 .reset_list = msm8996_usb3phy_reset_l, 2251 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2252 .vreg_list = qmp_phy_vreg_l, 2253 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2254 .regs = qmp_v6_n4_usb3phy_regs_layout, 2255 }; 2256 2257 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 2258 .offsets = &qmp_combo_offsets_v3, 2259 2260 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2261 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2262 .tx_tbl = qmp_v3_usb3_tx_tbl, 2263 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2264 .rx_tbl = sm6350_usb3_rx_tbl, 2265 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 2266 .pcs_tbl = sm6350_usb3_pcs_tbl, 2267 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 2268 2269 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2270 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2271 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2272 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2273 2274 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2275 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2276 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2277 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2278 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2279 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2280 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2281 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2282 2283 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2284 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2285 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2286 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2287 2288 .dp_aux_init = qmp_v3_dp_aux_init, 2289 .configure_dp_tx = qmp_v3_configure_dp_tx, 2290 .configure_dp_phy = qmp_v3_configure_dp_phy, 2291 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2292 2293 .reset_list = msm8996_usb3phy_reset_l, 2294 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2295 .vreg_list = qmp_phy_vreg_l, 2296 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2297 .regs = qmp_v3_usb3phy_regs_layout, 2298 }; 2299 2300 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 2301 .offsets = &qmp_combo_offsets_v3, 2302 2303 .serdes_tbl = sm8150_usb3_serdes_tbl, 2304 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2305 .tx_tbl = sm8250_usb3_tx_tbl, 2306 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 2307 .rx_tbl = sm8250_usb3_rx_tbl, 2308 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 2309 .pcs_tbl = sm8250_usb3_pcs_tbl, 2310 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 2311 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 2312 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 2313 2314 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2315 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2316 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2317 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2318 2319 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2320 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2321 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2322 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2323 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2324 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2325 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2326 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2327 2328 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2329 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2330 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2331 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2332 2333 .dp_aux_init = qmp_v4_dp_aux_init, 2334 .configure_dp_tx = qmp_v4_configure_dp_tx, 2335 .configure_dp_phy = qmp_v4_configure_dp_phy, 2336 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2337 2338 .reset_list = msm8996_usb3phy_reset_l, 2339 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2340 .vreg_list = qmp_phy_vreg_l, 2341 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2342 .regs = qmp_v45_usb3phy_regs_layout, 2343 .pcs_usb_offset = 0x300, 2344 2345 .has_pwrdn_delay = true, 2346 }; 2347 2348 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 2349 .offsets = &qmp_combo_offsets_v3, 2350 2351 .serdes_tbl = sm8150_usb3_serdes_tbl, 2352 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2353 .tx_tbl = sm8350_usb3_tx_tbl, 2354 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 2355 .rx_tbl = sm8350_usb3_rx_tbl, 2356 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 2357 .pcs_tbl = sm8350_usb3_pcs_tbl, 2358 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 2359 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 2360 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 2361 2362 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2363 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2364 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 2365 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 2366 2367 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2368 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2369 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2370 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2371 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2372 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2373 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2374 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2375 2376 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 2377 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 2378 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2379 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 2380 2381 .dp_aux_init = qmp_v4_dp_aux_init, 2382 .configure_dp_tx = qmp_v4_configure_dp_tx, 2383 .configure_dp_phy = qmp_v4_configure_dp_phy, 2384 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2385 2386 .reset_list = msm8996_usb3phy_reset_l, 2387 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2388 .vreg_list = qmp_phy_vreg_l, 2389 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2390 .regs = qmp_v45_usb3phy_regs_layout, 2391 2392 .has_pwrdn_delay = true, 2393 }; 2394 2395 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 2396 .offsets = &qmp_combo_offsets_v3, 2397 2398 .serdes_tbl = sm8550_usb3_serdes_tbl, 2399 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2400 .tx_tbl = sm8550_usb3_tx_tbl, 2401 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2402 .rx_tbl = sm8550_usb3_rx_tbl, 2403 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2404 .pcs_tbl = sm8550_usb3_pcs_tbl, 2405 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2406 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2407 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2408 2409 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2410 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2411 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2412 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2413 2414 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2415 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2416 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2417 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2418 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2419 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2420 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2421 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2422 2423 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2424 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2425 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2426 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2427 2428 .dp_aux_init = qmp_v4_dp_aux_init, 2429 .configure_dp_tx = qmp_v4_configure_dp_tx, 2430 .configure_dp_phy = qmp_v4_configure_dp_phy, 2431 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2432 2433 .regs = qmp_v6_usb3phy_regs_layout, 2434 .reset_list = msm8996_usb3phy_reset_l, 2435 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2436 .vreg_list = qmp_phy_vreg_l, 2437 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2438 }; 2439 2440 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = { 2441 .offsets = &qmp_combo_offsets_v3, 2442 2443 .serdes_tbl = sm8550_usb3_serdes_tbl, 2444 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2445 .tx_tbl = sm8550_usb3_tx_tbl, 2446 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2447 .rx_tbl = sm8550_usb3_rx_tbl, 2448 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2449 .pcs_tbl = sm8550_usb3_pcs_tbl, 2450 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2451 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2452 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2453 2454 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2455 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2456 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2457 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2458 2459 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2460 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2461 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2462 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2463 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2464 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2465 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2466 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2467 2468 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2469 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2470 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2471 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2472 2473 .dp_aux_init = qmp_v4_dp_aux_init, 2474 .configure_dp_tx = qmp_v4_configure_dp_tx, 2475 .configure_dp_phy = qmp_v4_configure_dp_phy, 2476 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2477 2478 .regs = qmp_v6_usb3phy_regs_layout, 2479 .reset_list = msm8996_usb3phy_reset_l, 2480 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2481 .vreg_list = qmp_phy_vreg_l, 2482 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2483 }; 2484 2485 static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { 2486 .offsets = &qmp_combo_offsets_v8, 2487 2488 .serdes_tbl = sm8750_usb3_serdes_tbl, 2489 .serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl), 2490 .tx_tbl = sm8750_usb3_tx_tbl, 2491 .tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl), 2492 .rx_tbl = sm8750_usb3_rx_tbl, 2493 .rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl), 2494 .pcs_tbl = sm8750_usb3_pcs_tbl, 2495 .pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl), 2496 .pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl, 2497 .pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), 2498 2499 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2500 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2501 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2502 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2503 2504 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2505 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2506 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2507 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2508 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2509 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2510 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2511 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2512 2513 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2514 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2515 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2516 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2517 2518 .dp_aux_init = qmp_v4_dp_aux_init, 2519 .configure_dp_tx = qmp_v4_configure_dp_tx, 2520 .configure_dp_phy = qmp_v4_configure_dp_phy, 2521 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2522 2523 .regs = qmp_v8_usb3phy_regs_layout, 2524 .reset_list = msm8996_usb3phy_reset_l, 2525 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2526 .vreg_list = qmp_phy_vreg_l, 2527 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2528 }; 2529 2530 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 2531 { 2532 const struct qmp_phy_cfg *cfg = qmp->cfg; 2533 void __iomem *serdes = qmp->dp_serdes; 2534 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2535 2536 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 2537 cfg->dp_serdes_tbl_num); 2538 2539 switch (dp_opts->link_rate) { 2540 case 1620: 2541 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 2542 cfg->serdes_tbl_rbr_num); 2543 break; 2544 case 2700: 2545 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 2546 cfg->serdes_tbl_hbr_num); 2547 break; 2548 case 5400: 2549 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 2550 cfg->serdes_tbl_hbr2_num); 2551 break; 2552 case 8100: 2553 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, 2554 cfg->serdes_tbl_hbr3_num); 2555 break; 2556 default: 2557 /* Other link rates aren't supported */ 2558 return -EINVAL; 2559 } 2560 2561 return 0; 2562 } 2563 2564 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 2565 { 2566 const struct qmp_phy_cfg *cfg = qmp->cfg; 2567 2568 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2569 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2570 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2571 2572 /* Turn on BIAS current for PHY/PLL */ 2573 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 2574 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 2575 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2576 2577 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2578 2579 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2580 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 2581 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 2582 DP_PHY_PD_CTL_DP_CLAMP_EN, 2583 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2584 2585 writel(QSERDES_V3_COM_BIAS_EN | 2586 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 2587 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 2588 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 2589 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2590 2591 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2592 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2593 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2594 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2595 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2596 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2597 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2598 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2599 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2600 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2601 qmp->dp_aux_cfg = 0; 2602 2603 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2604 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2605 PHY_AUX_REQ_ERR_MASK, 2606 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 2607 } 2608 2609 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 2610 { 2611 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2612 const struct qmp_phy_cfg *cfg = qmp->cfg; 2613 unsigned int v_level = 0, p_level = 0; 2614 u8 voltage_swing_cfg, pre_emphasis_cfg; 2615 int i; 2616 2617 for (i = 0; i < dp_opts->lanes; i++) { 2618 v_level = max(v_level, dp_opts->voltage[i]); 2619 p_level = max(p_level, dp_opts->pre[i]); 2620 } 2621 2622 if (dp_opts->link_rate <= 2700) { 2623 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 2624 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 2625 } else { 2626 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 2627 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 2628 } 2629 2630 /* TODO: Move check to config check */ 2631 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2632 return -EINVAL; 2633 2634 /* Enable MUX to use Cursor values from these registers */ 2635 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2636 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2637 2638 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2639 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2640 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2641 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2642 2643 return 0; 2644 } 2645 2646 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2647 { 2648 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2649 u32 bias_en, drvr_en; 2650 2651 if (qmp_combo_configure_dp_swing(qmp) < 0) 2652 return; 2653 2654 if (dp_opts->lanes == 1) { 2655 bias_en = 0x3e; 2656 drvr_en = 0x13; 2657 } else { 2658 bias_en = 0x3f; 2659 drvr_en = 0x10; 2660 } 2661 2662 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2663 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2664 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2665 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2666 } 2667 2668 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2669 { 2670 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2671 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2672 u32 val; 2673 2674 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2675 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2676 2677 if (dp_opts->lanes == 4 || reverse) 2678 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2679 if (dp_opts->lanes == 4 || !reverse) 2680 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2681 2682 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2683 2684 if (reverse) 2685 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2686 else 2687 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2688 2689 return reverse; 2690 } 2691 2692 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2693 { 2694 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2695 u32 phy_vco_div; 2696 unsigned long pixel_freq; 2697 const struct qmp_phy_cfg *cfg = qmp->cfg; 2698 2699 switch (dp_opts->link_rate) { 2700 case 1620: 2701 phy_vco_div = 0x1; 2702 pixel_freq = 1620000000UL / 2; 2703 break; 2704 case 2700: 2705 phy_vco_div = 0x1; 2706 pixel_freq = 2700000000UL / 2; 2707 break; 2708 case 5400: 2709 phy_vco_div = 0x2; 2710 pixel_freq = 5400000000UL / 4; 2711 break; 2712 case 8100: 2713 phy_vco_div = 0x0; 2714 pixel_freq = 8100000000UL / 6; 2715 break; 2716 default: 2717 /* Other link rates aren't supported */ 2718 return -EINVAL; 2719 } 2720 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 2721 2722 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2723 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2724 2725 return 0; 2726 } 2727 2728 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2729 { 2730 const struct qmp_phy_cfg *cfg = qmp->cfg; 2731 u32 status; 2732 int ret; 2733 2734 qmp_combo_configure_dp_mode(qmp); 2735 2736 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2737 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2738 2739 ret = qmp_combo_configure_dp_clocks(qmp); 2740 if (ret) 2741 return ret; 2742 2743 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2744 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2745 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2746 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2747 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2748 2749 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2750 2751 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2752 status, 2753 ((status & BIT(0)) > 0), 2754 500, 2755 10000)) 2756 return -ETIMEDOUT; 2757 2758 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2759 2760 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2761 status, 2762 ((status & BIT(1)) > 0), 2763 500, 2764 10000)) 2765 return -ETIMEDOUT; 2766 2767 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2768 udelay(2000); 2769 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2770 2771 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2772 status, 2773 ((status & BIT(1)) > 0), 2774 500, 2775 10000); 2776 } 2777 2778 /* 2779 * We need to calibrate the aux setting here as many times 2780 * as the caller tries 2781 */ 2782 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2783 { 2784 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2785 u8 val; 2786 2787 qmp->dp_aux_cfg++; 2788 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2789 val = cfg1_settings[qmp->dp_aux_cfg]; 2790 2791 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2792 2793 return 0; 2794 } 2795 2796 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2797 { 2798 const struct qmp_phy_cfg *cfg = qmp->cfg; 2799 2800 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2801 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2802 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2803 2804 /* Turn on BIAS current for PHY/PLL */ 2805 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2806 2807 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2808 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2809 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2810 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2811 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2812 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2813 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2814 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2815 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2816 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2817 qmp->dp_aux_cfg = 0; 2818 2819 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2820 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2821 PHY_AUX_REQ_ERR_MASK, 2822 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2823 } 2824 2825 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2826 { 2827 const struct qmp_phy_cfg *cfg = qmp->cfg; 2828 2829 /* Program default values before writing proper values */ 2830 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2831 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2832 2833 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2834 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2835 2836 qmp_combo_configure_dp_swing(qmp); 2837 } 2838 2839 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2840 { 2841 const struct qmp_phy_cfg *cfg = qmp->cfg; 2842 u32 status; 2843 int ret; 2844 2845 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 2846 2847 qmp_combo_configure_dp_mode(qmp); 2848 2849 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2850 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2851 2852 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2853 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2854 2855 ret = qmp_combo_configure_dp_clocks(qmp); 2856 if (ret) 2857 return ret; 2858 2859 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2860 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2861 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2862 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2863 2864 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2865 2866 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2867 status, 2868 ((status & BIT(0)) > 0), 2869 500, 2870 10000)) 2871 return -ETIMEDOUT; 2872 2873 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2874 status, 2875 ((status & BIT(0)) > 0), 2876 500, 2877 10000)) 2878 return -ETIMEDOUT; 2879 2880 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2881 status, 2882 ((status & BIT(1)) > 0), 2883 500, 2884 10000)) 2885 return -ETIMEDOUT; 2886 2887 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2888 2889 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2890 status, 2891 ((status & BIT(0)) > 0), 2892 500, 2893 10000)) 2894 return -ETIMEDOUT; 2895 2896 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2897 status, 2898 ((status & BIT(1)) > 0), 2899 500, 2900 10000)) 2901 return -ETIMEDOUT; 2902 2903 return 0; 2904 } 2905 2906 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2907 { 2908 const struct qmp_phy_cfg *cfg = qmp->cfg; 2909 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2910 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2911 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2912 u32 status; 2913 int ret; 2914 2915 ret = qmp_v456_configure_dp_phy(qmp); 2916 if (ret < 0) 2917 return ret; 2918 2919 /* 2920 * At least for 7nm DP PHY this has to be done after enabling link 2921 * clock. 2922 */ 2923 2924 if (dp_opts->lanes == 1) { 2925 bias0_en = reverse ? 0x3e : 0x15; 2926 bias1_en = reverse ? 0x15 : 0x3e; 2927 drvr0_en = reverse ? 0x13 : 0x10; 2928 drvr1_en = reverse ? 0x10 : 0x13; 2929 } else if (dp_opts->lanes == 2) { 2930 bias0_en = reverse ? 0x3f : 0x15; 2931 bias1_en = reverse ? 0x15 : 0x3f; 2932 drvr0_en = 0x10; 2933 drvr1_en = 0x10; 2934 } else { 2935 bias0_en = 0x3f; 2936 bias1_en = 0x3f; 2937 drvr0_en = 0x10; 2938 drvr1_en = 0x10; 2939 } 2940 2941 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2942 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2943 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2944 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2945 2946 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2947 udelay(2000); 2948 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2949 2950 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2951 status, 2952 ((status & BIT(1)) > 0), 2953 500, 2954 10000)) 2955 return -ETIMEDOUT; 2956 2957 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2958 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2959 2960 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2961 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2962 2963 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2964 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2965 2966 return 0; 2967 } 2968 2969 /* 2970 * We need to calibrate the aux setting here as many times 2971 * as the caller tries 2972 */ 2973 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2974 { 2975 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2976 u8 val; 2977 2978 qmp->dp_aux_cfg++; 2979 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2980 val = cfg1_settings[qmp->dp_aux_cfg]; 2981 2982 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2983 2984 return 0; 2985 } 2986 2987 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2988 { 2989 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2990 struct qmp_combo *qmp = phy_get_drvdata(phy); 2991 const struct qmp_phy_cfg *cfg = qmp->cfg; 2992 2993 mutex_lock(&qmp->phy_mutex); 2994 2995 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2996 if (qmp->dp_opts.set_voltages) { 2997 cfg->configure_dp_tx(qmp); 2998 qmp->dp_opts.set_voltages = 0; 2999 } 3000 3001 mutex_unlock(&qmp->phy_mutex); 3002 3003 return 0; 3004 } 3005 3006 static int qmp_combo_dp_calibrate(struct phy *phy) 3007 { 3008 struct qmp_combo *qmp = phy_get_drvdata(phy); 3009 const struct qmp_phy_cfg *cfg = qmp->cfg; 3010 int ret = 0; 3011 3012 mutex_lock(&qmp->phy_mutex); 3013 3014 if (cfg->calibrate_dp_phy) 3015 ret = cfg->calibrate_dp_phy(qmp); 3016 3017 mutex_unlock(&qmp->phy_mutex); 3018 3019 return ret; 3020 } 3021 3022 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 3023 { 3024 const struct qmp_phy_cfg *cfg = qmp->cfg; 3025 void __iomem *com = qmp->com; 3026 int ret; 3027 u32 val; 3028 3029 if (!force && qmp->init_count++) 3030 return 0; 3031 3032 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 3033 if (ret) { 3034 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 3035 goto err_decrement_count; 3036 } 3037 3038 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3039 if (ret) { 3040 dev_err(qmp->dev, "reset assert failed\n"); 3041 goto err_disable_regulators; 3042 } 3043 3044 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 3045 if (ret) { 3046 dev_err(qmp->dev, "reset deassert failed\n"); 3047 goto err_disable_regulators; 3048 } 3049 3050 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 3051 if (ret) 3052 goto err_assert_reset; 3053 3054 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 3055 3056 /* override hardware control for reset of qmp phy */ 3057 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3058 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3059 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3060 3061 /* Use software based port select and switch on typec orientation */ 3062 val = SW_PORTSELECT_MUX; 3063 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 3064 val |= SW_PORTSELECT_VAL; 3065 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 3066 3067 switch (qmp->qmpphy_mode) { 3068 case QMPPHY_MODE_USB3DP: 3069 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3070 3071 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 3072 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3073 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3074 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3075 break; 3076 3077 case QMPPHY_MODE_DP_ONLY: 3078 writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3079 3080 /* bring QMP DP PHY PCS block out of reset */ 3081 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3082 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET); 3083 break; 3084 3085 case QMPPHY_MODE_USB3_ONLY: 3086 writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3087 3088 /* bring QMP USB PHY PCS block out of reset */ 3089 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3090 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3091 break; 3092 } 3093 3094 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 3095 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 3096 3097 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3098 SW_PWRDN); 3099 3100 return 0; 3101 3102 err_assert_reset: 3103 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3104 err_disable_regulators: 3105 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3106 err_decrement_count: 3107 qmp->init_count--; 3108 3109 return ret; 3110 } 3111 3112 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 3113 { 3114 const struct qmp_phy_cfg *cfg = qmp->cfg; 3115 3116 if (!force && --qmp->init_count) 3117 return 0; 3118 3119 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3120 3121 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3122 3123 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3124 3125 return 0; 3126 } 3127 3128 static int qmp_combo_dp_init(struct phy *phy) 3129 { 3130 struct qmp_combo *qmp = phy_get_drvdata(phy); 3131 const struct qmp_phy_cfg *cfg = qmp->cfg; 3132 int ret; 3133 3134 mutex_lock(&qmp->phy_mutex); 3135 3136 ret = qmp_combo_com_init(qmp, false); 3137 if (ret) 3138 goto out_unlock; 3139 3140 cfg->dp_aux_init(qmp); 3141 3142 qmp->dp_init_count++; 3143 3144 out_unlock: 3145 mutex_unlock(&qmp->phy_mutex); 3146 return ret; 3147 } 3148 3149 static int qmp_combo_dp_exit(struct phy *phy) 3150 { 3151 struct qmp_combo *qmp = phy_get_drvdata(phy); 3152 3153 mutex_lock(&qmp->phy_mutex); 3154 3155 qmp_combo_com_exit(qmp, false); 3156 3157 qmp->dp_init_count--; 3158 3159 mutex_unlock(&qmp->phy_mutex); 3160 3161 return 0; 3162 } 3163 3164 static int qmp_combo_dp_power_on(struct phy *phy) 3165 { 3166 struct qmp_combo *qmp = phy_get_drvdata(phy); 3167 const struct qmp_phy_cfg *cfg = qmp->cfg; 3168 void __iomem *tx = qmp->dp_tx; 3169 void __iomem *tx2 = qmp->dp_tx2; 3170 3171 mutex_lock(&qmp->phy_mutex); 3172 3173 qmp_combo_dp_serdes_init(qmp); 3174 3175 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 3176 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 3177 3178 /* Configure special DP tx tunings */ 3179 cfg->configure_dp_tx(qmp); 3180 3181 /* Configure link rate, swing, etc. */ 3182 cfg->configure_dp_phy(qmp); 3183 3184 qmp->dp_powered_on = true; 3185 3186 mutex_unlock(&qmp->phy_mutex); 3187 3188 return 0; 3189 } 3190 3191 static int qmp_combo_dp_power_off(struct phy *phy) 3192 { 3193 struct qmp_combo *qmp = phy_get_drvdata(phy); 3194 3195 mutex_lock(&qmp->phy_mutex); 3196 3197 /* Assert DP PHY power down */ 3198 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3199 3200 qmp->dp_powered_on = false; 3201 3202 mutex_unlock(&qmp->phy_mutex); 3203 3204 return 0; 3205 } 3206 3207 static int qmp_combo_usb_power_on(struct phy *phy) 3208 { 3209 struct qmp_combo *qmp = phy_get_drvdata(phy); 3210 const struct qmp_phy_cfg *cfg = qmp->cfg; 3211 void __iomem *serdes = qmp->serdes; 3212 void __iomem *tx = qmp->tx; 3213 void __iomem *rx = qmp->rx; 3214 void __iomem *tx2 = qmp->tx2; 3215 void __iomem *rx2 = qmp->rx2; 3216 void __iomem *pcs = qmp->pcs; 3217 void __iomem *pcs_usb = qmp->pcs_usb; 3218 void __iomem *status; 3219 unsigned int val; 3220 int ret; 3221 3222 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 3223 3224 ret = clk_prepare_enable(qmp->pipe_clk); 3225 if (ret) { 3226 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 3227 return ret; 3228 } 3229 3230 /* Tx, Rx, and PCS configurations */ 3231 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 3232 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 3233 3234 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 3235 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 3236 3237 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 3238 3239 if (pcs_usb) 3240 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, 3241 cfg->pcs_usb_tbl_num); 3242 3243 if (cfg->has_pwrdn_delay) 3244 usleep_range(10, 20); 3245 3246 /* Pull PHY out of reset state */ 3247 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3248 3249 /* start SerDes and Phy-Coding-Sublayer */ 3250 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 3251 3252 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 3253 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 3254 PHY_INIT_COMPLETE_TIMEOUT); 3255 if (ret) { 3256 dev_err(qmp->dev, "phy initialization timed-out\n"); 3257 goto err_disable_pipe_clk; 3258 } 3259 3260 return 0; 3261 3262 err_disable_pipe_clk: 3263 clk_disable_unprepare(qmp->pipe_clk); 3264 3265 return ret; 3266 } 3267 3268 static int qmp_combo_usb_power_off(struct phy *phy) 3269 { 3270 struct qmp_combo *qmp = phy_get_drvdata(phy); 3271 const struct qmp_phy_cfg *cfg = qmp->cfg; 3272 3273 clk_disable_unprepare(qmp->pipe_clk); 3274 3275 /* PHY reset */ 3276 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3277 3278 /* stop SerDes and Phy-Coding-Sublayer */ 3279 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 3280 SERDES_START | PCS_START); 3281 3282 /* Put PHY into POWER DOWN state: active low */ 3283 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3284 SW_PWRDN); 3285 3286 return 0; 3287 } 3288 3289 static int qmp_combo_usb_init(struct phy *phy) 3290 { 3291 struct qmp_combo *qmp = phy_get_drvdata(phy); 3292 int ret; 3293 3294 mutex_lock(&qmp->phy_mutex); 3295 ret = qmp_combo_com_init(qmp, false); 3296 if (ret) 3297 goto out_unlock; 3298 3299 ret = qmp_combo_usb_power_on(phy); 3300 if (ret) { 3301 qmp_combo_com_exit(qmp, false); 3302 goto out_unlock; 3303 } 3304 3305 qmp->usb_init_count++; 3306 3307 out_unlock: 3308 mutex_unlock(&qmp->phy_mutex); 3309 return ret; 3310 } 3311 3312 static int qmp_combo_usb_exit(struct phy *phy) 3313 { 3314 struct qmp_combo *qmp = phy_get_drvdata(phy); 3315 int ret; 3316 3317 mutex_lock(&qmp->phy_mutex); 3318 ret = qmp_combo_usb_power_off(phy); 3319 if (ret) 3320 goto out_unlock; 3321 3322 ret = qmp_combo_com_exit(qmp, false); 3323 if (ret) 3324 goto out_unlock; 3325 3326 qmp->usb_init_count--; 3327 3328 out_unlock: 3329 mutex_unlock(&qmp->phy_mutex); 3330 return ret; 3331 } 3332 3333 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 3334 { 3335 struct qmp_combo *qmp = phy_get_drvdata(phy); 3336 3337 qmp->phy_mode = mode; 3338 3339 return 0; 3340 } 3341 3342 static const struct phy_ops qmp_combo_usb_phy_ops = { 3343 .init = qmp_combo_usb_init, 3344 .exit = qmp_combo_usb_exit, 3345 .set_mode = qmp_combo_usb_set_mode, 3346 .owner = THIS_MODULE, 3347 }; 3348 3349 static const struct phy_ops qmp_combo_dp_phy_ops = { 3350 .init = qmp_combo_dp_init, 3351 .configure = qmp_combo_dp_configure, 3352 .power_on = qmp_combo_dp_power_on, 3353 .calibrate = qmp_combo_dp_calibrate, 3354 .power_off = qmp_combo_dp_power_off, 3355 .exit = qmp_combo_dp_exit, 3356 .owner = THIS_MODULE, 3357 }; 3358 3359 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 3360 { 3361 const struct qmp_phy_cfg *cfg = qmp->cfg; 3362 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 3363 void __iomem *pcs_misc = qmp->pcs_misc; 3364 u32 intr_mask; 3365 3366 if (qmp->phy_mode == PHY_MODE_USB_HOST_SS || 3367 qmp->phy_mode == PHY_MODE_USB_DEVICE_SS) 3368 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 3369 else 3370 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 3371 3372 /* Clear any pending interrupts status */ 3373 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3374 /* Writing 1 followed by 0 clears the interrupt */ 3375 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3376 3377 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3378 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 3379 3380 /* Enable required PHY autonomous mode interrupts */ 3381 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 3382 3383 /* Enable i/o clamp_n for autonomous mode */ 3384 if (pcs_misc) 3385 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3386 } 3387 3388 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 3389 { 3390 const struct qmp_phy_cfg *cfg = qmp->cfg; 3391 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 3392 void __iomem *pcs_misc = qmp->pcs_misc; 3393 3394 /* Disable i/o clamp_n on resume for normal mode */ 3395 if (pcs_misc) 3396 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3397 3398 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3399 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 3400 3401 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3402 /* Writing 1 followed by 0 clears the interrupt */ 3403 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3404 } 3405 3406 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 3407 { 3408 struct qmp_combo *qmp = dev_get_drvdata(dev); 3409 3410 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->phy_mode); 3411 3412 if (!qmp->init_count) { 3413 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3414 return 0; 3415 } 3416 3417 qmp_combo_enable_autonomous_mode(qmp); 3418 3419 clk_disable_unprepare(qmp->pipe_clk); 3420 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3421 3422 return 0; 3423 } 3424 3425 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 3426 { 3427 struct qmp_combo *qmp = dev_get_drvdata(dev); 3428 int ret = 0; 3429 3430 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->phy_mode); 3431 3432 if (!qmp->init_count) { 3433 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3434 return 0; 3435 } 3436 3437 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 3438 if (ret) 3439 return ret; 3440 3441 ret = clk_prepare_enable(qmp->pipe_clk); 3442 if (ret) { 3443 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 3444 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3445 return ret; 3446 } 3447 3448 qmp_combo_disable_autonomous_mode(qmp); 3449 3450 return 0; 3451 } 3452 3453 static const struct dev_pm_ops qmp_combo_pm_ops = { 3454 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 3455 qmp_combo_runtime_resume, NULL) 3456 }; 3457 3458 static int qmp_combo_reset_init(struct qmp_combo *qmp) 3459 { 3460 const struct qmp_phy_cfg *cfg = qmp->cfg; 3461 struct device *dev = qmp->dev; 3462 int i; 3463 int ret; 3464 3465 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 3466 sizeof(*qmp->resets), GFP_KERNEL); 3467 if (!qmp->resets) 3468 return -ENOMEM; 3469 3470 for (i = 0; i < cfg->num_resets; i++) 3471 qmp->resets[i].id = cfg->reset_list[i]; 3472 3473 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 3474 if (ret) 3475 return dev_err_probe(dev, ret, "failed to get resets\n"); 3476 3477 return 0; 3478 } 3479 3480 static int qmp_combo_clk_init(struct qmp_combo *qmp) 3481 { 3482 struct device *dev = qmp->dev; 3483 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 3484 int i; 3485 3486 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3487 if (!qmp->clks) 3488 return -ENOMEM; 3489 3490 for (i = 0; i < num; i++) 3491 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 3492 3493 qmp->num_clks = num; 3494 3495 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 3496 } 3497 3498 static void phy_clk_release_provider(void *res) 3499 { 3500 of_clk_del_provider(res); 3501 } 3502 3503 /* 3504 * Register a fixed rate pipe clock. 3505 * 3506 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3507 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3508 * by the PHY driver for its operations. 3509 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3510 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3511 * Below picture shows this relationship. 3512 * 3513 * +---------------+ 3514 * | PHY block |<<---------------------------------------+ 3515 * | | | 3516 * | +-------+ | +-----+ | 3517 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3518 * clk | +-------+ | +-----+ 3519 * +---------------+ 3520 */ 3521 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 3522 { 3523 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3524 struct clk_init_data init = { }; 3525 char name[64]; 3526 3527 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 3528 init.name = name; 3529 init.ops = &clk_fixed_rate_ops; 3530 3531 /* controllers using QMP phys use 125MHz pipe clock interface */ 3532 fixed->fixed_rate = 125000000; 3533 fixed->hw.init = &init; 3534 3535 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3536 } 3537 3538 /* 3539 * Display Port PLL driver block diagram for branch clocks 3540 * 3541 * +------------------------------+ 3542 * | DP_VCO_CLK | 3543 * | | 3544 * | +-------------------+ | 3545 * | | (DP PLL/VCO) | | 3546 * | +---------+---------+ | 3547 * | v | 3548 * | +----------+-----------+ | 3549 * | | hsclk_divsel_clk_src | | 3550 * | +----------+-----------+ | 3551 * +------------------------------+ 3552 * | 3553 * +---------<---------v------------>----------+ 3554 * | | 3555 * +--------v----------------+ | 3556 * | dp_phy_pll_link_clk | | 3557 * | link_clk | | 3558 * +--------+----------------+ | 3559 * | | 3560 * | | 3561 * v v 3562 * Input to DISPCC block | 3563 * for link clk, crypto clk | 3564 * and interface clock | 3565 * | 3566 * | 3567 * +--------<------------+-----------------+---<---+ 3568 * | | | 3569 * +----v---------+ +--------v-----+ +--------v------+ 3570 * | vco_divided | | vco_divided | | vco_divided | 3571 * | _clk_src | | _clk_src | | _clk_src | 3572 * | | | | | | 3573 * |divsel_six | | divsel_two | | divsel_four | 3574 * +-------+------+ +-----+--------+ +--------+------+ 3575 * | | | 3576 * v---->----------v-------------<------v 3577 * | 3578 * +----------+-----------------+ 3579 * | dp_phy_pll_vco_div_clk | 3580 * +---------+------------------+ 3581 * | 3582 * v 3583 * Input to DISPCC block 3584 * for DP pixel clock 3585 * 3586 */ 3587 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3588 { 3589 switch (req->rate) { 3590 case 1620000000UL / 2: 3591 case 2700000000UL / 2: 3592 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3593 return 0; 3594 default: 3595 return -EINVAL; 3596 } 3597 } 3598 3599 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3600 { 3601 const struct qmp_combo *qmp; 3602 const struct phy_configure_opts_dp *dp_opts; 3603 3604 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 3605 dp_opts = &qmp->dp_opts; 3606 3607 switch (dp_opts->link_rate) { 3608 case 1620: 3609 return 1620000000UL / 2; 3610 case 2700: 3611 return 2700000000UL / 2; 3612 case 5400: 3613 return 5400000000UL / 4; 3614 case 8100: 3615 return 8100000000UL / 6; 3616 default: 3617 return 0; 3618 } 3619 } 3620 3621 static const struct clk_ops qmp_dp_pixel_clk_ops = { 3622 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3623 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3624 }; 3625 3626 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3627 { 3628 switch (req->rate) { 3629 case 162000000: 3630 case 270000000: 3631 case 540000000: 3632 case 810000000: 3633 return 0; 3634 default: 3635 return -EINVAL; 3636 } 3637 } 3638 3639 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3640 { 3641 const struct qmp_combo *qmp; 3642 const struct phy_configure_opts_dp *dp_opts; 3643 3644 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3645 dp_opts = &qmp->dp_opts; 3646 3647 switch (dp_opts->link_rate) { 3648 case 1620: 3649 case 2700: 3650 case 5400: 3651 case 8100: 3652 return dp_opts->link_rate * 100000; 3653 default: 3654 return 0; 3655 } 3656 } 3657 3658 static const struct clk_ops qmp_dp_link_clk_ops = { 3659 .determine_rate = qmp_dp_link_clk_determine_rate, 3660 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3661 }; 3662 3663 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3664 { 3665 struct qmp_combo *qmp = data; 3666 unsigned int idx = clkspec->args[0]; 3667 3668 if (idx >= 2) { 3669 pr_err("%s: invalid index %u\n", __func__, idx); 3670 return ERR_PTR(-EINVAL); 3671 } 3672 3673 if (idx == 0) 3674 return &qmp->dp_link_hw; 3675 3676 return &qmp->dp_pixel_hw; 3677 } 3678 3679 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3680 { 3681 struct clk_init_data init = { }; 3682 char name[64]; 3683 int ret; 3684 3685 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3686 init.ops = &qmp_dp_link_clk_ops; 3687 init.name = name; 3688 qmp->dp_link_hw.init = &init; 3689 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3690 if (ret) 3691 return ret; 3692 3693 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3694 init.ops = &qmp_dp_pixel_clk_ops; 3695 init.name = name; 3696 qmp->dp_pixel_hw.init = &init; 3697 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3698 if (ret) 3699 return ret; 3700 3701 return 0; 3702 } 3703 3704 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3705 { 3706 struct qmp_combo *qmp = data; 3707 3708 switch (clkspec->args[0]) { 3709 case QMP_USB43DP_USB3_PIPE_CLK: 3710 return &qmp->pipe_clk_fixed.hw; 3711 case QMP_USB43DP_DP_LINK_CLK: 3712 return &qmp->dp_link_hw; 3713 case QMP_USB43DP_DP_VCO_DIV_CLK: 3714 return &qmp->dp_pixel_hw; 3715 } 3716 3717 return ERR_PTR(-EINVAL); 3718 } 3719 3720 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3721 struct device_node *dp_np) 3722 { 3723 int ret; 3724 3725 ret = phy_pipe_clk_register(qmp, usb_np); 3726 if (ret) 3727 return ret; 3728 3729 ret = phy_dp_clks_register(qmp, dp_np); 3730 if (ret) 3731 return ret; 3732 3733 /* 3734 * Register a single provider for bindings without child nodes. 3735 */ 3736 if (usb_np == qmp->dev->of_node) 3737 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3738 3739 /* 3740 * Register multiple providers for legacy bindings with child nodes. 3741 */ 3742 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3743 &qmp->pipe_clk_fixed.hw); 3744 if (ret) 3745 return ret; 3746 3747 /* 3748 * Roll a devm action because the clock provider is the child node, but 3749 * the child node is not actually a device. 3750 */ 3751 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3752 if (ret) 3753 return ret; 3754 3755 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3756 if (ret) 3757 return ret; 3758 3759 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3760 } 3761 3762 #if IS_ENABLED(CONFIG_TYPEC) 3763 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3764 enum typec_orientation orientation) 3765 { 3766 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3767 const struct qmp_phy_cfg *cfg = qmp->cfg; 3768 3769 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3770 return 0; 3771 3772 mutex_lock(&qmp->phy_mutex); 3773 qmp->orientation = orientation; 3774 3775 if (qmp->init_count) { 3776 if (qmp->usb_init_count) 3777 qmp_combo_usb_power_off(qmp->usb_phy); 3778 qmp_combo_com_exit(qmp, true); 3779 3780 qmp_combo_com_init(qmp, true); 3781 if (qmp->usb_init_count) 3782 qmp_combo_usb_power_on(qmp->usb_phy); 3783 if (qmp->dp_init_count) 3784 cfg->dp_aux_init(qmp); 3785 } 3786 mutex_unlock(&qmp->phy_mutex); 3787 3788 return 0; 3789 } 3790 3791 static int qmp_combo_typec_mux_set(struct typec_mux_dev *mux, struct typec_mux_state *state) 3792 { 3793 struct qmp_combo *qmp = typec_mux_get_drvdata(mux); 3794 const struct qmp_phy_cfg *cfg = qmp->cfg; 3795 enum qmpphy_mode new_mode; 3796 unsigned int svid; 3797 3798 guard(mutex)(&qmp->phy_mutex); 3799 3800 if (state->alt) 3801 svid = state->alt->svid; 3802 else 3803 svid = 0; 3804 3805 if (svid == USB_TYPEC_DP_SID) { 3806 switch (state->mode) { 3807 /* DP Only */ 3808 case TYPEC_DP_STATE_C: 3809 case TYPEC_DP_STATE_E: 3810 new_mode = QMPPHY_MODE_DP_ONLY; 3811 break; 3812 3813 /* DP + USB */ 3814 case TYPEC_DP_STATE_D: 3815 case TYPEC_DP_STATE_F: 3816 3817 /* Safe fallback...*/ 3818 default: 3819 new_mode = QMPPHY_MODE_USB3DP; 3820 break; 3821 } 3822 } else { 3823 /* No DP SVID => don't care, assume it's just USB3 */ 3824 new_mode = QMPPHY_MODE_USB3_ONLY; 3825 } 3826 3827 if (new_mode == qmp->qmpphy_mode) { 3828 dev_dbg(qmp->dev, "typec_mux_set: same qmpphy mode, bail out\n"); 3829 return 0; 3830 } 3831 3832 if (qmp->qmpphy_mode != QMPPHY_MODE_USB3_ONLY && qmp->dp_powered_on) { 3833 dev_dbg(qmp->dev, "typec_mux_set: DP PHY is still in use, delaying switch\n"); 3834 return 0; 3835 } 3836 3837 dev_dbg(qmp->dev, "typec_mux_set: switching from qmpphy mode %d to %d\n", 3838 qmp->qmpphy_mode, new_mode); 3839 3840 qmp->qmpphy_mode = new_mode; 3841 3842 if (qmp->init_count) { 3843 if (qmp->usb_init_count) 3844 qmp_combo_usb_power_off(qmp->usb_phy); 3845 3846 if (qmp->dp_init_count) 3847 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3848 3849 qmp_combo_com_exit(qmp, true); 3850 3851 /* Now everything's powered down, power up the right PHYs */ 3852 qmp_combo_com_init(qmp, true); 3853 3854 if (new_mode == QMPPHY_MODE_DP_ONLY) { 3855 if (qmp->usb_init_count) 3856 qmp->usb_init_count--; 3857 } 3858 3859 if (new_mode == QMPPHY_MODE_USB3DP || new_mode == QMPPHY_MODE_USB3_ONLY) { 3860 qmp_combo_usb_power_on(qmp->usb_phy); 3861 if (!qmp->usb_init_count) 3862 qmp->usb_init_count++; 3863 } 3864 3865 if (new_mode == QMPPHY_MODE_DP_ONLY || new_mode == QMPPHY_MODE_USB3DP) { 3866 if (qmp->dp_init_count) 3867 cfg->dp_aux_init(qmp); 3868 } 3869 } 3870 3871 return 0; 3872 } 3873 3874 static void qmp_combo_typec_switch_unregister(void *data) 3875 { 3876 struct qmp_combo *qmp = data; 3877 3878 typec_switch_unregister(qmp->sw); 3879 } 3880 3881 static void qmp_combo_typec_mux_unregister(void *data) 3882 { 3883 struct qmp_combo *qmp = data; 3884 3885 typec_mux_unregister(qmp->mux); 3886 } 3887 3888 static int qmp_combo_typec_register(struct qmp_combo *qmp) 3889 { 3890 struct typec_switch_desc sw_desc = {}; 3891 struct typec_mux_desc mux_desc = { }; 3892 struct device *dev = qmp->dev; 3893 int ret; 3894 3895 sw_desc.drvdata = qmp; 3896 sw_desc.fwnode = dev->fwnode; 3897 sw_desc.set = qmp_combo_typec_switch_set; 3898 qmp->sw = typec_switch_register(dev, &sw_desc); 3899 if (IS_ERR(qmp->sw)) { 3900 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3901 return PTR_ERR(qmp->sw); 3902 } 3903 3904 ret = devm_add_action_or_reset(dev, qmp_combo_typec_switch_unregister, qmp); 3905 if (ret) 3906 return ret; 3907 3908 mux_desc.drvdata = qmp; 3909 mux_desc.fwnode = dev->fwnode; 3910 mux_desc.set = qmp_combo_typec_mux_set; 3911 qmp->mux = typec_mux_register(dev, &mux_desc); 3912 if (IS_ERR(qmp->mux)) { 3913 dev_err(dev, "Unable to register typec mux: %pe\n", qmp->mux); 3914 return PTR_ERR(qmp->mux); 3915 } 3916 3917 return devm_add_action_or_reset(dev, qmp_combo_typec_mux_unregister, qmp); 3918 } 3919 #else 3920 static int qmp_combo_typec_register(struct qmp_combo *qmp) 3921 { 3922 return 0; 3923 } 3924 #endif 3925 3926 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np) 3927 { 3928 struct device *dev = qmp->dev; 3929 3930 /* 3931 * Get memory resources from the DP child node: 3932 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3933 * tx2 -> 3; rx2 -> 4 3934 * 3935 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3936 * implementation. 3937 */ 3938 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3939 if (IS_ERR(qmp->dp_tx)) 3940 return PTR_ERR(qmp->dp_tx); 3941 3942 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3943 if (IS_ERR(qmp->dp_dp_phy)) 3944 return PTR_ERR(qmp->dp_dp_phy); 3945 3946 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3947 if (IS_ERR(qmp->dp_tx2)) 3948 return PTR_ERR(qmp->dp_tx2); 3949 3950 return 0; 3951 } 3952 3953 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np) 3954 { 3955 const struct qmp_phy_cfg *cfg = qmp->cfg; 3956 struct device *dev = qmp->dev; 3957 3958 /* 3959 * Get memory resources from the USB child node: 3960 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3961 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3962 */ 3963 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3964 if (IS_ERR(qmp->tx)) 3965 return PTR_ERR(qmp->tx); 3966 3967 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3968 if (IS_ERR(qmp->rx)) 3969 return PTR_ERR(qmp->rx); 3970 3971 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3972 if (IS_ERR(qmp->pcs)) 3973 return PTR_ERR(qmp->pcs); 3974 3975 if (cfg->pcs_usb_offset) 3976 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3977 3978 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3979 if (IS_ERR(qmp->tx2)) 3980 return PTR_ERR(qmp->tx2); 3981 3982 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3983 if (IS_ERR(qmp->rx2)) 3984 return PTR_ERR(qmp->rx2); 3985 3986 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3987 if (IS_ERR(qmp->pcs_misc)) { 3988 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3989 qmp->pcs_misc = NULL; 3990 } 3991 3992 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3993 if (IS_ERR(qmp->pipe_clk)) { 3994 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3995 "failed to get pipe clock\n"); 3996 } 3997 3998 return 0; 3999 } 4000 4001 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 4002 struct device_node *dp_np) 4003 { 4004 struct platform_device *pdev = to_platform_device(qmp->dev); 4005 int ret; 4006 4007 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 4008 if (IS_ERR(qmp->serdes)) 4009 return PTR_ERR(qmp->serdes); 4010 4011 qmp->com = devm_platform_ioremap_resource(pdev, 1); 4012 if (IS_ERR(qmp->com)) 4013 return PTR_ERR(qmp->com); 4014 4015 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 4016 if (IS_ERR(qmp->dp_serdes)) 4017 return PTR_ERR(qmp->dp_serdes); 4018 4019 ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np); 4020 if (ret) 4021 return ret; 4022 4023 ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np); 4024 if (ret) 4025 return ret; 4026 4027 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 4028 if (ret < 0) 4029 return ret; 4030 4031 qmp->num_clks = ret; 4032 4033 return 0; 4034 } 4035 4036 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 4037 { 4038 struct platform_device *pdev = to_platform_device(qmp->dev); 4039 const struct qmp_phy_cfg *cfg = qmp->cfg; 4040 const struct qmp_combo_offsets *offs = cfg->offsets; 4041 struct device *dev = qmp->dev; 4042 void __iomem *base; 4043 int ret; 4044 4045 if (!offs) 4046 return -EINVAL; 4047 4048 base = devm_platform_ioremap_resource(pdev, 0); 4049 if (IS_ERR(base)) 4050 return PTR_ERR(base); 4051 4052 qmp->com = base + offs->com; 4053 qmp->tx = base + offs->txa; 4054 qmp->rx = base + offs->rxa; 4055 qmp->tx2 = base + offs->txb; 4056 qmp->rx2 = base + offs->rxb; 4057 4058 qmp->serdes = base + offs->usb3_serdes; 4059 qmp->pcs_misc = base + offs->usb3_pcs_misc; 4060 qmp->pcs = base + offs->usb3_pcs; 4061 qmp->pcs_usb = base + offs->usb3_pcs_usb; 4062 4063 qmp->dp_serdes = base + offs->dp_serdes; 4064 if (offs->dp_txa) { 4065 qmp->dp_tx = base + offs->dp_txa; 4066 qmp->dp_tx2 = base + offs->dp_txb; 4067 } else { 4068 qmp->dp_tx = base + offs->txa; 4069 qmp->dp_tx2 = base + offs->txb; 4070 } 4071 qmp->dp_dp_phy = base + offs->dp_dp_phy; 4072 4073 ret = qmp_combo_clk_init(qmp); 4074 if (ret) 4075 return ret; 4076 4077 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 4078 if (IS_ERR(qmp->pipe_clk)) { 4079 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 4080 "failed to get usb3_pipe clock\n"); 4081 } 4082 4083 return 0; 4084 } 4085 4086 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 4087 { 4088 struct qmp_combo *qmp = dev_get_drvdata(dev); 4089 4090 if (args->args_count == 0) 4091 return ERR_PTR(-EINVAL); 4092 4093 switch (args->args[0]) { 4094 case QMP_USB43DP_USB3_PHY: 4095 return qmp->usb_phy; 4096 case QMP_USB43DP_DP_PHY: 4097 return qmp->dp_phy; 4098 } 4099 4100 return ERR_PTR(-EINVAL); 4101 } 4102 4103 static void qmp_combo_find_lanes_orientation(const struct qmp_combo_lane_mapping *mapping, 4104 unsigned int mapping_count, 4105 u32 *lanes, unsigned int lanes_count, 4106 enum typec_orientation *orientation) 4107 { 4108 int i; 4109 4110 for (i = 0; i < mapping_count; i++) { 4111 if (mapping[i].lanes_count != lanes_count) 4112 continue; 4113 if (!memcmp(mapping[i].lanes, lanes, sizeof(u32) * lanes_count)) { 4114 *orientation = mapping[i].orientation; 4115 return; 4116 } 4117 } 4118 } 4119 4120 static int qmp_combo_get_dt_lanes_mapping(struct device *dev, unsigned int endpoint, 4121 u32 *data_lanes, unsigned int max, 4122 unsigned int *count) 4123 { 4124 struct device_node *ep __free(device_node) = NULL; 4125 int ret; 4126 4127 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, endpoint); 4128 if (!ep) 4129 return -EINVAL; 4130 4131 ret = of_property_count_u32_elems(ep, "data-lanes"); 4132 if (ret < 0) 4133 return ret; 4134 4135 *count = ret; 4136 if (*count > max) 4137 return -EINVAL; 4138 4139 return of_property_read_u32_array(ep, "data-lanes", data_lanes, 4140 min_t(unsigned int, *count, max)); 4141 } 4142 4143 static int qmp_combo_get_dt_dp_orientation(struct device *dev, 4144 enum typec_orientation *orientation) 4145 { 4146 unsigned int count; 4147 u32 data_lanes[4]; 4148 int ret; 4149 4150 /* DP is described on the first endpoint of the first port */ 4151 ret = qmp_combo_get_dt_lanes_mapping(dev, 0, data_lanes, 4, &count); 4152 if (ret < 0) 4153 return ret == -EINVAL ? 0 : ret; 4154 4155 /* Search for a match and only update orientation if found */ 4156 qmp_combo_find_lanes_orientation(dp_data_lanes, ARRAY_SIZE(dp_data_lanes), 4157 data_lanes, count, orientation); 4158 4159 return 0; 4160 } 4161 4162 static int qmp_combo_get_dt_usb3_orientation(struct device *dev, 4163 enum typec_orientation *orientation) 4164 { 4165 unsigned int count; 4166 u32 data_lanes[2]; 4167 int ret; 4168 4169 /* USB3 is described on the second endpoint of the first port */ 4170 ret = qmp_combo_get_dt_lanes_mapping(dev, 1, data_lanes, 2, &count); 4171 if (ret < 0) 4172 return ret == -EINVAL ? 0 : ret; 4173 4174 /* Search for a match and only update orientation if found */ 4175 qmp_combo_find_lanes_orientation(usb3_data_lanes, ARRAY_SIZE(usb3_data_lanes), 4176 data_lanes, count, orientation); 4177 4178 return 0; 4179 } 4180 4181 static int qmp_combo_probe(struct platform_device *pdev) 4182 { 4183 struct qmp_combo *qmp; 4184 struct device *dev = &pdev->dev; 4185 struct device_node *dp_np, *usb_np; 4186 struct phy_provider *phy_provider; 4187 int ret; 4188 4189 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 4190 if (!qmp) 4191 return -ENOMEM; 4192 4193 qmp->dev = dev; 4194 dev_set_drvdata(dev, qmp); 4195 4196 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 4197 4198 qmp->cfg = of_device_get_match_data(dev); 4199 if (!qmp->cfg) 4200 return -EINVAL; 4201 4202 mutex_init(&qmp->phy_mutex); 4203 4204 ret = qmp_combo_reset_init(qmp); 4205 if (ret) 4206 return ret; 4207 4208 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 4209 qmp->cfg->vreg_list, &qmp->vregs); 4210 if (ret) 4211 return ret; 4212 4213 /* Check for legacy binding with child nodes. */ 4214 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 4215 if (usb_np) { 4216 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 4217 if (!dp_np) { 4218 of_node_put(usb_np); 4219 return -EINVAL; 4220 } 4221 4222 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 4223 } else { 4224 usb_np = of_node_get(dev->of_node); 4225 dp_np = of_node_get(dev->of_node); 4226 4227 ret = qmp_combo_parse_dt(qmp); 4228 } 4229 if (ret) 4230 goto err_node_put; 4231 4232 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 4233 4234 if (of_property_present(dev->of_node, "mode-switch") || 4235 of_property_present(dev->of_node, "orientation-switch")) { 4236 ret = qmp_combo_typec_register(qmp); 4237 if (ret) 4238 goto err_node_put; 4239 } else { 4240 enum typec_orientation dp_orientation = TYPEC_ORIENTATION_NONE; 4241 enum typec_orientation usb3_orientation = TYPEC_ORIENTATION_NONE; 4242 4243 ret = qmp_combo_get_dt_dp_orientation(dev, &dp_orientation); 4244 if (ret) 4245 goto err_node_put; 4246 4247 ret = qmp_combo_get_dt_usb3_orientation(dev, &usb3_orientation); 4248 if (ret) 4249 goto err_node_put; 4250 4251 if (dp_orientation == TYPEC_ORIENTATION_NONE && 4252 usb3_orientation != TYPEC_ORIENTATION_NONE) { 4253 qmp->qmpphy_mode = QMPPHY_MODE_USB3_ONLY; 4254 qmp->orientation = usb3_orientation; 4255 } else if (usb3_orientation == TYPEC_ORIENTATION_NONE && 4256 dp_orientation != TYPEC_ORIENTATION_NONE) { 4257 qmp->qmpphy_mode = QMPPHY_MODE_DP_ONLY; 4258 qmp->orientation = dp_orientation; 4259 } else if (dp_orientation != TYPEC_ORIENTATION_NONE && 4260 dp_orientation == usb3_orientation) { 4261 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 4262 qmp->orientation = dp_orientation; 4263 } else { 4264 dev_warn(dev, "unable to determine orientation & mode from data-lanes"); 4265 } 4266 } 4267 4268 ret = drm_aux_bridge_register(dev); 4269 if (ret) 4270 goto err_node_put; 4271 4272 pm_runtime_set_active(dev); 4273 ret = devm_pm_runtime_enable(dev); 4274 if (ret) 4275 goto err_node_put; 4276 /* 4277 * Prevent runtime pm from being ON by default. Users can enable 4278 * it using power/control in sysfs. 4279 */ 4280 pm_runtime_forbid(dev); 4281 4282 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 4283 if (ret) 4284 goto err_node_put; 4285 4286 4287 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 4288 if (IS_ERR(qmp->usb_phy)) { 4289 ret = PTR_ERR(qmp->usb_phy); 4290 dev_err(dev, "failed to create USB PHY: %d\n", ret); 4291 goto err_node_put; 4292 } 4293 4294 phy_set_drvdata(qmp->usb_phy, qmp); 4295 4296 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 4297 if (IS_ERR(qmp->dp_phy)) { 4298 ret = PTR_ERR(qmp->dp_phy); 4299 dev_err(dev, "failed to create DP PHY: %d\n", ret); 4300 goto err_node_put; 4301 } 4302 4303 phy_set_drvdata(qmp->dp_phy, qmp); 4304 4305 if (usb_np == dev->of_node) 4306 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 4307 else 4308 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4309 4310 of_node_put(usb_np); 4311 of_node_put(dp_np); 4312 4313 return PTR_ERR_OR_ZERO(phy_provider); 4314 4315 err_node_put: 4316 of_node_put(usb_np); 4317 of_node_put(dp_np); 4318 return ret; 4319 } 4320 4321 static const struct of_device_id qmp_combo_of_match_table[] = { 4322 { 4323 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 4324 .data = &sar2130p_usb3dpphy_cfg, 4325 }, 4326 { 4327 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 4328 .data = &sc7180_usb3dpphy_cfg, 4329 }, 4330 { 4331 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 4332 .data = &sm8250_usb3dpphy_cfg, 4333 }, 4334 { 4335 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 4336 .data = &sc8180x_usb3dpphy_cfg, 4337 }, 4338 { 4339 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 4340 .data = &sc8280xp_usb43dpphy_cfg, 4341 }, 4342 { 4343 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 4344 .data = &sdm845_usb3dpphy_cfg, 4345 }, 4346 { 4347 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 4348 .data = &sm6350_usb3dpphy_cfg, 4349 }, 4350 { 4351 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 4352 .data = &sc8180x_usb3dpphy_cfg, 4353 }, 4354 { 4355 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 4356 .data = &sm8250_usb3dpphy_cfg, 4357 }, 4358 { 4359 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 4360 .data = &sm8350_usb3dpphy_cfg, 4361 }, 4362 { 4363 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 4364 .data = &sm8350_usb3dpphy_cfg, 4365 }, 4366 { 4367 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 4368 .data = &sm8550_usb3dpphy_cfg, 4369 }, 4370 { 4371 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 4372 .data = &sm8650_usb3dpphy_cfg, 4373 }, 4374 { 4375 .compatible = "qcom,sm8750-qmp-usb3-dp-phy", 4376 .data = &sm8750_usb3dpphy_cfg, 4377 }, 4378 { 4379 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 4380 .data = &x1e80100_usb3dpphy_cfg, 4381 }, 4382 { } 4383 }; 4384 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 4385 4386 static struct platform_driver qmp_combo_driver = { 4387 .probe = qmp_combo_probe, 4388 .driver = { 4389 .name = "qcom-qmp-combo-phy", 4390 .pm = &qmp_combo_pm_ops, 4391 .of_match_table = qmp_combo_of_match_table, 4392 }, 4393 }; 4394 4395 module_platform_driver(qmp_combo_driver); 4396 4397 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 4398 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 4399 MODULE_LICENSE("GPL v2"); 4400