1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/bridge/aux-bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp-common.h" 29 30 #include "phy-qcom-qmp.h" 31 #include "phy-qcom-qmp-pcs-misc-v3.h" 32 #include "phy-qcom-qmp-pcs-usb-v4.h" 33 #include "phy-qcom-qmp-pcs-usb-v5.h" 34 #include "phy-qcom-qmp-pcs-usb-v6.h" 35 #include "phy-qcom-qmp-pcs-usb-v8.h" 36 37 #include "phy-qcom-qmp-dp-com-v3.h" 38 39 #include "phy-qcom-qmp-dp-phy.h" 40 #include "phy-qcom-qmp-dp-phy-v3.h" 41 #include "phy-qcom-qmp-dp-phy-v4.h" 42 #include "phy-qcom-qmp-dp-phy-v5.h" 43 #include "phy-qcom-qmp-dp-phy-v6.h" 44 45 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 46 /* DP PHY soft reset */ 47 #define SW_DPPHY_RESET BIT(0) 48 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 49 #define SW_DPPHY_RESET_MUX BIT(1) 50 /* USB3 PHY soft reset */ 51 #define SW_USB3PHY_RESET BIT(2) 52 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 53 #define SW_USB3PHY_RESET_MUX BIT(3) 54 55 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 56 #define USB3_MODE BIT(0) /* enables USB3 mode */ 57 #define DP_MODE BIT(1) /* enables DP mode */ 58 59 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 60 #define SW_PORTSELECT_VAL BIT(0) 61 #define SW_PORTSELECT_MUX BIT(1) 62 63 #define PHY_INIT_COMPLETE_TIMEOUT 10000 64 65 /* set of registers with offsets different per-PHY */ 66 enum qphy_reg_layout { 67 /* PCS registers */ 68 QPHY_SW_RESET, 69 QPHY_START_CTRL, 70 QPHY_PCS_STATUS, 71 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 72 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 73 QPHY_PCS_POWER_DOWN_CONTROL, 74 75 QPHY_COM_RESETSM_CNTRL, 76 QPHY_COM_C_READY_STATUS, 77 QPHY_COM_CMN_STATUS, 78 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 79 80 QPHY_DP_PHY_STATUS, 81 QPHY_DP_PHY_VCO_DIV, 82 83 QPHY_TX_TX_POL_INV, 84 QPHY_TX_TX_DRV_LVL, 85 QPHY_TX_TX_EMP_POST1_LVL, 86 QPHY_TX_HIGHZ_DRVR_EN, 87 QPHY_TX_TRANSCEIVER_BIAS_EN, 88 89 /* Keep last to ensure regs_layout arrays are properly initialized */ 90 QPHY_LAYOUT_SIZE 91 }; 92 93 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 94 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 95 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 96 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 97 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 98 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 99 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 100 101 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 102 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 103 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 104 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 105 106 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 107 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 108 109 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 110 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 111 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 112 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 113 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 114 }; 115 116 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 117 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 118 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 119 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 120 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 121 122 /* In PCS_USB */ 123 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 124 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 125 126 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 127 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 128 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 129 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 130 131 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 132 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 133 134 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 135 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 136 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 137 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 138 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 139 }; 140 141 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 142 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 143 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 144 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 145 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 146 147 /* In PCS_USB */ 148 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 149 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 150 151 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 152 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 153 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 154 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 155 156 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 157 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 158 159 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 160 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 161 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 162 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 163 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 164 }; 165 166 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 167 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 168 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 169 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 170 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 171 172 /* In PCS_USB */ 173 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 174 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 175 176 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 177 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 178 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 179 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 180 181 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 182 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 183 184 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 185 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 186 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 187 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 188 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 189 }; 190 191 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 192 [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET, 193 [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL, 194 [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1, 195 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL, 196 197 /* In PCS_USB */ 198 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 199 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 200 201 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 202 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 203 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 204 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 205 206 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 207 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 208 209 [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV, 210 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL, 211 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, 212 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, 213 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, 214 }; 215 216 static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 217 [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET, 218 [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL, 219 [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1, 220 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL, 221 222 /* In PCS_USB */ 223 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 224 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 225 226 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 227 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 228 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 229 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 230 231 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 232 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 233 234 [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV, 235 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL, 236 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL, 237 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN, 238 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, 239 }; 240 241 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 278 }; 279 280 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 281 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 282 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 283 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 284 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 285 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 286 }; 287 288 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 310 }; 311 312 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 320 }; 321 322 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 329 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 330 }; 331 332 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 334 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 335 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 336 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 337 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 338 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 339 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 340 }; 341 342 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 343 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 344 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 345 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 346 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 347 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 348 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 349 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 350 }; 351 352 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 353 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 354 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 355 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 356 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 357 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 358 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 359 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 360 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 361 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 362 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 363 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 364 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 365 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 366 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 367 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 368 }; 369 370 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 371 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 372 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 373 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 374 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 375 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 376 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 377 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 378 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 379 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 380 }; 381 382 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 383 /* FLL settings */ 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 389 390 /* Lock Det settings */ 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 395 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 415 416 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 417 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 419 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 427 }; 428 429 static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = { 430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), 431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), 432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), 439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), 440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), 442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), 443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), 451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), 452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), 458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), 459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), 461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), 474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 478 }; 479 480 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 481 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 482 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 483 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 484 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 485 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 486 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 487 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 488 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 489 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 490 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 491 }; 492 493 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 494 /* FLL settings */ 495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 500 501 /* Lock Det settings */ 502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 506 507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 517 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 518 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 519 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 521 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 522 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 523 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 524 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 525 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 526 527 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 528 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 529 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 530 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 531 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 532 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 533 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 534 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 535 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 536 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 537 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 538 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 539 540 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 541 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 542 }; 543 544 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 548 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 549 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 550 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 558 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 559 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 560 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 561 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 562 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 563 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 564 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 565 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 566 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 567 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 568 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 569 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 570 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 571 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 572 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 573 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 574 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 575 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 576 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 577 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 578 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 579 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 580 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 585 }; 586 587 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 590 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 591 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 592 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 593 }; 594 595 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 632 }; 633 634 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 635 /* Lock Det settings */ 636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 639 640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 648 }; 649 650 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 653 }; 654 655 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 656 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 657 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 658 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 659 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 660 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 661 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 662 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 663 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 664 }; 665 666 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 687 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 688 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 689 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 690 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 705 }; 706 707 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 720 }; 721 722 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 725 }; 726 727 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 728 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 729 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 730 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 731 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 732 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 733 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 734 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 735 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 736 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 737 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 738 }; 739 740 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 744 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 745 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 746 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 747 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 748 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 753 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 754 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 755 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 756 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 757 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 758 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 759 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 760 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 761 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 762 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 763 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 764 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 765 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 766 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 767 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 768 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 769 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 770 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 771 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 772 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 773 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 774 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 778 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 779 }; 780 781 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 782 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 783 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 784 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 785 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 786 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 787 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 788 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 789 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 790 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 791 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 792 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 793 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 796 }; 797 798 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 799 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 800 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 801 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 802 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 803 }; 804 805 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 848 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 849 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 850 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 854 }; 855 856 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 857 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 858 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 859 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 860 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 861 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 862 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 863 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 864 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 865 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 866 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 867 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 868 }; 869 870 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 871 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 872 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 873 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 874 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 875 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 876 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 877 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 878 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 879 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 880 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 881 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 882 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 883 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 884 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 885 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 886 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 887 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 888 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 889 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 890 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 891 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 892 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 893 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 894 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 895 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 896 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 897 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 898 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 899 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 900 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 901 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 902 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 903 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 904 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 905 906 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 907 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 908 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 909 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 910 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 911 912 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 913 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 914 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 915 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 916 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 917 }; 918 919 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 920 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 921 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 922 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 923 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 924 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 925 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 926 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 927 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 929 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 930 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 931 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 932 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 933 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 934 }; 935 936 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 937 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 938 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 939 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 940 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 941 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 942 }; 943 944 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 945 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 946 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 947 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 948 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 949 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 950 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 951 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 952 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 965 }; 966 967 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 975 }; 976 977 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 985 }; 986 987 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 995 }; 996 997 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1005 }; 1006 1007 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 1008 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 1022 }; 1023 1024 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1048 }; 1049 1050 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 1051 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 1062 }; 1063 1064 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 1065 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1077 }; 1078 1079 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1080 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1090 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1091 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1092 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1093 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1094 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1095 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1096 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1097 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1098 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1099 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1100 }; 1101 1102 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = { 1103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1107 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1108 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1109 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1110 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1111 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1112 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1113 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1114 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1115 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1116 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1117 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1118 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1119 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1120 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1121 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1122 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1123 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1124 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1125 }; 1126 1127 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1128 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1129 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1130 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1131 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1132 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1133 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1134 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1135 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1136 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1137 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1138 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1139 }; 1140 1141 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = { 1142 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40), 1143 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00), 1144 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff), 1145 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f), 1146 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03), 1147 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1148 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1149 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1150 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1151 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1), 1152 }; 1153 1154 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1155 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1156 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1157 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1158 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1159 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1160 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1161 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1162 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1163 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1164 }; 1165 1166 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1167 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1168 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1169 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1170 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1171 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1172 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1173 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1174 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1175 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1176 }; 1177 1178 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1184 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1185 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1188 }; 1189 1190 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1196 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1200 }; 1201 1202 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = { 1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1217 }; 1218 1219 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = { 1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1227 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1234 }; 1235 1236 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = { 1237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1242 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1243 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1244 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1245 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1246 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1247 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1248 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1249 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1250 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1251 }; 1252 1253 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = { 1254 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1255 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1256 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1257 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1258 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1259 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1260 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1261 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1262 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1263 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1264 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1265 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1266 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1267 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1268 }; 1269 1270 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1271 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1318 }; 1319 1320 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1321 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1326 }; 1327 1328 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1329 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1346 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1347 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1355 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1356 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1357 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1358 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1359 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1363 }; 1364 1365 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1366 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1367 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1368 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1369 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1370 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1371 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1372 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1373 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1374 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1375 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1376 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1377 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1378 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1379 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1380 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1381 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1382 }; 1383 1384 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1385 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1386 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1387 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1388 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1389 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1390 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1391 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1392 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1393 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1394 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1395 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1396 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1397 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1398 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1399 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1400 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1401 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1402 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1403 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1404 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1405 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1406 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1407 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1408 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1409 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1410 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1411 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1412 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1413 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1414 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1415 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1416 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1417 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1418 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1419 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1420 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1421 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1422 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1423 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1424 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1425 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1435 }; 1436 1437 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1438 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1443 }; 1444 1445 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1446 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1447 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1448 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1451 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1452 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1453 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1454 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1455 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1456 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1457 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1458 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1459 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1460 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1461 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1462 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1463 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1464 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1465 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1466 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1467 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1468 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1469 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1470 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1471 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1472 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1473 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1474 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1475 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1476 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1477 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1478 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1479 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1480 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1481 }; 1482 1483 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1484 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1485 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1486 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1487 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89), 1488 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1489 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1490 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1491 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55), 1492 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a), 1493 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1494 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1495 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1496 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b), 1497 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), 1498 }; 1499 1500 static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = { 1501 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1502 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1503 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), 1504 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 1505 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 1506 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 1507 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), 1508 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), 1509 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), 1510 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), 1511 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 1512 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), 1513 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 1514 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 1515 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), 1516 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), 1517 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1518 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1519 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1520 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1521 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1522 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1523 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), 1524 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 1525 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 1526 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), 1527 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), 1528 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 1529 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), 1530 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), 1531 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), 1532 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 1533 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), 1534 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), 1535 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 1536 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), 1537 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 1538 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 1539 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), 1540 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), 1541 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), 1542 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), 1543 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), 1544 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 1545 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1546 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 1547 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 1548 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), 1549 }; 1550 1551 static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = { 1552 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), 1553 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), 1554 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1555 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1556 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), 1557 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), 1558 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31), 1559 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), 1560 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), 1561 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1), 1562 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2), 1563 }; 1564 1565 static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = { 1566 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a), 1567 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06), 1568 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1569 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1570 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1571 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1572 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), 1573 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), 1574 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), 1575 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), 1576 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), 1577 QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 1578 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), 1579 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), 1580 QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13), 1581 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1582 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1583 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1584 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1585 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1586 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1587 1588 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), 1589 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), 1590 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1591 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f), 1592 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), 1593 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), 1594 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), 1595 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), 1596 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), 1597 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), 1598 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), 1599 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), 1600 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), 1601 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), 1602 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1603 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), 1604 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), 1605 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), 1606 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), 1607 }; 1608 1609 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = { 1610 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1611 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), 1612 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), 1613 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), 1614 QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), 1615 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), 1616 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1617 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1618 QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), 1619 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1620 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1621 QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), 1622 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), 1623 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), 1624 }; 1625 1626 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = { 1627 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1628 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 1629 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), 1630 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00), 1631 }; 1632 1633 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1634 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1635 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1636 }; 1637 1638 /* list of regulators */ 1639 struct qmp_regulator_data { 1640 const char *name; 1641 unsigned int enable_load; 1642 }; 1643 1644 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1645 { .name = "vdda-phy", .enable_load = 21800 }, 1646 { .name = "vdda-pll", .enable_load = 36000 }, 1647 }; 1648 1649 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1650 { 0x00, 0x0c, 0x15, 0x1a }, 1651 { 0x02, 0x0e, 0x16, 0xff }, 1652 { 0x02, 0x11, 0xff, 0xff }, 1653 { 0x04, 0xff, 0xff, 0xff } 1654 }; 1655 1656 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1657 { 0x02, 0x12, 0x16, 0x1a }, 1658 { 0x09, 0x19, 0x1f, 0xff }, 1659 { 0x10, 0x1f, 0xff, 0xff }, 1660 { 0x1f, 0xff, 0xff, 0xff } 1661 }; 1662 1663 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1664 { 0x00, 0x0c, 0x14, 0x19 }, 1665 { 0x00, 0x0b, 0x12, 0xff }, 1666 { 0x00, 0x0b, 0xff, 0xff }, 1667 { 0x04, 0xff, 0xff, 0xff } 1668 }; 1669 1670 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1671 { 0x08, 0x0f, 0x16, 0x1f }, 1672 { 0x11, 0x1e, 0x1f, 0xff }, 1673 { 0x19, 0x1f, 0xff, 0xff }, 1674 { 0x1f, 0xff, 0xff, 0xff } 1675 }; 1676 1677 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1678 { 0x00, 0x0c, 0x15, 0x1b }, 1679 { 0x02, 0x0e, 0x16, 0xff }, 1680 { 0x02, 0x11, 0xff, 0xff }, 1681 { 0x04, 0xff, 0xff, 0xff } 1682 }; 1683 1684 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1685 { 0x00, 0x0d, 0x14, 0x1a }, 1686 { 0x00, 0x0e, 0x15, 0xff }, 1687 { 0x00, 0x0d, 0xff, 0xff }, 1688 { 0x03, 0xff, 0xff, 0xff } 1689 }; 1690 1691 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1692 { 0x08, 0x0f, 0x16, 0x1f }, 1693 { 0x11, 0x1e, 0x1f, 0xff }, 1694 { 0x16, 0x1f, 0xff, 0xff }, 1695 { 0x1f, 0xff, 0xff, 0xff } 1696 }; 1697 1698 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1699 { 0x20, 0x2c, 0x35, 0x3b }, 1700 { 0x22, 0x2e, 0x36, 0xff }, 1701 { 0x22, 0x31, 0xff, 0xff }, 1702 { 0x24, 0xff, 0xff, 0xff } 1703 }; 1704 1705 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1706 { 0x22, 0x32, 0x36, 0x3a }, 1707 { 0x29, 0x39, 0x3f, 0xff }, 1708 { 0x30, 0x3f, 0xff, 0xff }, 1709 { 0x3f, 0xff, 0xff, 0xff } 1710 }; 1711 1712 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1713 { 0x20, 0x2d, 0x34, 0x3a }, 1714 { 0x20, 0x2e, 0x35, 0xff }, 1715 { 0x20, 0x2e, 0xff, 0xff }, 1716 { 0x24, 0xff, 0xff, 0xff } 1717 }; 1718 1719 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1720 { 0x28, 0x2f, 0x36, 0x3f }, 1721 { 0x31, 0x3e, 0x3f, 0xff }, 1722 { 0x36, 0x3f, 0xff, 0xff }, 1723 { 0x3f, 0xff, 0xff, 0xff } 1724 }; 1725 1726 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = { 1727 { 0x27, 0x2f, 0x36, 0x3f }, 1728 { 0x31, 0x3e, 0x3f, 0xff }, 1729 { 0x36, 0x3f, 0xff, 0xff }, 1730 { 0x3f, 0xff, 0xff, 0xff } 1731 }; 1732 1733 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1734 { 0x20, 0x2d, 0x34, 0x3a }, 1735 { 0x20, 0x2e, 0x35, 0xff }, 1736 { 0x20, 0x2e, 0xff, 0xff }, 1737 { 0x22, 0xff, 0xff, 0xff } 1738 }; 1739 1740 struct qmp_combo; 1741 1742 struct qmp_combo_offsets { 1743 u16 com; 1744 u16 txa; 1745 u16 rxa; 1746 u16 txb; 1747 u16 rxb; 1748 u16 usb3_serdes; 1749 u16 usb3_pcs_misc; 1750 u16 usb3_pcs; 1751 u16 usb3_pcs_usb; 1752 u16 dp_serdes; 1753 u16 dp_txa; 1754 u16 dp_txb; 1755 u16 dp_dp_phy; 1756 }; 1757 1758 struct qmp_phy_cfg { 1759 const struct qmp_combo_offsets *offsets; 1760 1761 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1762 const struct qmp_phy_init_tbl *serdes_tbl; 1763 int serdes_tbl_num; 1764 const struct qmp_phy_init_tbl *tx_tbl; 1765 int tx_tbl_num; 1766 const struct qmp_phy_init_tbl *rx_tbl; 1767 int rx_tbl_num; 1768 const struct qmp_phy_init_tbl *pcs_tbl; 1769 int pcs_tbl_num; 1770 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1771 int pcs_usb_tbl_num; 1772 1773 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1774 int dp_serdes_tbl_num; 1775 const struct qmp_phy_init_tbl *dp_tx_tbl; 1776 int dp_tx_tbl_num; 1777 1778 /* Init sequence for DP PHY block link rates */ 1779 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1780 int serdes_tbl_rbr_num; 1781 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1782 int serdes_tbl_hbr_num; 1783 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1784 int serdes_tbl_hbr2_num; 1785 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1786 int serdes_tbl_hbr3_num; 1787 1788 /* DP PHY swing and pre_emphasis tables */ 1789 const u8 (*swing_hbr_rbr)[4][4]; 1790 const u8 (*swing_hbr3_hbr2)[4][4]; 1791 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1792 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1793 1794 /* DP PHY callbacks */ 1795 int (*configure_dp_phy)(struct qmp_combo *qmp); 1796 void (*configure_dp_tx)(struct qmp_combo *qmp); 1797 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1798 void (*dp_aux_init)(struct qmp_combo *qmp); 1799 1800 /* resets to be requested */ 1801 const char * const *reset_list; 1802 int num_resets; 1803 /* regulators to be requested */ 1804 const struct qmp_regulator_data *vreg_list; 1805 int num_vregs; 1806 1807 /* array of registers with different offsets */ 1808 const unsigned int *regs; 1809 1810 /* true, if PHY needs delay after POWER_DOWN */ 1811 bool has_pwrdn_delay; 1812 1813 /* Offset from PCS to PCS_USB region */ 1814 unsigned int pcs_usb_offset; 1815 1816 }; 1817 1818 struct qmp_combo { 1819 struct device *dev; 1820 1821 const struct qmp_phy_cfg *cfg; 1822 1823 void __iomem *com; 1824 1825 void __iomem *serdes; 1826 void __iomem *tx; 1827 void __iomem *rx; 1828 void __iomem *pcs; 1829 void __iomem *tx2; 1830 void __iomem *rx2; 1831 void __iomem *pcs_misc; 1832 void __iomem *pcs_usb; 1833 1834 void __iomem *dp_serdes; 1835 void __iomem *dp_tx; 1836 void __iomem *dp_tx2; 1837 void __iomem *dp_dp_phy; 1838 1839 struct clk *pipe_clk; 1840 struct clk_bulk_data *clks; 1841 int num_clks; 1842 struct reset_control_bulk_data *resets; 1843 struct regulator_bulk_data *vregs; 1844 1845 struct mutex phy_mutex; 1846 int init_count; 1847 1848 struct phy *usb_phy; 1849 enum phy_mode mode; 1850 unsigned int usb_init_count; 1851 1852 struct phy *dp_phy; 1853 unsigned int dp_aux_cfg; 1854 struct phy_configure_opts_dp dp_opts; 1855 unsigned int dp_init_count; 1856 1857 struct clk_fixed_rate pipe_clk_fixed; 1858 struct clk_hw dp_link_hw; 1859 struct clk_hw dp_pixel_hw; 1860 1861 struct typec_switch_dev *sw; 1862 enum typec_orientation orientation; 1863 }; 1864 1865 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1866 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1867 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1868 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1869 1870 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1871 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1872 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1873 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1874 1875 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1876 { 1877 u32 reg; 1878 1879 reg = readl(base + offset); 1880 reg |= val; 1881 writel(reg, base + offset); 1882 1883 /* ensure that above write is through */ 1884 readl(base + offset); 1885 } 1886 1887 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1888 { 1889 u32 reg; 1890 1891 reg = readl(base + offset); 1892 reg &= ~val; 1893 writel(reg, base + offset); 1894 1895 /* ensure that above write is through */ 1896 readl(base + offset); 1897 } 1898 1899 /* list of clocks required by phy */ 1900 static const char * const qmp_combo_phy_clk_l[] = { 1901 "aux", "cfg_ahb", "ref", "com_aux", 1902 }; 1903 1904 /* list of resets */ 1905 static const char * const msm8996_usb3phy_reset_l[] = { 1906 "phy", "common", 1907 }; 1908 1909 static const char * const sc7180_usb3phy_reset_l[] = { 1910 "phy", 1911 }; 1912 1913 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1914 .com = 0x0000, 1915 .txa = 0x1200, 1916 .rxa = 0x1400, 1917 .txb = 0x1600, 1918 .rxb = 0x1800, 1919 .usb3_serdes = 0x1000, 1920 .usb3_pcs_misc = 0x1a00, 1921 .usb3_pcs = 0x1c00, 1922 .usb3_pcs_usb = 0x1f00, 1923 .dp_serdes = 0x2000, 1924 .dp_txa = 0x2200, 1925 .dp_txb = 0x2600, 1926 .dp_dp_phy = 0x2a00, 1927 }; 1928 1929 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1930 .com = 0x0000, 1931 .txa = 0x0400, 1932 .rxa = 0x0600, 1933 .txb = 0x0a00, 1934 .rxb = 0x0c00, 1935 .usb3_serdes = 0x1000, 1936 .usb3_pcs_misc = 0x1200, 1937 .usb3_pcs = 0x1400, 1938 .usb3_pcs_usb = 0x1700, 1939 .dp_serdes = 0x2000, 1940 .dp_dp_phy = 0x2200, 1941 }; 1942 1943 static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { 1944 .com = 0x0000, 1945 .txa = 0x1400, 1946 .rxa = 0x1600, 1947 .txb = 0x1800, 1948 .rxb = 0x1a00, 1949 .usb3_serdes = 0x1000, 1950 .usb3_pcs_misc = 0x1c00, 1951 .usb3_pcs = 0x1e00, 1952 .usb3_pcs_usb = 0x2100, 1953 .dp_serdes = 0x3000, 1954 .dp_txa = 0x3400, 1955 .dp_txb = 0x3800, 1956 .dp_dp_phy = 0x3c00, 1957 }; 1958 1959 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { 1960 .offsets = &qmp_combo_offsets_v3, 1961 1962 .serdes_tbl = sar2130p_usb3_serdes_tbl, 1963 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 1964 .tx_tbl = sm8550_usb3_tx_tbl, 1965 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1966 .rx_tbl = sm8550_usb3_rx_tbl, 1967 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1968 .pcs_tbl = sm8550_usb3_pcs_tbl, 1969 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1970 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1971 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1972 1973 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1974 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1975 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1976 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1977 1978 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1979 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1980 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1981 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1982 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1983 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1984 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1985 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1986 1987 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1988 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1989 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1990 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1991 1992 .dp_aux_init = qmp_v4_dp_aux_init, 1993 .configure_dp_tx = qmp_v4_configure_dp_tx, 1994 .configure_dp_phy = qmp_v4_configure_dp_phy, 1995 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1996 1997 .regs = qmp_v6_usb3phy_regs_layout, 1998 .reset_list = msm8996_usb3phy_reset_l, 1999 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2000 .vreg_list = qmp_phy_vreg_l, 2001 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2002 }; 2003 2004 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 2005 .offsets = &qmp_combo_offsets_v3, 2006 2007 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2008 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2009 .tx_tbl = qmp_v3_usb3_tx_tbl, 2010 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2011 .rx_tbl = qmp_v3_usb3_rx_tbl, 2012 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2013 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2014 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2015 2016 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2017 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2018 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2019 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2020 2021 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2022 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2023 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2024 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2025 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2026 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2027 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2028 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2029 2030 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2031 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2032 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2033 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2034 2035 .dp_aux_init = qmp_v3_dp_aux_init, 2036 .configure_dp_tx = qmp_v3_configure_dp_tx, 2037 .configure_dp_phy = qmp_v3_configure_dp_phy, 2038 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2039 2040 .reset_list = sc7180_usb3phy_reset_l, 2041 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 2042 .vreg_list = qmp_phy_vreg_l, 2043 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2044 .regs = qmp_v3_usb3phy_regs_layout, 2045 2046 .has_pwrdn_delay = true, 2047 }; 2048 2049 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 2050 .offsets = &qmp_combo_offsets_v3, 2051 2052 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2053 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2054 .tx_tbl = qmp_v3_usb3_tx_tbl, 2055 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2056 .rx_tbl = qmp_v3_usb3_rx_tbl, 2057 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2058 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2059 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2060 2061 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2062 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2063 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2064 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2065 2066 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2067 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2068 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2069 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2070 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2071 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2072 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2073 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2074 2075 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2076 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2077 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2078 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2079 2080 .dp_aux_init = qmp_v3_dp_aux_init, 2081 .configure_dp_tx = qmp_v3_configure_dp_tx, 2082 .configure_dp_phy = qmp_v3_configure_dp_phy, 2083 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2084 2085 .reset_list = msm8996_usb3phy_reset_l, 2086 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2087 .vreg_list = qmp_phy_vreg_l, 2088 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2089 .regs = qmp_v3_usb3phy_regs_layout, 2090 2091 .has_pwrdn_delay = true, 2092 }; 2093 2094 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 2095 .offsets = &qmp_combo_offsets_v3, 2096 2097 .serdes_tbl = sm8150_usb3_serdes_tbl, 2098 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2099 .tx_tbl = sm8150_usb3_tx_tbl, 2100 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 2101 .rx_tbl = sm8150_usb3_rx_tbl, 2102 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 2103 .pcs_tbl = sm8150_usb3_pcs_tbl, 2104 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 2105 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 2106 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 2107 2108 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2109 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2110 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2111 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2112 2113 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2114 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2115 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2116 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2117 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2118 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2119 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2120 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2121 2122 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2123 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2124 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2125 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2126 2127 .dp_aux_init = qmp_v4_dp_aux_init, 2128 .configure_dp_tx = qmp_v4_configure_dp_tx, 2129 .configure_dp_phy = qmp_v4_configure_dp_phy, 2130 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2131 2132 .reset_list = msm8996_usb3phy_reset_l, 2133 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2134 .vreg_list = qmp_phy_vreg_l, 2135 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2136 .regs = qmp_v45_usb3phy_regs_layout, 2137 .pcs_usb_offset = 0x300, 2138 2139 .has_pwrdn_delay = true, 2140 }; 2141 2142 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 2143 .offsets = &qmp_combo_offsets_v5, 2144 2145 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 2146 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 2147 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 2148 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 2149 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 2150 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 2151 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 2152 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 2153 2154 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 2155 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 2156 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 2157 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 2158 2159 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2160 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2161 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2162 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2163 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2164 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2165 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2166 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2167 2168 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2169 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 2170 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2171 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2172 2173 .dp_aux_init = qmp_v4_dp_aux_init, 2174 .configure_dp_tx = qmp_v4_configure_dp_tx, 2175 .configure_dp_phy = qmp_v4_configure_dp_phy, 2176 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2177 2178 .reset_list = msm8996_usb3phy_reset_l, 2179 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2180 .vreg_list = qmp_phy_vreg_l, 2181 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2182 .regs = qmp_v5_5nm_usb3phy_regs_layout, 2183 }; 2184 2185 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 2186 .offsets = &qmp_combo_offsets_v5, 2187 2188 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 2189 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 2190 .tx_tbl = x1e80100_usb43dp_tx_tbl, 2191 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 2192 .rx_tbl = x1e80100_usb43dp_rx_tbl, 2193 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 2194 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 2195 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 2196 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 2197 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 2198 2199 .dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl, 2200 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl), 2201 .dp_tx_tbl = qmp_v6_n4_dp_tx_tbl, 2202 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl), 2203 2204 .serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr, 2205 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr), 2206 .serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr, 2207 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr), 2208 .serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2, 2209 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2), 2210 .serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3, 2211 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3), 2212 2213 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2214 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2215 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2216 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2217 2218 .dp_aux_init = qmp_v4_dp_aux_init, 2219 .configure_dp_tx = qmp_v4_configure_dp_tx, 2220 .configure_dp_phy = qmp_v4_configure_dp_phy, 2221 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2222 2223 .reset_list = msm8996_usb3phy_reset_l, 2224 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2225 .vreg_list = qmp_phy_vreg_l, 2226 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2227 .regs = qmp_v6_n4_usb3phy_regs_layout, 2228 }; 2229 2230 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 2231 .offsets = &qmp_combo_offsets_v3, 2232 2233 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2234 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2235 .tx_tbl = qmp_v3_usb3_tx_tbl, 2236 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2237 .rx_tbl = sm6350_usb3_rx_tbl, 2238 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 2239 .pcs_tbl = sm6350_usb3_pcs_tbl, 2240 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 2241 2242 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2243 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2244 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2245 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2246 2247 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2248 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2249 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2250 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2251 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2252 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2253 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2254 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2255 2256 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2257 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2258 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2259 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2260 2261 .dp_aux_init = qmp_v3_dp_aux_init, 2262 .configure_dp_tx = qmp_v3_configure_dp_tx, 2263 .configure_dp_phy = qmp_v3_configure_dp_phy, 2264 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2265 2266 .reset_list = msm8996_usb3phy_reset_l, 2267 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2268 .vreg_list = qmp_phy_vreg_l, 2269 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2270 .regs = qmp_v3_usb3phy_regs_layout, 2271 }; 2272 2273 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 2274 .offsets = &qmp_combo_offsets_v3, 2275 2276 .serdes_tbl = sm8150_usb3_serdes_tbl, 2277 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2278 .tx_tbl = sm8250_usb3_tx_tbl, 2279 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 2280 .rx_tbl = sm8250_usb3_rx_tbl, 2281 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 2282 .pcs_tbl = sm8250_usb3_pcs_tbl, 2283 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 2284 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 2285 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 2286 2287 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2288 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2289 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2290 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2291 2292 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2293 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2294 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2295 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2296 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2297 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2298 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2299 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2300 2301 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2302 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2303 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2304 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2305 2306 .dp_aux_init = qmp_v4_dp_aux_init, 2307 .configure_dp_tx = qmp_v4_configure_dp_tx, 2308 .configure_dp_phy = qmp_v4_configure_dp_phy, 2309 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2310 2311 .reset_list = msm8996_usb3phy_reset_l, 2312 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2313 .vreg_list = qmp_phy_vreg_l, 2314 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2315 .regs = qmp_v45_usb3phy_regs_layout, 2316 .pcs_usb_offset = 0x300, 2317 2318 .has_pwrdn_delay = true, 2319 }; 2320 2321 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 2322 .offsets = &qmp_combo_offsets_v3, 2323 2324 .serdes_tbl = sm8150_usb3_serdes_tbl, 2325 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2326 .tx_tbl = sm8350_usb3_tx_tbl, 2327 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 2328 .rx_tbl = sm8350_usb3_rx_tbl, 2329 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 2330 .pcs_tbl = sm8350_usb3_pcs_tbl, 2331 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 2332 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 2333 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 2334 2335 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2336 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2337 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 2338 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 2339 2340 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2341 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2342 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2343 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2344 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2345 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2346 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2347 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2348 2349 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 2350 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 2351 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2352 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 2353 2354 .dp_aux_init = qmp_v4_dp_aux_init, 2355 .configure_dp_tx = qmp_v4_configure_dp_tx, 2356 .configure_dp_phy = qmp_v4_configure_dp_phy, 2357 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2358 2359 .reset_list = msm8996_usb3phy_reset_l, 2360 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2361 .vreg_list = qmp_phy_vreg_l, 2362 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2363 .regs = qmp_v45_usb3phy_regs_layout, 2364 2365 .has_pwrdn_delay = true, 2366 }; 2367 2368 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 2369 .offsets = &qmp_combo_offsets_v3, 2370 2371 .serdes_tbl = sm8550_usb3_serdes_tbl, 2372 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2373 .tx_tbl = sm8550_usb3_tx_tbl, 2374 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2375 .rx_tbl = sm8550_usb3_rx_tbl, 2376 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2377 .pcs_tbl = sm8550_usb3_pcs_tbl, 2378 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2379 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2380 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2381 2382 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2383 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2384 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2385 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2386 2387 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2388 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2389 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2390 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2391 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2392 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2393 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2394 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2395 2396 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2397 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2398 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2399 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2400 2401 .dp_aux_init = qmp_v4_dp_aux_init, 2402 .configure_dp_tx = qmp_v4_configure_dp_tx, 2403 .configure_dp_phy = qmp_v4_configure_dp_phy, 2404 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2405 2406 .regs = qmp_v6_usb3phy_regs_layout, 2407 .reset_list = msm8996_usb3phy_reset_l, 2408 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2409 .vreg_list = qmp_phy_vreg_l, 2410 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2411 }; 2412 2413 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = { 2414 .offsets = &qmp_combo_offsets_v3, 2415 2416 .serdes_tbl = sm8550_usb3_serdes_tbl, 2417 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2418 .tx_tbl = sm8550_usb3_tx_tbl, 2419 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2420 .rx_tbl = sm8550_usb3_rx_tbl, 2421 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2422 .pcs_tbl = sm8550_usb3_pcs_tbl, 2423 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2424 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2425 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2426 2427 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2428 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2429 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2430 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2431 2432 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2433 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2434 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2435 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2436 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2437 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2438 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2439 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2440 2441 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2442 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2443 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2444 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2445 2446 .dp_aux_init = qmp_v4_dp_aux_init, 2447 .configure_dp_tx = qmp_v4_configure_dp_tx, 2448 .configure_dp_phy = qmp_v4_configure_dp_phy, 2449 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2450 2451 .regs = qmp_v6_usb3phy_regs_layout, 2452 .reset_list = msm8996_usb3phy_reset_l, 2453 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2454 .vreg_list = qmp_phy_vreg_l, 2455 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2456 }; 2457 2458 static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { 2459 .offsets = &qmp_combo_offsets_v8, 2460 2461 .serdes_tbl = sm8750_usb3_serdes_tbl, 2462 .serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl), 2463 .tx_tbl = sm8750_usb3_tx_tbl, 2464 .tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl), 2465 .rx_tbl = sm8750_usb3_rx_tbl, 2466 .rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl), 2467 .pcs_tbl = sm8750_usb3_pcs_tbl, 2468 .pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl), 2469 .pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl, 2470 .pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), 2471 2472 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2473 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2474 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2475 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2476 2477 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2478 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2479 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2480 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2481 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2482 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2483 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2484 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2485 2486 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2487 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2488 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2489 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2490 2491 .dp_aux_init = qmp_v4_dp_aux_init, 2492 .configure_dp_tx = qmp_v4_configure_dp_tx, 2493 .configure_dp_phy = qmp_v4_configure_dp_phy, 2494 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2495 2496 .regs = qmp_v8_usb3phy_regs_layout, 2497 .reset_list = msm8996_usb3phy_reset_l, 2498 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2499 .vreg_list = qmp_phy_vreg_l, 2500 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2501 }; 2502 2503 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 2504 { 2505 const struct qmp_phy_cfg *cfg = qmp->cfg; 2506 void __iomem *serdes = qmp->dp_serdes; 2507 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2508 2509 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 2510 cfg->dp_serdes_tbl_num); 2511 2512 switch (dp_opts->link_rate) { 2513 case 1620: 2514 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 2515 cfg->serdes_tbl_rbr_num); 2516 break; 2517 case 2700: 2518 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 2519 cfg->serdes_tbl_hbr_num); 2520 break; 2521 case 5400: 2522 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 2523 cfg->serdes_tbl_hbr2_num); 2524 break; 2525 case 8100: 2526 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, 2527 cfg->serdes_tbl_hbr3_num); 2528 break; 2529 default: 2530 /* Other link rates aren't supported */ 2531 return -EINVAL; 2532 } 2533 2534 return 0; 2535 } 2536 2537 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 2538 { 2539 const struct qmp_phy_cfg *cfg = qmp->cfg; 2540 2541 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2542 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2543 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2544 2545 /* Turn on BIAS current for PHY/PLL */ 2546 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 2547 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 2548 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2549 2550 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2551 2552 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2553 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 2554 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 2555 DP_PHY_PD_CTL_DP_CLAMP_EN, 2556 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2557 2558 writel(QSERDES_V3_COM_BIAS_EN | 2559 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 2560 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 2561 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 2562 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2563 2564 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2565 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2566 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2567 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2568 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2569 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2570 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2571 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2572 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2573 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2574 qmp->dp_aux_cfg = 0; 2575 2576 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2577 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2578 PHY_AUX_REQ_ERR_MASK, 2579 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 2580 } 2581 2582 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 2583 { 2584 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2585 const struct qmp_phy_cfg *cfg = qmp->cfg; 2586 unsigned int v_level = 0, p_level = 0; 2587 u8 voltage_swing_cfg, pre_emphasis_cfg; 2588 int i; 2589 2590 for (i = 0; i < dp_opts->lanes; i++) { 2591 v_level = max(v_level, dp_opts->voltage[i]); 2592 p_level = max(p_level, dp_opts->pre[i]); 2593 } 2594 2595 if (dp_opts->link_rate <= 2700) { 2596 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 2597 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 2598 } else { 2599 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 2600 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 2601 } 2602 2603 /* TODO: Move check to config check */ 2604 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2605 return -EINVAL; 2606 2607 /* Enable MUX to use Cursor values from these registers */ 2608 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2609 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2610 2611 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2612 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2613 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2614 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2615 2616 return 0; 2617 } 2618 2619 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2620 { 2621 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2622 u32 bias_en, drvr_en; 2623 2624 if (qmp_combo_configure_dp_swing(qmp) < 0) 2625 return; 2626 2627 if (dp_opts->lanes == 1) { 2628 bias_en = 0x3e; 2629 drvr_en = 0x13; 2630 } else { 2631 bias_en = 0x3f; 2632 drvr_en = 0x10; 2633 } 2634 2635 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2636 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2637 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2638 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2639 } 2640 2641 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2642 { 2643 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2644 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2645 u32 val; 2646 2647 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2648 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2649 2650 if (dp_opts->lanes == 4 || reverse) 2651 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2652 if (dp_opts->lanes == 4 || !reverse) 2653 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2654 2655 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2656 2657 if (reverse) 2658 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2659 else 2660 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2661 2662 return reverse; 2663 } 2664 2665 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2666 { 2667 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2668 u32 phy_vco_div; 2669 unsigned long pixel_freq; 2670 const struct qmp_phy_cfg *cfg = qmp->cfg; 2671 2672 switch (dp_opts->link_rate) { 2673 case 1620: 2674 phy_vco_div = 0x1; 2675 pixel_freq = 1620000000UL / 2; 2676 break; 2677 case 2700: 2678 phy_vco_div = 0x1; 2679 pixel_freq = 2700000000UL / 2; 2680 break; 2681 case 5400: 2682 phy_vco_div = 0x2; 2683 pixel_freq = 5400000000UL / 4; 2684 break; 2685 case 8100: 2686 phy_vco_div = 0x0; 2687 pixel_freq = 8100000000UL / 6; 2688 break; 2689 default: 2690 /* Other link rates aren't supported */ 2691 return -EINVAL; 2692 } 2693 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 2694 2695 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2696 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2697 2698 return 0; 2699 } 2700 2701 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2702 { 2703 const struct qmp_phy_cfg *cfg = qmp->cfg; 2704 u32 status; 2705 int ret; 2706 2707 qmp_combo_configure_dp_mode(qmp); 2708 2709 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2710 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2711 2712 ret = qmp_combo_configure_dp_clocks(qmp); 2713 if (ret) 2714 return ret; 2715 2716 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2717 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2718 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2719 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2720 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2721 2722 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2723 2724 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2725 status, 2726 ((status & BIT(0)) > 0), 2727 500, 2728 10000)) 2729 return -ETIMEDOUT; 2730 2731 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2732 2733 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2734 status, 2735 ((status & BIT(1)) > 0), 2736 500, 2737 10000)) 2738 return -ETIMEDOUT; 2739 2740 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2741 udelay(2000); 2742 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2743 2744 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2745 status, 2746 ((status & BIT(1)) > 0), 2747 500, 2748 10000); 2749 } 2750 2751 /* 2752 * We need to calibrate the aux setting here as many times 2753 * as the caller tries 2754 */ 2755 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2756 { 2757 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2758 u8 val; 2759 2760 qmp->dp_aux_cfg++; 2761 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2762 val = cfg1_settings[qmp->dp_aux_cfg]; 2763 2764 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2765 2766 return 0; 2767 } 2768 2769 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2770 { 2771 const struct qmp_phy_cfg *cfg = qmp->cfg; 2772 2773 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2774 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2775 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2776 2777 /* Turn on BIAS current for PHY/PLL */ 2778 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2779 2780 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2781 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2782 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2783 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2784 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2785 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2786 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2787 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2788 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2789 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2790 qmp->dp_aux_cfg = 0; 2791 2792 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2793 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2794 PHY_AUX_REQ_ERR_MASK, 2795 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2796 } 2797 2798 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2799 { 2800 const struct qmp_phy_cfg *cfg = qmp->cfg; 2801 2802 /* Program default values before writing proper values */ 2803 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2804 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2805 2806 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2807 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2808 2809 qmp_combo_configure_dp_swing(qmp); 2810 } 2811 2812 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2813 { 2814 const struct qmp_phy_cfg *cfg = qmp->cfg; 2815 u32 status; 2816 int ret; 2817 2818 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 2819 2820 qmp_combo_configure_dp_mode(qmp); 2821 2822 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2823 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2824 2825 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2826 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2827 2828 ret = qmp_combo_configure_dp_clocks(qmp); 2829 if (ret) 2830 return ret; 2831 2832 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2833 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2834 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2835 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2836 2837 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2838 2839 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2840 status, 2841 ((status & BIT(0)) > 0), 2842 500, 2843 10000)) 2844 return -ETIMEDOUT; 2845 2846 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2847 status, 2848 ((status & BIT(0)) > 0), 2849 500, 2850 10000)) 2851 return -ETIMEDOUT; 2852 2853 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2854 status, 2855 ((status & BIT(1)) > 0), 2856 500, 2857 10000)) 2858 return -ETIMEDOUT; 2859 2860 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2861 2862 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2863 status, 2864 ((status & BIT(0)) > 0), 2865 500, 2866 10000)) 2867 return -ETIMEDOUT; 2868 2869 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2870 status, 2871 ((status & BIT(1)) > 0), 2872 500, 2873 10000)) 2874 return -ETIMEDOUT; 2875 2876 return 0; 2877 } 2878 2879 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2880 { 2881 const struct qmp_phy_cfg *cfg = qmp->cfg; 2882 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2883 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2884 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2885 u32 status; 2886 int ret; 2887 2888 ret = qmp_v456_configure_dp_phy(qmp); 2889 if (ret < 0) 2890 return ret; 2891 2892 /* 2893 * At least for 7nm DP PHY this has to be done after enabling link 2894 * clock. 2895 */ 2896 2897 if (dp_opts->lanes == 1) { 2898 bias0_en = reverse ? 0x3e : 0x15; 2899 bias1_en = reverse ? 0x15 : 0x3e; 2900 drvr0_en = reverse ? 0x13 : 0x10; 2901 drvr1_en = reverse ? 0x10 : 0x13; 2902 } else if (dp_opts->lanes == 2) { 2903 bias0_en = reverse ? 0x3f : 0x15; 2904 bias1_en = reverse ? 0x15 : 0x3f; 2905 drvr0_en = 0x10; 2906 drvr1_en = 0x10; 2907 } else { 2908 bias0_en = 0x3f; 2909 bias1_en = 0x3f; 2910 drvr0_en = 0x10; 2911 drvr1_en = 0x10; 2912 } 2913 2914 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2915 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2916 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2917 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2918 2919 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2920 udelay(2000); 2921 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2922 2923 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2924 status, 2925 ((status & BIT(1)) > 0), 2926 500, 2927 10000)) 2928 return -ETIMEDOUT; 2929 2930 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2931 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2932 2933 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2934 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2935 2936 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2937 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2938 2939 return 0; 2940 } 2941 2942 /* 2943 * We need to calibrate the aux setting here as many times 2944 * as the caller tries 2945 */ 2946 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2947 { 2948 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2949 u8 val; 2950 2951 qmp->dp_aux_cfg++; 2952 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2953 val = cfg1_settings[qmp->dp_aux_cfg]; 2954 2955 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2956 2957 return 0; 2958 } 2959 2960 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2961 { 2962 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2963 struct qmp_combo *qmp = phy_get_drvdata(phy); 2964 const struct qmp_phy_cfg *cfg = qmp->cfg; 2965 2966 mutex_lock(&qmp->phy_mutex); 2967 2968 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2969 if (qmp->dp_opts.set_voltages) { 2970 cfg->configure_dp_tx(qmp); 2971 qmp->dp_opts.set_voltages = 0; 2972 } 2973 2974 mutex_unlock(&qmp->phy_mutex); 2975 2976 return 0; 2977 } 2978 2979 static int qmp_combo_dp_calibrate(struct phy *phy) 2980 { 2981 struct qmp_combo *qmp = phy_get_drvdata(phy); 2982 const struct qmp_phy_cfg *cfg = qmp->cfg; 2983 int ret = 0; 2984 2985 mutex_lock(&qmp->phy_mutex); 2986 2987 if (cfg->calibrate_dp_phy) 2988 ret = cfg->calibrate_dp_phy(qmp); 2989 2990 mutex_unlock(&qmp->phy_mutex); 2991 2992 return ret; 2993 } 2994 2995 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2996 { 2997 const struct qmp_phy_cfg *cfg = qmp->cfg; 2998 void __iomem *com = qmp->com; 2999 int ret; 3000 u32 val; 3001 3002 if (!force && qmp->init_count++) 3003 return 0; 3004 3005 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 3006 if (ret) { 3007 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 3008 goto err_decrement_count; 3009 } 3010 3011 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3012 if (ret) { 3013 dev_err(qmp->dev, "reset assert failed\n"); 3014 goto err_disable_regulators; 3015 } 3016 3017 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 3018 if (ret) { 3019 dev_err(qmp->dev, "reset deassert failed\n"); 3020 goto err_disable_regulators; 3021 } 3022 3023 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 3024 if (ret) 3025 goto err_assert_reset; 3026 3027 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 3028 3029 /* override hardware control for reset of qmp phy */ 3030 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3031 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3032 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3033 3034 /* Use software based port select and switch on typec orientation */ 3035 val = SW_PORTSELECT_MUX; 3036 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 3037 val |= SW_PORTSELECT_VAL; 3038 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 3039 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3040 3041 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 3042 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3043 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3044 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3045 3046 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 3047 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 3048 3049 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3050 SW_PWRDN); 3051 3052 return 0; 3053 3054 err_assert_reset: 3055 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3056 err_disable_regulators: 3057 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3058 err_decrement_count: 3059 qmp->init_count--; 3060 3061 return ret; 3062 } 3063 3064 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 3065 { 3066 const struct qmp_phy_cfg *cfg = qmp->cfg; 3067 3068 if (!force && --qmp->init_count) 3069 return 0; 3070 3071 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3072 3073 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3074 3075 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3076 3077 return 0; 3078 } 3079 3080 static int qmp_combo_dp_init(struct phy *phy) 3081 { 3082 struct qmp_combo *qmp = phy_get_drvdata(phy); 3083 const struct qmp_phy_cfg *cfg = qmp->cfg; 3084 int ret; 3085 3086 mutex_lock(&qmp->phy_mutex); 3087 3088 ret = qmp_combo_com_init(qmp, false); 3089 if (ret) 3090 goto out_unlock; 3091 3092 cfg->dp_aux_init(qmp); 3093 3094 qmp->dp_init_count++; 3095 3096 out_unlock: 3097 mutex_unlock(&qmp->phy_mutex); 3098 return ret; 3099 } 3100 3101 static int qmp_combo_dp_exit(struct phy *phy) 3102 { 3103 struct qmp_combo *qmp = phy_get_drvdata(phy); 3104 3105 mutex_lock(&qmp->phy_mutex); 3106 3107 qmp_combo_com_exit(qmp, false); 3108 3109 qmp->dp_init_count--; 3110 3111 mutex_unlock(&qmp->phy_mutex); 3112 3113 return 0; 3114 } 3115 3116 static int qmp_combo_dp_power_on(struct phy *phy) 3117 { 3118 struct qmp_combo *qmp = phy_get_drvdata(phy); 3119 const struct qmp_phy_cfg *cfg = qmp->cfg; 3120 void __iomem *tx = qmp->dp_tx; 3121 void __iomem *tx2 = qmp->dp_tx2; 3122 3123 mutex_lock(&qmp->phy_mutex); 3124 3125 qmp_combo_dp_serdes_init(qmp); 3126 3127 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 3128 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 3129 3130 /* Configure special DP tx tunings */ 3131 cfg->configure_dp_tx(qmp); 3132 3133 /* Configure link rate, swing, etc. */ 3134 cfg->configure_dp_phy(qmp); 3135 3136 mutex_unlock(&qmp->phy_mutex); 3137 3138 return 0; 3139 } 3140 3141 static int qmp_combo_dp_power_off(struct phy *phy) 3142 { 3143 struct qmp_combo *qmp = phy_get_drvdata(phy); 3144 3145 mutex_lock(&qmp->phy_mutex); 3146 3147 /* Assert DP PHY power down */ 3148 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3149 3150 mutex_unlock(&qmp->phy_mutex); 3151 3152 return 0; 3153 } 3154 3155 static int qmp_combo_usb_power_on(struct phy *phy) 3156 { 3157 struct qmp_combo *qmp = phy_get_drvdata(phy); 3158 const struct qmp_phy_cfg *cfg = qmp->cfg; 3159 void __iomem *serdes = qmp->serdes; 3160 void __iomem *tx = qmp->tx; 3161 void __iomem *rx = qmp->rx; 3162 void __iomem *tx2 = qmp->tx2; 3163 void __iomem *rx2 = qmp->rx2; 3164 void __iomem *pcs = qmp->pcs; 3165 void __iomem *pcs_usb = qmp->pcs_usb; 3166 void __iomem *status; 3167 unsigned int val; 3168 int ret; 3169 3170 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 3171 3172 ret = clk_prepare_enable(qmp->pipe_clk); 3173 if (ret) { 3174 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 3175 return ret; 3176 } 3177 3178 /* Tx, Rx, and PCS configurations */ 3179 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 3180 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 3181 3182 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 3183 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 3184 3185 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 3186 3187 if (pcs_usb) 3188 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, 3189 cfg->pcs_usb_tbl_num); 3190 3191 if (cfg->has_pwrdn_delay) 3192 usleep_range(10, 20); 3193 3194 /* Pull PHY out of reset state */ 3195 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3196 3197 /* start SerDes and Phy-Coding-Sublayer */ 3198 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 3199 3200 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 3201 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 3202 PHY_INIT_COMPLETE_TIMEOUT); 3203 if (ret) { 3204 dev_err(qmp->dev, "phy initialization timed-out\n"); 3205 goto err_disable_pipe_clk; 3206 } 3207 3208 return 0; 3209 3210 err_disable_pipe_clk: 3211 clk_disable_unprepare(qmp->pipe_clk); 3212 3213 return ret; 3214 } 3215 3216 static int qmp_combo_usb_power_off(struct phy *phy) 3217 { 3218 struct qmp_combo *qmp = phy_get_drvdata(phy); 3219 const struct qmp_phy_cfg *cfg = qmp->cfg; 3220 3221 clk_disable_unprepare(qmp->pipe_clk); 3222 3223 /* PHY reset */ 3224 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3225 3226 /* stop SerDes and Phy-Coding-Sublayer */ 3227 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 3228 SERDES_START | PCS_START); 3229 3230 /* Put PHY into POWER DOWN state: active low */ 3231 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3232 SW_PWRDN); 3233 3234 return 0; 3235 } 3236 3237 static int qmp_combo_usb_init(struct phy *phy) 3238 { 3239 struct qmp_combo *qmp = phy_get_drvdata(phy); 3240 int ret; 3241 3242 mutex_lock(&qmp->phy_mutex); 3243 ret = qmp_combo_com_init(qmp, false); 3244 if (ret) 3245 goto out_unlock; 3246 3247 ret = qmp_combo_usb_power_on(phy); 3248 if (ret) { 3249 qmp_combo_com_exit(qmp, false); 3250 goto out_unlock; 3251 } 3252 3253 qmp->usb_init_count++; 3254 3255 out_unlock: 3256 mutex_unlock(&qmp->phy_mutex); 3257 return ret; 3258 } 3259 3260 static int qmp_combo_usb_exit(struct phy *phy) 3261 { 3262 struct qmp_combo *qmp = phy_get_drvdata(phy); 3263 int ret; 3264 3265 mutex_lock(&qmp->phy_mutex); 3266 ret = qmp_combo_usb_power_off(phy); 3267 if (ret) 3268 goto out_unlock; 3269 3270 ret = qmp_combo_com_exit(qmp, false); 3271 if (ret) 3272 goto out_unlock; 3273 3274 qmp->usb_init_count--; 3275 3276 out_unlock: 3277 mutex_unlock(&qmp->phy_mutex); 3278 return ret; 3279 } 3280 3281 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 3282 { 3283 struct qmp_combo *qmp = phy_get_drvdata(phy); 3284 3285 qmp->mode = mode; 3286 3287 return 0; 3288 } 3289 3290 static const struct phy_ops qmp_combo_usb_phy_ops = { 3291 .init = qmp_combo_usb_init, 3292 .exit = qmp_combo_usb_exit, 3293 .set_mode = qmp_combo_usb_set_mode, 3294 .owner = THIS_MODULE, 3295 }; 3296 3297 static const struct phy_ops qmp_combo_dp_phy_ops = { 3298 .init = qmp_combo_dp_init, 3299 .configure = qmp_combo_dp_configure, 3300 .power_on = qmp_combo_dp_power_on, 3301 .calibrate = qmp_combo_dp_calibrate, 3302 .power_off = qmp_combo_dp_power_off, 3303 .exit = qmp_combo_dp_exit, 3304 .owner = THIS_MODULE, 3305 }; 3306 3307 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 3308 { 3309 const struct qmp_phy_cfg *cfg = qmp->cfg; 3310 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 3311 void __iomem *pcs_misc = qmp->pcs_misc; 3312 u32 intr_mask; 3313 3314 if (qmp->mode == PHY_MODE_USB_HOST_SS || 3315 qmp->mode == PHY_MODE_USB_DEVICE_SS) 3316 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 3317 else 3318 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 3319 3320 /* Clear any pending interrupts status */ 3321 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3322 /* Writing 1 followed by 0 clears the interrupt */ 3323 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3324 3325 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3326 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 3327 3328 /* Enable required PHY autonomous mode interrupts */ 3329 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 3330 3331 /* Enable i/o clamp_n for autonomous mode */ 3332 if (pcs_misc) 3333 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3334 } 3335 3336 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 3337 { 3338 const struct qmp_phy_cfg *cfg = qmp->cfg; 3339 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 3340 void __iomem *pcs_misc = qmp->pcs_misc; 3341 3342 /* Disable i/o clamp_n on resume for normal mode */ 3343 if (pcs_misc) 3344 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3345 3346 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3347 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 3348 3349 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3350 /* Writing 1 followed by 0 clears the interrupt */ 3351 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3352 } 3353 3354 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 3355 { 3356 struct qmp_combo *qmp = dev_get_drvdata(dev); 3357 3358 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 3359 3360 if (!qmp->init_count) { 3361 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3362 return 0; 3363 } 3364 3365 qmp_combo_enable_autonomous_mode(qmp); 3366 3367 clk_disable_unprepare(qmp->pipe_clk); 3368 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3369 3370 return 0; 3371 } 3372 3373 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 3374 { 3375 struct qmp_combo *qmp = dev_get_drvdata(dev); 3376 int ret = 0; 3377 3378 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 3379 3380 if (!qmp->init_count) { 3381 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3382 return 0; 3383 } 3384 3385 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 3386 if (ret) 3387 return ret; 3388 3389 ret = clk_prepare_enable(qmp->pipe_clk); 3390 if (ret) { 3391 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 3392 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3393 return ret; 3394 } 3395 3396 qmp_combo_disable_autonomous_mode(qmp); 3397 3398 return 0; 3399 } 3400 3401 static const struct dev_pm_ops qmp_combo_pm_ops = { 3402 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 3403 qmp_combo_runtime_resume, NULL) 3404 }; 3405 3406 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 3407 { 3408 const struct qmp_phy_cfg *cfg = qmp->cfg; 3409 struct device *dev = qmp->dev; 3410 int num = cfg->num_vregs; 3411 int ret, i; 3412 3413 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 3414 if (!qmp->vregs) 3415 return -ENOMEM; 3416 3417 for (i = 0; i < num; i++) 3418 qmp->vregs[i].supply = cfg->vreg_list[i].name; 3419 3420 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 3421 if (ret) { 3422 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 3423 return ret; 3424 } 3425 3426 for (i = 0; i < num; i++) { 3427 ret = regulator_set_load(qmp->vregs[i].consumer, 3428 cfg->vreg_list[i].enable_load); 3429 if (ret) { 3430 dev_err(dev, "failed to set load at %s\n", 3431 qmp->vregs[i].supply); 3432 return ret; 3433 } 3434 } 3435 3436 return 0; 3437 } 3438 3439 static int qmp_combo_reset_init(struct qmp_combo *qmp) 3440 { 3441 const struct qmp_phy_cfg *cfg = qmp->cfg; 3442 struct device *dev = qmp->dev; 3443 int i; 3444 int ret; 3445 3446 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 3447 sizeof(*qmp->resets), GFP_KERNEL); 3448 if (!qmp->resets) 3449 return -ENOMEM; 3450 3451 for (i = 0; i < cfg->num_resets; i++) 3452 qmp->resets[i].id = cfg->reset_list[i]; 3453 3454 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 3455 if (ret) 3456 return dev_err_probe(dev, ret, "failed to get resets\n"); 3457 3458 return 0; 3459 } 3460 3461 static int qmp_combo_clk_init(struct qmp_combo *qmp) 3462 { 3463 struct device *dev = qmp->dev; 3464 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 3465 int i; 3466 3467 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3468 if (!qmp->clks) 3469 return -ENOMEM; 3470 3471 for (i = 0; i < num; i++) 3472 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 3473 3474 qmp->num_clks = num; 3475 3476 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 3477 } 3478 3479 static void phy_clk_release_provider(void *res) 3480 { 3481 of_clk_del_provider(res); 3482 } 3483 3484 /* 3485 * Register a fixed rate pipe clock. 3486 * 3487 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3488 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3489 * by the PHY driver for its operations. 3490 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3491 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3492 * Below picture shows this relationship. 3493 * 3494 * +---------------+ 3495 * | PHY block |<<---------------------------------------+ 3496 * | | | 3497 * | +-------+ | +-----+ | 3498 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3499 * clk | +-------+ | +-----+ 3500 * +---------------+ 3501 */ 3502 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 3503 { 3504 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3505 struct clk_init_data init = { }; 3506 char name[64]; 3507 3508 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 3509 init.name = name; 3510 init.ops = &clk_fixed_rate_ops; 3511 3512 /* controllers using QMP phys use 125MHz pipe clock interface */ 3513 fixed->fixed_rate = 125000000; 3514 fixed->hw.init = &init; 3515 3516 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3517 } 3518 3519 /* 3520 * Display Port PLL driver block diagram for branch clocks 3521 * 3522 * +------------------------------+ 3523 * | DP_VCO_CLK | 3524 * | | 3525 * | +-------------------+ | 3526 * | | (DP PLL/VCO) | | 3527 * | +---------+---------+ | 3528 * | v | 3529 * | +----------+-----------+ | 3530 * | | hsclk_divsel_clk_src | | 3531 * | +----------+-----------+ | 3532 * +------------------------------+ 3533 * | 3534 * +---------<---------v------------>----------+ 3535 * | | 3536 * +--------v----------------+ | 3537 * | dp_phy_pll_link_clk | | 3538 * | link_clk | | 3539 * +--------+----------------+ | 3540 * | | 3541 * | | 3542 * v v 3543 * Input to DISPCC block | 3544 * for link clk, crypto clk | 3545 * and interface clock | 3546 * | 3547 * | 3548 * +--------<------------+-----------------+---<---+ 3549 * | | | 3550 * +----v---------+ +--------v-----+ +--------v------+ 3551 * | vco_divided | | vco_divided | | vco_divided | 3552 * | _clk_src | | _clk_src | | _clk_src | 3553 * | | | | | | 3554 * |divsel_six | | divsel_two | | divsel_four | 3555 * +-------+------+ +-----+--------+ +--------+------+ 3556 * | | | 3557 * v---->----------v-------------<------v 3558 * | 3559 * +----------+-----------------+ 3560 * | dp_phy_pll_vco_div_clk | 3561 * +---------+------------------+ 3562 * | 3563 * v 3564 * Input to DISPCC block 3565 * for DP pixel clock 3566 * 3567 */ 3568 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3569 { 3570 switch (req->rate) { 3571 case 1620000000UL / 2: 3572 case 2700000000UL / 2: 3573 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3574 return 0; 3575 default: 3576 return -EINVAL; 3577 } 3578 } 3579 3580 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3581 { 3582 const struct qmp_combo *qmp; 3583 const struct phy_configure_opts_dp *dp_opts; 3584 3585 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 3586 dp_opts = &qmp->dp_opts; 3587 3588 switch (dp_opts->link_rate) { 3589 case 1620: 3590 return 1620000000UL / 2; 3591 case 2700: 3592 return 2700000000UL / 2; 3593 case 5400: 3594 return 5400000000UL / 4; 3595 case 8100: 3596 return 8100000000UL / 6; 3597 default: 3598 return 0; 3599 } 3600 } 3601 3602 static const struct clk_ops qmp_dp_pixel_clk_ops = { 3603 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3604 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3605 }; 3606 3607 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3608 { 3609 switch (req->rate) { 3610 case 162000000: 3611 case 270000000: 3612 case 540000000: 3613 case 810000000: 3614 return 0; 3615 default: 3616 return -EINVAL; 3617 } 3618 } 3619 3620 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3621 { 3622 const struct qmp_combo *qmp; 3623 const struct phy_configure_opts_dp *dp_opts; 3624 3625 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3626 dp_opts = &qmp->dp_opts; 3627 3628 switch (dp_opts->link_rate) { 3629 case 1620: 3630 case 2700: 3631 case 5400: 3632 case 8100: 3633 return dp_opts->link_rate * 100000; 3634 default: 3635 return 0; 3636 } 3637 } 3638 3639 static const struct clk_ops qmp_dp_link_clk_ops = { 3640 .determine_rate = qmp_dp_link_clk_determine_rate, 3641 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3642 }; 3643 3644 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3645 { 3646 struct qmp_combo *qmp = data; 3647 unsigned int idx = clkspec->args[0]; 3648 3649 if (idx >= 2) { 3650 pr_err("%s: invalid index %u\n", __func__, idx); 3651 return ERR_PTR(-EINVAL); 3652 } 3653 3654 if (idx == 0) 3655 return &qmp->dp_link_hw; 3656 3657 return &qmp->dp_pixel_hw; 3658 } 3659 3660 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3661 { 3662 struct clk_init_data init = { }; 3663 char name[64]; 3664 int ret; 3665 3666 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3667 init.ops = &qmp_dp_link_clk_ops; 3668 init.name = name; 3669 qmp->dp_link_hw.init = &init; 3670 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3671 if (ret) 3672 return ret; 3673 3674 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3675 init.ops = &qmp_dp_pixel_clk_ops; 3676 init.name = name; 3677 qmp->dp_pixel_hw.init = &init; 3678 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3679 if (ret) 3680 return ret; 3681 3682 return 0; 3683 } 3684 3685 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3686 { 3687 struct qmp_combo *qmp = data; 3688 3689 switch (clkspec->args[0]) { 3690 case QMP_USB43DP_USB3_PIPE_CLK: 3691 return &qmp->pipe_clk_fixed.hw; 3692 case QMP_USB43DP_DP_LINK_CLK: 3693 return &qmp->dp_link_hw; 3694 case QMP_USB43DP_DP_VCO_DIV_CLK: 3695 return &qmp->dp_pixel_hw; 3696 } 3697 3698 return ERR_PTR(-EINVAL); 3699 } 3700 3701 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3702 struct device_node *dp_np) 3703 { 3704 int ret; 3705 3706 ret = phy_pipe_clk_register(qmp, usb_np); 3707 if (ret) 3708 return ret; 3709 3710 ret = phy_dp_clks_register(qmp, dp_np); 3711 if (ret) 3712 return ret; 3713 3714 /* 3715 * Register a single provider for bindings without child nodes. 3716 */ 3717 if (usb_np == qmp->dev->of_node) 3718 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3719 3720 /* 3721 * Register multiple providers for legacy bindings with child nodes. 3722 */ 3723 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3724 &qmp->pipe_clk_fixed.hw); 3725 if (ret) 3726 return ret; 3727 3728 /* 3729 * Roll a devm action because the clock provider is the child node, but 3730 * the child node is not actually a device. 3731 */ 3732 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3733 if (ret) 3734 return ret; 3735 3736 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3737 if (ret) 3738 return ret; 3739 3740 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3741 } 3742 3743 #if IS_ENABLED(CONFIG_TYPEC) 3744 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3745 enum typec_orientation orientation) 3746 { 3747 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3748 const struct qmp_phy_cfg *cfg = qmp->cfg; 3749 3750 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3751 return 0; 3752 3753 mutex_lock(&qmp->phy_mutex); 3754 qmp->orientation = orientation; 3755 3756 if (qmp->init_count) { 3757 if (qmp->usb_init_count) 3758 qmp_combo_usb_power_off(qmp->usb_phy); 3759 qmp_combo_com_exit(qmp, true); 3760 3761 qmp_combo_com_init(qmp, true); 3762 if (qmp->usb_init_count) 3763 qmp_combo_usb_power_on(qmp->usb_phy); 3764 if (qmp->dp_init_count) 3765 cfg->dp_aux_init(qmp); 3766 } 3767 mutex_unlock(&qmp->phy_mutex); 3768 3769 return 0; 3770 } 3771 3772 static void qmp_combo_typec_unregister(void *data) 3773 { 3774 struct qmp_combo *qmp = data; 3775 3776 typec_switch_unregister(qmp->sw); 3777 } 3778 3779 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3780 { 3781 struct typec_switch_desc sw_desc = {}; 3782 struct device *dev = qmp->dev; 3783 3784 sw_desc.drvdata = qmp; 3785 sw_desc.fwnode = dev->fwnode; 3786 sw_desc.set = qmp_combo_typec_switch_set; 3787 qmp->sw = typec_switch_register(dev, &sw_desc); 3788 if (IS_ERR(qmp->sw)) { 3789 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3790 return PTR_ERR(qmp->sw); 3791 } 3792 3793 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3794 } 3795 #else 3796 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3797 { 3798 return 0; 3799 } 3800 #endif 3801 3802 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np) 3803 { 3804 struct device *dev = qmp->dev; 3805 3806 /* 3807 * Get memory resources from the DP child node: 3808 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3809 * tx2 -> 3; rx2 -> 4 3810 * 3811 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3812 * implementation. 3813 */ 3814 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3815 if (IS_ERR(qmp->dp_tx)) 3816 return PTR_ERR(qmp->dp_tx); 3817 3818 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3819 if (IS_ERR(qmp->dp_dp_phy)) 3820 return PTR_ERR(qmp->dp_dp_phy); 3821 3822 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3823 if (IS_ERR(qmp->dp_tx2)) 3824 return PTR_ERR(qmp->dp_tx2); 3825 3826 return 0; 3827 } 3828 3829 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np) 3830 { 3831 const struct qmp_phy_cfg *cfg = qmp->cfg; 3832 struct device *dev = qmp->dev; 3833 3834 /* 3835 * Get memory resources from the USB child node: 3836 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3837 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3838 */ 3839 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3840 if (IS_ERR(qmp->tx)) 3841 return PTR_ERR(qmp->tx); 3842 3843 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3844 if (IS_ERR(qmp->rx)) 3845 return PTR_ERR(qmp->rx); 3846 3847 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3848 if (IS_ERR(qmp->pcs)) 3849 return PTR_ERR(qmp->pcs); 3850 3851 if (cfg->pcs_usb_offset) 3852 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3853 3854 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3855 if (IS_ERR(qmp->tx2)) 3856 return PTR_ERR(qmp->tx2); 3857 3858 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3859 if (IS_ERR(qmp->rx2)) 3860 return PTR_ERR(qmp->rx2); 3861 3862 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3863 if (IS_ERR(qmp->pcs_misc)) { 3864 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3865 qmp->pcs_misc = NULL; 3866 } 3867 3868 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3869 if (IS_ERR(qmp->pipe_clk)) { 3870 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3871 "failed to get pipe clock\n"); 3872 } 3873 3874 return 0; 3875 } 3876 3877 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3878 struct device_node *dp_np) 3879 { 3880 struct platform_device *pdev = to_platform_device(qmp->dev); 3881 int ret; 3882 3883 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3884 if (IS_ERR(qmp->serdes)) 3885 return PTR_ERR(qmp->serdes); 3886 3887 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3888 if (IS_ERR(qmp->com)) 3889 return PTR_ERR(qmp->com); 3890 3891 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3892 if (IS_ERR(qmp->dp_serdes)) 3893 return PTR_ERR(qmp->dp_serdes); 3894 3895 ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np); 3896 if (ret) 3897 return ret; 3898 3899 ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np); 3900 if (ret) 3901 return ret; 3902 3903 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3904 if (ret < 0) 3905 return ret; 3906 3907 qmp->num_clks = ret; 3908 3909 return 0; 3910 } 3911 3912 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3913 { 3914 struct platform_device *pdev = to_platform_device(qmp->dev); 3915 const struct qmp_phy_cfg *cfg = qmp->cfg; 3916 const struct qmp_combo_offsets *offs = cfg->offsets; 3917 struct device *dev = qmp->dev; 3918 void __iomem *base; 3919 int ret; 3920 3921 if (!offs) 3922 return -EINVAL; 3923 3924 base = devm_platform_ioremap_resource(pdev, 0); 3925 if (IS_ERR(base)) 3926 return PTR_ERR(base); 3927 3928 qmp->com = base + offs->com; 3929 qmp->tx = base + offs->txa; 3930 qmp->rx = base + offs->rxa; 3931 qmp->tx2 = base + offs->txb; 3932 qmp->rx2 = base + offs->rxb; 3933 3934 qmp->serdes = base + offs->usb3_serdes; 3935 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3936 qmp->pcs = base + offs->usb3_pcs; 3937 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3938 3939 qmp->dp_serdes = base + offs->dp_serdes; 3940 if (offs->dp_txa) { 3941 qmp->dp_tx = base + offs->dp_txa; 3942 qmp->dp_tx2 = base + offs->dp_txb; 3943 } else { 3944 qmp->dp_tx = base + offs->txa; 3945 qmp->dp_tx2 = base + offs->txb; 3946 } 3947 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3948 3949 ret = qmp_combo_clk_init(qmp); 3950 if (ret) 3951 return ret; 3952 3953 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3954 if (IS_ERR(qmp->pipe_clk)) { 3955 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3956 "failed to get usb3_pipe clock\n"); 3957 } 3958 3959 return 0; 3960 } 3961 3962 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 3963 { 3964 struct qmp_combo *qmp = dev_get_drvdata(dev); 3965 3966 if (args->args_count == 0) 3967 return ERR_PTR(-EINVAL); 3968 3969 switch (args->args[0]) { 3970 case QMP_USB43DP_USB3_PHY: 3971 return qmp->usb_phy; 3972 case QMP_USB43DP_DP_PHY: 3973 return qmp->dp_phy; 3974 } 3975 3976 return ERR_PTR(-EINVAL); 3977 } 3978 3979 static int qmp_combo_probe(struct platform_device *pdev) 3980 { 3981 struct qmp_combo *qmp; 3982 struct device *dev = &pdev->dev; 3983 struct device_node *dp_np, *usb_np; 3984 struct phy_provider *phy_provider; 3985 int ret; 3986 3987 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3988 if (!qmp) 3989 return -ENOMEM; 3990 3991 qmp->dev = dev; 3992 dev_set_drvdata(dev, qmp); 3993 3994 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3995 3996 qmp->cfg = of_device_get_match_data(dev); 3997 if (!qmp->cfg) 3998 return -EINVAL; 3999 4000 mutex_init(&qmp->phy_mutex); 4001 4002 ret = qmp_combo_reset_init(qmp); 4003 if (ret) 4004 return ret; 4005 4006 ret = qmp_combo_vreg_init(qmp); 4007 if (ret) 4008 return ret; 4009 4010 /* Check for legacy binding with child nodes. */ 4011 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 4012 if (usb_np) { 4013 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 4014 if (!dp_np) { 4015 of_node_put(usb_np); 4016 return -EINVAL; 4017 } 4018 4019 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 4020 } else { 4021 usb_np = of_node_get(dev->of_node); 4022 dp_np = of_node_get(dev->of_node); 4023 4024 ret = qmp_combo_parse_dt(qmp); 4025 } 4026 if (ret) 4027 goto err_node_put; 4028 4029 ret = qmp_combo_typec_switch_register(qmp); 4030 if (ret) 4031 goto err_node_put; 4032 4033 ret = drm_aux_bridge_register(dev); 4034 if (ret) 4035 goto err_node_put; 4036 4037 pm_runtime_set_active(dev); 4038 ret = devm_pm_runtime_enable(dev); 4039 if (ret) 4040 goto err_node_put; 4041 /* 4042 * Prevent runtime pm from being ON by default. Users can enable 4043 * it using power/control in sysfs. 4044 */ 4045 pm_runtime_forbid(dev); 4046 4047 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 4048 if (ret) 4049 goto err_node_put; 4050 4051 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 4052 if (IS_ERR(qmp->usb_phy)) { 4053 ret = PTR_ERR(qmp->usb_phy); 4054 dev_err(dev, "failed to create USB PHY: %d\n", ret); 4055 goto err_node_put; 4056 } 4057 4058 phy_set_drvdata(qmp->usb_phy, qmp); 4059 4060 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 4061 if (IS_ERR(qmp->dp_phy)) { 4062 ret = PTR_ERR(qmp->dp_phy); 4063 dev_err(dev, "failed to create DP PHY: %d\n", ret); 4064 goto err_node_put; 4065 } 4066 4067 phy_set_drvdata(qmp->dp_phy, qmp); 4068 4069 if (usb_np == dev->of_node) 4070 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 4071 else 4072 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4073 4074 of_node_put(usb_np); 4075 of_node_put(dp_np); 4076 4077 return PTR_ERR_OR_ZERO(phy_provider); 4078 4079 err_node_put: 4080 of_node_put(usb_np); 4081 of_node_put(dp_np); 4082 return ret; 4083 } 4084 4085 static const struct of_device_id qmp_combo_of_match_table[] = { 4086 { 4087 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 4088 .data = &sar2130p_usb3dpphy_cfg, 4089 }, 4090 { 4091 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 4092 .data = &sc7180_usb3dpphy_cfg, 4093 }, 4094 { 4095 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 4096 .data = &sm8250_usb3dpphy_cfg, 4097 }, 4098 { 4099 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 4100 .data = &sc8180x_usb3dpphy_cfg, 4101 }, 4102 { 4103 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 4104 .data = &sc8280xp_usb43dpphy_cfg, 4105 }, 4106 { 4107 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 4108 .data = &sdm845_usb3dpphy_cfg, 4109 }, 4110 { 4111 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 4112 .data = &sm6350_usb3dpphy_cfg, 4113 }, 4114 { 4115 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 4116 .data = &sc8180x_usb3dpphy_cfg, 4117 }, 4118 { 4119 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 4120 .data = &sm8250_usb3dpphy_cfg, 4121 }, 4122 { 4123 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 4124 .data = &sm8350_usb3dpphy_cfg, 4125 }, 4126 { 4127 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 4128 .data = &sm8350_usb3dpphy_cfg, 4129 }, 4130 { 4131 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 4132 .data = &sm8550_usb3dpphy_cfg, 4133 }, 4134 { 4135 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 4136 .data = &sm8650_usb3dpphy_cfg, 4137 }, 4138 { 4139 .compatible = "qcom,sm8750-qmp-usb3-dp-phy", 4140 .data = &sm8750_usb3dpphy_cfg, 4141 }, 4142 { 4143 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 4144 .data = &x1e80100_usb3dpphy_cfg, 4145 }, 4146 { } 4147 }; 4148 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 4149 4150 static struct platform_driver qmp_combo_driver = { 4151 .probe = qmp_combo_probe, 4152 .driver = { 4153 .name = "qcom-qmp-combo-phy", 4154 .pm = &qmp_combo_pm_ops, 4155 .of_match_table = qmp_combo_of_match_table, 4156 }, 4157 }; 4158 4159 module_platform_driver(qmp_combo_driver); 4160 4161 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 4162 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 4163 MODULE_LICENSE("GPL v2"); 4164