1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 /* QPHY_START_CONTROL bits */ 32 #define SERDES_START BIT(0) 33 #define PCS_START BIT(1) 34 /* QPHY_PCS_STATUS bit */ 35 #define PHYSTATUS BIT(6) 36 37 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 38 /* DP PHY soft reset */ 39 #define SW_DPPHY_RESET BIT(0) 40 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 41 #define SW_DPPHY_RESET_MUX BIT(1) 42 /* USB3 PHY soft reset */ 43 #define SW_USB3PHY_RESET BIT(2) 44 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 45 #define SW_USB3PHY_RESET_MUX BIT(3) 46 47 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 48 #define USB3_MODE BIT(0) /* enables USB3 mode */ 49 #define DP_MODE BIT(1) /* enables DP mode */ 50 51 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 52 #define ARCVR_DTCT_EN BIT(0) 53 #define ALFPS_DTCT_EN BIT(1) 54 #define ARCVR_DTCT_EVENT_SEL BIT(4) 55 56 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 57 #define IRQ_CLEAR BIT(0) 58 59 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ 60 #define RCVR_DETECT BIT(0) 61 62 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 63 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 64 65 #define PHY_INIT_COMPLETE_TIMEOUT 10000 66 67 struct qmp_phy_init_tbl { 68 unsigned int offset; 69 unsigned int val; 70 /* 71 * mask of lanes for which this register is written 72 * for cases when second lane needs different values 73 */ 74 u8 lane_mask; 75 }; 76 77 #define QMP_PHY_INIT_CFG(o, v) \ 78 { \ 79 .offset = o, \ 80 .val = v, \ 81 .lane_mask = 0xff, \ 82 } 83 84 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 85 { \ 86 .offset = o, \ 87 .val = v, \ 88 .lane_mask = l, \ 89 } 90 91 /* set of registers with offsets different per-PHY */ 92 enum qphy_reg_layout { 93 /* PCS registers */ 94 QPHY_SW_RESET, 95 QPHY_START_CTRL, 96 QPHY_PCS_STATUS, 97 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 98 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 99 QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, 100 QPHY_PCS_POWER_DOWN_CONTROL, 101 /* Keep last to ensure regs_layout arrays are properly initialized */ 102 QPHY_LAYOUT_SIZE 103 }; 104 105 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = 0x00, 107 [QPHY_START_CTRL] = 0x08, 108 [QPHY_PCS_STATUS] = 0x174, 109 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 110 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 111 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 112 [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, 113 }; 114 115 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_SW_RESET] = 0x00, 117 [QPHY_START_CTRL] = 0x44, 118 [QPHY_PCS_STATUS] = 0x14, 119 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 120 121 /* In PCS_USB */ 122 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, 123 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, 124 }; 125 126 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 163 }; 164 165 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 170 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 171 }; 172 173 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 174 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 177 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 178 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 179 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 180 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 181 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 182 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 183 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 186 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 195 }; 196 197 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 205 }; 206 207 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 215 }; 216 217 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 225 }; 226 227 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 235 }; 236 237 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 238 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 239 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 240 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 241 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 242 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 243 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 244 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 245 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 248 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 249 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 250 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 251 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 252 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 253 }; 254 255 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 265 }; 266 267 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 268 /* FLL settings */ 269 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 273 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 274 275 /* Lock Det settings */ 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 280 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 300 301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 312 }; 313 314 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 315 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 316 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 317 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 318 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 319 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 320 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 321 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 322 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 323 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 324 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 325 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 326 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 327 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 328 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 329 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 330 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 331 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 332 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 333 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 334 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 335 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 336 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 337 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 338 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 339 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 340 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 341 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 342 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 343 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 344 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 345 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 346 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 347 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 348 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 349 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 350 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 351 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 352 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 353 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 354 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 355 }; 356 357 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 358 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 359 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 360 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 361 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 362 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 363 }; 364 365 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 366 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 367 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 368 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 369 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 370 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 371 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 372 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 373 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 374 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 375 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 376 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 377 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 378 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 379 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 380 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 381 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 382 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 383 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 384 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 385 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 386 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 387 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 388 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 389 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 390 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 391 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 392 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 393 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 394 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 395 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 396 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 397 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 398 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 399 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 400 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 401 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 402 }; 403 404 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 405 /* Lock Det settings */ 406 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 407 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 408 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 409 410 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 411 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 412 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 413 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 414 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 415 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 416 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 417 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 418 }; 419 420 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 421 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 422 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 423 }; 424 425 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 426 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 427 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 428 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 429 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 430 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 431 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 432 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 433 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 434 }; 435 436 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 457 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 458 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 459 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 460 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 475 }; 476 477 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 490 }; 491 492 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 495 }; 496 497 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 518 }; 519 520 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 528 }; 529 530 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 538 }; 539 540 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 548 }; 549 550 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 558 }; 559 560 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 561 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 562 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 563 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 564 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 565 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 566 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 567 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 568 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 569 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 570 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 571 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 572 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 573 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 574 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 575 }; 576 577 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 578 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 579 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 580 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 588 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 589 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 601 }; 602 603 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 604 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 605 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 606 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 607 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 608 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 609 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 610 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 611 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 612 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 613 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 614 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 615 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 616 }; 617 618 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 628 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 629 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 630 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 631 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 632 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 633 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 634 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 635 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 636 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 637 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 638 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 639 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 640 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 641 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 642 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 643 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 644 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 645 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 646 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 647 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 648 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 649 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 650 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 651 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 652 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 653 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 654 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 655 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 656 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 657 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 658 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 659 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 660 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 661 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 666 }; 667 668 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 669 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 670 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 671 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 672 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 673 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 674 }; 675 676 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 677 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 678 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 679 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 680 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 681 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 682 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 683 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 684 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 685 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 686 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 687 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 688 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 689 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 690 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 691 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 692 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 693 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 694 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 695 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 696 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 697 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 698 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 699 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 700 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 701 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 702 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 703 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 704 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 705 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 707 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 708 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 709 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 710 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 711 }; 712 713 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 714 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 715 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 716 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 717 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 718 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 719 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 720 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 721 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 722 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 724 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 725 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 726 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 730 }; 731 732 /* list of regulators */ 733 struct qmp_regulator_data { 734 const char *name; 735 unsigned int enable_load; 736 }; 737 738 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 739 { .name = "vdda-phy", .enable_load = 21800 }, 740 { .name = "vdda-pll", .enable_load = 36000 }, 741 }; 742 743 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 744 { 0x00, 0x0c, 0x15, 0x1a }, 745 { 0x02, 0x0e, 0x16, 0xff }, 746 { 0x02, 0x11, 0xff, 0xff }, 747 { 0x04, 0xff, 0xff, 0xff } 748 }; 749 750 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 751 { 0x02, 0x12, 0x16, 0x1a }, 752 { 0x09, 0x19, 0x1f, 0xff }, 753 { 0x10, 0x1f, 0xff, 0xff }, 754 { 0x1f, 0xff, 0xff, 0xff } 755 }; 756 757 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 758 { 0x00, 0x0c, 0x14, 0x19 }, 759 { 0x00, 0x0b, 0x12, 0xff }, 760 { 0x00, 0x0b, 0xff, 0xff }, 761 { 0x04, 0xff, 0xff, 0xff } 762 }; 763 764 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 765 { 0x08, 0x0f, 0x16, 0x1f }, 766 { 0x11, 0x1e, 0x1f, 0xff }, 767 { 0x19, 0x1f, 0xff, 0xff }, 768 { 0x1f, 0xff, 0xff, 0xff } 769 }; 770 771 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 772 { 0x20, 0x2c, 0x35, 0x3b }, 773 { 0x22, 0x2e, 0x36, 0xff }, 774 { 0x22, 0x31, 0xff, 0xff }, 775 { 0x24, 0xff, 0xff, 0xff } 776 }; 777 778 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 779 { 0x22, 0x32, 0x36, 0x3a }, 780 { 0x29, 0x39, 0x3f, 0xff }, 781 { 0x30, 0x3f, 0xff, 0xff }, 782 { 0x3f, 0xff, 0xff, 0xff } 783 }; 784 785 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 786 { 0x20, 0x2d, 0x34, 0x3a }, 787 { 0x20, 0x2e, 0x35, 0xff }, 788 { 0x20, 0x2e, 0xff, 0xff }, 789 { 0x24, 0xff, 0xff, 0xff } 790 }; 791 792 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 793 { 0x28, 0x2f, 0x36, 0x3f }, 794 { 0x31, 0x3e, 0x3f, 0xff }, 795 { 0x36, 0x3f, 0xff, 0xff }, 796 { 0x3f, 0xff, 0xff, 0xff } 797 }; 798 799 struct qmp_phy; 800 801 /* struct qmp_phy_cfg - per-PHY initialization config */ 802 struct qmp_phy_cfg { 803 /* phy-type - PCIE/UFS/USB */ 804 unsigned int type; 805 int lanes; 806 807 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 808 const struct qmp_phy_init_tbl *serdes_tbl; 809 int serdes_tbl_num; 810 const struct qmp_phy_init_tbl *tx_tbl; 811 int tx_tbl_num; 812 const struct qmp_phy_init_tbl *rx_tbl; 813 int rx_tbl_num; 814 const struct qmp_phy_init_tbl *pcs_tbl; 815 int pcs_tbl_num; 816 const struct qmp_phy_init_tbl *pcs_usb_tbl; 817 int pcs_usb_tbl_num; 818 819 /* Init sequence for DP PHY block link rates */ 820 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 821 int serdes_tbl_rbr_num; 822 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 823 int serdes_tbl_hbr_num; 824 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 825 int serdes_tbl_hbr2_num; 826 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 827 int serdes_tbl_hbr3_num; 828 829 /* DP PHY swing and pre_emphasis tables */ 830 const u8 (*swing_hbr_rbr)[4][4]; 831 const u8 (*swing_hbr3_hbr2)[4][4]; 832 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 833 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 834 835 /* DP PHY callbacks */ 836 int (*configure_dp_phy)(struct qmp_phy *qphy); 837 void (*configure_dp_tx)(struct qmp_phy *qphy); 838 int (*calibrate_dp_phy)(struct qmp_phy *qphy); 839 void (*dp_aux_init)(struct qmp_phy *qphy); 840 841 /* clock ids to be requested */ 842 const char * const *clk_list; 843 int num_clks; 844 /* resets to be requested */ 845 const char * const *reset_list; 846 int num_resets; 847 /* regulators to be requested */ 848 const struct qmp_regulator_data *vreg_list; 849 int num_vregs; 850 851 /* array of registers with different offsets */ 852 const unsigned int *regs; 853 854 /* true, if PHY needs delay after POWER_DOWN */ 855 bool has_pwrdn_delay; 856 857 /* Offset from PCS to PCS_USB region */ 858 unsigned int pcs_usb_offset; 859 860 }; 861 862 struct qmp_phy_combo_cfg { 863 const struct qmp_phy_cfg *usb_cfg; 864 const struct qmp_phy_cfg *dp_cfg; 865 }; 866 867 /** 868 * struct qmp_phy - per-lane phy descriptor 869 * 870 * @phy: generic phy 871 * @cfg: phy specific configuration 872 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 873 * @tx: iomapped memory space for lane's tx 874 * @rx: iomapped memory space for lane's rx 875 * @pcs: iomapped memory space for lane's pcs 876 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 877 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 878 * @pcs_misc: iomapped memory space for lane's pcs_misc 879 * @pcs_usb: iomapped memory space for lane's pcs_usb 880 * @pipe_clk: pipe clock 881 * @qmp: QMP phy to which this lane belongs 882 * @mode: current PHY mode 883 * @dp_aux_cfg: Display port aux config 884 * @dp_opts: Display port optional config 885 * @dp_clks: Display port clocks 886 */ 887 struct qmp_phy { 888 struct phy *phy; 889 const struct qmp_phy_cfg *cfg; 890 void __iomem *serdes; 891 void __iomem *tx; 892 void __iomem *rx; 893 void __iomem *pcs; 894 void __iomem *tx2; 895 void __iomem *rx2; 896 void __iomem *pcs_misc; 897 void __iomem *pcs_usb; 898 struct clk *pipe_clk; 899 struct qcom_qmp *qmp; 900 enum phy_mode mode; 901 unsigned int dp_aux_cfg; 902 struct phy_configure_opts_dp dp_opts; 903 struct qmp_phy_dp_clks *dp_clks; 904 }; 905 906 struct qmp_phy_dp_clks { 907 struct qmp_phy *qphy; 908 struct clk_hw dp_link_hw; 909 struct clk_hw dp_pixel_hw; 910 }; 911 912 /** 913 * struct qcom_qmp - structure holding QMP phy block attributes 914 * 915 * @dev: device 916 * @dp_com: iomapped memory space for phy's dp_com control block 917 * 918 * @clks: array of clocks required by phy 919 * @resets: array of resets required by phy 920 * @vregs: regulator supplies bulk data 921 * 922 * @phys: array of per-lane phy descriptors 923 * @phy_mutex: mutex lock for PHY common block initialization 924 * @init_count: phy common block initialization count 925 */ 926 struct qcom_qmp { 927 struct device *dev; 928 void __iomem *dp_com; 929 930 struct clk_bulk_data *clks; 931 struct reset_control_bulk_data *resets; 932 struct regulator_bulk_data *vregs; 933 934 struct qmp_phy **phys; 935 936 struct mutex phy_mutex; 937 int init_count; 938 }; 939 940 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy); 941 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy); 942 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy); 943 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy); 944 945 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy); 946 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy); 947 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy); 948 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy); 949 950 static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy); 951 952 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 953 { 954 u32 reg; 955 956 reg = readl(base + offset); 957 reg |= val; 958 writel(reg, base + offset); 959 960 /* ensure that above write is through */ 961 readl(base + offset); 962 } 963 964 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 965 { 966 u32 reg; 967 968 reg = readl(base + offset); 969 reg &= ~val; 970 writel(reg, base + offset); 971 972 /* ensure that above write is through */ 973 readl(base + offset); 974 } 975 976 /* list of clocks required by phy */ 977 static const char * const qmp_v3_phy_clk_l[] = { 978 "aux", "cfg_ahb", "ref", "com_aux", 979 }; 980 981 static const char * const qmp_v4_phy_clk_l[] = { 982 "aux", "ref_clk_src", "ref", "com_aux", 983 }; 984 985 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 986 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 987 "aux", "ref_clk_src", "com_aux" 988 }; 989 990 /* list of resets */ 991 static const char * const msm8996_usb3phy_reset_l[] = { 992 "phy", "common", 993 }; 994 995 static const char * const sc7180_usb3phy_reset_l[] = { 996 "phy", 997 }; 998 999 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 1000 .type = PHY_TYPE_USB3, 1001 .lanes = 2, 1002 1003 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1004 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1005 .tx_tbl = qmp_v3_usb3_tx_tbl, 1006 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1007 .rx_tbl = qmp_v3_usb3_rx_tbl, 1008 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1009 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1010 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1011 .clk_list = qmp_v3_phy_clk_l, 1012 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1013 .reset_list = sc7180_usb3phy_reset_l, 1014 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1015 .vreg_list = qmp_phy_vreg_l, 1016 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1017 .regs = qmp_v3_usb3phy_regs_layout, 1018 1019 .has_pwrdn_delay = true, 1020 }; 1021 1022 static const struct qmp_phy_cfg sc7180_dpphy_cfg = { 1023 .type = PHY_TYPE_DP, 1024 .lanes = 2, 1025 1026 .serdes_tbl = qmp_v3_dp_serdes_tbl, 1027 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1028 .tx_tbl = qmp_v3_dp_tx_tbl, 1029 .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1030 1031 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1032 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1033 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1034 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1035 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1036 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1037 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1038 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1039 1040 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1041 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1042 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1043 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1044 1045 .clk_list = qmp_v3_phy_clk_l, 1046 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1047 .reset_list = sc7180_usb3phy_reset_l, 1048 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1049 .vreg_list = qmp_phy_vreg_l, 1050 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1051 .regs = qmp_v3_usb3phy_regs_layout, 1052 1053 .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init, 1054 .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx, 1055 .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy, 1056 .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate, 1057 }; 1058 1059 static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { 1060 .usb_cfg = &sc7180_usb3phy_cfg, 1061 .dp_cfg = &sc7180_dpphy_cfg, 1062 }; 1063 1064 static const struct qmp_phy_cfg sdm845_usb3phy_cfg = { 1065 .type = PHY_TYPE_USB3, 1066 .lanes = 2, 1067 1068 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1069 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1070 .tx_tbl = qmp_v3_usb3_tx_tbl, 1071 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1072 .rx_tbl = qmp_v3_usb3_rx_tbl, 1073 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1074 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1075 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1076 .clk_list = qmp_v3_phy_clk_l, 1077 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1078 .reset_list = msm8996_usb3phy_reset_l, 1079 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1080 .vreg_list = qmp_phy_vreg_l, 1081 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1082 .regs = qmp_v3_usb3phy_regs_layout, 1083 1084 .has_pwrdn_delay = true, 1085 }; 1086 1087 static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { 1088 .usb_cfg = &sdm845_usb3phy_cfg, 1089 .dp_cfg = &sc7180_dpphy_cfg, 1090 }; 1091 1092 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1093 .type = PHY_TYPE_USB3, 1094 .lanes = 2, 1095 1096 .serdes_tbl = sm8150_usb3_serdes_tbl, 1097 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1098 .tx_tbl = sm8150_usb3_tx_tbl, 1099 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1100 .rx_tbl = sm8150_usb3_rx_tbl, 1101 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1102 .pcs_tbl = sm8150_usb3_pcs_tbl, 1103 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1104 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1105 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1106 .clk_list = qmp_v4_phy_clk_l, 1107 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1108 .reset_list = msm8996_usb3phy_reset_l, 1109 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1110 .vreg_list = qmp_phy_vreg_l, 1111 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1112 .regs = qmp_v4_usb3phy_regs_layout, 1113 .pcs_usb_offset = 0x300, 1114 1115 .has_pwrdn_delay = true, 1116 }; 1117 1118 static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { 1119 .type = PHY_TYPE_DP, 1120 .lanes = 2, 1121 1122 .serdes_tbl = qmp_v4_dp_serdes_tbl, 1123 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1124 .tx_tbl = qmp_v4_dp_tx_tbl, 1125 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1126 1127 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1128 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1129 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1130 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1131 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1132 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1133 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1134 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1135 1136 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1137 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1138 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1139 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1140 1141 .clk_list = qmp_v3_phy_clk_l, 1142 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1143 .reset_list = sc7180_usb3phy_reset_l, 1144 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1145 .vreg_list = qmp_phy_vreg_l, 1146 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1147 .regs = qmp_v3_usb3phy_regs_layout, 1148 1149 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1150 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1151 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1152 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1153 }; 1154 1155 static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = { 1156 .usb_cfg = &sm8150_usb3phy_cfg, 1157 .dp_cfg = &sc8180x_dpphy_cfg, 1158 }; 1159 1160 static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = { 1161 .type = PHY_TYPE_USB3, 1162 .lanes = 2, 1163 1164 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1165 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1166 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1167 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1168 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1169 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1170 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1171 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1172 .clk_list = qmp_v4_phy_clk_l, 1173 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1174 .reset_list = msm8996_usb3phy_reset_l, 1175 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1176 .vreg_list = qmp_phy_vreg_l, 1177 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1178 .regs = qmp_v4_usb3phy_regs_layout, 1179 .pcs_usb_offset = 0x300, 1180 }; 1181 1182 static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = { 1183 .type = PHY_TYPE_DP, 1184 .lanes = 2, 1185 1186 .serdes_tbl = qmp_v5_dp_serdes_tbl, 1187 .serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1188 .tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1189 .tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1190 1191 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1192 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1193 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1194 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1195 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1196 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1197 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1198 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1199 1200 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1201 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1202 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1203 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1204 1205 .clk_list = qmp_v4_phy_clk_l, 1206 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1207 .reset_list = msm8996_usb3phy_reset_l, 1208 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1209 .vreg_list = qmp_phy_vreg_l, 1210 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1211 .regs = qmp_v4_usb3phy_regs_layout, 1212 1213 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1214 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1215 .configure_dp_phy = qcom_qmp_v5_phy_configure_dp_phy, 1216 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1217 }; 1218 1219 static const struct qmp_phy_combo_cfg sc8280xp_usb43dpphy_combo_cfg = { 1220 .usb_cfg = &sc8280xp_usb43dp_usb_cfg, 1221 .dp_cfg = &sc8280xp_usb43dp_dp_cfg, 1222 }; 1223 1224 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1225 .type = PHY_TYPE_USB3, 1226 .lanes = 2, 1227 1228 .serdes_tbl = sm8150_usb3_serdes_tbl, 1229 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1230 .tx_tbl = sm8250_usb3_tx_tbl, 1231 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1232 .rx_tbl = sm8250_usb3_rx_tbl, 1233 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1234 .pcs_tbl = sm8250_usb3_pcs_tbl, 1235 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1236 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1237 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1238 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1239 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1240 .reset_list = msm8996_usb3phy_reset_l, 1241 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1242 .vreg_list = qmp_phy_vreg_l, 1243 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1244 .regs = qmp_v4_usb3phy_regs_layout, 1245 .pcs_usb_offset = 0x300, 1246 1247 .has_pwrdn_delay = true, 1248 }; 1249 1250 static const struct qmp_phy_cfg sm8250_dpphy_cfg = { 1251 .type = PHY_TYPE_DP, 1252 .lanes = 2, 1253 1254 .serdes_tbl = qmp_v4_dp_serdes_tbl, 1255 .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1256 .tx_tbl = qmp_v4_dp_tx_tbl, 1257 .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1258 1259 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1260 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1261 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1262 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1263 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1264 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1265 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1266 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1267 1268 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1269 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1270 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1271 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1272 1273 .clk_list = qmp_v4_phy_clk_l, 1274 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1275 .reset_list = msm8996_usb3phy_reset_l, 1276 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1277 .vreg_list = qmp_phy_vreg_l, 1278 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1279 .regs = qmp_v4_usb3phy_regs_layout, 1280 1281 .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init, 1282 .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx, 1283 .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy, 1284 .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate, 1285 }; 1286 1287 static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = { 1288 .usb_cfg = &sm8250_usb3phy_cfg, 1289 .dp_cfg = &sm8250_dpphy_cfg, 1290 }; 1291 1292 static void qmp_combo_configure_lane(void __iomem *base, 1293 const struct qmp_phy_init_tbl tbl[], 1294 int num, 1295 u8 lane_mask) 1296 { 1297 int i; 1298 const struct qmp_phy_init_tbl *t = tbl; 1299 1300 if (!t) 1301 return; 1302 1303 for (i = 0; i < num; i++, t++) { 1304 if (!(t->lane_mask & lane_mask)) 1305 continue; 1306 1307 writel(t->val, base + t->offset); 1308 } 1309 } 1310 1311 static void qmp_combo_configure(void __iomem *base, 1312 const struct qmp_phy_init_tbl tbl[], 1313 int num) 1314 { 1315 qmp_combo_configure_lane(base, tbl, num, 0xff); 1316 } 1317 1318 static int qmp_combo_serdes_init(struct qmp_phy *qphy) 1319 { 1320 const struct qmp_phy_cfg *cfg = qphy->cfg; 1321 void __iomem *serdes = qphy->serdes; 1322 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1323 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1324 int serdes_tbl_num = cfg->serdes_tbl_num; 1325 1326 qmp_combo_configure(serdes, serdes_tbl, serdes_tbl_num); 1327 1328 if (cfg->type == PHY_TYPE_DP) { 1329 switch (dp_opts->link_rate) { 1330 case 1620: 1331 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1332 cfg->serdes_tbl_rbr_num); 1333 break; 1334 case 2700: 1335 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1336 cfg->serdes_tbl_hbr_num); 1337 break; 1338 case 5400: 1339 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1340 cfg->serdes_tbl_hbr2_num); 1341 break; 1342 case 8100: 1343 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1344 cfg->serdes_tbl_hbr3_num); 1345 break; 1346 default: 1347 /* Other link rates aren't supported */ 1348 return -EINVAL; 1349 } 1350 } 1351 1352 return 0; 1353 } 1354 1355 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy) 1356 { 1357 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1358 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1359 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1360 1361 /* Turn on BIAS current for PHY/PLL */ 1362 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1363 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1364 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1365 1366 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1367 1368 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1369 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1370 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1371 DP_PHY_PD_CTL_DP_CLAMP_EN, 1372 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1373 1374 writel(QSERDES_V3_COM_BIAS_EN | 1375 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1376 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1377 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1378 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1379 1380 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1381 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1382 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1383 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1384 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1385 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1386 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1387 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1388 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1389 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1390 qphy->dp_aux_cfg = 0; 1391 1392 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1393 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1394 PHY_AUX_REQ_ERR_MASK, 1395 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1396 } 1397 1398 static int qmp_combo_configure_dp_swing(struct qmp_phy *qphy, 1399 unsigned int drv_lvl_reg, unsigned int emp_post_reg) 1400 { 1401 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1402 const struct qmp_phy_cfg *cfg = qphy->cfg; 1403 unsigned int v_level = 0, p_level = 0; 1404 u8 voltage_swing_cfg, pre_emphasis_cfg; 1405 int i; 1406 1407 for (i = 0; i < dp_opts->lanes; i++) { 1408 v_level = max(v_level, dp_opts->voltage[i]); 1409 p_level = max(p_level, dp_opts->pre[i]); 1410 } 1411 1412 if (dp_opts->link_rate <= 2700) { 1413 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1414 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1415 } else { 1416 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1417 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1418 } 1419 1420 /* TODO: Move check to config check */ 1421 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1422 return -EINVAL; 1423 1424 /* Enable MUX to use Cursor values from these registers */ 1425 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1426 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 1427 1428 writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg); 1429 writel(pre_emphasis_cfg, qphy->tx + emp_post_reg); 1430 writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg); 1431 writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg); 1432 1433 return 0; 1434 } 1435 1436 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy) 1437 { 1438 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1439 u32 bias_en, drvr_en; 1440 1441 if (qmp_combo_configure_dp_swing(qphy, QSERDES_V3_TX_TX_DRV_LVL, 1442 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) 1443 return; 1444 1445 if (dp_opts->lanes == 1) { 1446 bias_en = 0x3e; 1447 drvr_en = 0x13; 1448 } else { 1449 bias_en = 0x3f; 1450 drvr_en = 0x10; 1451 } 1452 1453 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1454 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1455 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1456 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1457 } 1458 1459 static bool qmp_combo_configure_dp_mode(struct qmp_phy *qphy) 1460 { 1461 u32 val; 1462 bool reverse = false; 1463 1464 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1465 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 1466 1467 /* 1468 * TODO: Assume orientation is CC1 for now and two lanes, need to 1469 * use type-c connector to understand orientation and lanes. 1470 * 1471 * Otherwise val changes to be like below if this code understood 1472 * the orientation of the type-c cable. 1473 * 1474 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) 1475 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 1476 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 1477 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1478 * if (orientation == ORIENTATION_CC2) 1479 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE); 1480 */ 1481 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1482 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1483 1484 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); 1485 1486 return reverse; 1487 } 1488 1489 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy) 1490 { 1491 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1492 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1493 u32 phy_vco_div, status; 1494 unsigned long pixel_freq; 1495 1496 qmp_combo_configure_dp_mode(qphy); 1497 1498 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 1499 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 1500 1501 switch (dp_opts->link_rate) { 1502 case 1620: 1503 phy_vco_div = 0x1; 1504 pixel_freq = 1620000000UL / 2; 1505 break; 1506 case 2700: 1507 phy_vco_div = 0x1; 1508 pixel_freq = 2700000000UL / 2; 1509 break; 1510 case 5400: 1511 phy_vco_div = 0x2; 1512 pixel_freq = 5400000000UL / 4; 1513 break; 1514 case 8100: 1515 phy_vco_div = 0x0; 1516 pixel_freq = 8100000000UL / 6; 1517 break; 1518 default: 1519 /* Other link rates aren't supported */ 1520 return -EINVAL; 1521 } 1522 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); 1523 1524 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1525 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1526 1527 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1528 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1529 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1530 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1531 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1532 1533 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL); 1534 1535 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS, 1536 status, 1537 ((status & BIT(0)) > 0), 1538 500, 1539 10000)) 1540 return -ETIMEDOUT; 1541 1542 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1543 1544 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1545 status, 1546 ((status & BIT(1)) > 0), 1547 500, 1548 10000)) 1549 return -ETIMEDOUT; 1550 1551 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1552 udelay(2000); 1553 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1554 1555 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, 1556 status, 1557 ((status & BIT(1)) > 0), 1558 500, 1559 10000); 1560 } 1561 1562 /* 1563 * We need to calibrate the aux setting here as many times 1564 * as the caller tries 1565 */ 1566 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy) 1567 { 1568 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 1569 u8 val; 1570 1571 qphy->dp_aux_cfg++; 1572 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1573 val = cfg1_settings[qphy->dp_aux_cfg]; 1574 1575 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1576 1577 return 0; 1578 } 1579 1580 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy) 1581 { 1582 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1583 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1584 qphy->pcs + QSERDES_DP_PHY_PD_CTL); 1585 1586 /* Turn on BIAS current for PHY/PLL */ 1587 writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 1588 1589 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); 1590 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1591 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1592 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); 1593 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); 1594 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); 1595 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); 1596 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); 1597 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); 1598 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); 1599 qphy->dp_aux_cfg = 0; 1600 1601 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1602 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1603 PHY_AUX_REQ_ERR_MASK, 1604 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 1605 } 1606 1607 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy) 1608 { 1609 /* Program default values before writing proper values */ 1610 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1611 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1612 1613 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1614 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1615 1616 qmp_combo_configure_dp_swing(qphy, QSERDES_V4_TX_TX_DRV_LVL, 1617 QSERDES_V4_TX_TX_EMP_POST1_LVL); 1618 } 1619 1620 static int qcom_qmp_v45_phy_configure_dp_phy(struct qmp_phy *qphy) 1621 { 1622 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks; 1623 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1624 u32 phy_vco_div, status; 1625 unsigned long pixel_freq; 1626 1627 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); 1628 1629 qmp_combo_configure_dp_mode(qphy); 1630 1631 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1632 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); 1633 1634 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 1635 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 1636 1637 switch (dp_opts->link_rate) { 1638 case 1620: 1639 phy_vco_div = 0x1; 1640 pixel_freq = 1620000000UL / 2; 1641 break; 1642 case 2700: 1643 phy_vco_div = 0x1; 1644 pixel_freq = 2700000000UL / 2; 1645 break; 1646 case 5400: 1647 phy_vco_div = 0x2; 1648 pixel_freq = 5400000000UL / 4; 1649 break; 1650 case 8100: 1651 phy_vco_div = 0x0; 1652 pixel_freq = 8100000000UL / 6; 1653 break; 1654 default: 1655 /* Other link rates aren't supported */ 1656 return -EINVAL; 1657 } 1658 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); 1659 1660 clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000); 1661 clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq); 1662 1663 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1664 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); 1665 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); 1666 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); 1667 1668 writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL); 1669 1670 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS, 1671 status, 1672 ((status & BIT(0)) > 0), 1673 500, 1674 10000)) 1675 return -ETIMEDOUT; 1676 1677 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1678 status, 1679 ((status & BIT(0)) > 0), 1680 500, 1681 10000)) 1682 return -ETIMEDOUT; 1683 1684 if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS, 1685 status, 1686 ((status & BIT(1)) > 0), 1687 500, 1688 10000)) 1689 return -ETIMEDOUT; 1690 1691 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1692 1693 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1694 status, 1695 ((status & BIT(0)) > 0), 1696 500, 1697 10000)) 1698 return -ETIMEDOUT; 1699 1700 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1701 status, 1702 ((status & BIT(1)) > 0), 1703 500, 1704 10000)) 1705 return -ETIMEDOUT; 1706 1707 return 0; 1708 } 1709 1710 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy) 1711 { 1712 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1713 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1714 bool reverse = false; 1715 u32 status; 1716 int ret; 1717 1718 ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); 1719 if (ret < 0) 1720 return ret; 1721 1722 /* 1723 * At least for 7nm DP PHY this has to be done after enabling link 1724 * clock. 1725 */ 1726 1727 if (dp_opts->lanes == 1) { 1728 bias0_en = reverse ? 0x3e : 0x15; 1729 bias1_en = reverse ? 0x15 : 0x3e; 1730 drvr0_en = reverse ? 0x13 : 0x10; 1731 drvr1_en = reverse ? 0x10 : 0x13; 1732 } else if (dp_opts->lanes == 2) { 1733 bias0_en = reverse ? 0x3f : 0x15; 1734 bias1_en = reverse ? 0x15 : 0x3f; 1735 drvr0_en = 0x10; 1736 drvr1_en = 0x10; 1737 } else { 1738 bias0_en = 0x3f; 1739 bias1_en = 0x3f; 1740 drvr0_en = 0x10; 1741 drvr1_en = 0x10; 1742 } 1743 1744 writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1745 writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1746 writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 1747 writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 1748 1749 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1750 udelay(2000); 1751 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1752 1753 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1754 status, 1755 ((status & BIT(1)) > 0), 1756 500, 1757 10000)) 1758 return -ETIMEDOUT; 1759 1760 writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV); 1761 writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV); 1762 1763 writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL); 1764 writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL); 1765 1766 writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1767 writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 1768 1769 return 0; 1770 } 1771 1772 static int qcom_qmp_v5_phy_configure_dp_phy(struct qmp_phy *qphy) 1773 { 1774 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts; 1775 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 1776 bool reverse = false; 1777 u32 status; 1778 int ret; 1779 1780 ret = qcom_qmp_v45_phy_configure_dp_phy(qphy); 1781 if (ret < 0) 1782 return ret; 1783 1784 if (dp_opts->lanes == 1) { 1785 bias0_en = reverse ? 0x3e : 0x1a; 1786 drvr0_en = reverse ? 0x13 : 0x10; 1787 bias1_en = reverse ? 0x15 : 0x3e; 1788 drvr1_en = reverse ? 0x10 : 0x13; 1789 } else if (dp_opts->lanes == 2) { 1790 bias0_en = reverse ? 0x3f : 0x15; 1791 drvr0_en = 0x10; 1792 bias1_en = reverse ? 0x15 : 0x3f; 1793 drvr1_en = 0x10; 1794 } else { 1795 bias0_en = 0x3f; 1796 bias1_en = 0x3f; 1797 drvr0_en = 0x10; 1798 drvr1_en = 0x10; 1799 } 1800 1801 writel(drvr0_en, qphy->tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1802 writel(bias0_en, qphy->tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1803 writel(drvr1_en, qphy->tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 1804 writel(bias1_en, qphy->tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 1805 1806 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); 1807 udelay(2000); 1808 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); 1809 1810 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, 1811 status, 1812 ((status & BIT(1)) > 0), 1813 500, 1814 10000)) 1815 return -ETIMEDOUT; 1816 1817 writel(0x0a, qphy->tx + QSERDES_V5_5NM_TX_TX_POL_INV); 1818 writel(0x0a, qphy->tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); 1819 1820 writel(0x27, qphy->tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1821 writel(0x27, qphy->tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); 1822 1823 writel(0x20, qphy->tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1824 writel(0x20, qphy->tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 1825 1826 return 0; 1827 } 1828 1829 /* 1830 * We need to calibrate the aux setting here as many times 1831 * as the caller tries 1832 */ 1833 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy) 1834 { 1835 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 1836 u8 val; 1837 1838 qphy->dp_aux_cfg++; 1839 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 1840 val = cfg1_settings[qphy->dp_aux_cfg]; 1841 1842 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); 1843 1844 return 0; 1845 } 1846 1847 static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1848 { 1849 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 1850 struct qmp_phy *qphy = phy_get_drvdata(phy); 1851 const struct qmp_phy_cfg *cfg = qphy->cfg; 1852 1853 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts)); 1854 if (qphy->dp_opts.set_voltages) { 1855 cfg->configure_dp_tx(qphy); 1856 qphy->dp_opts.set_voltages = 0; 1857 } 1858 1859 return 0; 1860 } 1861 1862 static int qcom_qmp_dp_phy_calibrate(struct phy *phy) 1863 { 1864 struct qmp_phy *qphy = phy_get_drvdata(phy); 1865 const struct qmp_phy_cfg *cfg = qphy->cfg; 1866 1867 if (cfg->calibrate_dp_phy) 1868 return cfg->calibrate_dp_phy(qphy); 1869 1870 return 0; 1871 } 1872 1873 static int qmp_combo_com_init(struct qmp_phy *qphy) 1874 { 1875 struct qcom_qmp *qmp = qphy->qmp; 1876 const struct qmp_phy_cfg *cfg = qphy->cfg; 1877 void __iomem *pcs = qphy->pcs; 1878 void __iomem *dp_com = qmp->dp_com; 1879 int ret; 1880 1881 mutex_lock(&qmp->phy_mutex); 1882 if (qmp->init_count++) { 1883 mutex_unlock(&qmp->phy_mutex); 1884 return 0; 1885 } 1886 1887 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1888 if (ret) { 1889 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1890 goto err_unlock; 1891 } 1892 1893 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1894 if (ret) { 1895 dev_err(qmp->dev, "reset assert failed\n"); 1896 goto err_disable_regulators; 1897 } 1898 1899 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1900 if (ret) { 1901 dev_err(qmp->dev, "reset deassert failed\n"); 1902 goto err_disable_regulators; 1903 } 1904 1905 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1906 if (ret) 1907 goto err_assert_reset; 1908 1909 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 1910 1911 /* override hardware control for reset of qmp phy */ 1912 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1913 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1914 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1915 1916 /* Default type-c orientation, i.e CC1 */ 1917 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 1918 1919 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); 1920 1921 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 1922 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 1923 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 1924 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 1925 1926 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 1927 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 1928 1929 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1930 1931 mutex_unlock(&qmp->phy_mutex); 1932 1933 return 0; 1934 1935 err_assert_reset: 1936 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1937 err_disable_regulators: 1938 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1939 err_unlock: 1940 mutex_unlock(&qmp->phy_mutex); 1941 1942 return ret; 1943 } 1944 1945 static int qmp_combo_com_exit(struct qmp_phy *qphy) 1946 { 1947 struct qcom_qmp *qmp = qphy->qmp; 1948 const struct qmp_phy_cfg *cfg = qphy->cfg; 1949 1950 mutex_lock(&qmp->phy_mutex); 1951 if (--qmp->init_count) { 1952 mutex_unlock(&qmp->phy_mutex); 1953 return 0; 1954 } 1955 1956 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1957 1958 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1959 1960 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1961 1962 mutex_unlock(&qmp->phy_mutex); 1963 1964 return 0; 1965 } 1966 1967 static int qmp_combo_init(struct phy *phy) 1968 { 1969 struct qmp_phy *qphy = phy_get_drvdata(phy); 1970 struct qcom_qmp *qmp = qphy->qmp; 1971 const struct qmp_phy_cfg *cfg = qphy->cfg; 1972 int ret; 1973 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 1974 1975 ret = qmp_combo_com_init(qphy); 1976 if (ret) 1977 return ret; 1978 1979 if (cfg->type == PHY_TYPE_DP) 1980 cfg->dp_aux_init(qphy); 1981 1982 return 0; 1983 } 1984 1985 static int qmp_combo_power_on(struct phy *phy) 1986 { 1987 struct qmp_phy *qphy = phy_get_drvdata(phy); 1988 struct qcom_qmp *qmp = qphy->qmp; 1989 const struct qmp_phy_cfg *cfg = qphy->cfg; 1990 void __iomem *tx = qphy->tx; 1991 void __iomem *rx = qphy->rx; 1992 void __iomem *pcs = qphy->pcs; 1993 void __iomem *status; 1994 unsigned int val; 1995 int ret; 1996 1997 qmp_combo_serdes_init(qphy); 1998 1999 ret = clk_prepare_enable(qphy->pipe_clk); 2000 if (ret) { 2001 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2002 return ret; 2003 } 2004 2005 /* Tx, Rx, and PCS configurations */ 2006 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2007 2008 if (cfg->lanes >= 2) 2009 qmp_combo_configure_lane(qphy->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2010 2011 /* Configure special DP tx tunings */ 2012 if (cfg->type == PHY_TYPE_DP) 2013 cfg->configure_dp_tx(qphy); 2014 2015 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2016 2017 if (cfg->lanes >= 2) 2018 qmp_combo_configure_lane(qphy->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2019 2020 /* Configure link rate, swing, etc. */ 2021 if (cfg->type == PHY_TYPE_DP) 2022 cfg->configure_dp_phy(qphy); 2023 else 2024 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2025 2026 if (cfg->has_pwrdn_delay) 2027 usleep_range(10, 20); 2028 2029 if (cfg->type != PHY_TYPE_DP) { 2030 /* Pull PHY out of reset state */ 2031 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2032 /* start SerDes and Phy-Coding-Sublayer */ 2033 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], 2034 SERDES_START | PCS_START); 2035 2036 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2037 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2038 PHY_INIT_COMPLETE_TIMEOUT); 2039 if (ret) { 2040 dev_err(qmp->dev, "phy initialization timed-out\n"); 2041 goto err_disable_pipe_clk; 2042 } 2043 } 2044 return 0; 2045 2046 err_disable_pipe_clk: 2047 clk_disable_unprepare(qphy->pipe_clk); 2048 2049 return ret; 2050 } 2051 2052 static int qmp_combo_power_off(struct phy *phy) 2053 { 2054 struct qmp_phy *qphy = phy_get_drvdata(phy); 2055 const struct qmp_phy_cfg *cfg = qphy->cfg; 2056 2057 clk_disable_unprepare(qphy->pipe_clk); 2058 2059 if (cfg->type == PHY_TYPE_DP) { 2060 /* Assert DP PHY power down */ 2061 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); 2062 } else { 2063 /* PHY reset */ 2064 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2065 2066 /* stop SerDes and Phy-Coding-Sublayer */ 2067 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], 2068 SERDES_START | PCS_START); 2069 2070 /* Put PHY into POWER DOWN state: active low */ 2071 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2072 SW_PWRDN); 2073 } 2074 2075 return 0; 2076 } 2077 2078 static int qmp_combo_exit(struct phy *phy) 2079 { 2080 struct qmp_phy *qphy = phy_get_drvdata(phy); 2081 2082 qmp_combo_com_exit(qphy); 2083 2084 return 0; 2085 } 2086 2087 static int qmp_combo_enable(struct phy *phy) 2088 { 2089 int ret; 2090 2091 ret = qmp_combo_init(phy); 2092 if (ret) 2093 return ret; 2094 2095 ret = qmp_combo_power_on(phy); 2096 if (ret) 2097 qmp_combo_exit(phy); 2098 2099 return ret; 2100 } 2101 2102 static int qmp_combo_disable(struct phy *phy) 2103 { 2104 int ret; 2105 2106 ret = qmp_combo_power_off(phy); 2107 if (ret) 2108 return ret; 2109 return qmp_combo_exit(phy); 2110 } 2111 2112 static int qmp_combo_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2113 { 2114 struct qmp_phy *qphy = phy_get_drvdata(phy); 2115 2116 qphy->mode = mode; 2117 2118 return 0; 2119 } 2120 2121 static void qmp_combo_enable_autonomous_mode(struct qmp_phy *qphy) 2122 { 2123 const struct qmp_phy_cfg *cfg = qphy->cfg; 2124 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2125 void __iomem *pcs_misc = qphy->pcs_misc; 2126 u32 intr_mask; 2127 2128 if (qphy->mode == PHY_MODE_USB_HOST_SS || 2129 qphy->mode == PHY_MODE_USB_DEVICE_SS) 2130 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2131 else 2132 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2133 2134 /* Clear any pending interrupts status */ 2135 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2136 /* Writing 1 followed by 0 clears the interrupt */ 2137 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2138 2139 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2140 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2141 2142 /* Enable required PHY autonomous mode interrupts */ 2143 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2144 2145 /* Enable i/o clamp_n for autonomous mode */ 2146 if (pcs_misc) 2147 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2148 } 2149 2150 static void qmp_combo_disable_autonomous_mode(struct qmp_phy *qphy) 2151 { 2152 const struct qmp_phy_cfg *cfg = qphy->cfg; 2153 void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs; 2154 void __iomem *pcs_misc = qphy->pcs_misc; 2155 2156 /* Disable i/o clamp_n on resume for normal mode */ 2157 if (pcs_misc) 2158 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2159 2160 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2161 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2162 2163 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2164 /* Writing 1 followed by 0 clears the interrupt */ 2165 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2166 } 2167 2168 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2169 { 2170 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2171 struct qmp_phy *qphy = qmp->phys[0]; 2172 const struct qmp_phy_cfg *cfg = qphy->cfg; 2173 2174 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode); 2175 2176 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2177 if (cfg->type != PHY_TYPE_USB3) 2178 return 0; 2179 2180 if (!qmp->init_count) { 2181 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2182 return 0; 2183 } 2184 2185 qmp_combo_enable_autonomous_mode(qphy); 2186 2187 clk_disable_unprepare(qphy->pipe_clk); 2188 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2189 2190 return 0; 2191 } 2192 2193 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2194 { 2195 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2196 struct qmp_phy *qphy = qmp->phys[0]; 2197 const struct qmp_phy_cfg *cfg = qphy->cfg; 2198 int ret = 0; 2199 2200 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode); 2201 2202 /* Supported only for USB3 PHY and luckily USB3 is the first phy */ 2203 if (cfg->type != PHY_TYPE_USB3) 2204 return 0; 2205 2206 if (!qmp->init_count) { 2207 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2208 return 0; 2209 } 2210 2211 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2212 if (ret) 2213 return ret; 2214 2215 ret = clk_prepare_enable(qphy->pipe_clk); 2216 if (ret) { 2217 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2218 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2219 return ret; 2220 } 2221 2222 qmp_combo_disable_autonomous_mode(qphy); 2223 2224 return 0; 2225 } 2226 2227 static int qmp_combo_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2228 { 2229 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2230 int num = cfg->num_vregs; 2231 int ret, i; 2232 2233 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2234 if (!qmp->vregs) 2235 return -ENOMEM; 2236 2237 for (i = 0; i < num; i++) 2238 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2239 2240 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2241 if (ret) { 2242 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2243 return ret; 2244 } 2245 2246 for (i = 0; i < num; i++) { 2247 ret = regulator_set_load(qmp->vregs[i].consumer, 2248 cfg->vreg_list[i].enable_load); 2249 if (ret) { 2250 dev_err(dev, "failed to set load at %s\n", 2251 qmp->vregs[i].supply); 2252 return ret; 2253 } 2254 } 2255 2256 return 0; 2257 } 2258 2259 static int qmp_combo_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2260 { 2261 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2262 int i; 2263 int ret; 2264 2265 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2266 sizeof(*qmp->resets), GFP_KERNEL); 2267 if (!qmp->resets) 2268 return -ENOMEM; 2269 2270 for (i = 0; i < cfg->num_resets; i++) 2271 qmp->resets[i].id = cfg->reset_list[i]; 2272 2273 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2274 if (ret) 2275 return dev_err_probe(dev, ret, "failed to get resets\n"); 2276 2277 return 0; 2278 } 2279 2280 static int qmp_combo_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2281 { 2282 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2283 int num = cfg->num_clks; 2284 int i; 2285 2286 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2287 if (!qmp->clks) 2288 return -ENOMEM; 2289 2290 for (i = 0; i < num; i++) 2291 qmp->clks[i].id = cfg->clk_list[i]; 2292 2293 return devm_clk_bulk_get(dev, num, qmp->clks); 2294 } 2295 2296 static void phy_clk_release_provider(void *res) 2297 { 2298 of_clk_del_provider(res); 2299 } 2300 2301 /* 2302 * Register a fixed rate pipe clock. 2303 * 2304 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2305 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2306 * by the PHY driver for its operations. 2307 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2308 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2309 * Below picture shows this relationship. 2310 * 2311 * +---------------+ 2312 * | PHY block |<<---------------------------------------+ 2313 * | | | 2314 * | +-------+ | +-----+ | 2315 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2316 * clk | +-------+ | +-----+ 2317 * +---------------+ 2318 */ 2319 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2320 { 2321 struct clk_fixed_rate *fixed; 2322 struct clk_init_data init = { }; 2323 int ret; 2324 2325 ret = of_property_read_string(np, "clock-output-names", &init.name); 2326 if (ret) { 2327 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2328 return ret; 2329 } 2330 2331 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2332 if (!fixed) 2333 return -ENOMEM; 2334 2335 init.ops = &clk_fixed_rate_ops; 2336 2337 /* controllers using QMP phys use 125MHz pipe clock interface */ 2338 fixed->fixed_rate = 125000000; 2339 fixed->hw.init = &init; 2340 2341 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2342 if (ret) 2343 return ret; 2344 2345 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2346 if (ret) 2347 return ret; 2348 2349 /* 2350 * Roll a devm action because the clock provider is the child node, but 2351 * the child node is not actually a device. 2352 */ 2353 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2354 } 2355 2356 /* 2357 * Display Port PLL driver block diagram for branch clocks 2358 * 2359 * +------------------------------+ 2360 * | DP_VCO_CLK | 2361 * | | 2362 * | +-------------------+ | 2363 * | | (DP PLL/VCO) | | 2364 * | +---------+---------+ | 2365 * | v | 2366 * | +----------+-----------+ | 2367 * | | hsclk_divsel_clk_src | | 2368 * | +----------+-----------+ | 2369 * +------------------------------+ 2370 * | 2371 * +---------<---------v------------>----------+ 2372 * | | 2373 * +--------v----------------+ | 2374 * | dp_phy_pll_link_clk | | 2375 * | link_clk | | 2376 * +--------+----------------+ | 2377 * | | 2378 * | | 2379 * v v 2380 * Input to DISPCC block | 2381 * for link clk, crypto clk | 2382 * and interface clock | 2383 * | 2384 * | 2385 * +--------<------------+-----------------+---<---+ 2386 * | | | 2387 * +----v---------+ +--------v-----+ +--------v------+ 2388 * | vco_divided | | vco_divided | | vco_divided | 2389 * | _clk_src | | _clk_src | | _clk_src | 2390 * | | | | | | 2391 * |divsel_six | | divsel_two | | divsel_four | 2392 * +-------+------+ +-----+--------+ +--------+------+ 2393 * | | | 2394 * v---->----------v-------------<------v 2395 * | 2396 * +----------+-----------------+ 2397 * | dp_phy_pll_vco_div_clk | 2398 * +---------+------------------+ 2399 * | 2400 * v 2401 * Input to DISPCC block 2402 * for DP pixel clock 2403 * 2404 */ 2405 static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 2406 struct clk_rate_request *req) 2407 { 2408 switch (req->rate) { 2409 case 1620000000UL / 2: 2410 case 2700000000UL / 2: 2411 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2412 return 0; 2413 default: 2414 return -EINVAL; 2415 } 2416 } 2417 2418 static unsigned long 2419 qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2420 { 2421 const struct qmp_phy_dp_clks *dp_clks; 2422 const struct qmp_phy *qphy; 2423 const struct phy_configure_opts_dp *dp_opts; 2424 2425 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw); 2426 qphy = dp_clks->qphy; 2427 dp_opts = &qphy->dp_opts; 2428 2429 switch (dp_opts->link_rate) { 2430 case 1620: 2431 return 1620000000UL / 2; 2432 case 2700: 2433 return 2700000000UL / 2; 2434 case 5400: 2435 return 5400000000UL / 4; 2436 case 8100: 2437 return 8100000000UL / 6; 2438 default: 2439 return 0; 2440 } 2441 } 2442 2443 static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = { 2444 .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate, 2445 .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate, 2446 }; 2447 2448 static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw, 2449 struct clk_rate_request *req) 2450 { 2451 switch (req->rate) { 2452 case 162000000: 2453 case 270000000: 2454 case 540000000: 2455 case 810000000: 2456 return 0; 2457 default: 2458 return -EINVAL; 2459 } 2460 } 2461 2462 static unsigned long 2463 qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2464 { 2465 const struct qmp_phy_dp_clks *dp_clks; 2466 const struct qmp_phy *qphy; 2467 const struct phy_configure_opts_dp *dp_opts; 2468 2469 dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw); 2470 qphy = dp_clks->qphy; 2471 dp_opts = &qphy->dp_opts; 2472 2473 switch (dp_opts->link_rate) { 2474 case 1620: 2475 case 2700: 2476 case 5400: 2477 case 8100: 2478 return dp_opts->link_rate * 100000; 2479 default: 2480 return 0; 2481 } 2482 } 2483 2484 static const struct clk_ops qcom_qmp_dp_link_clk_ops = { 2485 .determine_rate = qcom_qmp_dp_link_clk_determine_rate, 2486 .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate, 2487 }; 2488 2489 static struct clk_hw * 2490 qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 2491 { 2492 struct qmp_phy_dp_clks *dp_clks = data; 2493 unsigned int idx = clkspec->args[0]; 2494 2495 if (idx >= 2) { 2496 pr_err("%s: invalid index %u\n", __func__, idx); 2497 return ERR_PTR(-EINVAL); 2498 } 2499 2500 if (idx == 0) 2501 return &dp_clks->dp_link_hw; 2502 2503 return &dp_clks->dp_pixel_hw; 2504 } 2505 2506 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy, 2507 struct device_node *np) 2508 { 2509 struct clk_init_data init = { }; 2510 struct qmp_phy_dp_clks *dp_clks; 2511 char name[64]; 2512 int ret; 2513 2514 dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL); 2515 if (!dp_clks) 2516 return -ENOMEM; 2517 2518 dp_clks->qphy = qphy; 2519 qphy->dp_clks = dp_clks; 2520 2521 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 2522 init.ops = &qcom_qmp_dp_link_clk_ops; 2523 init.name = name; 2524 dp_clks->dp_link_hw.init = &init; 2525 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw); 2526 if (ret) 2527 return ret; 2528 2529 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 2530 init.ops = &qcom_qmp_dp_pixel_clk_ops; 2531 init.name = name; 2532 dp_clks->dp_pixel_hw.init = &init; 2533 ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw); 2534 if (ret) 2535 return ret; 2536 2537 ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks); 2538 if (ret) 2539 return ret; 2540 2541 /* 2542 * Roll a devm action because the clock provider is the child node, but 2543 * the child node is not actually a device. 2544 */ 2545 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2546 } 2547 2548 static const struct phy_ops qmp_combo_usb_ops = { 2549 .init = qmp_combo_enable, 2550 .exit = qmp_combo_disable, 2551 .set_mode = qmp_combo_set_mode, 2552 .owner = THIS_MODULE, 2553 }; 2554 2555 static const struct phy_ops qmp_combo_dp_ops = { 2556 .init = qmp_combo_init, 2557 .configure = qcom_qmp_dp_phy_configure, 2558 .power_on = qmp_combo_power_on, 2559 .calibrate = qcom_qmp_dp_phy_calibrate, 2560 .power_off = qmp_combo_power_off, 2561 .exit = qmp_combo_exit, 2562 .set_mode = qmp_combo_set_mode, 2563 .owner = THIS_MODULE, 2564 }; 2565 2566 static int qmp_combo_create(struct device *dev, struct device_node *np, int id, 2567 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2568 { 2569 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2570 struct phy *generic_phy; 2571 struct qmp_phy *qphy; 2572 const struct phy_ops *ops; 2573 int ret; 2574 2575 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2576 if (!qphy) 2577 return -ENOMEM; 2578 2579 qphy->cfg = cfg; 2580 qphy->serdes = serdes; 2581 /* 2582 * Get memory resources for each PHY: 2583 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2584 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2585 * For single lane PHYs: pcs_misc (optional) -> 3. 2586 */ 2587 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2588 if (IS_ERR(qphy->tx)) 2589 return PTR_ERR(qphy->tx); 2590 2591 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2592 if (IS_ERR(qphy->rx)) 2593 return PTR_ERR(qphy->rx); 2594 2595 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2596 if (IS_ERR(qphy->pcs)) 2597 return PTR_ERR(qphy->pcs); 2598 2599 if (cfg->pcs_usb_offset) 2600 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset; 2601 2602 if (cfg->lanes >= 2) { 2603 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2604 if (IS_ERR(qphy->tx2)) 2605 return PTR_ERR(qphy->tx2); 2606 2607 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2608 if (IS_ERR(qphy->rx2)) 2609 return PTR_ERR(qphy->rx2); 2610 2611 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2612 } else { 2613 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2614 } 2615 2616 if (IS_ERR(qphy->pcs_misc)) { 2617 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2618 qphy->pcs_misc = NULL; 2619 } 2620 2621 /* 2622 * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3 2623 * based phys, so they essentially have pipe clock. So, 2624 * we return error in case phy is USB3 or PIPE type. 2625 * Otherwise, we initialize pipe clock to NULL for 2626 * all phys that don't need this. 2627 */ 2628 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2629 if (IS_ERR(qphy->pipe_clk)) { 2630 if (cfg->type == PHY_TYPE_USB3) 2631 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2632 "failed to get lane%d pipe_clk\n", 2633 id); 2634 qphy->pipe_clk = NULL; 2635 } 2636 2637 if (cfg->type == PHY_TYPE_DP) 2638 ops = &qmp_combo_dp_ops; 2639 else 2640 ops = &qmp_combo_usb_ops; 2641 2642 generic_phy = devm_phy_create(dev, np, ops); 2643 if (IS_ERR(generic_phy)) { 2644 ret = PTR_ERR(generic_phy); 2645 dev_err(dev, "failed to create qphy %d\n", ret); 2646 return ret; 2647 } 2648 2649 qphy->phy = generic_phy; 2650 qphy->qmp = qmp; 2651 qmp->phys[id] = qphy; 2652 phy_set_drvdata(generic_phy, qphy); 2653 2654 return 0; 2655 } 2656 2657 static const struct of_device_id qmp_combo_of_match_table[] = { 2658 { 2659 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 2660 .data = &sc7180_usb3dpphy_cfg, 2661 }, 2662 { 2663 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 2664 .data = &sdm845_usb3dpphy_cfg, 2665 }, 2666 { 2667 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 2668 .data = &sm8250_usb3dpphy_cfg, 2669 }, 2670 { 2671 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 2672 .data = &sc8180x_usb3dpphy_cfg, 2673 }, 2674 { 2675 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 2676 .data = &sc8280xp_usb43dpphy_combo_cfg, 2677 }, 2678 { } 2679 }; 2680 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 2681 2682 static const struct dev_pm_ops qmp_combo_pm_ops = { 2683 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2684 qmp_combo_runtime_resume, NULL) 2685 }; 2686 2687 static int qmp_combo_probe(struct platform_device *pdev) 2688 { 2689 struct qcom_qmp *qmp; 2690 struct device *dev = &pdev->dev; 2691 struct device_node *child; 2692 struct phy_provider *phy_provider; 2693 void __iomem *serdes; 2694 void __iomem *usb_serdes; 2695 void __iomem *dp_serdes = NULL; 2696 const struct qmp_phy_combo_cfg *combo_cfg = NULL; 2697 const struct qmp_phy_cfg *cfg = NULL; 2698 const struct qmp_phy_cfg *usb_cfg = NULL; 2699 const struct qmp_phy_cfg *dp_cfg = NULL; 2700 int num, id, expected_phys; 2701 int ret; 2702 2703 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2704 if (!qmp) 2705 return -ENOMEM; 2706 2707 qmp->dev = dev; 2708 dev_set_drvdata(dev, qmp); 2709 2710 combo_cfg = of_device_get_match_data(dev); 2711 if (!combo_cfg) 2712 return -EINVAL; 2713 2714 usb_cfg = combo_cfg->usb_cfg; 2715 cfg = usb_cfg; /* Setup clks and regulators */ 2716 2717 usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0); 2718 if (IS_ERR(serdes)) 2719 return PTR_ERR(serdes); 2720 2721 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2722 if (IS_ERR(qmp->dp_com)) 2723 return PTR_ERR(qmp->dp_com); 2724 2725 dp_serdes = devm_platform_ioremap_resource(pdev, 2); 2726 if (IS_ERR(dp_serdes)) 2727 return PTR_ERR(dp_serdes); 2728 2729 dp_cfg = combo_cfg->dp_cfg; 2730 expected_phys = 2; 2731 2732 mutex_init(&qmp->phy_mutex); 2733 2734 ret = qmp_combo_clk_init(dev, cfg); 2735 if (ret) 2736 return ret; 2737 2738 ret = qmp_combo_reset_init(dev, cfg); 2739 if (ret) 2740 return ret; 2741 2742 ret = qmp_combo_vreg_init(dev, cfg); 2743 if (ret) 2744 return ret; 2745 2746 num = of_get_available_child_count(dev->of_node); 2747 /* do we have a rogue child node ? */ 2748 if (num > expected_phys) 2749 return -EINVAL; 2750 2751 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2752 if (!qmp->phys) 2753 return -ENOMEM; 2754 2755 pm_runtime_set_active(dev); 2756 ret = devm_pm_runtime_enable(dev); 2757 if (ret) 2758 return ret; 2759 /* 2760 * Prevent runtime pm from being ON by default. Users can enable 2761 * it using power/control in sysfs. 2762 */ 2763 pm_runtime_forbid(dev); 2764 2765 id = 0; 2766 for_each_available_child_of_node(dev->of_node, child) { 2767 if (of_node_name_eq(child, "dp-phy")) { 2768 cfg = dp_cfg; 2769 serdes = dp_serdes; 2770 2771 /* Create per-lane phy */ 2772 ret = qmp_combo_create(dev, child, id, serdes, cfg); 2773 if (ret) { 2774 dev_err(dev, "failed to create lane%d phy, %d\n", 2775 id, ret); 2776 goto err_node_put; 2777 } 2778 2779 ret = phy_dp_clks_register(qmp, qmp->phys[id], child); 2780 if (ret) { 2781 dev_err(qmp->dev, 2782 "failed to register DP clock source\n"); 2783 goto err_node_put; 2784 } 2785 } else if (of_node_name_eq(child, "usb3-phy")) { 2786 cfg = usb_cfg; 2787 serdes = usb_serdes; 2788 2789 /* Create per-lane phy */ 2790 ret = qmp_combo_create(dev, child, id, serdes, cfg); 2791 if (ret) { 2792 dev_err(dev, "failed to create lane%d phy, %d\n", 2793 id, ret); 2794 goto err_node_put; 2795 } 2796 2797 /* 2798 * Register the pipe clock provided by phy. 2799 * See function description to see details of this pipe clock. 2800 */ 2801 ret = phy_pipe_clk_register(qmp, child); 2802 if (ret) { 2803 dev_err(qmp->dev, 2804 "failed to register pipe clock source\n"); 2805 goto err_node_put; 2806 } 2807 } 2808 2809 id++; 2810 } 2811 2812 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2813 2814 return PTR_ERR_OR_ZERO(phy_provider); 2815 2816 err_node_put: 2817 of_node_put(child); 2818 return ret; 2819 } 2820 2821 static struct platform_driver qmp_combo_driver = { 2822 .probe = qmp_combo_probe, 2823 .driver = { 2824 .name = "qcom-qmp-combo-phy", 2825 .pm = &qmp_combo_pm_ops, 2826 .of_match_table = qmp_combo_of_match_table, 2827 }, 2828 }; 2829 2830 module_platform_driver(qmp_combo_driver); 2831 2832 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2833 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 2834 MODULE_LICENSE("GPL v2"); 2835