1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/bridge/aux-bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp-common.h" 29 30 #include "phy-qcom-qmp.h" 31 #include "phy-qcom-qmp-pcs-misc-v3.h" 32 #include "phy-qcom-qmp-pcs-usb-v4.h" 33 #include "phy-qcom-qmp-pcs-usb-v5.h" 34 #include "phy-qcom-qmp-pcs-usb-v6.h" 35 36 #include "phy-qcom-qmp-dp-com-v3.h" 37 38 #include "phy-qcom-qmp-dp-phy.h" 39 #include "phy-qcom-qmp-dp-phy-v3.h" 40 #include "phy-qcom-qmp-dp-phy-v4.h" 41 #include "phy-qcom-qmp-dp-phy-v5.h" 42 #include "phy-qcom-qmp-dp-phy-v6.h" 43 44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45 /* DP PHY soft reset */ 46 #define SW_DPPHY_RESET BIT(0) 47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_DPPHY_RESET_MUX BIT(1) 49 /* USB3 PHY soft reset */ 50 #define SW_USB3PHY_RESET BIT(2) 51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52 #define SW_USB3PHY_RESET_MUX BIT(3) 53 54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55 #define USB3_MODE BIT(0) /* enables USB3 mode */ 56 #define DP_MODE BIT(1) /* enables DP mode */ 57 58 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 59 #define SW_PORTSELECT_VAL BIT(0) 60 #define SW_PORTSELECT_MUX BIT(1) 61 62 #define PHY_INIT_COMPLETE_TIMEOUT 10000 63 64 /* set of registers with offsets different per-PHY */ 65 enum qphy_reg_layout { 66 /* PCS registers */ 67 QPHY_SW_RESET, 68 QPHY_START_CTRL, 69 QPHY_PCS_STATUS, 70 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 71 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 72 QPHY_PCS_POWER_DOWN_CONTROL, 73 74 QPHY_COM_RESETSM_CNTRL, 75 QPHY_COM_C_READY_STATUS, 76 QPHY_COM_CMN_STATUS, 77 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 78 79 QPHY_DP_PHY_STATUS, 80 QPHY_DP_PHY_VCO_DIV, 81 82 QPHY_TX_TX_POL_INV, 83 QPHY_TX_TX_DRV_LVL, 84 QPHY_TX_TX_EMP_POST1_LVL, 85 QPHY_TX_HIGHZ_DRVR_EN, 86 QPHY_TX_TRANSCEIVER_BIAS_EN, 87 88 /* Keep last to ensure regs_layout arrays are properly initialized */ 89 QPHY_LAYOUT_SIZE 90 }; 91 92 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 93 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 94 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 95 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 96 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 97 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 98 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 99 100 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 101 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 102 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 103 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 104 105 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 106 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 107 108 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 109 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 110 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 111 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 112 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 113 }; 114 115 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 117 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 118 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 119 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 120 121 /* In PCS_USB */ 122 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 123 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 124 125 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 126 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 127 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 128 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 129 130 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 131 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 132 133 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 134 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 135 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 136 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 137 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 138 }; 139 140 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 141 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 142 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 143 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 144 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 145 146 /* In PCS_USB */ 147 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 148 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 149 150 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 151 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 152 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 153 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 154 155 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 156 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 157 158 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 159 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 160 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 161 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 162 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 163 }; 164 165 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 166 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 167 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 168 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 169 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 170 171 /* In PCS_USB */ 172 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 173 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 174 175 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 176 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 177 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 178 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 179 180 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 181 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 182 183 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 184 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 185 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 186 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 187 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 188 }; 189 190 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 191 [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET, 192 [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL, 193 [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1, 194 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL, 195 196 /* In PCS_USB */ 197 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 198 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 199 200 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 201 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 202 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 203 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 204 205 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 206 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 207 208 [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV, 209 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL, 210 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, 211 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, 212 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, 213 }; 214 215 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 252 }; 253 254 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 255 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 256 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 257 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 258 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 259 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 260 }; 261 262 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 284 }; 285 286 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 294 }; 295 296 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 304 }; 305 306 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 314 }; 315 316 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 324 }; 325 326 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 327 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 328 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 329 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 330 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 331 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 333 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 342 }; 343 344 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 345 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 346 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 347 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 348 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 349 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 354 }; 355 356 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 357 /* FLL settings */ 358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 363 364 /* Lock Det settings */ 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 369 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 389 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 401 }; 402 403 static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = { 404 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), 405 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), 406 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 407 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 408 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 409 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 410 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 411 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 412 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), 413 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), 414 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 415 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), 416 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), 417 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 418 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 419 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 420 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 421 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 422 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 423 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 424 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), 425 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), 426 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), 432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), 433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), 435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), 448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 452 }; 453 454 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 457 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 458 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 459 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 460 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 465 }; 466 467 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 468 /* FLL settings */ 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 474 475 /* Lock Det settings */ 476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 480 481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 500 501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 513 514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 516 }; 517 518 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 519 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 520 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 521 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 522 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 523 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 524 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 525 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 526 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 527 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 528 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 529 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 530 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 531 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 532 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 548 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 549 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 550 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 558 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 559 }; 560 561 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 562 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 563 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 564 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 565 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 566 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 567 }; 568 569 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 606 }; 607 608 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 609 /* Lock Det settings */ 610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 612 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 613 614 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 617 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 618 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 619 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 620 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 621 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 622 }; 623 624 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 625 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 626 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 627 }; 628 629 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 630 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 631 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 632 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 633 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 634 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 635 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 636 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 637 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 638 }; 639 640 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 661 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 662 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 663 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 664 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 679 }; 680 681 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 694 }; 695 696 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 699 }; 700 701 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 702 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 703 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 704 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 705 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 706 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 707 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 708 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 709 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 710 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 711 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 712 }; 713 714 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 739 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 740 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 744 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 745 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 746 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 747 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 748 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 753 }; 754 755 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 756 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 757 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 758 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 759 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 762 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 763 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 764 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 765 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 766 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 767 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 769 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 770 }; 771 772 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 773 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 774 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 775 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 776 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 777 }; 778 779 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 787 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 793 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 794 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 795 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 796 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 800 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 801 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 802 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 828 }; 829 830 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 831 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 832 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 833 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 834 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 835 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 836 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 837 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 838 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 839 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 840 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 841 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 842 }; 843 844 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 845 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 846 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 847 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 848 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 849 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 850 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 851 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 852 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 853 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 854 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 855 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 856 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 857 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 858 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 859 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 860 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 861 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 862 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 863 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 864 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 865 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 866 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 867 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 868 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 869 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 870 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 871 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 872 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 873 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 874 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 875 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 876 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 877 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 878 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 879 880 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 881 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 882 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 883 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 884 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 885 886 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 887 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 888 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 889 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 890 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 891 }; 892 893 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 894 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 895 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 896 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 897 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 898 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 899 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 900 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 901 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 902 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 903 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 904 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 905 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 906 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 907 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 908 }; 909 910 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 911 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 912 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 913 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 914 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 915 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 916 }; 917 918 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 923 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 924 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 925 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 938 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 939 }; 940 941 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 942 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 943 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 944 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 945 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 946 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 947 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 948 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 949 }; 950 951 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 952 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 959 }; 960 961 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 969 }; 970 971 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 979 }; 980 981 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 982 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 983 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 984 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 985 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 986 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 987 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 988 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 989 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 990 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 991 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 992 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 993 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 994 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 995 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 996 }; 997 998 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1022 }; 1023 1024 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 1025 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 1026 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1034 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 1036 }; 1037 1038 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 1039 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1051 }; 1052 1053 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1055 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1056 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1060 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1061 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1062 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1063 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1064 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1065 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1066 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1067 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1068 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1071 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1073 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1074 }; 1075 1076 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = { 1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1078 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1079 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1080 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1090 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1091 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1092 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1093 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1094 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1095 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1096 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1097 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1098 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1099 }; 1100 1101 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1102 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1103 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1104 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1105 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1106 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1107 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1108 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1109 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1110 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1111 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1112 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1113 }; 1114 1115 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = { 1116 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40), 1117 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00), 1118 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff), 1119 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f), 1120 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03), 1121 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1122 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1123 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1124 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1125 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1), 1126 }; 1127 1128 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1129 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1130 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1131 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1132 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1133 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1134 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1135 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1136 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1137 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1138 }; 1139 1140 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1141 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1142 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1143 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1144 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1145 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1146 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1147 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1148 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1149 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1150 }; 1151 1152 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1153 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1154 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1155 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1156 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1157 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1158 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1159 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1160 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1161 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1162 }; 1163 1164 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1165 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1166 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1167 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1168 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1169 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1170 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1171 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1172 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1173 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1174 }; 1175 1176 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = { 1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1184 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1185 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1191 }; 1192 1193 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = { 1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1196 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1208 }; 1209 1210 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = { 1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1225 }; 1226 1227 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = { 1228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1235 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1236 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1242 }; 1243 1244 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1292 }; 1293 1294 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1295 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1300 }; 1301 1302 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1303 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1337 }; 1338 1339 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1340 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1341 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1342 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1343 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1344 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1345 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1346 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1347 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1348 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1349 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1350 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1351 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1352 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1353 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1354 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1355 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1356 }; 1357 1358 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1361 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1362 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1363 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1380 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1381 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1382 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1383 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1384 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1385 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1386 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1387 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1388 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1389 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1390 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1391 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1392 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1393 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1394 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1395 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1396 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1397 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1398 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1399 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1400 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1401 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1402 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1403 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1404 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1405 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1406 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1407 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1408 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1409 }; 1410 1411 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1412 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1413 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1414 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1415 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1416 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1417 }; 1418 1419 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1420 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1421 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1422 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1423 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1424 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1425 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1432 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1433 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1435 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1443 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1444 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1445 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1446 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1447 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1448 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1451 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1452 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1453 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1454 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1455 }; 1456 1457 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1458 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1459 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1460 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1461 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89), 1462 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1463 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1464 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1465 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55), 1466 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a), 1467 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1468 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1469 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1470 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b), 1471 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), 1472 }; 1473 1474 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1475 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1476 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1477 }; 1478 1479 /* list of regulators */ 1480 struct qmp_regulator_data { 1481 const char *name; 1482 unsigned int enable_load; 1483 }; 1484 1485 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1486 { .name = "vdda-phy", .enable_load = 21800 }, 1487 { .name = "vdda-pll", .enable_load = 36000 }, 1488 }; 1489 1490 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1491 { 0x00, 0x0c, 0x15, 0x1a }, 1492 { 0x02, 0x0e, 0x16, 0xff }, 1493 { 0x02, 0x11, 0xff, 0xff }, 1494 { 0x04, 0xff, 0xff, 0xff } 1495 }; 1496 1497 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1498 { 0x02, 0x12, 0x16, 0x1a }, 1499 { 0x09, 0x19, 0x1f, 0xff }, 1500 { 0x10, 0x1f, 0xff, 0xff }, 1501 { 0x1f, 0xff, 0xff, 0xff } 1502 }; 1503 1504 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1505 { 0x00, 0x0c, 0x14, 0x19 }, 1506 { 0x00, 0x0b, 0x12, 0xff }, 1507 { 0x00, 0x0b, 0xff, 0xff }, 1508 { 0x04, 0xff, 0xff, 0xff } 1509 }; 1510 1511 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1512 { 0x08, 0x0f, 0x16, 0x1f }, 1513 { 0x11, 0x1e, 0x1f, 0xff }, 1514 { 0x19, 0x1f, 0xff, 0xff }, 1515 { 0x1f, 0xff, 0xff, 0xff } 1516 }; 1517 1518 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1519 { 0x00, 0x0c, 0x15, 0x1b }, 1520 { 0x02, 0x0e, 0x16, 0xff }, 1521 { 0x02, 0x11, 0xff, 0xff }, 1522 { 0x04, 0xff, 0xff, 0xff } 1523 }; 1524 1525 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1526 { 0x00, 0x0d, 0x14, 0x1a }, 1527 { 0x00, 0x0e, 0x15, 0xff }, 1528 { 0x00, 0x0d, 0xff, 0xff }, 1529 { 0x03, 0xff, 0xff, 0xff } 1530 }; 1531 1532 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1533 { 0x08, 0x0f, 0x16, 0x1f }, 1534 { 0x11, 0x1e, 0x1f, 0xff }, 1535 { 0x16, 0x1f, 0xff, 0xff }, 1536 { 0x1f, 0xff, 0xff, 0xff } 1537 }; 1538 1539 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1540 { 0x20, 0x2c, 0x35, 0x3b }, 1541 { 0x22, 0x2e, 0x36, 0xff }, 1542 { 0x22, 0x31, 0xff, 0xff }, 1543 { 0x24, 0xff, 0xff, 0xff } 1544 }; 1545 1546 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1547 { 0x22, 0x32, 0x36, 0x3a }, 1548 { 0x29, 0x39, 0x3f, 0xff }, 1549 { 0x30, 0x3f, 0xff, 0xff }, 1550 { 0x3f, 0xff, 0xff, 0xff } 1551 }; 1552 1553 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1554 { 0x20, 0x2d, 0x34, 0x3a }, 1555 { 0x20, 0x2e, 0x35, 0xff }, 1556 { 0x20, 0x2e, 0xff, 0xff }, 1557 { 0x24, 0xff, 0xff, 0xff } 1558 }; 1559 1560 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1561 { 0x28, 0x2f, 0x36, 0x3f }, 1562 { 0x31, 0x3e, 0x3f, 0xff }, 1563 { 0x36, 0x3f, 0xff, 0xff }, 1564 { 0x3f, 0xff, 0xff, 0xff } 1565 }; 1566 1567 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = { 1568 { 0x27, 0x2f, 0x36, 0x3f }, 1569 { 0x31, 0x3e, 0x3f, 0xff }, 1570 { 0x36, 0x3f, 0xff, 0xff }, 1571 { 0x3f, 0xff, 0xff, 0xff } 1572 }; 1573 1574 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1575 { 0x20, 0x2d, 0x34, 0x3a }, 1576 { 0x20, 0x2e, 0x35, 0xff }, 1577 { 0x20, 0x2e, 0xff, 0xff }, 1578 { 0x22, 0xff, 0xff, 0xff } 1579 }; 1580 1581 struct qmp_combo; 1582 1583 struct qmp_combo_offsets { 1584 u16 com; 1585 u16 txa; 1586 u16 rxa; 1587 u16 txb; 1588 u16 rxb; 1589 u16 usb3_serdes; 1590 u16 usb3_pcs_misc; 1591 u16 usb3_pcs; 1592 u16 usb3_pcs_usb; 1593 u16 dp_serdes; 1594 u16 dp_txa; 1595 u16 dp_txb; 1596 u16 dp_dp_phy; 1597 }; 1598 1599 struct qmp_phy_cfg { 1600 const struct qmp_combo_offsets *offsets; 1601 1602 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1603 const struct qmp_phy_init_tbl *serdes_tbl; 1604 int serdes_tbl_num; 1605 const struct qmp_phy_init_tbl *tx_tbl; 1606 int tx_tbl_num; 1607 const struct qmp_phy_init_tbl *rx_tbl; 1608 int rx_tbl_num; 1609 const struct qmp_phy_init_tbl *pcs_tbl; 1610 int pcs_tbl_num; 1611 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1612 int pcs_usb_tbl_num; 1613 1614 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1615 int dp_serdes_tbl_num; 1616 const struct qmp_phy_init_tbl *dp_tx_tbl; 1617 int dp_tx_tbl_num; 1618 1619 /* Init sequence for DP PHY block link rates */ 1620 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1621 int serdes_tbl_rbr_num; 1622 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1623 int serdes_tbl_hbr_num; 1624 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1625 int serdes_tbl_hbr2_num; 1626 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1627 int serdes_tbl_hbr3_num; 1628 1629 /* DP PHY swing and pre_emphasis tables */ 1630 const u8 (*swing_hbr_rbr)[4][4]; 1631 const u8 (*swing_hbr3_hbr2)[4][4]; 1632 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1633 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1634 1635 /* DP PHY callbacks */ 1636 int (*configure_dp_phy)(struct qmp_combo *qmp); 1637 void (*configure_dp_tx)(struct qmp_combo *qmp); 1638 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1639 void (*dp_aux_init)(struct qmp_combo *qmp); 1640 1641 /* resets to be requested */ 1642 const char * const *reset_list; 1643 int num_resets; 1644 /* regulators to be requested */ 1645 const struct qmp_regulator_data *vreg_list; 1646 int num_vregs; 1647 1648 /* array of registers with different offsets */ 1649 const unsigned int *regs; 1650 1651 /* true, if PHY needs delay after POWER_DOWN */ 1652 bool has_pwrdn_delay; 1653 1654 /* Offset from PCS to PCS_USB region */ 1655 unsigned int pcs_usb_offset; 1656 1657 }; 1658 1659 struct qmp_combo { 1660 struct device *dev; 1661 1662 const struct qmp_phy_cfg *cfg; 1663 1664 void __iomem *com; 1665 1666 void __iomem *serdes; 1667 void __iomem *tx; 1668 void __iomem *rx; 1669 void __iomem *pcs; 1670 void __iomem *tx2; 1671 void __iomem *rx2; 1672 void __iomem *pcs_misc; 1673 void __iomem *pcs_usb; 1674 1675 void __iomem *dp_serdes; 1676 void __iomem *dp_tx; 1677 void __iomem *dp_tx2; 1678 void __iomem *dp_dp_phy; 1679 1680 struct clk *pipe_clk; 1681 struct clk_bulk_data *clks; 1682 int num_clks; 1683 struct reset_control_bulk_data *resets; 1684 struct regulator_bulk_data *vregs; 1685 1686 struct mutex phy_mutex; 1687 int init_count; 1688 1689 struct phy *usb_phy; 1690 enum phy_mode mode; 1691 unsigned int usb_init_count; 1692 1693 struct phy *dp_phy; 1694 unsigned int dp_aux_cfg; 1695 struct phy_configure_opts_dp dp_opts; 1696 unsigned int dp_init_count; 1697 1698 struct clk_fixed_rate pipe_clk_fixed; 1699 struct clk_hw dp_link_hw; 1700 struct clk_hw dp_pixel_hw; 1701 1702 struct typec_switch_dev *sw; 1703 enum typec_orientation orientation; 1704 }; 1705 1706 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1707 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1708 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1709 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1710 1711 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1712 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1713 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1714 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1715 1716 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1717 { 1718 u32 reg; 1719 1720 reg = readl(base + offset); 1721 reg |= val; 1722 writel(reg, base + offset); 1723 1724 /* ensure that above write is through */ 1725 readl(base + offset); 1726 } 1727 1728 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1729 { 1730 u32 reg; 1731 1732 reg = readl(base + offset); 1733 reg &= ~val; 1734 writel(reg, base + offset); 1735 1736 /* ensure that above write is through */ 1737 readl(base + offset); 1738 } 1739 1740 /* list of clocks required by phy */ 1741 static const char * const qmp_combo_phy_clk_l[] = { 1742 "aux", "cfg_ahb", "ref", "com_aux", 1743 }; 1744 1745 /* list of resets */ 1746 static const char * const msm8996_usb3phy_reset_l[] = { 1747 "phy", "common", 1748 }; 1749 1750 static const char * const sc7180_usb3phy_reset_l[] = { 1751 "phy", 1752 }; 1753 1754 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1755 .com = 0x0000, 1756 .txa = 0x1200, 1757 .rxa = 0x1400, 1758 .txb = 0x1600, 1759 .rxb = 0x1800, 1760 .usb3_serdes = 0x1000, 1761 .usb3_pcs_misc = 0x1a00, 1762 .usb3_pcs = 0x1c00, 1763 .usb3_pcs_usb = 0x1f00, 1764 .dp_serdes = 0x2000, 1765 .dp_txa = 0x2200, 1766 .dp_txb = 0x2600, 1767 .dp_dp_phy = 0x2a00, 1768 }; 1769 1770 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1771 .com = 0x0000, 1772 .txa = 0x0400, 1773 .rxa = 0x0600, 1774 .txb = 0x0a00, 1775 .rxb = 0x0c00, 1776 .usb3_serdes = 0x1000, 1777 .usb3_pcs_misc = 0x1200, 1778 .usb3_pcs = 0x1400, 1779 .usb3_pcs_usb = 0x1700, 1780 .dp_serdes = 0x2000, 1781 .dp_dp_phy = 0x2200, 1782 }; 1783 1784 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { 1785 .offsets = &qmp_combo_offsets_v3, 1786 1787 .serdes_tbl = sar2130p_usb3_serdes_tbl, 1788 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 1789 .tx_tbl = sm8550_usb3_tx_tbl, 1790 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1791 .rx_tbl = sm8550_usb3_rx_tbl, 1792 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1793 .pcs_tbl = sm8550_usb3_pcs_tbl, 1794 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1795 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1796 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1797 1798 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1799 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1800 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1801 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1802 1803 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1804 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1805 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1806 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1807 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1808 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1809 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1810 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1811 1812 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1813 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1814 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1815 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1816 1817 .dp_aux_init = qmp_v4_dp_aux_init, 1818 .configure_dp_tx = qmp_v4_configure_dp_tx, 1819 .configure_dp_phy = qmp_v4_configure_dp_phy, 1820 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1821 1822 .regs = qmp_v6_usb3phy_regs_layout, 1823 .reset_list = msm8996_usb3phy_reset_l, 1824 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1825 .vreg_list = qmp_phy_vreg_l, 1826 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1827 }; 1828 1829 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1830 .offsets = &qmp_combo_offsets_v3, 1831 1832 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1833 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1834 .tx_tbl = qmp_v3_usb3_tx_tbl, 1835 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1836 .rx_tbl = qmp_v3_usb3_rx_tbl, 1837 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1838 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1839 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1840 1841 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1842 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1843 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1844 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1845 1846 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1847 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1848 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1849 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1850 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1851 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1852 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1853 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1854 1855 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1856 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1857 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1858 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1859 1860 .dp_aux_init = qmp_v3_dp_aux_init, 1861 .configure_dp_tx = qmp_v3_configure_dp_tx, 1862 .configure_dp_phy = qmp_v3_configure_dp_phy, 1863 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1864 1865 .reset_list = sc7180_usb3phy_reset_l, 1866 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1867 .vreg_list = qmp_phy_vreg_l, 1868 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1869 .regs = qmp_v3_usb3phy_regs_layout, 1870 1871 .has_pwrdn_delay = true, 1872 }; 1873 1874 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1875 .offsets = &qmp_combo_offsets_v3, 1876 1877 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1878 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1879 .tx_tbl = qmp_v3_usb3_tx_tbl, 1880 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1881 .rx_tbl = qmp_v3_usb3_rx_tbl, 1882 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1883 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1884 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1885 1886 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1887 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1888 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1889 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1890 1891 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1892 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1893 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1894 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1895 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1896 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1897 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1898 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1899 1900 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1901 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1902 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1903 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1904 1905 .dp_aux_init = qmp_v3_dp_aux_init, 1906 .configure_dp_tx = qmp_v3_configure_dp_tx, 1907 .configure_dp_phy = qmp_v3_configure_dp_phy, 1908 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1909 1910 .reset_list = msm8996_usb3phy_reset_l, 1911 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1912 .vreg_list = qmp_phy_vreg_l, 1913 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1914 .regs = qmp_v3_usb3phy_regs_layout, 1915 1916 .has_pwrdn_delay = true, 1917 }; 1918 1919 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1920 .offsets = &qmp_combo_offsets_v3, 1921 1922 .serdes_tbl = sm8150_usb3_serdes_tbl, 1923 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1924 .tx_tbl = sm8150_usb3_tx_tbl, 1925 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1926 .rx_tbl = sm8150_usb3_rx_tbl, 1927 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1928 .pcs_tbl = sm8150_usb3_pcs_tbl, 1929 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1930 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1931 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1932 1933 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1934 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1935 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1936 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1937 1938 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1939 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1940 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1941 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1942 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1943 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1944 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1945 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1946 1947 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1948 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1949 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1950 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1951 1952 .dp_aux_init = qmp_v4_dp_aux_init, 1953 .configure_dp_tx = qmp_v4_configure_dp_tx, 1954 .configure_dp_phy = qmp_v4_configure_dp_phy, 1955 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1956 1957 .reset_list = msm8996_usb3phy_reset_l, 1958 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1959 .vreg_list = qmp_phy_vreg_l, 1960 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1961 .regs = qmp_v45_usb3phy_regs_layout, 1962 .pcs_usb_offset = 0x300, 1963 1964 .has_pwrdn_delay = true, 1965 }; 1966 1967 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1968 .offsets = &qmp_combo_offsets_v5, 1969 1970 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1971 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1972 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1973 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1974 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1975 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1976 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1977 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1978 1979 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1980 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1981 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1982 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1983 1984 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1985 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1986 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1987 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1988 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1989 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1990 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1991 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1992 1993 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1994 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1995 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1996 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1997 1998 .dp_aux_init = qmp_v4_dp_aux_init, 1999 .configure_dp_tx = qmp_v4_configure_dp_tx, 2000 .configure_dp_phy = qmp_v4_configure_dp_phy, 2001 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2002 2003 .reset_list = msm8996_usb3phy_reset_l, 2004 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2005 .vreg_list = qmp_phy_vreg_l, 2006 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2007 .regs = qmp_v5_5nm_usb3phy_regs_layout, 2008 }; 2009 2010 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 2011 .offsets = &qmp_combo_offsets_v5, 2012 2013 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 2014 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 2015 .tx_tbl = x1e80100_usb43dp_tx_tbl, 2016 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 2017 .rx_tbl = x1e80100_usb43dp_rx_tbl, 2018 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 2019 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 2020 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 2021 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 2022 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 2023 2024 .dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl, 2025 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl), 2026 .dp_tx_tbl = qmp_v6_n4_dp_tx_tbl, 2027 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl), 2028 2029 .serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr, 2030 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr), 2031 .serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr, 2032 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr), 2033 .serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2, 2034 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2), 2035 .serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3, 2036 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3), 2037 2038 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2039 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2040 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2041 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2042 2043 .dp_aux_init = qmp_v4_dp_aux_init, 2044 .configure_dp_tx = qmp_v4_configure_dp_tx, 2045 .configure_dp_phy = qmp_v4_configure_dp_phy, 2046 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2047 2048 .reset_list = msm8996_usb3phy_reset_l, 2049 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2050 .vreg_list = qmp_phy_vreg_l, 2051 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2052 .regs = qmp_v6_n4_usb3phy_regs_layout, 2053 }; 2054 2055 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 2056 .offsets = &qmp_combo_offsets_v3, 2057 2058 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2059 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2060 .tx_tbl = qmp_v3_usb3_tx_tbl, 2061 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2062 .rx_tbl = sm6350_usb3_rx_tbl, 2063 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 2064 .pcs_tbl = sm6350_usb3_pcs_tbl, 2065 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 2066 2067 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2068 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2069 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2070 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2071 2072 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2073 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2074 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2075 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2076 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2077 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2078 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2079 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2080 2081 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2082 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2083 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2084 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2085 2086 .dp_aux_init = qmp_v3_dp_aux_init, 2087 .configure_dp_tx = qmp_v3_configure_dp_tx, 2088 .configure_dp_phy = qmp_v3_configure_dp_phy, 2089 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2090 2091 .reset_list = msm8996_usb3phy_reset_l, 2092 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2093 .vreg_list = qmp_phy_vreg_l, 2094 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2095 .regs = qmp_v3_usb3phy_regs_layout, 2096 }; 2097 2098 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 2099 .offsets = &qmp_combo_offsets_v3, 2100 2101 .serdes_tbl = sm8150_usb3_serdes_tbl, 2102 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2103 .tx_tbl = sm8250_usb3_tx_tbl, 2104 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 2105 .rx_tbl = sm8250_usb3_rx_tbl, 2106 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 2107 .pcs_tbl = sm8250_usb3_pcs_tbl, 2108 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 2109 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 2110 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 2111 2112 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2113 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2114 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2115 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2116 2117 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2118 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2119 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2120 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2121 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2122 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2123 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2124 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2125 2126 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2127 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2128 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2129 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2130 2131 .dp_aux_init = qmp_v4_dp_aux_init, 2132 .configure_dp_tx = qmp_v4_configure_dp_tx, 2133 .configure_dp_phy = qmp_v4_configure_dp_phy, 2134 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2135 2136 .reset_list = msm8996_usb3phy_reset_l, 2137 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2138 .vreg_list = qmp_phy_vreg_l, 2139 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2140 .regs = qmp_v45_usb3phy_regs_layout, 2141 .pcs_usb_offset = 0x300, 2142 2143 .has_pwrdn_delay = true, 2144 }; 2145 2146 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 2147 .offsets = &qmp_combo_offsets_v3, 2148 2149 .serdes_tbl = sm8150_usb3_serdes_tbl, 2150 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2151 .tx_tbl = sm8350_usb3_tx_tbl, 2152 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 2153 .rx_tbl = sm8350_usb3_rx_tbl, 2154 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 2155 .pcs_tbl = sm8350_usb3_pcs_tbl, 2156 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 2157 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 2158 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 2159 2160 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2161 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2162 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 2163 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 2164 2165 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2166 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2167 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2168 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2169 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2170 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2171 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2172 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2173 2174 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 2175 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 2176 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2177 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 2178 2179 .dp_aux_init = qmp_v4_dp_aux_init, 2180 .configure_dp_tx = qmp_v4_configure_dp_tx, 2181 .configure_dp_phy = qmp_v4_configure_dp_phy, 2182 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2183 2184 .reset_list = msm8996_usb3phy_reset_l, 2185 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2186 .vreg_list = qmp_phy_vreg_l, 2187 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2188 .regs = qmp_v45_usb3phy_regs_layout, 2189 2190 .has_pwrdn_delay = true, 2191 }; 2192 2193 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 2194 .offsets = &qmp_combo_offsets_v3, 2195 2196 .serdes_tbl = sm8550_usb3_serdes_tbl, 2197 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2198 .tx_tbl = sm8550_usb3_tx_tbl, 2199 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2200 .rx_tbl = sm8550_usb3_rx_tbl, 2201 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2202 .pcs_tbl = sm8550_usb3_pcs_tbl, 2203 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2204 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2205 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2206 2207 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2208 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2209 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2210 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2211 2212 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2213 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2214 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2215 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2216 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2217 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2218 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2219 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2220 2221 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2222 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2223 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2224 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2225 2226 .dp_aux_init = qmp_v4_dp_aux_init, 2227 .configure_dp_tx = qmp_v4_configure_dp_tx, 2228 .configure_dp_phy = qmp_v4_configure_dp_phy, 2229 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2230 2231 .regs = qmp_v6_usb3phy_regs_layout, 2232 .reset_list = msm8996_usb3phy_reset_l, 2233 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2234 .vreg_list = qmp_phy_vreg_l, 2235 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2236 }; 2237 2238 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = { 2239 .offsets = &qmp_combo_offsets_v3, 2240 2241 .serdes_tbl = sm8550_usb3_serdes_tbl, 2242 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2243 .tx_tbl = sm8550_usb3_tx_tbl, 2244 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2245 .rx_tbl = sm8550_usb3_rx_tbl, 2246 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2247 .pcs_tbl = sm8550_usb3_pcs_tbl, 2248 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2249 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2250 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2251 2252 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2253 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2254 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2255 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2256 2257 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2258 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2259 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2260 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2261 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2262 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2263 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2264 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2265 2266 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2267 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2268 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2269 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2270 2271 .dp_aux_init = qmp_v4_dp_aux_init, 2272 .configure_dp_tx = qmp_v4_configure_dp_tx, 2273 .configure_dp_phy = qmp_v4_configure_dp_phy, 2274 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2275 2276 .regs = qmp_v6_usb3phy_regs_layout, 2277 .reset_list = msm8996_usb3phy_reset_l, 2278 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2279 .vreg_list = qmp_phy_vreg_l, 2280 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2281 }; 2282 2283 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 2284 { 2285 const struct qmp_phy_cfg *cfg = qmp->cfg; 2286 void __iomem *serdes = qmp->dp_serdes; 2287 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2288 2289 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 2290 cfg->dp_serdes_tbl_num); 2291 2292 switch (dp_opts->link_rate) { 2293 case 1620: 2294 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 2295 cfg->serdes_tbl_rbr_num); 2296 break; 2297 case 2700: 2298 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 2299 cfg->serdes_tbl_hbr_num); 2300 break; 2301 case 5400: 2302 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 2303 cfg->serdes_tbl_hbr2_num); 2304 break; 2305 case 8100: 2306 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, 2307 cfg->serdes_tbl_hbr3_num); 2308 break; 2309 default: 2310 /* Other link rates aren't supported */ 2311 return -EINVAL; 2312 } 2313 2314 return 0; 2315 } 2316 2317 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 2318 { 2319 const struct qmp_phy_cfg *cfg = qmp->cfg; 2320 2321 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2322 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2323 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2324 2325 /* Turn on BIAS current for PHY/PLL */ 2326 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 2327 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 2328 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2329 2330 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2331 2332 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2333 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 2334 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 2335 DP_PHY_PD_CTL_DP_CLAMP_EN, 2336 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2337 2338 writel(QSERDES_V3_COM_BIAS_EN | 2339 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 2340 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 2341 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 2342 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2343 2344 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2345 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2346 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2347 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2348 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2349 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2350 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2351 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2352 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2353 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2354 qmp->dp_aux_cfg = 0; 2355 2356 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2357 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2358 PHY_AUX_REQ_ERR_MASK, 2359 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 2360 } 2361 2362 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 2363 { 2364 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2365 const struct qmp_phy_cfg *cfg = qmp->cfg; 2366 unsigned int v_level = 0, p_level = 0; 2367 u8 voltage_swing_cfg, pre_emphasis_cfg; 2368 int i; 2369 2370 for (i = 0; i < dp_opts->lanes; i++) { 2371 v_level = max(v_level, dp_opts->voltage[i]); 2372 p_level = max(p_level, dp_opts->pre[i]); 2373 } 2374 2375 if (dp_opts->link_rate <= 2700) { 2376 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 2377 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 2378 } else { 2379 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 2380 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 2381 } 2382 2383 /* TODO: Move check to config check */ 2384 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2385 return -EINVAL; 2386 2387 /* Enable MUX to use Cursor values from these registers */ 2388 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2389 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2390 2391 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2392 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2393 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2394 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2395 2396 return 0; 2397 } 2398 2399 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2400 { 2401 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2402 u32 bias_en, drvr_en; 2403 2404 if (qmp_combo_configure_dp_swing(qmp) < 0) 2405 return; 2406 2407 if (dp_opts->lanes == 1) { 2408 bias_en = 0x3e; 2409 drvr_en = 0x13; 2410 } else { 2411 bias_en = 0x3f; 2412 drvr_en = 0x10; 2413 } 2414 2415 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2416 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2417 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2418 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2419 } 2420 2421 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2422 { 2423 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2424 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2425 u32 val; 2426 2427 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2428 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2429 2430 if (dp_opts->lanes == 4 || reverse) 2431 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2432 if (dp_opts->lanes == 4 || !reverse) 2433 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2434 2435 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2436 2437 if (reverse) 2438 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2439 else 2440 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2441 2442 return reverse; 2443 } 2444 2445 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2446 { 2447 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2448 u32 phy_vco_div; 2449 unsigned long pixel_freq; 2450 const struct qmp_phy_cfg *cfg = qmp->cfg; 2451 2452 switch (dp_opts->link_rate) { 2453 case 1620: 2454 phy_vco_div = 0x1; 2455 pixel_freq = 1620000000UL / 2; 2456 break; 2457 case 2700: 2458 phy_vco_div = 0x1; 2459 pixel_freq = 2700000000UL / 2; 2460 break; 2461 case 5400: 2462 phy_vco_div = 0x2; 2463 pixel_freq = 5400000000UL / 4; 2464 break; 2465 case 8100: 2466 phy_vco_div = 0x0; 2467 pixel_freq = 8100000000UL / 6; 2468 break; 2469 default: 2470 /* Other link rates aren't supported */ 2471 return -EINVAL; 2472 } 2473 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 2474 2475 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2476 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2477 2478 return 0; 2479 } 2480 2481 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2482 { 2483 const struct qmp_phy_cfg *cfg = qmp->cfg; 2484 u32 status; 2485 int ret; 2486 2487 qmp_combo_configure_dp_mode(qmp); 2488 2489 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2490 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2491 2492 ret = qmp_combo_configure_dp_clocks(qmp); 2493 if (ret) 2494 return ret; 2495 2496 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2497 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2498 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2499 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2500 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2501 2502 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2503 2504 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2505 status, 2506 ((status & BIT(0)) > 0), 2507 500, 2508 10000)) 2509 return -ETIMEDOUT; 2510 2511 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2512 2513 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2514 status, 2515 ((status & BIT(1)) > 0), 2516 500, 2517 10000)) 2518 return -ETIMEDOUT; 2519 2520 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2521 udelay(2000); 2522 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2523 2524 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2525 status, 2526 ((status & BIT(1)) > 0), 2527 500, 2528 10000); 2529 } 2530 2531 /* 2532 * We need to calibrate the aux setting here as many times 2533 * as the caller tries 2534 */ 2535 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2536 { 2537 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2538 u8 val; 2539 2540 qmp->dp_aux_cfg++; 2541 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2542 val = cfg1_settings[qmp->dp_aux_cfg]; 2543 2544 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2545 2546 return 0; 2547 } 2548 2549 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2550 { 2551 const struct qmp_phy_cfg *cfg = qmp->cfg; 2552 2553 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2554 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2555 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2556 2557 /* Turn on BIAS current for PHY/PLL */ 2558 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2559 2560 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2561 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2562 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2563 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2564 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2565 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2566 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2567 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2568 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2569 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2570 qmp->dp_aux_cfg = 0; 2571 2572 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2573 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2574 PHY_AUX_REQ_ERR_MASK, 2575 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2576 } 2577 2578 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2579 { 2580 const struct qmp_phy_cfg *cfg = qmp->cfg; 2581 2582 /* Program default values before writing proper values */ 2583 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2584 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2585 2586 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2587 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2588 2589 qmp_combo_configure_dp_swing(qmp); 2590 } 2591 2592 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2593 { 2594 const struct qmp_phy_cfg *cfg = qmp->cfg; 2595 u32 status; 2596 int ret; 2597 2598 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 2599 2600 qmp_combo_configure_dp_mode(qmp); 2601 2602 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2603 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2604 2605 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2606 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2607 2608 ret = qmp_combo_configure_dp_clocks(qmp); 2609 if (ret) 2610 return ret; 2611 2612 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2613 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2614 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2615 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2616 2617 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2618 2619 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2620 status, 2621 ((status & BIT(0)) > 0), 2622 500, 2623 10000)) 2624 return -ETIMEDOUT; 2625 2626 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2627 status, 2628 ((status & BIT(0)) > 0), 2629 500, 2630 10000)) 2631 return -ETIMEDOUT; 2632 2633 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2634 status, 2635 ((status & BIT(1)) > 0), 2636 500, 2637 10000)) 2638 return -ETIMEDOUT; 2639 2640 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2641 2642 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2643 status, 2644 ((status & BIT(0)) > 0), 2645 500, 2646 10000)) 2647 return -ETIMEDOUT; 2648 2649 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2650 status, 2651 ((status & BIT(1)) > 0), 2652 500, 2653 10000)) 2654 return -ETIMEDOUT; 2655 2656 return 0; 2657 } 2658 2659 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2660 { 2661 const struct qmp_phy_cfg *cfg = qmp->cfg; 2662 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2663 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2664 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2665 u32 status; 2666 int ret; 2667 2668 ret = qmp_v456_configure_dp_phy(qmp); 2669 if (ret < 0) 2670 return ret; 2671 2672 /* 2673 * At least for 7nm DP PHY this has to be done after enabling link 2674 * clock. 2675 */ 2676 2677 if (dp_opts->lanes == 1) { 2678 bias0_en = reverse ? 0x3e : 0x15; 2679 bias1_en = reverse ? 0x15 : 0x3e; 2680 drvr0_en = reverse ? 0x13 : 0x10; 2681 drvr1_en = reverse ? 0x10 : 0x13; 2682 } else if (dp_opts->lanes == 2) { 2683 bias0_en = reverse ? 0x3f : 0x15; 2684 bias1_en = reverse ? 0x15 : 0x3f; 2685 drvr0_en = 0x10; 2686 drvr1_en = 0x10; 2687 } else { 2688 bias0_en = 0x3f; 2689 bias1_en = 0x3f; 2690 drvr0_en = 0x10; 2691 drvr1_en = 0x10; 2692 } 2693 2694 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2695 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2696 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2697 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2698 2699 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2700 udelay(2000); 2701 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2702 2703 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2704 status, 2705 ((status & BIT(1)) > 0), 2706 500, 2707 10000)) 2708 return -ETIMEDOUT; 2709 2710 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2711 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2712 2713 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2714 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2715 2716 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2717 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2718 2719 return 0; 2720 } 2721 2722 /* 2723 * We need to calibrate the aux setting here as many times 2724 * as the caller tries 2725 */ 2726 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2727 { 2728 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2729 u8 val; 2730 2731 qmp->dp_aux_cfg++; 2732 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2733 val = cfg1_settings[qmp->dp_aux_cfg]; 2734 2735 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2736 2737 return 0; 2738 } 2739 2740 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2741 { 2742 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2743 struct qmp_combo *qmp = phy_get_drvdata(phy); 2744 const struct qmp_phy_cfg *cfg = qmp->cfg; 2745 2746 mutex_lock(&qmp->phy_mutex); 2747 2748 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2749 if (qmp->dp_opts.set_voltages) { 2750 cfg->configure_dp_tx(qmp); 2751 qmp->dp_opts.set_voltages = 0; 2752 } 2753 2754 mutex_unlock(&qmp->phy_mutex); 2755 2756 return 0; 2757 } 2758 2759 static int qmp_combo_dp_calibrate(struct phy *phy) 2760 { 2761 struct qmp_combo *qmp = phy_get_drvdata(phy); 2762 const struct qmp_phy_cfg *cfg = qmp->cfg; 2763 int ret = 0; 2764 2765 mutex_lock(&qmp->phy_mutex); 2766 2767 if (cfg->calibrate_dp_phy) 2768 ret = cfg->calibrate_dp_phy(qmp); 2769 2770 mutex_unlock(&qmp->phy_mutex); 2771 2772 return ret; 2773 } 2774 2775 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2776 { 2777 const struct qmp_phy_cfg *cfg = qmp->cfg; 2778 void __iomem *com = qmp->com; 2779 int ret; 2780 u32 val; 2781 2782 if (!force && qmp->init_count++) 2783 return 0; 2784 2785 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2786 if (ret) { 2787 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2788 goto err_decrement_count; 2789 } 2790 2791 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2792 if (ret) { 2793 dev_err(qmp->dev, "reset assert failed\n"); 2794 goto err_disable_regulators; 2795 } 2796 2797 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2798 if (ret) { 2799 dev_err(qmp->dev, "reset deassert failed\n"); 2800 goto err_disable_regulators; 2801 } 2802 2803 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2804 if (ret) 2805 goto err_assert_reset; 2806 2807 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2808 2809 /* override hardware control for reset of qmp phy */ 2810 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2811 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2812 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2813 2814 /* Use software based port select and switch on typec orientation */ 2815 val = SW_PORTSELECT_MUX; 2816 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2817 val |= SW_PORTSELECT_VAL; 2818 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2819 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2820 2821 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2822 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2823 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2824 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2825 2826 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2827 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2828 2829 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2830 SW_PWRDN); 2831 2832 return 0; 2833 2834 err_assert_reset: 2835 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2836 err_disable_regulators: 2837 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2838 err_decrement_count: 2839 qmp->init_count--; 2840 2841 return ret; 2842 } 2843 2844 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2845 { 2846 const struct qmp_phy_cfg *cfg = qmp->cfg; 2847 2848 if (!force && --qmp->init_count) 2849 return 0; 2850 2851 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2852 2853 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2854 2855 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2856 2857 return 0; 2858 } 2859 2860 static int qmp_combo_dp_init(struct phy *phy) 2861 { 2862 struct qmp_combo *qmp = phy_get_drvdata(phy); 2863 const struct qmp_phy_cfg *cfg = qmp->cfg; 2864 int ret; 2865 2866 mutex_lock(&qmp->phy_mutex); 2867 2868 ret = qmp_combo_com_init(qmp, false); 2869 if (ret) 2870 goto out_unlock; 2871 2872 cfg->dp_aux_init(qmp); 2873 2874 qmp->dp_init_count++; 2875 2876 out_unlock: 2877 mutex_unlock(&qmp->phy_mutex); 2878 return ret; 2879 } 2880 2881 static int qmp_combo_dp_exit(struct phy *phy) 2882 { 2883 struct qmp_combo *qmp = phy_get_drvdata(phy); 2884 2885 mutex_lock(&qmp->phy_mutex); 2886 2887 qmp_combo_com_exit(qmp, false); 2888 2889 qmp->dp_init_count--; 2890 2891 mutex_unlock(&qmp->phy_mutex); 2892 2893 return 0; 2894 } 2895 2896 static int qmp_combo_dp_power_on(struct phy *phy) 2897 { 2898 struct qmp_combo *qmp = phy_get_drvdata(phy); 2899 const struct qmp_phy_cfg *cfg = qmp->cfg; 2900 void __iomem *tx = qmp->dp_tx; 2901 void __iomem *tx2 = qmp->dp_tx2; 2902 2903 mutex_lock(&qmp->phy_mutex); 2904 2905 qmp_combo_dp_serdes_init(qmp); 2906 2907 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2908 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2909 2910 /* Configure special DP tx tunings */ 2911 cfg->configure_dp_tx(qmp); 2912 2913 /* Configure link rate, swing, etc. */ 2914 cfg->configure_dp_phy(qmp); 2915 2916 mutex_unlock(&qmp->phy_mutex); 2917 2918 return 0; 2919 } 2920 2921 static int qmp_combo_dp_power_off(struct phy *phy) 2922 { 2923 struct qmp_combo *qmp = phy_get_drvdata(phy); 2924 2925 mutex_lock(&qmp->phy_mutex); 2926 2927 /* Assert DP PHY power down */ 2928 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2929 2930 mutex_unlock(&qmp->phy_mutex); 2931 2932 return 0; 2933 } 2934 2935 static int qmp_combo_usb_power_on(struct phy *phy) 2936 { 2937 struct qmp_combo *qmp = phy_get_drvdata(phy); 2938 const struct qmp_phy_cfg *cfg = qmp->cfg; 2939 void __iomem *serdes = qmp->serdes; 2940 void __iomem *tx = qmp->tx; 2941 void __iomem *rx = qmp->rx; 2942 void __iomem *tx2 = qmp->tx2; 2943 void __iomem *rx2 = qmp->rx2; 2944 void __iomem *pcs = qmp->pcs; 2945 void __iomem *pcs_usb = qmp->pcs_usb; 2946 void __iomem *status; 2947 unsigned int val; 2948 int ret; 2949 2950 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2951 2952 ret = clk_prepare_enable(qmp->pipe_clk); 2953 if (ret) { 2954 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2955 return ret; 2956 } 2957 2958 /* Tx, Rx, and PCS configurations */ 2959 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2960 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2961 2962 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2963 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2964 2965 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2966 2967 if (pcs_usb) 2968 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, 2969 cfg->pcs_usb_tbl_num); 2970 2971 if (cfg->has_pwrdn_delay) 2972 usleep_range(10, 20); 2973 2974 /* Pull PHY out of reset state */ 2975 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2976 2977 /* start SerDes and Phy-Coding-Sublayer */ 2978 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2979 2980 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2981 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2982 PHY_INIT_COMPLETE_TIMEOUT); 2983 if (ret) { 2984 dev_err(qmp->dev, "phy initialization timed-out\n"); 2985 goto err_disable_pipe_clk; 2986 } 2987 2988 return 0; 2989 2990 err_disable_pipe_clk: 2991 clk_disable_unprepare(qmp->pipe_clk); 2992 2993 return ret; 2994 } 2995 2996 static int qmp_combo_usb_power_off(struct phy *phy) 2997 { 2998 struct qmp_combo *qmp = phy_get_drvdata(phy); 2999 const struct qmp_phy_cfg *cfg = qmp->cfg; 3000 3001 clk_disable_unprepare(qmp->pipe_clk); 3002 3003 /* PHY reset */ 3004 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3005 3006 /* stop SerDes and Phy-Coding-Sublayer */ 3007 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 3008 SERDES_START | PCS_START); 3009 3010 /* Put PHY into POWER DOWN state: active low */ 3011 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3012 SW_PWRDN); 3013 3014 return 0; 3015 } 3016 3017 static int qmp_combo_usb_init(struct phy *phy) 3018 { 3019 struct qmp_combo *qmp = phy_get_drvdata(phy); 3020 int ret; 3021 3022 mutex_lock(&qmp->phy_mutex); 3023 ret = qmp_combo_com_init(qmp, false); 3024 if (ret) 3025 goto out_unlock; 3026 3027 ret = qmp_combo_usb_power_on(phy); 3028 if (ret) { 3029 qmp_combo_com_exit(qmp, false); 3030 goto out_unlock; 3031 } 3032 3033 qmp->usb_init_count++; 3034 3035 out_unlock: 3036 mutex_unlock(&qmp->phy_mutex); 3037 return ret; 3038 } 3039 3040 static int qmp_combo_usb_exit(struct phy *phy) 3041 { 3042 struct qmp_combo *qmp = phy_get_drvdata(phy); 3043 int ret; 3044 3045 mutex_lock(&qmp->phy_mutex); 3046 ret = qmp_combo_usb_power_off(phy); 3047 if (ret) 3048 goto out_unlock; 3049 3050 ret = qmp_combo_com_exit(qmp, false); 3051 if (ret) 3052 goto out_unlock; 3053 3054 qmp->usb_init_count--; 3055 3056 out_unlock: 3057 mutex_unlock(&qmp->phy_mutex); 3058 return ret; 3059 } 3060 3061 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 3062 { 3063 struct qmp_combo *qmp = phy_get_drvdata(phy); 3064 3065 qmp->mode = mode; 3066 3067 return 0; 3068 } 3069 3070 static const struct phy_ops qmp_combo_usb_phy_ops = { 3071 .init = qmp_combo_usb_init, 3072 .exit = qmp_combo_usb_exit, 3073 .set_mode = qmp_combo_usb_set_mode, 3074 .owner = THIS_MODULE, 3075 }; 3076 3077 static const struct phy_ops qmp_combo_dp_phy_ops = { 3078 .init = qmp_combo_dp_init, 3079 .configure = qmp_combo_dp_configure, 3080 .power_on = qmp_combo_dp_power_on, 3081 .calibrate = qmp_combo_dp_calibrate, 3082 .power_off = qmp_combo_dp_power_off, 3083 .exit = qmp_combo_dp_exit, 3084 .owner = THIS_MODULE, 3085 }; 3086 3087 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 3088 { 3089 const struct qmp_phy_cfg *cfg = qmp->cfg; 3090 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 3091 void __iomem *pcs_misc = qmp->pcs_misc; 3092 u32 intr_mask; 3093 3094 if (qmp->mode == PHY_MODE_USB_HOST_SS || 3095 qmp->mode == PHY_MODE_USB_DEVICE_SS) 3096 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 3097 else 3098 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 3099 3100 /* Clear any pending interrupts status */ 3101 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3102 /* Writing 1 followed by 0 clears the interrupt */ 3103 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3104 3105 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3106 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 3107 3108 /* Enable required PHY autonomous mode interrupts */ 3109 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 3110 3111 /* Enable i/o clamp_n for autonomous mode */ 3112 if (pcs_misc) 3113 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3114 } 3115 3116 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 3117 { 3118 const struct qmp_phy_cfg *cfg = qmp->cfg; 3119 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 3120 void __iomem *pcs_misc = qmp->pcs_misc; 3121 3122 /* Disable i/o clamp_n on resume for normal mode */ 3123 if (pcs_misc) 3124 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 3125 3126 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 3127 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 3128 3129 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3130 /* Writing 1 followed by 0 clears the interrupt */ 3131 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 3132 } 3133 3134 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 3135 { 3136 struct qmp_combo *qmp = dev_get_drvdata(dev); 3137 3138 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 3139 3140 if (!qmp->init_count) { 3141 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3142 return 0; 3143 } 3144 3145 qmp_combo_enable_autonomous_mode(qmp); 3146 3147 clk_disable_unprepare(qmp->pipe_clk); 3148 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3149 3150 return 0; 3151 } 3152 3153 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 3154 { 3155 struct qmp_combo *qmp = dev_get_drvdata(dev); 3156 int ret = 0; 3157 3158 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 3159 3160 if (!qmp->init_count) { 3161 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 3162 return 0; 3163 } 3164 3165 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 3166 if (ret) 3167 return ret; 3168 3169 ret = clk_prepare_enable(qmp->pipe_clk); 3170 if (ret) { 3171 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 3172 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3173 return ret; 3174 } 3175 3176 qmp_combo_disable_autonomous_mode(qmp); 3177 3178 return 0; 3179 } 3180 3181 static const struct dev_pm_ops qmp_combo_pm_ops = { 3182 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 3183 qmp_combo_runtime_resume, NULL) 3184 }; 3185 3186 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 3187 { 3188 const struct qmp_phy_cfg *cfg = qmp->cfg; 3189 struct device *dev = qmp->dev; 3190 int num = cfg->num_vregs; 3191 int ret, i; 3192 3193 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 3194 if (!qmp->vregs) 3195 return -ENOMEM; 3196 3197 for (i = 0; i < num; i++) 3198 qmp->vregs[i].supply = cfg->vreg_list[i].name; 3199 3200 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 3201 if (ret) { 3202 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 3203 return ret; 3204 } 3205 3206 for (i = 0; i < num; i++) { 3207 ret = regulator_set_load(qmp->vregs[i].consumer, 3208 cfg->vreg_list[i].enable_load); 3209 if (ret) { 3210 dev_err(dev, "failed to set load at %s\n", 3211 qmp->vregs[i].supply); 3212 return ret; 3213 } 3214 } 3215 3216 return 0; 3217 } 3218 3219 static int qmp_combo_reset_init(struct qmp_combo *qmp) 3220 { 3221 const struct qmp_phy_cfg *cfg = qmp->cfg; 3222 struct device *dev = qmp->dev; 3223 int i; 3224 int ret; 3225 3226 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 3227 sizeof(*qmp->resets), GFP_KERNEL); 3228 if (!qmp->resets) 3229 return -ENOMEM; 3230 3231 for (i = 0; i < cfg->num_resets; i++) 3232 qmp->resets[i].id = cfg->reset_list[i]; 3233 3234 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 3235 if (ret) 3236 return dev_err_probe(dev, ret, "failed to get resets\n"); 3237 3238 return 0; 3239 } 3240 3241 static int qmp_combo_clk_init(struct qmp_combo *qmp) 3242 { 3243 struct device *dev = qmp->dev; 3244 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 3245 int i; 3246 3247 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3248 if (!qmp->clks) 3249 return -ENOMEM; 3250 3251 for (i = 0; i < num; i++) 3252 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 3253 3254 qmp->num_clks = num; 3255 3256 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 3257 } 3258 3259 static void phy_clk_release_provider(void *res) 3260 { 3261 of_clk_del_provider(res); 3262 } 3263 3264 /* 3265 * Register a fixed rate pipe clock. 3266 * 3267 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3268 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3269 * by the PHY driver for its operations. 3270 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3271 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3272 * Below picture shows this relationship. 3273 * 3274 * +---------------+ 3275 * | PHY block |<<---------------------------------------+ 3276 * | | | 3277 * | +-------+ | +-----+ | 3278 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3279 * clk | +-------+ | +-----+ 3280 * +---------------+ 3281 */ 3282 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 3283 { 3284 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3285 struct clk_init_data init = { }; 3286 char name[64]; 3287 3288 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 3289 init.name = name; 3290 init.ops = &clk_fixed_rate_ops; 3291 3292 /* controllers using QMP phys use 125MHz pipe clock interface */ 3293 fixed->fixed_rate = 125000000; 3294 fixed->hw.init = &init; 3295 3296 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3297 } 3298 3299 /* 3300 * Display Port PLL driver block diagram for branch clocks 3301 * 3302 * +------------------------------+ 3303 * | DP_VCO_CLK | 3304 * | | 3305 * | +-------------------+ | 3306 * | | (DP PLL/VCO) | | 3307 * | +---------+---------+ | 3308 * | v | 3309 * | +----------+-----------+ | 3310 * | | hsclk_divsel_clk_src | | 3311 * | +----------+-----------+ | 3312 * +------------------------------+ 3313 * | 3314 * +---------<---------v------------>----------+ 3315 * | | 3316 * +--------v----------------+ | 3317 * | dp_phy_pll_link_clk | | 3318 * | link_clk | | 3319 * +--------+----------------+ | 3320 * | | 3321 * | | 3322 * v v 3323 * Input to DISPCC block | 3324 * for link clk, crypto clk | 3325 * and interface clock | 3326 * | 3327 * | 3328 * +--------<------------+-----------------+---<---+ 3329 * | | | 3330 * +----v---------+ +--------v-----+ +--------v------+ 3331 * | vco_divided | | vco_divided | | vco_divided | 3332 * | _clk_src | | _clk_src | | _clk_src | 3333 * | | | | | | 3334 * |divsel_six | | divsel_two | | divsel_four | 3335 * +-------+------+ +-----+--------+ +--------+------+ 3336 * | | | 3337 * v---->----------v-------------<------v 3338 * | 3339 * +----------+-----------------+ 3340 * | dp_phy_pll_vco_div_clk | 3341 * +---------+------------------+ 3342 * | 3343 * v 3344 * Input to DISPCC block 3345 * for DP pixel clock 3346 * 3347 */ 3348 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3349 { 3350 switch (req->rate) { 3351 case 1620000000UL / 2: 3352 case 2700000000UL / 2: 3353 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3354 return 0; 3355 default: 3356 return -EINVAL; 3357 } 3358 } 3359 3360 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3361 { 3362 const struct qmp_combo *qmp; 3363 const struct phy_configure_opts_dp *dp_opts; 3364 3365 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 3366 dp_opts = &qmp->dp_opts; 3367 3368 switch (dp_opts->link_rate) { 3369 case 1620: 3370 return 1620000000UL / 2; 3371 case 2700: 3372 return 2700000000UL / 2; 3373 case 5400: 3374 return 5400000000UL / 4; 3375 case 8100: 3376 return 8100000000UL / 6; 3377 default: 3378 return 0; 3379 } 3380 } 3381 3382 static const struct clk_ops qmp_dp_pixel_clk_ops = { 3383 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3384 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3385 }; 3386 3387 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3388 { 3389 switch (req->rate) { 3390 case 162000000: 3391 case 270000000: 3392 case 540000000: 3393 case 810000000: 3394 return 0; 3395 default: 3396 return -EINVAL; 3397 } 3398 } 3399 3400 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3401 { 3402 const struct qmp_combo *qmp; 3403 const struct phy_configure_opts_dp *dp_opts; 3404 3405 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3406 dp_opts = &qmp->dp_opts; 3407 3408 switch (dp_opts->link_rate) { 3409 case 1620: 3410 case 2700: 3411 case 5400: 3412 case 8100: 3413 return dp_opts->link_rate * 100000; 3414 default: 3415 return 0; 3416 } 3417 } 3418 3419 static const struct clk_ops qmp_dp_link_clk_ops = { 3420 .determine_rate = qmp_dp_link_clk_determine_rate, 3421 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3422 }; 3423 3424 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3425 { 3426 struct qmp_combo *qmp = data; 3427 unsigned int idx = clkspec->args[0]; 3428 3429 if (idx >= 2) { 3430 pr_err("%s: invalid index %u\n", __func__, idx); 3431 return ERR_PTR(-EINVAL); 3432 } 3433 3434 if (idx == 0) 3435 return &qmp->dp_link_hw; 3436 3437 return &qmp->dp_pixel_hw; 3438 } 3439 3440 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3441 { 3442 struct clk_init_data init = { }; 3443 char name[64]; 3444 int ret; 3445 3446 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3447 init.ops = &qmp_dp_link_clk_ops; 3448 init.name = name; 3449 qmp->dp_link_hw.init = &init; 3450 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3451 if (ret) 3452 return ret; 3453 3454 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3455 init.ops = &qmp_dp_pixel_clk_ops; 3456 init.name = name; 3457 qmp->dp_pixel_hw.init = &init; 3458 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3459 if (ret) 3460 return ret; 3461 3462 return 0; 3463 } 3464 3465 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3466 { 3467 struct qmp_combo *qmp = data; 3468 3469 switch (clkspec->args[0]) { 3470 case QMP_USB43DP_USB3_PIPE_CLK: 3471 return &qmp->pipe_clk_fixed.hw; 3472 case QMP_USB43DP_DP_LINK_CLK: 3473 return &qmp->dp_link_hw; 3474 case QMP_USB43DP_DP_VCO_DIV_CLK: 3475 return &qmp->dp_pixel_hw; 3476 } 3477 3478 return ERR_PTR(-EINVAL); 3479 } 3480 3481 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3482 struct device_node *dp_np) 3483 { 3484 int ret; 3485 3486 ret = phy_pipe_clk_register(qmp, usb_np); 3487 if (ret) 3488 return ret; 3489 3490 ret = phy_dp_clks_register(qmp, dp_np); 3491 if (ret) 3492 return ret; 3493 3494 /* 3495 * Register a single provider for bindings without child nodes. 3496 */ 3497 if (usb_np == qmp->dev->of_node) 3498 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3499 3500 /* 3501 * Register multiple providers for legacy bindings with child nodes. 3502 */ 3503 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3504 &qmp->pipe_clk_fixed.hw); 3505 if (ret) 3506 return ret; 3507 3508 /* 3509 * Roll a devm action because the clock provider is the child node, but 3510 * the child node is not actually a device. 3511 */ 3512 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3513 if (ret) 3514 return ret; 3515 3516 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3517 if (ret) 3518 return ret; 3519 3520 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3521 } 3522 3523 #if IS_ENABLED(CONFIG_TYPEC) 3524 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3525 enum typec_orientation orientation) 3526 { 3527 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3528 const struct qmp_phy_cfg *cfg = qmp->cfg; 3529 3530 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3531 return 0; 3532 3533 mutex_lock(&qmp->phy_mutex); 3534 qmp->orientation = orientation; 3535 3536 if (qmp->init_count) { 3537 if (qmp->usb_init_count) 3538 qmp_combo_usb_power_off(qmp->usb_phy); 3539 qmp_combo_com_exit(qmp, true); 3540 3541 qmp_combo_com_init(qmp, true); 3542 if (qmp->usb_init_count) 3543 qmp_combo_usb_power_on(qmp->usb_phy); 3544 if (qmp->dp_init_count) 3545 cfg->dp_aux_init(qmp); 3546 } 3547 mutex_unlock(&qmp->phy_mutex); 3548 3549 return 0; 3550 } 3551 3552 static void qmp_combo_typec_unregister(void *data) 3553 { 3554 struct qmp_combo *qmp = data; 3555 3556 typec_switch_unregister(qmp->sw); 3557 } 3558 3559 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3560 { 3561 struct typec_switch_desc sw_desc = {}; 3562 struct device *dev = qmp->dev; 3563 3564 sw_desc.drvdata = qmp; 3565 sw_desc.fwnode = dev->fwnode; 3566 sw_desc.set = qmp_combo_typec_switch_set; 3567 qmp->sw = typec_switch_register(dev, &sw_desc); 3568 if (IS_ERR(qmp->sw)) { 3569 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3570 return PTR_ERR(qmp->sw); 3571 } 3572 3573 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3574 } 3575 #else 3576 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3577 { 3578 return 0; 3579 } 3580 #endif 3581 3582 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np) 3583 { 3584 struct device *dev = qmp->dev; 3585 3586 /* 3587 * Get memory resources from the DP child node: 3588 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3589 * tx2 -> 3; rx2 -> 4 3590 * 3591 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3592 * implementation. 3593 */ 3594 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3595 if (IS_ERR(qmp->dp_tx)) 3596 return PTR_ERR(qmp->dp_tx); 3597 3598 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3599 if (IS_ERR(qmp->dp_dp_phy)) 3600 return PTR_ERR(qmp->dp_dp_phy); 3601 3602 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3603 if (IS_ERR(qmp->dp_tx2)) 3604 return PTR_ERR(qmp->dp_tx2); 3605 3606 return 0; 3607 } 3608 3609 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np) 3610 { 3611 const struct qmp_phy_cfg *cfg = qmp->cfg; 3612 struct device *dev = qmp->dev; 3613 3614 /* 3615 * Get memory resources from the USB child node: 3616 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3617 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3618 */ 3619 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3620 if (IS_ERR(qmp->tx)) 3621 return PTR_ERR(qmp->tx); 3622 3623 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3624 if (IS_ERR(qmp->rx)) 3625 return PTR_ERR(qmp->rx); 3626 3627 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3628 if (IS_ERR(qmp->pcs)) 3629 return PTR_ERR(qmp->pcs); 3630 3631 if (cfg->pcs_usb_offset) 3632 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3633 3634 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3635 if (IS_ERR(qmp->tx2)) 3636 return PTR_ERR(qmp->tx2); 3637 3638 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3639 if (IS_ERR(qmp->rx2)) 3640 return PTR_ERR(qmp->rx2); 3641 3642 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3643 if (IS_ERR(qmp->pcs_misc)) { 3644 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3645 qmp->pcs_misc = NULL; 3646 } 3647 3648 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3649 if (IS_ERR(qmp->pipe_clk)) { 3650 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3651 "failed to get pipe clock\n"); 3652 } 3653 3654 return 0; 3655 } 3656 3657 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3658 struct device_node *dp_np) 3659 { 3660 struct platform_device *pdev = to_platform_device(qmp->dev); 3661 int ret; 3662 3663 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3664 if (IS_ERR(qmp->serdes)) 3665 return PTR_ERR(qmp->serdes); 3666 3667 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3668 if (IS_ERR(qmp->com)) 3669 return PTR_ERR(qmp->com); 3670 3671 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3672 if (IS_ERR(qmp->dp_serdes)) 3673 return PTR_ERR(qmp->dp_serdes); 3674 3675 ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np); 3676 if (ret) 3677 return ret; 3678 3679 ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np); 3680 if (ret) 3681 return ret; 3682 3683 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3684 if (ret < 0) 3685 return ret; 3686 3687 qmp->num_clks = ret; 3688 3689 return 0; 3690 } 3691 3692 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3693 { 3694 struct platform_device *pdev = to_platform_device(qmp->dev); 3695 const struct qmp_phy_cfg *cfg = qmp->cfg; 3696 const struct qmp_combo_offsets *offs = cfg->offsets; 3697 struct device *dev = qmp->dev; 3698 void __iomem *base; 3699 int ret; 3700 3701 if (!offs) 3702 return -EINVAL; 3703 3704 base = devm_platform_ioremap_resource(pdev, 0); 3705 if (IS_ERR(base)) 3706 return PTR_ERR(base); 3707 3708 qmp->com = base + offs->com; 3709 qmp->tx = base + offs->txa; 3710 qmp->rx = base + offs->rxa; 3711 qmp->tx2 = base + offs->txb; 3712 qmp->rx2 = base + offs->rxb; 3713 3714 qmp->serdes = base + offs->usb3_serdes; 3715 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3716 qmp->pcs = base + offs->usb3_pcs; 3717 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3718 3719 qmp->dp_serdes = base + offs->dp_serdes; 3720 if (offs->dp_txa) { 3721 qmp->dp_tx = base + offs->dp_txa; 3722 qmp->dp_tx2 = base + offs->dp_txb; 3723 } else { 3724 qmp->dp_tx = base + offs->txa; 3725 qmp->dp_tx2 = base + offs->txb; 3726 } 3727 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3728 3729 ret = qmp_combo_clk_init(qmp); 3730 if (ret) 3731 return ret; 3732 3733 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3734 if (IS_ERR(qmp->pipe_clk)) { 3735 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3736 "failed to get usb3_pipe clock\n"); 3737 } 3738 3739 return 0; 3740 } 3741 3742 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 3743 { 3744 struct qmp_combo *qmp = dev_get_drvdata(dev); 3745 3746 if (args->args_count == 0) 3747 return ERR_PTR(-EINVAL); 3748 3749 switch (args->args[0]) { 3750 case QMP_USB43DP_USB3_PHY: 3751 return qmp->usb_phy; 3752 case QMP_USB43DP_DP_PHY: 3753 return qmp->dp_phy; 3754 } 3755 3756 return ERR_PTR(-EINVAL); 3757 } 3758 3759 static int qmp_combo_probe(struct platform_device *pdev) 3760 { 3761 struct qmp_combo *qmp; 3762 struct device *dev = &pdev->dev; 3763 struct device_node *dp_np, *usb_np; 3764 struct phy_provider *phy_provider; 3765 int ret; 3766 3767 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3768 if (!qmp) 3769 return -ENOMEM; 3770 3771 qmp->dev = dev; 3772 dev_set_drvdata(dev, qmp); 3773 3774 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3775 3776 qmp->cfg = of_device_get_match_data(dev); 3777 if (!qmp->cfg) 3778 return -EINVAL; 3779 3780 mutex_init(&qmp->phy_mutex); 3781 3782 ret = qmp_combo_reset_init(qmp); 3783 if (ret) 3784 return ret; 3785 3786 ret = qmp_combo_vreg_init(qmp); 3787 if (ret) 3788 return ret; 3789 3790 /* Check for legacy binding with child nodes. */ 3791 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3792 if (usb_np) { 3793 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3794 if (!dp_np) { 3795 of_node_put(usb_np); 3796 return -EINVAL; 3797 } 3798 3799 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3800 } else { 3801 usb_np = of_node_get(dev->of_node); 3802 dp_np = of_node_get(dev->of_node); 3803 3804 ret = qmp_combo_parse_dt(qmp); 3805 } 3806 if (ret) 3807 goto err_node_put; 3808 3809 ret = qmp_combo_typec_switch_register(qmp); 3810 if (ret) 3811 goto err_node_put; 3812 3813 ret = drm_aux_bridge_register(dev); 3814 if (ret) 3815 goto err_node_put; 3816 3817 pm_runtime_set_active(dev); 3818 ret = devm_pm_runtime_enable(dev); 3819 if (ret) 3820 goto err_node_put; 3821 /* 3822 * Prevent runtime pm from being ON by default. Users can enable 3823 * it using power/control in sysfs. 3824 */ 3825 pm_runtime_forbid(dev); 3826 3827 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3828 if (ret) 3829 goto err_node_put; 3830 3831 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3832 if (IS_ERR(qmp->usb_phy)) { 3833 ret = PTR_ERR(qmp->usb_phy); 3834 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3835 goto err_node_put; 3836 } 3837 3838 phy_set_drvdata(qmp->usb_phy, qmp); 3839 3840 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3841 if (IS_ERR(qmp->dp_phy)) { 3842 ret = PTR_ERR(qmp->dp_phy); 3843 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3844 goto err_node_put; 3845 } 3846 3847 phy_set_drvdata(qmp->dp_phy, qmp); 3848 3849 if (usb_np == dev->of_node) 3850 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3851 else 3852 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3853 3854 of_node_put(usb_np); 3855 of_node_put(dp_np); 3856 3857 return PTR_ERR_OR_ZERO(phy_provider); 3858 3859 err_node_put: 3860 of_node_put(usb_np); 3861 of_node_put(dp_np); 3862 return ret; 3863 } 3864 3865 static const struct of_device_id qmp_combo_of_match_table[] = { 3866 { 3867 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 3868 .data = &sar2130p_usb3dpphy_cfg, 3869 }, 3870 { 3871 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3872 .data = &sc7180_usb3dpphy_cfg, 3873 }, 3874 { 3875 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3876 .data = &sm8250_usb3dpphy_cfg, 3877 }, 3878 { 3879 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3880 .data = &sc8180x_usb3dpphy_cfg, 3881 }, 3882 { 3883 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3884 .data = &sc8280xp_usb43dpphy_cfg, 3885 }, 3886 { 3887 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3888 .data = &sdm845_usb3dpphy_cfg, 3889 }, 3890 { 3891 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3892 .data = &sm6350_usb3dpphy_cfg, 3893 }, 3894 { 3895 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3896 .data = &sc8180x_usb3dpphy_cfg, 3897 }, 3898 { 3899 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3900 .data = &sm8250_usb3dpphy_cfg, 3901 }, 3902 { 3903 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3904 .data = &sm8350_usb3dpphy_cfg, 3905 }, 3906 { 3907 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3908 .data = &sm8350_usb3dpphy_cfg, 3909 }, 3910 { 3911 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3912 .data = &sm8550_usb3dpphy_cfg, 3913 }, 3914 { 3915 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 3916 .data = &sm8650_usb3dpphy_cfg, 3917 }, 3918 { 3919 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 3920 .data = &x1e80100_usb3dpphy_cfg, 3921 }, 3922 { } 3923 }; 3924 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3925 3926 static struct platform_driver qmp_combo_driver = { 3927 .probe = qmp_combo_probe, 3928 .driver = { 3929 .name = "qcom-qmp-combo-phy", 3930 .pm = &qmp_combo_pm_ops, 3931 .of_match_table = qmp_combo_of_match_table, 3932 }, 3933 }; 3934 3935 module_platform_driver(qmp_combo_driver); 3936 3937 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3938 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3939 MODULE_LICENSE("GPL v2"); 3940