1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_graph.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/usb/typec.h> 23 #include <linux/usb/typec_dp.h> 24 #include <linux/usb/typec_mux.h> 25 26 #include <drm/bridge/aux-bridge.h> 27 28 #include <dt-bindings/phy/phy-qcom-qmp.h> 29 30 #include "phy-qcom-qmp-common.h" 31 32 #include "phy-qcom-qmp.h" 33 #include "phy-qcom-qmp-pcs-aon-v6.h" 34 #include "phy-qcom-qmp-pcs-aon-v8.h" 35 #include "phy-qcom-qmp-pcs-misc-v3.h" 36 #include "phy-qcom-qmp-pcs-misc-v4.h" 37 #include "phy-qcom-qmp-pcs-misc-v5.h" 38 #include "phy-qcom-qmp-pcs-misc-v8.h" 39 #include "phy-qcom-qmp-pcs-usb-v4.h" 40 #include "phy-qcom-qmp-pcs-usb-v5.h" 41 #include "phy-qcom-qmp-pcs-usb-v6.h" 42 #include "phy-qcom-qmp-pcs-usb-v8.h" 43 44 #include "phy-qcom-qmp-dp-com-v3.h" 45 46 #include "phy-qcom-qmp-dp-phy.h" 47 #include "phy-qcom-qmp-dp-phy-v3.h" 48 #include "phy-qcom-qmp-dp-phy-v4.h" 49 #include "phy-qcom-qmp-dp-phy-v5.h" 50 #include "phy-qcom-qmp-dp-phy-v6.h" 51 #include "phy-qcom-qmp-dp-phy-v8.h" 52 53 #include "phy-qcom-qmp-usb43-pcs-v8.h" 54 55 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 56 /* DP PHY soft reset */ 57 #define SW_DPPHY_RESET BIT(0) 58 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 59 #define SW_DPPHY_RESET_MUX BIT(1) 60 /* USB3 PHY soft reset */ 61 #define SW_USB3PHY_RESET BIT(2) 62 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 63 #define SW_USB3PHY_RESET_MUX BIT(3) 64 65 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 66 #define USB3_MODE BIT(0) /* enables USB3 mode */ 67 #define DP_MODE BIT(1) /* enables DP mode */ 68 69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 70 #define SW_PORTSELECT_VAL BIT(0) 71 #define SW_PORTSELECT_MUX BIT(1) 72 #define INVERT_CC_POLARITY BIT(2) 73 74 #define PHY_INIT_COMPLETE_TIMEOUT 10000 75 76 enum qmpphy_mode { 77 QMPPHY_MODE_USB3DP = 0, 78 QMPPHY_MODE_DP_ONLY, 79 QMPPHY_MODE_USB3_ONLY, 80 }; 81 82 /* set of registers with offsets different per-PHY */ 83 enum qphy_reg_layout { 84 /* PCS registers */ 85 QPHY_SW_RESET, 86 QPHY_START_CTRL, 87 QPHY_PCS_STATUS, 88 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 89 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 90 QPHY_PCS_POWER_DOWN_CONTROL, 91 QPHY_PCS_CLAMP_ENABLE, 92 93 QPHY_COM_RESETSM_CNTRL, 94 QPHY_COM_C_READY_STATUS, 95 QPHY_COM_CMN_STATUS, 96 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 97 98 QPHY_DP_PHY_STATUS, 99 QPHY_DP_PHY_VCO_DIV, 100 101 QPHY_TX_TX_POL_INV, 102 QPHY_TX_TX_DRV_LVL, 103 QPHY_TX_TX_EMP_POST1_LVL, 104 QPHY_TX_HIGHZ_DRVR_EN, 105 QPHY_TX_TRANSCEIVER_BIAS_EN, 106 107 QPHY_AON_TOGGLE_ENABLE, 108 QPHY_DP_AON_TOGGLE_ENABLE, 109 /* Keep last to ensure regs_layout arrays are properly initialized */ 110 QPHY_LAYOUT_SIZE 111 }; 112 113 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 114 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 115 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 116 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 118 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 119 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 120 121 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, 122 123 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 124 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 125 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 126 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 127 128 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 129 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 130 131 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 132 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 133 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 134 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 135 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 136 }; 137 138 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 139 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 140 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 141 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 142 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 143 144 /* In PCS_USB */ 145 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 146 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 147 148 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE, 149 150 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 151 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 152 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 153 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 154 155 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 156 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 157 158 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 159 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 160 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 161 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 162 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 163 }; 164 165 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 166 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 167 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 168 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 169 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 170 171 /* In PCS_USB */ 172 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 173 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 174 175 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V5_PCS_MISC_CLAMP_ENABLE, 176 177 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 178 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 179 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 180 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 181 182 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 183 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 184 185 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 186 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 187 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 188 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 189 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 190 }; 191 192 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 193 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 194 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 195 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 196 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 197 198 /* In PCS_USB */ 199 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 200 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 201 202 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V6_PCS_AON_CLAMP_ENABLE, 203 204 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 205 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 206 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 207 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 208 209 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 210 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 211 212 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 213 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 214 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 215 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 216 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 217 }; 218 219 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 220 [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET, 221 [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL, 222 [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1, 223 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL, 224 225 /* In PCS_USB */ 226 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 227 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 228 229 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V6_PCS_AON_CLAMP_ENABLE, 230 231 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 232 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 233 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 234 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 235 236 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 237 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 238 239 [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV, 240 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL, 241 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, 242 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, 243 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, 244 }; 245 246 static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 247 [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET, 248 [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL, 249 [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1, 250 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL, 251 252 /* In PCS_USB */ 253 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 254 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 255 256 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 257 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 258 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 259 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 260 261 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 262 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 263 264 [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV, 265 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL, 266 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL, 267 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN, 268 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, 269 }; 270 271 static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = { 272 [QPHY_SW_RESET] = QPHY_V8_USB43_PCS_SW_RESET, 273 [QPHY_START_CTRL] = QPHY_V8_USB43_PCS_START_CONTROL, 274 [QPHY_PCS_STATUS] = QPHY_V8_USB43_PCS_PCS_STATUS1, 275 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_USB43_PCS_POWER_DOWN_CONTROL, 276 277 /* In PCS_USB */ 278 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 279 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 280 281 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE, 282 [QPHY_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE, 283 [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE, 284 285 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 286 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 287 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 288 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 289 290 [QPHY_DP_PHY_STATUS] = QSERDES_V8_DP_PHY_STATUS, 291 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V8_DP_PHY_VCO_DIV, 292 293 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_LALB_TX0_DRV_LVL, 294 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 295 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_LALB_HIGHZ_DRVR_EN, 296 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 297 }; 298 299 static const struct qmp_phy_init_tbl glymur_usb43dp_serdes_tbl[] = { 300 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1, 0xe1), 301 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1, 0x01), 302 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE1, 0x06), 303 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x16), 304 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x36), 305 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1, 0x02), 306 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1, 0x1a), 307 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1, 0x41), 308 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE1, 0x41), 309 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1, 0x00), 310 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1, 0xab), 311 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1, 0xaa), 312 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1, 0x01), 313 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x13), 314 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 315 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1, 0x4d), 316 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1, 0x03), 317 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x95), 318 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 319 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x4b), 320 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 321 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0xe1), 322 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x01), 323 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 324 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 325 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 326 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x05), 327 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x0a), 328 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x1a), 329 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x41), 330 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0, 0x00), 331 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0xab), 332 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xaa), 333 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01), 334 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 335 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 336 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0x4d), 337 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x03), 338 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a), 339 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00), 340 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x62), 341 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02), 342 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x0a), 343 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x0f), 344 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO_MODE1, 0x0f), 345 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x1a), 346 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x04), 347 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_CFG, 0x04), 348 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 349 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x14), 350 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0xa0), 351 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x76), 352 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x0a), 353 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x01), 354 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO, 0x40), 355 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), 356 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_2, 0x01), 357 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60), 358 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x05), 359 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x33), 360 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xaf), 361 }; 362 363 static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_misc_tbl[] = { 364 QMP_PHY_INIT_CFG(QPHY_V8_PCS_MISC_PCS_MISC_CONFIG1, 0x01), 365 }; 366 367 static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_tbl[] = { 368 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1, 0xc4), 369 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2, 0x89), 370 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3, 0x20), 371 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6, 0x13), 372 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1, 0x21), 373 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_SIGDET_LVL, 0x55), 374 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 375 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 376 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME, 0xa4), 377 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_CONFIG, 0x0a), 378 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_DLY_TIME, 0x04), 379 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 380 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2, 0x30), 381 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG, 0x0c), 382 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG1, 0x4b), 383 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG5, 0x10), 384 }; 385 386 static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_usb_tbl[] = { 387 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 388 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 389 }; 390 391 static const struct qmp_phy_init_tbl glymur_usb43dp_lalb_tbl[] = { 392 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x81), 393 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0d), 394 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL1, 0x00), 395 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL2, 0x00), 396 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL3, 0x80), 397 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL4, 0x8D), 398 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x13), 399 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0c), 400 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x00), 401 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x11), 402 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_4, 0x11), 403 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), 404 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), 405 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), 406 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_VREF_SEL, 0x00), 407 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_VREF_SEL, 0x00), 408 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x00), 409 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x00), 410 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B0, 0xa4), 411 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B1, 0xa2), 412 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B2, 0x6e), 413 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B3, 0x51), 414 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B4, 0x0a), 415 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B5, 0x26), 416 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B6, 0x12), 417 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B7, 0x2a), 418 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B0, 0x4c), 419 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B1, 0xc4), 420 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B2, 0x38), 421 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B3, 0x64), 422 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B4, 0x0c), 423 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B5, 0x4b), 424 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B6, 0x12), 425 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B7, 0x0a), 426 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c), 427 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, 0x26), 428 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, 0x26), 429 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, 0x26), 430 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, 0x26), 431 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_0_1, 0x11), 432 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_2_3, 0x11), 433 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE1, 0x03), 434 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE2, 0x03), 435 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE1, 0x15), 436 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE1, 0x00), 437 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE2, 0x22), 438 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE2, 0x00), 439 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CODE_OVRD_RATE_2_3, 0x22), 440 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1, 0xff), 441 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE1, 0x00), 442 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2, 0xff), 443 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE2, 0x00), 444 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1, 0x07), 445 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2, 0x09), 446 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_SUMMER_CAL_SPD_MODE_RATE_0123, 0x2f), 447 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE1, 0x00), 448 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE2, 0x00), 449 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL2, 0x85), 450 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL3, 0x45), 451 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE1, 0x00), 452 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE2, 0x00), 453 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_ENABLES, 0x0c), 454 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CNTRL, 0xa3), 455 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_LVL, 0x04), 456 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_DEGLITCH_CNTRL, 0x0e), 457 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL1, 0x14), 458 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE, 0x00), 459 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_TRIM, 0x66), 460 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE1, 0xff), 461 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE2, 0x32), 462 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE1, 0x07), 463 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE2, 0x0a), 464 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE1, 0x02), 465 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE2, 0x04), 466 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_01, 0x76), 467 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_23, 0x67), 468 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_0_1, 0x20), 469 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_2_3, 0x02), 470 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_0_1, 0x33), 471 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_2_3, 0x43), 472 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_0_1, 0x00), 473 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_2_3, 0x51), 474 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_FLL_DIV_RATIO_RATE_0123, 0xe5), 475 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_RATE_0123, 0xf5), 476 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_TYPE_CONFIG, 0x1f), 477 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_EN_LOWFREQ, 0x07), 478 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_FUNC_CTRL, 0xd0), 479 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_EN, 0x1f), 480 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE0_1, 0x88), 481 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE2_3, 0x88), 482 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_AUX_CLK_CTRL, 0x20), 483 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_EOM_CTRL1, 0x10), 484 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 485 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL3, 0x0a), 486 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL4, 0xaa), 487 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CTLE_POST_CAL_OFFSET_RATE_0_1_2, 0x77), 488 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_CNTRL1, 0x00), 489 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE0_1, 0xdd), 490 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE2_3, 0xd8), 491 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP1_DAC_ENABLE, 0x1c), 492 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP2_DAC_ENABLE, 0x1c), 493 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP345_DAC_ENABLE, 0x18), 494 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP67_DAC_ENABLE, 0x10), 495 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_CTRL, 0x00), 496 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_MAN_INDEX, 0x10), 497 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_DIV2_CTRL_RATE0123, 0x1C), 498 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_OVRD_MUXES, 0x00), 499 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DIG_BKUP_CTRL16, 0x37), 500 }; 501 502 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 539 }; 540 541 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 542 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 543 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 544 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 545 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 546 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 547 }; 548 549 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 562 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 563 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 564 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 565 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 566 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 567 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 568 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 569 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 570 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 571 }; 572 573 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 574 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 575 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 576 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 577 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 578 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 579 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 580 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 581 }; 582 583 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 584 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 585 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 586 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 587 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 588 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 589 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 590 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 591 }; 592 593 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 601 }; 602 603 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 606 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 607 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 608 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 609 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 611 }; 612 613 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 614 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 615 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 616 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 617 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 618 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 619 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 620 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 621 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 622 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 623 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 624 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 625 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 626 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 627 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 628 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 629 }; 630 631 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 632 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 633 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 634 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 635 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 636 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 637 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 638 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 639 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 640 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 641 }; 642 643 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 644 /* FLL settings */ 645 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 646 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 647 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 648 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 649 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 650 651 /* Lock Det settings */ 652 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 653 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 654 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 655 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 656 657 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 658 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 659 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 660 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 661 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 662 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 663 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 664 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 665 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 666 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 667 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 668 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 669 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 670 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 671 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 672 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 673 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 674 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 675 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 676 677 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 678 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 679 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 681 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 682 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 683 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 684 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 685 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 686 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 687 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 688 }; 689 690 static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = { 691 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), 692 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), 693 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 694 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 695 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 696 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 697 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 698 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 699 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), 700 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), 701 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 702 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), 703 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), 704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), 712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), 713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), 719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), 720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), 722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 724 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 725 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 739 }; 740 741 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 742 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 743 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 744 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 745 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 746 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 747 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 748 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 749 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 750 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 751 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 752 }; 753 754 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 755 /* FLL settings */ 756 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 757 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 758 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 759 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 760 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 761 762 /* Lock Det settings */ 763 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 764 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 765 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 766 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 767 768 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 769 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 770 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 771 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 772 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 773 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 774 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 775 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 776 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 777 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 778 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 779 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 780 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 781 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 782 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 783 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 784 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 785 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 786 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 787 788 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 789 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 790 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 791 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 792 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 793 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 794 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 795 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 796 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 797 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 798 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 799 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 800 801 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 802 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 803 }; 804 805 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 846 }; 847 848 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 849 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 850 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 851 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 852 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 853 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 854 }; 855 856 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 890 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 893 }; 894 895 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 896 /* Lock Det settings */ 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 899 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 900 901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 903 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 904 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 905 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 906 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 907 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 909 }; 910 911 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 914 }; 915 916 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 917 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 918 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 920 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 921 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 922 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 923 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 924 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 925 }; 926 927 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 948 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 949 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 950 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 951 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 962 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 963 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 966 }; 967 968 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 969 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 973 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 974 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 975 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 978 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 979 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 980 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 981 }; 982 983 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 984 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 985 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 986 }; 987 988 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 990 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 991 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 992 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 993 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 994 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 995 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 996 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 997 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 998 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 999 }; 1000 1001 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 1002 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1003 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1004 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1005 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1006 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1007 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1008 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1009 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1010 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1011 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1012 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1013 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1014 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1015 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1016 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1017 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1018 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1019 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1020 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1021 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1022 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1023 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 1024 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 1026 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 1027 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1034 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1036 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 1040 }; 1041 1042 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 1043 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1044 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1045 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1046 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1047 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1048 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1049 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1050 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1051 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1052 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1053 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1054 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1055 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1056 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1057 }; 1058 1059 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 1060 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1061 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1062 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1063 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1064 }; 1065 1066 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 1067 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1068 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1071 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1072 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1073 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1074 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1075 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 1076 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1078 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 1079 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 1080 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1090 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1091 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1092 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1093 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1094 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1095 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1096 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1097 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 1098 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1099 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 1100 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 1101 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1102 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 1106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1107 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 1108 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 1109 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 1110 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 1111 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1112 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 1113 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 1114 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 1115 }; 1116 1117 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 1118 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 1119 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 1120 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1121 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1122 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 1123 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 1124 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 1125 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 1126 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 1127 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 1128 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 1129 }; 1130 1131 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 1132 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 1133 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 1134 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1135 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1136 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1137 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1138 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 1139 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 1140 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 1141 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 1142 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 1143 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1144 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 1145 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 1146 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 1147 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1148 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1149 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1150 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1151 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1152 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1153 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 1154 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1155 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 1156 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 1157 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 1158 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 1159 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 1160 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 1161 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1162 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 1163 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 1164 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 1165 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1166 1167 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 1168 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 1169 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 1170 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 1171 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 1172 1173 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 1174 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 1175 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 1176 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 1177 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 1178 }; 1179 1180 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 1181 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1182 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 1183 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 1184 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 1185 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 1186 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 1187 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1188 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1189 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 1190 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1191 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1192 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 1193 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 1194 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 1195 }; 1196 1197 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 1198 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1199 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1200 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1201 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1202 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 1203 }; 1204 1205 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 1206 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1207 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1208 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1209 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1210 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1211 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1212 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1213 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1214 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1215 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1216 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1217 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1218 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1219 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 1220 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1221 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1222 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1223 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1224 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1225 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1226 }; 1227 1228 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 1229 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 1230 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1231 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1232 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1233 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 1234 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 1235 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 1236 }; 1237 1238 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 1239 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 1240 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1241 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1242 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1243 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 1244 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 1245 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1246 }; 1247 1248 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 1249 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1250 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 1251 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 1252 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 1253 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 1254 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 1255 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1256 }; 1257 1258 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 1259 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 1260 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1261 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1262 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1263 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 1264 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 1265 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1266 }; 1267 1268 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 1269 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 1270 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1271 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 1272 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 1273 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 1274 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1275 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1276 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 1277 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1278 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1279 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 1280 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 1281 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 1282 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 1283 }; 1284 1285 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 1286 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1287 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1288 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1289 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1290 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1291 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1292 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1293 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1294 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1295 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1296 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1297 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1298 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1299 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1300 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1301 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1302 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1303 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1304 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1305 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1306 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1307 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1308 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1309 }; 1310 1311 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 1312 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 1323 }; 1324 1325 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 1326 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1338 }; 1339 1340 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1341 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1342 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1343 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1344 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1345 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1346 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1347 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1348 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1349 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1350 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1351 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1352 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1353 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1354 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1355 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1356 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1357 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1358 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1359 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1360 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1361 }; 1362 1363 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = { 1364 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1365 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1366 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1367 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1368 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1369 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1370 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1371 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1372 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1373 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1374 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1375 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1376 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1377 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1378 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1379 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1380 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1381 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1382 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1383 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1384 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1385 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1386 }; 1387 1388 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] = { 1389 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x00), 1390 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 1391 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x10), 1392 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x01), 1393 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), 1394 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), 1395 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1396 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1397 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a), 1398 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00), 1399 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_ADJ_PER1, 0x00), 1400 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x00), 1401 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x00), 1402 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_ENABLE1, 0x0c), 1403 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), 1404 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), 1405 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), 1406 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), 1407 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x00), 1408 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 1409 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), 1410 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), 1411 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), 1412 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x56), 1413 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), 1414 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), 1415 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), 1416 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60), 1417 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x01), 1418 }; 1419 1420 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1421 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1422 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1423 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1424 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1425 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1432 }; 1433 1434 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = { 1435 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1443 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1444 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1), 1445 }; 1446 1447 static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx_tbl[] = { 1448 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x3f), 1449 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VMODE_CTRL1, 0x40), 1450 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT1, 0x07), 1451 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x18), 1452 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x50), 1453 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0d), 1454 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x07), 1455 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0a), 1456 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0f), 1457 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRAN_DRVR_EMP_EN, 0x5f), 1458 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x20), 1459 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x20), 1460 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_PRE1_EMPH, 0x20), 1461 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_PRE1_EMPH, 0x20), 1462 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_DRV_LVL, 0x00), 1463 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_DRV_LVL, 0x00), 1464 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x30), 1465 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x50), 1466 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x51), 1467 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x00), 1468 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), 1469 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), 1470 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), 1471 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET, 0x10), 1472 }; 1473 1474 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1478 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1481 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1482 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1483 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1484 }; 1485 1486 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1487 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1488 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1489 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1490 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1491 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1492 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1493 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1494 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1495 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1496 }; 1497 1498 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1499 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1500 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1501 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1502 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1503 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1504 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1505 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1506 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1507 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1508 }; 1509 1510 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1511 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1512 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1513 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1514 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1515 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1516 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1517 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1518 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1519 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1520 }; 1521 1522 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = { 1523 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1524 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1525 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1526 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1527 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1528 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1529 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1530 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1531 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1532 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1533 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1534 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1535 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1536 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1537 }; 1538 1539 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = { 1540 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1541 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1542 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1543 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1544 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1545 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1546 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1547 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1548 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1549 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1550 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1551 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1552 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1553 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1554 }; 1555 1556 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = { 1557 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1558 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1559 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1560 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1561 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1562 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1563 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1564 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1565 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1566 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1567 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1568 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1569 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1570 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1571 }; 1572 1573 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = { 1574 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1575 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1576 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1577 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1578 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1579 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1580 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1581 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1582 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1583 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1584 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1585 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1586 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1587 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1588 }; 1589 1590 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] = { 1591 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x05), 1592 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x7a), 1593 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x02), 1594 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x83), 1595 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x37), 1596 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x04), 1597 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x54), 1598 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1599 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x06), 1600 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xfe), 1601 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x00), 1602 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x05), 1603 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), 1604 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), 1605 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa4), 1606 }; 1607 1608 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr[] = { 1609 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x04), 1610 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x21), 1611 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x04), 1612 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1613 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x07), 1614 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x07), 1615 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), 1616 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1617 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), 1618 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), 1619 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), 1620 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x04), 1621 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), 1622 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), 1623 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa3), 1624 }; 1625 1626 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr2[] = { 1627 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x03), 1628 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), 1629 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), 1630 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x0), 1631 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 1632 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 1633 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x10), 1634 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x0e), 1635 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), 1636 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1637 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), 1638 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), 1639 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), 1640 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x00), 1641 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xbf), 1642 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1643 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), 1644 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x03), 1645 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), 1646 }; 1647 1648 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] = { 1649 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x02), 1650 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x63), 1651 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1652 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x5b), 1653 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1654 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 1655 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 1656 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 1657 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), 1658 1659 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x17), 1660 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x15), 1661 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x4f), 1662 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), 1663 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xa0), 1664 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01), 1665 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1666 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1667 1668 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xa0), 1669 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x01), 1670 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_ADJ_PER1, 0x00), 1671 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x6b), 1672 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02), 1673 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_ENABLE1, 0x0c), 1674 1675 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), 1676 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), 1677 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), 1678 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x04), 1679 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 1680 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), 1681 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), 1682 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), 1683 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), 1684 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), 1685 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), 1686 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x10), 1687 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x05), 1688 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), 1689 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x02), 1690 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0x84), 1691 }; 1692 1693 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1694 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1695 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1696 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1697 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1698 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1699 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1700 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1701 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1702 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1703 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1704 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1705 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1706 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1707 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1708 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1709 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1710 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1711 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1712 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1713 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1714 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1715 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1716 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1717 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1718 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1719 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1720 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1721 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1722 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1723 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1724 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1725 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1726 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1727 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1728 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1729 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1730 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1731 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1732 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1733 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1734 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1735 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1736 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1737 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1738 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1739 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1740 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1741 }; 1742 1743 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1744 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1745 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1746 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1747 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1748 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1749 }; 1750 1751 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1752 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1753 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1754 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1755 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1756 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1757 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1758 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1759 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1760 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1761 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1762 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1763 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1764 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1765 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1766 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1767 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1768 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1769 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1770 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1771 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1772 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1773 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1774 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1775 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1776 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1777 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1778 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1779 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1780 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1781 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1782 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1783 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1784 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1785 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1786 }; 1787 1788 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1789 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1790 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1791 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1792 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1793 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1794 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1795 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1796 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1797 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1798 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1799 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1800 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1801 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1802 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1803 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1804 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1805 }; 1806 1807 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1848 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1849 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1850 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1855 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1856 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1857 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1858 }; 1859 1860 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1861 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1862 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1863 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1864 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1865 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1866 }; 1867 1868 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1869 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1870 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1871 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1872 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1873 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1874 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1875 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1876 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1877 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1878 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1879 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1880 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1881 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1882 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1883 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1884 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1885 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1886 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1887 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1888 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1889 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1890 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1891 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1892 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1893 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1894 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1895 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1896 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1897 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1898 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1899 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1900 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1901 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1902 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1903 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1904 }; 1905 1906 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1907 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1908 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1909 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1910 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89), 1911 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1912 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1913 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1914 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55), 1915 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a), 1916 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1917 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1918 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1919 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b), 1920 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), 1921 }; 1922 1923 static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = { 1924 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1925 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1926 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), 1927 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 1928 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 1929 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 1930 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), 1931 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), 1932 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), 1933 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), 1934 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 1935 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), 1936 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 1937 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 1938 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), 1939 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), 1940 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1941 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1942 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1943 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1944 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1945 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1946 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), 1947 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 1948 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 1949 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), 1950 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), 1951 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 1952 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), 1953 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), 1954 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), 1955 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 1956 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), 1957 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), 1958 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 1959 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), 1960 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 1961 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 1962 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), 1963 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), 1964 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), 1965 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), 1966 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), 1967 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 1968 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1969 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 1970 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 1971 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), 1972 }; 1973 1974 static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = { 1975 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), 1976 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), 1977 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1978 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1979 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), 1980 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), 1981 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31), 1982 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), 1983 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), 1984 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1), 1985 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2), 1986 }; 1987 1988 static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = { 1989 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a), 1990 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06), 1991 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1992 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1993 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1994 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1995 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), 1996 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), 1997 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), 1998 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), 1999 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), 2000 QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 2001 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), 2002 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), 2003 QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13), 2004 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 2005 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 2006 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 2007 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2008 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 2009 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 2010 2011 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), 2012 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), 2013 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 2014 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f), 2015 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), 2016 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), 2017 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), 2018 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), 2019 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), 2020 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), 2021 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), 2022 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), 2023 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), 2024 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), 2025 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2026 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), 2027 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), 2028 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), 2029 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), 2030 }; 2031 2032 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = { 2033 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), 2034 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), 2035 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), 2036 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), 2037 QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), 2038 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), 2039 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 2040 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 2041 QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), 2042 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88), 2043 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13), 2044 QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), 2045 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), 2046 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), 2047 }; 2048 2049 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = { 2050 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 2051 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 2052 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), 2053 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00), 2054 }; 2055 2056 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 2057 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 2058 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 2059 }; 2060 2061 /* list of regulators */ 2062 static struct regulator_bulk_data qmp_phy_vreg_l[] = { 2063 { .supply = "vdda-phy", .init_load_uA = 21800, }, 2064 { .supply = "vdda-pll", .init_load_uA = 36000, }, 2065 }; 2066 2067 static struct regulator_bulk_data qmp_phy_vreg_refgen[] = { 2068 { .supply = "vdda-phy", .init_load_uA = 21800 }, 2069 { .supply = "vdda-pll", .init_load_uA = 36000 }, 2070 { .supply = "refgen", .init_load_uA = 3270 }, 2071 }; 2072 2073 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 2074 { 0x00, 0x0c, 0x15, 0x1a }, 2075 { 0x02, 0x0e, 0x16, 0xff }, 2076 { 0x02, 0x11, 0xff, 0xff }, 2077 { 0x04, 0xff, 0xff, 0xff } 2078 }; 2079 2080 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 2081 { 0x02, 0x12, 0x16, 0x1a }, 2082 { 0x09, 0x19, 0x1f, 0xff }, 2083 { 0x10, 0x1f, 0xff, 0xff }, 2084 { 0x1f, 0xff, 0xff, 0xff } 2085 }; 2086 2087 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 2088 { 0x00, 0x0c, 0x14, 0x19 }, 2089 { 0x00, 0x0b, 0x12, 0xff }, 2090 { 0x00, 0x0b, 0xff, 0xff }, 2091 { 0x04, 0xff, 0xff, 0xff } 2092 }; 2093 2094 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 2095 { 0x08, 0x0f, 0x16, 0x1f }, 2096 { 0x11, 0x1e, 0x1f, 0xff }, 2097 { 0x19, 0x1f, 0xff, 0xff }, 2098 { 0x1f, 0xff, 0xff, 0xff } 2099 }; 2100 2101 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 2102 { 0x00, 0x0c, 0x15, 0x1b }, 2103 { 0x02, 0x0e, 0x16, 0xff }, 2104 { 0x02, 0x11, 0xff, 0xff }, 2105 { 0x04, 0xff, 0xff, 0xff } 2106 }; 2107 2108 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 2109 { 0x00, 0x0d, 0x14, 0x1a }, 2110 { 0x00, 0x0e, 0x15, 0xff }, 2111 { 0x00, 0x0d, 0xff, 0xff }, 2112 { 0x03, 0xff, 0xff, 0xff } 2113 }; 2114 2115 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 2116 { 0x08, 0x0f, 0x16, 0x1f }, 2117 { 0x11, 0x1e, 0x1f, 0xff }, 2118 { 0x16, 0x1f, 0xff, 0xff }, 2119 { 0x1f, 0xff, 0xff, 0xff } 2120 }; 2121 2122 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 2123 { 0x20, 0x2c, 0x35, 0x3b }, 2124 { 0x22, 0x2e, 0x36, 0xff }, 2125 { 0x22, 0x31, 0xff, 0xff }, 2126 { 0x24, 0xff, 0xff, 0xff } 2127 }; 2128 2129 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 2130 { 0x22, 0x32, 0x36, 0x3a }, 2131 { 0x29, 0x39, 0x3f, 0xff }, 2132 { 0x30, 0x3f, 0xff, 0xff }, 2133 { 0x3f, 0xff, 0xff, 0xff } 2134 }; 2135 2136 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 2137 { 0x20, 0x2d, 0x34, 0x3a }, 2138 { 0x20, 0x2e, 0x35, 0xff }, 2139 { 0x20, 0x2e, 0xff, 0xff }, 2140 { 0x24, 0xff, 0xff, 0xff } 2141 }; 2142 2143 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 2144 { 0x28, 0x2f, 0x36, 0x3f }, 2145 { 0x31, 0x3e, 0x3f, 0xff }, 2146 { 0x36, 0x3f, 0xff, 0xff }, 2147 { 0x3f, 0xff, 0xff, 0xff } 2148 }; 2149 2150 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = { 2151 { 0x27, 0x2f, 0x36, 0x3f }, 2152 { 0x31, 0x3e, 0x3f, 0xff }, 2153 { 0x36, 0x3f, 0xff, 0xff }, 2154 { 0x3f, 0xff, 0xff, 0xff } 2155 }; 2156 2157 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 2158 { 0x20, 0x2d, 0x34, 0x3a }, 2159 { 0x20, 0x2e, 0x35, 0xff }, 2160 { 0x20, 0x2e, 0xff, 0xff }, 2161 { 0x22, 0xff, 0xff, 0xff } 2162 }; 2163 2164 struct qmp_combo_lane_mapping { 2165 unsigned int lanes_count; 2166 enum typec_orientation orientation; 2167 u32 lanes[4]; 2168 }; 2169 2170 static const struct qmp_combo_lane_mapping usb3_data_lanes[] = { 2171 { 2, TYPEC_ORIENTATION_NORMAL, { 1, 0 }}, 2172 { 2, TYPEC_ORIENTATION_REVERSE, { 2, 3 }}, 2173 }; 2174 2175 static const struct qmp_combo_lane_mapping dp_data_lanes[] = { 2176 { 1, TYPEC_ORIENTATION_NORMAL, { 3 }}, 2177 { 1, TYPEC_ORIENTATION_REVERSE, { 0 }}, 2178 { 2, TYPEC_ORIENTATION_NORMAL, { 3, 2 }}, 2179 { 2, TYPEC_ORIENTATION_REVERSE, { 0, 1 }}, 2180 { 4, TYPEC_ORIENTATION_NORMAL, { 3, 2, 1, 0 }}, 2181 { 4, TYPEC_ORIENTATION_REVERSE, { 0, 1, 2, 3 }}, 2182 }; 2183 2184 struct qmp_combo; 2185 2186 struct qmp_combo_offsets { 2187 u16 com; 2188 u16 txa; 2189 u16 rxa; 2190 u16 txb; 2191 u16 rxb; 2192 u16 usb3_serdes; 2193 u16 usb3_pcs_misc; 2194 u16 usb3_pcs; 2195 u16 usb3_pcs_aon; 2196 u16 usb3_pcs_usb; 2197 u16 dp_serdes; 2198 u16 dp_txa; 2199 u16 dp_txb; 2200 u16 dp_dp_phy; 2201 }; 2202 2203 struct qmp_phy_cfg { 2204 const struct qmp_combo_offsets *offsets; 2205 2206 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 2207 const struct qmp_phy_init_tbl *serdes_tbl; 2208 int serdes_tbl_num; 2209 const struct qmp_phy_init_tbl *tx_tbl; 2210 int tx_tbl_num; 2211 const struct qmp_phy_init_tbl *rx_tbl; 2212 int rx_tbl_num; 2213 const struct qmp_phy_init_tbl *pcs_tbl; 2214 int pcs_tbl_num; 2215 const struct qmp_phy_init_tbl *pcs_usb_tbl; 2216 int pcs_usb_tbl_num; 2217 const struct qmp_phy_init_tbl *pcs_misc_tbl; 2218 int pcs_misc_tbl_num; 2219 2220 const struct qmp_phy_init_tbl *dp_serdes_tbl; 2221 int dp_serdes_tbl_num; 2222 const struct qmp_phy_init_tbl *dp_tx_tbl; 2223 int dp_tx_tbl_num; 2224 2225 /* Init sequence for DP PHY block link rates */ 2226 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 2227 int serdes_tbl_rbr_num; 2228 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 2229 int serdes_tbl_hbr_num; 2230 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 2231 int serdes_tbl_hbr2_num; 2232 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 2233 int serdes_tbl_hbr3_num; 2234 2235 /* DP PHY swing and pre_emphasis tables */ 2236 const u8 (*swing_hbr_rbr)[4][4]; 2237 const u8 (*swing_hbr3_hbr2)[4][4]; 2238 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 2239 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 2240 2241 /* DP PHY callbacks */ 2242 int (*configure_dp_clocks)(struct qmp_combo *qmp); 2243 int (*configure_dp_phy)(struct qmp_combo *qmp); 2244 void (*configure_dp_tx)(struct qmp_combo *qmp); 2245 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 2246 void (*dp_aux_init)(struct qmp_combo *qmp); 2247 2248 /* resets to be requested */ 2249 const char * const *reset_list; 2250 int num_resets; 2251 /* regulators to be requested */ 2252 const struct regulator_bulk_data *vreg_list; 2253 int num_vregs; 2254 2255 /* array of registers with different offsets */ 2256 const unsigned int *regs; 2257 2258 /* true, if PHY needs delay after POWER_DOWN */ 2259 bool has_pwrdn_delay; 2260 2261 /* Offset from PCS to PCS_USB region */ 2262 unsigned int pcs_usb_offset; 2263 2264 bool invert_cc_polarity; 2265 }; 2266 2267 struct qmp_combo { 2268 struct device *dev; 2269 2270 const struct qmp_phy_cfg *cfg; 2271 2272 void __iomem *com; 2273 2274 void __iomem *serdes; 2275 void __iomem *tx; 2276 void __iomem *rx; 2277 void __iomem *pcs; 2278 void __iomem *tx2; 2279 void __iomem *rx2; 2280 void __iomem *pcs_misc; 2281 void __iomem *pcs_aon; 2282 void __iomem *pcs_usb; 2283 2284 void __iomem *dp_serdes; 2285 void __iomem *dp_tx; 2286 void __iomem *dp_tx2; 2287 void __iomem *dp_dp_phy; 2288 2289 struct clk *pipe_clk; 2290 struct clk_bulk_data *clks; 2291 int num_clks; 2292 struct reset_control_bulk_data *resets; 2293 struct regulator_bulk_data *vregs; 2294 2295 struct mutex phy_mutex; 2296 int init_count; 2297 enum qmpphy_mode qmpphy_mode; 2298 2299 struct phy *usb_phy; 2300 enum phy_mode phy_mode; 2301 unsigned int usb_init_count; 2302 2303 struct phy *dp_phy; 2304 unsigned int dp_aux_cfg; 2305 struct phy_configure_opts_dp dp_opts; 2306 unsigned int dp_init_count; 2307 bool dp_powered_on; 2308 2309 struct clk_fixed_rate pipe_clk_fixed; 2310 struct clk_hw dp_link_hw; 2311 struct clk_hw dp_pixel_hw; 2312 2313 struct typec_switch_dev *sw; 2314 enum typec_orientation orientation; 2315 2316 struct typec_mux_dev *mux; 2317 }; 2318 2319 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 2320 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 2321 static int qmp_v3_configure_dp_clocks(struct qmp_combo *qmp); 2322 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 2323 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 2324 2325 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 2326 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 2327 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 2328 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 2329 2330 static void qmp_v8_dp_aux_init(struct qmp_combo *qmp); 2331 static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp); 2332 static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp); 2333 2334 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 2335 { 2336 u32 reg; 2337 2338 reg = readl(base + offset); 2339 reg |= val; 2340 writel(reg, base + offset); 2341 2342 /* ensure that above write is through */ 2343 readl(base + offset); 2344 } 2345 2346 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 2347 { 2348 u32 reg; 2349 2350 reg = readl(base + offset); 2351 reg &= ~val; 2352 writel(reg, base + offset); 2353 2354 /* ensure that above write is through */ 2355 readl(base + offset); 2356 } 2357 2358 /* list of clocks required by phy */ 2359 static const char * const qmp_combo_phy_clk_l[] = { 2360 "aux", "cfg_ahb", "ref", "com_aux", 2361 }; 2362 2363 /* list of resets */ 2364 static const char * const msm8996_usb3phy_reset_l[] = { 2365 "phy", "common", 2366 }; 2367 2368 static const char * const sc7180_usb3phy_reset_l[] = { 2369 "phy", 2370 }; 2371 2372 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 2373 .com = 0x0000, 2374 .txa = 0x1200, 2375 .rxa = 0x1400, 2376 .txb = 0x1600, 2377 .rxb = 0x1800, 2378 .usb3_serdes = 0x1000, 2379 .usb3_pcs_misc = 0x1a00, 2380 .usb3_pcs = 0x1c00, 2381 .usb3_pcs_usb = 0x1f00, 2382 .dp_serdes = 0x2000, 2383 .dp_txa = 0x2200, 2384 .dp_txb = 0x2600, 2385 .dp_dp_phy = 0x2a00, 2386 }; 2387 2388 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 2389 .com = 0x0000, 2390 .txa = 0x0400, 2391 .rxa = 0x0600, 2392 .txb = 0x0a00, 2393 .rxb = 0x0c00, 2394 .usb3_serdes = 0x1000, 2395 .usb3_pcs_misc = 0x1200, 2396 .usb3_pcs = 0x1400, 2397 .usb3_pcs_usb = 0x1700, 2398 .dp_serdes = 0x2000, 2399 .dp_dp_phy = 0x2200, 2400 }; 2401 2402 static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { 2403 .com = 0x0000, 2404 .txa = 0x1400, 2405 .rxa = 0x1600, 2406 .txb = 0x1800, 2407 .rxb = 0x1a00, 2408 .usb3_serdes = 0x1000, 2409 .usb3_pcs_misc = 0x1c00, 2410 .usb3_pcs = 0x1e00, 2411 .usb3_pcs_aon = 0x2000, 2412 .usb3_pcs_usb = 0x2100, 2413 .dp_serdes = 0x3000, 2414 .dp_txa = 0x3400, 2415 .dp_txb = 0x3800, 2416 .dp_dp_phy = 0x3c00, 2417 }; 2418 2419 static const struct qmp_combo_offsets qmp_combo_usb43dp_offsets_v8 = { 2420 .com = 0x0000, 2421 .usb3_pcs_aon = 0x0100, 2422 .usb3_serdes = 0x1000, 2423 .usb3_pcs_misc = 0x1400, 2424 .usb3_pcs = 0x1600, 2425 .usb3_pcs_usb = 0x1900, 2426 .dp_serdes = 0x2000, 2427 .dp_dp_phy = 0x2400, 2428 .txa = 0x4000, 2429 .txb = 0x5000, 2430 }; 2431 2432 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { 2433 .offsets = &qmp_combo_offsets_v3, 2434 2435 .serdes_tbl = sar2130p_usb3_serdes_tbl, 2436 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 2437 .tx_tbl = sm8550_usb3_tx_tbl, 2438 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2439 .rx_tbl = sm8550_usb3_rx_tbl, 2440 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2441 .pcs_tbl = sm8550_usb3_pcs_tbl, 2442 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2443 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2444 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2445 2446 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2447 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2448 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2449 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2450 2451 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2452 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2453 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2454 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2455 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2456 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2457 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2458 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2459 2460 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2461 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2462 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2463 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2464 2465 .dp_aux_init = qmp_v4_dp_aux_init, 2466 .configure_dp_tx = qmp_v4_configure_dp_tx, 2467 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2468 .configure_dp_phy = qmp_v4_configure_dp_phy, 2469 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2470 2471 .regs = qmp_v6_usb3phy_regs_layout, 2472 .reset_list = msm8996_usb3phy_reset_l, 2473 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2474 .vreg_list = qmp_phy_vreg_l, 2475 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2476 .invert_cc_polarity = true, 2477 }; 2478 2479 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 2480 .offsets = &qmp_combo_offsets_v3, 2481 2482 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2483 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2484 .tx_tbl = qmp_v3_usb3_tx_tbl, 2485 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2486 .rx_tbl = qmp_v3_usb3_rx_tbl, 2487 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2488 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2489 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2490 2491 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2492 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2493 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2494 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2495 2496 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2497 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2498 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2499 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2500 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2501 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2502 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2503 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2504 2505 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2506 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2507 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2508 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2509 2510 .dp_aux_init = qmp_v3_dp_aux_init, 2511 .configure_dp_tx = qmp_v3_configure_dp_tx, 2512 .configure_dp_phy = qmp_v3_configure_dp_phy, 2513 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2514 2515 .reset_list = sc7180_usb3phy_reset_l, 2516 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 2517 .vreg_list = qmp_phy_vreg_l, 2518 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2519 .regs = qmp_v3_usb3phy_regs_layout, 2520 2521 .has_pwrdn_delay = true, 2522 }; 2523 2524 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 2525 .offsets = &qmp_combo_offsets_v3, 2526 2527 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2528 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2529 .tx_tbl = qmp_v3_usb3_tx_tbl, 2530 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2531 .rx_tbl = qmp_v3_usb3_rx_tbl, 2532 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2533 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2534 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2535 2536 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2537 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2538 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2539 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2540 2541 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2542 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2543 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2544 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2545 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2546 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2547 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2548 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2549 2550 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2551 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2552 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2553 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2554 2555 .dp_aux_init = qmp_v3_dp_aux_init, 2556 .configure_dp_tx = qmp_v3_configure_dp_tx, 2557 .configure_dp_phy = qmp_v3_configure_dp_phy, 2558 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2559 2560 .reset_list = msm8996_usb3phy_reset_l, 2561 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2562 .vreg_list = qmp_phy_vreg_l, 2563 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2564 .regs = qmp_v3_usb3phy_regs_layout, 2565 2566 .has_pwrdn_delay = true, 2567 }; 2568 2569 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 2570 .offsets = &qmp_combo_offsets_v3, 2571 2572 .serdes_tbl = sm8150_usb3_serdes_tbl, 2573 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2574 .tx_tbl = sm8150_usb3_tx_tbl, 2575 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 2576 .rx_tbl = sm8150_usb3_rx_tbl, 2577 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 2578 .pcs_tbl = sm8150_usb3_pcs_tbl, 2579 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 2580 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 2581 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 2582 2583 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2584 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2585 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2586 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2587 2588 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2589 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2590 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2591 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2592 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2593 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2594 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2595 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2596 2597 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2598 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2599 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2600 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2601 2602 .dp_aux_init = qmp_v4_dp_aux_init, 2603 .configure_dp_tx = qmp_v4_configure_dp_tx, 2604 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2605 .configure_dp_phy = qmp_v4_configure_dp_phy, 2606 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2607 2608 .reset_list = msm8996_usb3phy_reset_l, 2609 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2610 .vreg_list = qmp_phy_vreg_l, 2611 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2612 .regs = qmp_v45_usb3phy_regs_layout, 2613 .pcs_usb_offset = 0x300, 2614 2615 .has_pwrdn_delay = true, 2616 }; 2617 2618 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 2619 .offsets = &qmp_combo_offsets_v5, 2620 2621 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 2622 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 2623 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 2624 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 2625 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 2626 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 2627 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 2628 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 2629 2630 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 2631 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 2632 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 2633 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 2634 2635 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2636 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2637 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2638 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2639 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2640 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2641 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2642 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2643 2644 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2645 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 2646 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2647 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2648 2649 .dp_aux_init = qmp_v4_dp_aux_init, 2650 .configure_dp_tx = qmp_v4_configure_dp_tx, 2651 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2652 .configure_dp_phy = qmp_v4_configure_dp_phy, 2653 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2654 2655 .reset_list = msm8996_usb3phy_reset_l, 2656 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2657 .vreg_list = qmp_phy_vreg_l, 2658 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2659 .regs = qmp_v5_5nm_usb3phy_regs_layout, 2660 }; 2661 2662 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 2663 .offsets = &qmp_combo_offsets_v5, 2664 2665 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 2666 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 2667 .tx_tbl = x1e80100_usb43dp_tx_tbl, 2668 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 2669 .rx_tbl = x1e80100_usb43dp_rx_tbl, 2670 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 2671 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 2672 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 2673 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 2674 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 2675 2676 .dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl, 2677 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl), 2678 .dp_tx_tbl = qmp_v6_n4_dp_tx_tbl, 2679 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl), 2680 2681 .serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr, 2682 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr), 2683 .serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr, 2684 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr), 2685 .serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2, 2686 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2), 2687 .serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3, 2688 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3), 2689 2690 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2691 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2692 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2693 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2694 2695 .dp_aux_init = qmp_v4_dp_aux_init, 2696 .configure_dp_tx = qmp_v4_configure_dp_tx, 2697 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2698 .configure_dp_phy = qmp_v4_configure_dp_phy, 2699 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2700 2701 .reset_list = msm8996_usb3phy_reset_l, 2702 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2703 .vreg_list = qmp_phy_vreg_l, 2704 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2705 .regs = qmp_v6_n4_usb3phy_regs_layout, 2706 }; 2707 2708 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 2709 .offsets = &qmp_combo_offsets_v3, 2710 2711 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2712 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2713 .tx_tbl = qmp_v3_usb3_tx_tbl, 2714 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2715 .rx_tbl = sm6350_usb3_rx_tbl, 2716 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 2717 .pcs_tbl = sm6350_usb3_pcs_tbl, 2718 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 2719 2720 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2721 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2722 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2723 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2724 2725 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2726 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2727 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2728 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2729 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2730 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2731 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2732 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2733 2734 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2735 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2736 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2737 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2738 2739 .dp_aux_init = qmp_v3_dp_aux_init, 2740 .configure_dp_tx = qmp_v3_configure_dp_tx, 2741 .configure_dp_phy = qmp_v3_configure_dp_phy, 2742 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2743 2744 .reset_list = msm8996_usb3phy_reset_l, 2745 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2746 .vreg_list = qmp_phy_vreg_l, 2747 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2748 .regs = qmp_v3_usb3phy_regs_layout, 2749 }; 2750 2751 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 2752 .offsets = &qmp_combo_offsets_v3, 2753 2754 .serdes_tbl = sm8150_usb3_serdes_tbl, 2755 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2756 .tx_tbl = sm8250_usb3_tx_tbl, 2757 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 2758 .rx_tbl = sm8250_usb3_rx_tbl, 2759 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 2760 .pcs_tbl = sm8250_usb3_pcs_tbl, 2761 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 2762 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 2763 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 2764 2765 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2766 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2767 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2768 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2769 2770 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2771 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2772 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2773 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2774 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2775 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2776 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2777 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2778 2779 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2780 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2781 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2782 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2783 2784 .dp_aux_init = qmp_v4_dp_aux_init, 2785 .configure_dp_tx = qmp_v4_configure_dp_tx, 2786 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2787 .configure_dp_phy = qmp_v4_configure_dp_phy, 2788 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2789 2790 .reset_list = msm8996_usb3phy_reset_l, 2791 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2792 .vreg_list = qmp_phy_vreg_l, 2793 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2794 .regs = qmp_v45_usb3phy_regs_layout, 2795 .pcs_usb_offset = 0x300, 2796 2797 .has_pwrdn_delay = true, 2798 }; 2799 2800 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 2801 .offsets = &qmp_combo_offsets_v3, 2802 2803 .serdes_tbl = sm8150_usb3_serdes_tbl, 2804 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2805 .tx_tbl = sm8350_usb3_tx_tbl, 2806 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 2807 .rx_tbl = sm8350_usb3_rx_tbl, 2808 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 2809 .pcs_tbl = sm8350_usb3_pcs_tbl, 2810 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 2811 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 2812 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 2813 2814 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2815 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2816 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 2817 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 2818 2819 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2820 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2821 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2822 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2823 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2824 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2825 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2826 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2827 2828 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 2829 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 2830 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2831 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 2832 2833 .dp_aux_init = qmp_v4_dp_aux_init, 2834 .configure_dp_tx = qmp_v4_configure_dp_tx, 2835 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2836 .configure_dp_phy = qmp_v4_configure_dp_phy, 2837 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2838 2839 .reset_list = msm8996_usb3phy_reset_l, 2840 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2841 .vreg_list = qmp_phy_vreg_l, 2842 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2843 .regs = qmp_v45_usb3phy_regs_layout, 2844 2845 .has_pwrdn_delay = true, 2846 }; 2847 2848 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 2849 .offsets = &qmp_combo_offsets_v3, 2850 2851 .serdes_tbl = sm8550_usb3_serdes_tbl, 2852 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2853 .tx_tbl = sm8550_usb3_tx_tbl, 2854 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2855 .rx_tbl = sm8550_usb3_rx_tbl, 2856 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2857 .pcs_tbl = sm8550_usb3_pcs_tbl, 2858 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2859 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2860 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2861 2862 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2863 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2864 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2865 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2866 2867 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2868 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2869 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2870 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2871 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2872 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2873 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2874 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2875 2876 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2877 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2878 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2879 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2880 2881 .dp_aux_init = qmp_v4_dp_aux_init, 2882 .configure_dp_tx = qmp_v4_configure_dp_tx, 2883 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2884 .configure_dp_phy = qmp_v4_configure_dp_phy, 2885 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2886 2887 .regs = qmp_v6_usb3phy_regs_layout, 2888 .reset_list = msm8996_usb3phy_reset_l, 2889 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2890 .vreg_list = qmp_phy_vreg_l, 2891 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2892 }; 2893 2894 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = { 2895 .offsets = &qmp_combo_offsets_v3, 2896 2897 .serdes_tbl = sm8550_usb3_serdes_tbl, 2898 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2899 .tx_tbl = sm8550_usb3_tx_tbl, 2900 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2901 .rx_tbl = sm8550_usb3_rx_tbl, 2902 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2903 .pcs_tbl = sm8550_usb3_pcs_tbl, 2904 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2905 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2906 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2907 2908 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2909 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2910 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2911 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2912 2913 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2914 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2915 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2916 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2917 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2918 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2919 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2920 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2921 2922 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2923 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2924 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2925 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2926 2927 .dp_aux_init = qmp_v4_dp_aux_init, 2928 .configure_dp_tx = qmp_v4_configure_dp_tx, 2929 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2930 .configure_dp_phy = qmp_v4_configure_dp_phy, 2931 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2932 2933 .regs = qmp_v6_usb3phy_regs_layout, 2934 .reset_list = msm8996_usb3phy_reset_l, 2935 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2936 .vreg_list = qmp_phy_vreg_l, 2937 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2938 }; 2939 2940 static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { 2941 .offsets = &qmp_combo_offsets_v8, 2942 2943 .serdes_tbl = sm8750_usb3_serdes_tbl, 2944 .serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl), 2945 .tx_tbl = sm8750_usb3_tx_tbl, 2946 .tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl), 2947 .rx_tbl = sm8750_usb3_rx_tbl, 2948 .rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl), 2949 .pcs_tbl = sm8750_usb3_pcs_tbl, 2950 .pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl), 2951 .pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl, 2952 .pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), 2953 2954 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2955 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2956 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2957 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2958 2959 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2960 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2961 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2962 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2963 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2964 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2965 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2966 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2967 2968 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2969 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2970 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2971 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2972 2973 .dp_aux_init = qmp_v4_dp_aux_init, 2974 .configure_dp_tx = qmp_v4_configure_dp_tx, 2975 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2976 .configure_dp_phy = qmp_v4_configure_dp_phy, 2977 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2978 2979 .regs = qmp_v8_usb3phy_regs_layout, 2980 .reset_list = msm8996_usb3phy_reset_l, 2981 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2982 .vreg_list = qmp_phy_vreg_l, 2983 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2984 }; 2985 2986 static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = { 2987 .offsets = &qmp_combo_usb43dp_offsets_v8, 2988 2989 .serdes_tbl = glymur_usb43dp_serdes_tbl, 2990 .serdes_tbl_num = ARRAY_SIZE(glymur_usb43dp_serdes_tbl), 2991 .tx_tbl = glymur_usb43dp_lalb_tbl, 2992 .tx_tbl_num = ARRAY_SIZE(glymur_usb43dp_lalb_tbl), 2993 .pcs_tbl = glymur_usb43dp_pcs_tbl, 2994 .pcs_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_tbl), 2995 .pcs_usb_tbl = glymur_usb43dp_pcs_usb_tbl, 2996 .pcs_usb_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl), 2997 .pcs_misc_tbl = glymur_usb43dp_pcs_misc_tbl, 2998 .pcs_misc_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl), 2999 3000 .dp_serdes_tbl = qmp_v8_dp_serdes_tbl, 3001 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl), 3002 .dp_tx_tbl = qmp_v8_n3p_dp_tx_tbl, 3003 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v8_n3p_dp_tx_tbl), 3004 3005 .serdes_tbl_rbr = qmp_v8_dp_serdes_tbl_rbr, 3006 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_rbr), 3007 .serdes_tbl_hbr = qmp_v8_dp_serdes_tbl_hbr, 3008 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr), 3009 .serdes_tbl_hbr2 = qmp_v8_dp_serdes_tbl_hbr2, 3010 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr2), 3011 .serdes_tbl_hbr3 = qmp_v8_dp_serdes_tbl_hbr3, 3012 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr3), 3013 3014 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 3015 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 3016 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 3017 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3018 3019 .dp_aux_init = qmp_v8_dp_aux_init, 3020 .configure_dp_tx = qmp_v4_configure_dp_tx, 3021 .configure_dp_clocks = qmp_v8_configure_dp_clocks, 3022 .configure_dp_phy = qmp_v8_configure_dp_phy, 3023 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 3024 3025 .regs = qmp_v8_n3_usb43dpphy_regs_layout, 3026 .reset_list = msm8996_usb3phy_reset_l, 3027 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3028 .vreg_list = qmp_phy_vreg_refgen, 3029 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_refgen), 3030 }; 3031 3032 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 3033 { 3034 const struct qmp_phy_cfg *cfg = qmp->cfg; 3035 void __iomem *serdes = qmp->dp_serdes; 3036 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3037 3038 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 3039 cfg->dp_serdes_tbl_num); 3040 3041 switch (dp_opts->link_rate) { 3042 case 1620: 3043 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 3044 cfg->serdes_tbl_rbr_num); 3045 break; 3046 case 2700: 3047 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 3048 cfg->serdes_tbl_hbr_num); 3049 break; 3050 case 5400: 3051 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 3052 cfg->serdes_tbl_hbr2_num); 3053 break; 3054 case 8100: 3055 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, 3056 cfg->serdes_tbl_hbr3_num); 3057 break; 3058 default: 3059 /* Other link rates aren't supported */ 3060 return -EINVAL; 3061 } 3062 3063 return 0; 3064 } 3065 3066 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 3067 { 3068 const struct qmp_phy_cfg *cfg = qmp->cfg; 3069 3070 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3071 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3072 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3073 3074 /* Turn on BIAS current for PHY/PLL */ 3075 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 3076 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 3077 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3078 3079 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3080 3081 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3082 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 3083 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 3084 DP_PHY_PD_CTL_DP_CLAMP_EN, 3085 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3086 3087 writel(QSERDES_V3_COM_BIAS_EN | 3088 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 3089 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 3090 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 3091 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3092 3093 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3094 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3095 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3096 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3097 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3098 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3099 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3100 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3101 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3102 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3103 qmp->dp_aux_cfg = 0; 3104 3105 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3106 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3107 PHY_AUX_REQ_ERR_MASK, 3108 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 3109 } 3110 3111 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 3112 { 3113 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3114 const struct qmp_phy_cfg *cfg = qmp->cfg; 3115 unsigned int v_level = 0, p_level = 0; 3116 u8 voltage_swing_cfg, pre_emphasis_cfg; 3117 int i; 3118 3119 for (i = 0; i < dp_opts->lanes; i++) { 3120 v_level = max(v_level, dp_opts->voltage[i]); 3121 p_level = max(p_level, dp_opts->pre[i]); 3122 } 3123 3124 if (dp_opts->link_rate <= 2700) { 3125 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 3126 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 3127 } else { 3128 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 3129 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 3130 } 3131 3132 /* TODO: Move check to config check */ 3133 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 3134 return -EINVAL; 3135 3136 /* Enable MUX to use Cursor values from these registers */ 3137 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 3138 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 3139 3140 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3141 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3142 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3143 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3144 3145 return 0; 3146 } 3147 3148 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 3149 { 3150 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3151 u32 bias_en, drvr_en; 3152 3153 if (qmp_combo_configure_dp_swing(qmp) < 0) 3154 return; 3155 3156 if (dp_opts->lanes == 1) { 3157 bias_en = 0x3e; 3158 drvr_en = 0x13; 3159 } else { 3160 bias_en = 0x3f; 3161 drvr_en = 0x10; 3162 } 3163 3164 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 3165 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 3166 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 3167 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 3168 } 3169 3170 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 3171 { 3172 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3173 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3174 u32 val; 3175 3176 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3177 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 3178 3179 if (dp_opts->lanes == 4 || reverse) 3180 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 3181 if (dp_opts->lanes == 4 || !reverse) 3182 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 3183 3184 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3185 3186 if (reverse) 3187 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 3188 else 3189 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 3190 3191 return reverse; 3192 } 3193 3194 static int qmp_v3_configure_dp_clocks(struct qmp_combo *qmp) 3195 { 3196 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3197 u32 phy_vco_div; 3198 unsigned long pixel_freq; 3199 const struct qmp_phy_cfg *cfg = qmp->cfg; 3200 3201 switch (dp_opts->link_rate) { 3202 case 1620: 3203 phy_vco_div = 0x1; 3204 pixel_freq = 1620000000UL / 2; 3205 break; 3206 case 2700: 3207 phy_vco_div = 0x1; 3208 pixel_freq = 2700000000UL / 2; 3209 break; 3210 case 5400: 3211 phy_vco_div = 0x2; 3212 pixel_freq = 5400000000UL / 4; 3213 break; 3214 case 8100: 3215 phy_vco_div = 0x0; 3216 pixel_freq = 8100000000UL / 6; 3217 break; 3218 default: 3219 /* Other link rates aren't supported */ 3220 return -EINVAL; 3221 } 3222 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 3223 3224 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 3225 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 3226 3227 return 0; 3228 } 3229 3230 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 3231 { 3232 const struct qmp_phy_cfg *cfg = qmp->cfg; 3233 u32 status; 3234 int ret; 3235 3236 qmp_combo_configure_dp_mode(qmp); 3237 3238 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 3239 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 3240 3241 ret = qmp_v3_configure_dp_clocks(qmp); 3242 if (ret) 3243 return ret; 3244 3245 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3246 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3247 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3248 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3249 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3250 3251 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 3252 3253 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 3254 status, 3255 ((status & BIT(0)) > 0), 3256 500, 3257 10000)) 3258 return -ETIMEDOUT; 3259 3260 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3261 3262 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3263 status, 3264 ((status & BIT(1)) > 0), 3265 500, 3266 10000)) 3267 return -ETIMEDOUT; 3268 3269 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3270 udelay(2000); 3271 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3272 3273 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3274 status, 3275 ((status & BIT(1)) > 0), 3276 500, 3277 10000); 3278 } 3279 3280 /* 3281 * We need to calibrate the aux setting here as many times 3282 * as the caller tries 3283 */ 3284 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 3285 { 3286 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 3287 u8 val; 3288 3289 qmp->dp_aux_cfg++; 3290 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 3291 val = cfg1_settings[qmp->dp_aux_cfg]; 3292 3293 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3294 3295 return 0; 3296 } 3297 3298 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 3299 { 3300 const struct qmp_phy_cfg *cfg = qmp->cfg; 3301 3302 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3303 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3304 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3305 3306 /* Turn on BIAS current for PHY/PLL */ 3307 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3308 3309 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3310 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3311 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3312 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3313 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3314 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3315 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3316 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3317 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3318 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3319 qmp->dp_aux_cfg = 0; 3320 3321 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3322 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3323 PHY_AUX_REQ_ERR_MASK, 3324 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 3325 } 3326 3327 static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) 3328 { 3329 const struct qmp_phy_cfg *cfg = qmp->cfg; 3330 3331 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3332 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3333 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3334 3335 /* Turn on BIAS current for PHY/PLL */ 3336 writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3337 3338 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3339 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3340 writel(0x06, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3341 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3342 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3343 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3344 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3345 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3346 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3347 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3348 qmp->dp_aux_cfg = 0; 3349 3350 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3351 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3352 PHY_AUX_REQ_ERR_MASK, 3353 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 3354 } 3355 3356 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 3357 { 3358 const struct qmp_phy_cfg *cfg = qmp->cfg; 3359 3360 /* Program default values before writing proper values */ 3361 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3362 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3363 3364 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3365 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3366 3367 qmp_combo_configure_dp_swing(qmp); 3368 } 3369 3370 static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) 3371 { 3372 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3373 u32 phy_vco_div; 3374 unsigned long pixel_freq; 3375 const struct qmp_phy_cfg *cfg = qmp->cfg; 3376 3377 switch (dp_opts->link_rate) { 3378 case 1620: 3379 phy_vco_div = 0x4; 3380 pixel_freq = 1620000000UL / 2; 3381 break; 3382 case 2700: 3383 phy_vco_div = 0x2; 3384 pixel_freq = 2700000000UL / 2; 3385 break; 3386 case 5400: 3387 phy_vco_div = 0x4; 3388 pixel_freq = 5400000000UL / 4; 3389 break; 3390 case 8100: 3391 phy_vco_div = 0x3; 3392 pixel_freq = 8100000000UL / 6; 3393 break; 3394 default: 3395 /* Other link rates aren't supported */ 3396 return -EINVAL; 3397 } 3398 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 3399 3400 /* disable core reset tsync */ 3401 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3402 3403 writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); 3404 writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); 3405 writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); 3406 writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); 3407 3408 writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); 3409 writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); 3410 writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); 3411 writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); 3412 writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); 3413 writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); 3414 writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); 3415 3416 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 3417 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 3418 3419 return 0; 3420 } 3421 3422 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 3423 { 3424 const struct qmp_phy_cfg *cfg = qmp->cfg; 3425 u32 status; 3426 int ret; 3427 3428 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 3429 3430 qmp_combo_configure_dp_mode(qmp); 3431 3432 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3433 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3434 3435 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 3436 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 3437 3438 ret = qmp->cfg->configure_dp_clocks(qmp); 3439 if (ret) 3440 return ret; 3441 3442 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3443 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3444 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3445 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3446 3447 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 3448 3449 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 3450 status, 3451 ((status & BIT(0)) > 0), 3452 500, 3453 10000)) 3454 return -ETIMEDOUT; 3455 3456 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 3457 status, 3458 ((status & BIT(0)) > 0), 3459 500, 3460 10000)) 3461 return -ETIMEDOUT; 3462 3463 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 3464 status, 3465 ((status & BIT(1)) > 0), 3466 500, 3467 10000)) 3468 return -ETIMEDOUT; 3469 3470 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3471 3472 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3473 status, 3474 ((status & BIT(0)) > 0), 3475 500, 3476 10000)) 3477 return -ETIMEDOUT; 3478 3479 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3480 status, 3481 ((status & BIT(1)) > 0), 3482 500, 3483 10000)) 3484 return -ETIMEDOUT; 3485 3486 return 0; 3487 } 3488 3489 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 3490 { 3491 const struct qmp_phy_cfg *cfg = qmp->cfg; 3492 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3493 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3494 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 3495 u32 status; 3496 int ret; 3497 3498 ret = qmp_v456_configure_dp_phy(qmp); 3499 if (ret < 0) 3500 return ret; 3501 3502 /* 3503 * At least for 7nm DP PHY this has to be done after enabling link 3504 * clock. 3505 */ 3506 3507 if (dp_opts->lanes == 1) { 3508 bias0_en = reverse ? 0x3e : 0x15; 3509 bias1_en = reverse ? 0x15 : 0x3e; 3510 drvr0_en = reverse ? 0x13 : 0x10; 3511 drvr1_en = reverse ? 0x10 : 0x13; 3512 } else if (dp_opts->lanes == 2) { 3513 bias0_en = reverse ? 0x3f : 0x15; 3514 bias1_en = reverse ? 0x15 : 0x3f; 3515 drvr0_en = 0x10; 3516 drvr1_en = 0x10; 3517 } else { 3518 bias0_en = 0x3f; 3519 bias1_en = 0x3f; 3520 drvr0_en = 0x10; 3521 drvr1_en = 0x10; 3522 } 3523 3524 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3525 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3526 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3527 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3528 3529 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3530 udelay(2000); 3531 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3532 3533 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3534 status, 3535 ((status & BIT(1)) > 0), 3536 500, 3537 10000)) 3538 return -ETIMEDOUT; 3539 3540 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 3541 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 3542 3543 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3544 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3545 3546 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3547 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3548 3549 return 0; 3550 } 3551 3552 static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) 3553 { 3554 const struct qmp_phy_cfg *cfg = qmp->cfg; 3555 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3556 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3557 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 3558 u32 status; 3559 int ret; 3560 3561 ret = qmp_v456_configure_dp_phy(qmp); 3562 if (ret < 0) 3563 return ret; 3564 3565 if (dp_opts->lanes == 1) { 3566 bias0_en = reverse ? 0x3e : 0x15; 3567 bias1_en = reverse ? 0x15 : 0x3e; 3568 drvr0_en = reverse ? 0x13 : 0x10; 3569 drvr1_en = reverse ? 0x10 : 0x13; 3570 } else if (dp_opts->lanes == 2) { 3571 bias0_en = reverse ? 0x3f : 0x15; 3572 bias1_en = reverse ? 0x15 : 0x3f; 3573 drvr0_en = 0x10; 3574 drvr1_en = 0x10; 3575 } else { 3576 bias0_en = 0x3f; 3577 bias1_en = 0x3f; 3578 drvr0_en = 0x34; 3579 drvr1_en = 0x34; 3580 } 3581 3582 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3583 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3584 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3585 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3586 3587 writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3588 udelay(100); 3589 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3590 udelay(500); 3591 3592 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3593 status, 3594 ((status & BIT(1)) > 0), 3595 500, 3596 10000)) 3597 return -ETIMEDOUT; 3598 3599 writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3600 writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3601 3602 writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3603 writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3604 3605 return 0; 3606 } 3607 3608 /* 3609 * We need to calibrate the aux setting here as many times 3610 * as the caller tries 3611 */ 3612 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 3613 { 3614 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 3615 u8 val; 3616 3617 qmp->dp_aux_cfg++; 3618 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 3619 val = cfg1_settings[qmp->dp_aux_cfg]; 3620 3621 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3622 3623 return 0; 3624 } 3625 3626 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 3627 { 3628 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 3629 struct qmp_combo *qmp = phy_get_drvdata(phy); 3630 const struct qmp_phy_cfg *cfg = qmp->cfg; 3631 3632 mutex_lock(&qmp->phy_mutex); 3633 3634 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 3635 if (qmp->dp_opts.set_voltages) { 3636 cfg->configure_dp_tx(qmp); 3637 qmp->dp_opts.set_voltages = 0; 3638 } 3639 3640 mutex_unlock(&qmp->phy_mutex); 3641 3642 return 0; 3643 } 3644 3645 static int qmp_combo_dp_calibrate(struct phy *phy) 3646 { 3647 struct qmp_combo *qmp = phy_get_drvdata(phy); 3648 const struct qmp_phy_cfg *cfg = qmp->cfg; 3649 int ret = 0; 3650 3651 mutex_lock(&qmp->phy_mutex); 3652 3653 if (cfg->calibrate_dp_phy) 3654 ret = cfg->calibrate_dp_phy(qmp); 3655 3656 mutex_unlock(&qmp->phy_mutex); 3657 3658 return ret; 3659 } 3660 3661 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 3662 { 3663 const struct qmp_phy_cfg *cfg = qmp->cfg; 3664 void __iomem *com = qmp->com; 3665 void __iomem *pcs_aon = qmp->pcs_aon; 3666 int ret; 3667 u32 val; 3668 3669 if (!force && qmp->init_count++) 3670 return 0; 3671 3672 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 3673 if (ret) { 3674 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 3675 goto err_decrement_count; 3676 } 3677 3678 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3679 if (ret) { 3680 dev_err(qmp->dev, "reset assert failed\n"); 3681 goto err_disable_regulators; 3682 } 3683 3684 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 3685 if (ret) { 3686 dev_err(qmp->dev, "reset deassert failed\n"); 3687 goto err_disable_regulators; 3688 } 3689 3690 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 3691 if (ret) 3692 goto err_assert_reset; 3693 3694 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 3695 3696 /* override hardware control for reset of qmp phy */ 3697 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3698 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3699 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3700 3701 /* override hardware control for reset of qmp phy */ 3702 if (pcs_aon && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) { 3703 qphy_clrbits(pcs_aon, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); 3704 qphy_clrbits(pcs_aon, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1); 3705 } 3706 3707 /* Use software based port select and switch on typec orientation */ 3708 val = SW_PORTSELECT_MUX; 3709 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 3710 val |= SW_PORTSELECT_VAL; 3711 3712 if (cfg->invert_cc_polarity) 3713 val |= INVERT_CC_POLARITY; 3714 3715 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 3716 3717 switch (qmp->qmpphy_mode) { 3718 case QMPPHY_MODE_USB3DP: 3719 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3720 3721 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 3722 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3723 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 3724 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3725 break; 3726 3727 case QMPPHY_MODE_DP_ONLY: 3728 writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3729 3730 /* bring QMP DP PHY PCS block out of reset */ 3731 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3732 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET); 3733 break; 3734 3735 case QMPPHY_MODE_USB3_ONLY: 3736 writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 3737 3738 /* bring QMP USB PHY PCS block out of reset */ 3739 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 3740 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 3741 break; 3742 } 3743 3744 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 3745 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 3746 3747 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3748 SW_PWRDN); 3749 3750 return 0; 3751 3752 err_assert_reset: 3753 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3754 err_disable_regulators: 3755 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3756 err_decrement_count: 3757 qmp->init_count--; 3758 3759 return ret; 3760 } 3761 3762 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 3763 { 3764 const struct qmp_phy_cfg *cfg = qmp->cfg; 3765 3766 if (!force && --qmp->init_count) 3767 return 0; 3768 3769 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 3770 3771 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 3772 3773 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 3774 3775 return 0; 3776 } 3777 3778 static int qmp_combo_dp_init(struct phy *phy) 3779 { 3780 struct qmp_combo *qmp = phy_get_drvdata(phy); 3781 const struct qmp_phy_cfg *cfg = qmp->cfg; 3782 int ret; 3783 3784 mutex_lock(&qmp->phy_mutex); 3785 3786 ret = qmp_combo_com_init(qmp, false); 3787 if (ret) 3788 goto out_unlock; 3789 3790 cfg->dp_aux_init(qmp); 3791 3792 qmp->dp_init_count++; 3793 3794 out_unlock: 3795 mutex_unlock(&qmp->phy_mutex); 3796 return ret; 3797 } 3798 3799 static int qmp_combo_dp_exit(struct phy *phy) 3800 { 3801 struct qmp_combo *qmp = phy_get_drvdata(phy); 3802 3803 mutex_lock(&qmp->phy_mutex); 3804 3805 qmp_combo_com_exit(qmp, false); 3806 3807 qmp->dp_init_count--; 3808 3809 mutex_unlock(&qmp->phy_mutex); 3810 3811 return 0; 3812 } 3813 3814 static int qmp_combo_dp_power_on(struct phy *phy) 3815 { 3816 struct qmp_combo *qmp = phy_get_drvdata(phy); 3817 const struct qmp_phy_cfg *cfg = qmp->cfg; 3818 void __iomem *tx = qmp->dp_tx; 3819 void __iomem *tx2 = qmp->dp_tx2; 3820 3821 mutex_lock(&qmp->phy_mutex); 3822 3823 qmp_combo_dp_serdes_init(qmp); 3824 3825 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 3826 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 3827 3828 /* Configure special DP tx tunings */ 3829 cfg->configure_dp_tx(qmp); 3830 3831 /* Configure link rate, swing, etc. */ 3832 cfg->configure_dp_phy(qmp); 3833 3834 qmp->dp_powered_on = true; 3835 3836 mutex_unlock(&qmp->phy_mutex); 3837 3838 return 0; 3839 } 3840 3841 static int qmp_combo_dp_power_off(struct phy *phy) 3842 { 3843 struct qmp_combo *qmp = phy_get_drvdata(phy); 3844 3845 mutex_lock(&qmp->phy_mutex); 3846 3847 /* Assert DP PHY power down */ 3848 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3849 3850 qmp->dp_powered_on = false; 3851 3852 mutex_unlock(&qmp->phy_mutex); 3853 3854 return 0; 3855 } 3856 3857 static int qmp_combo_usb_power_on(struct phy *phy) 3858 { 3859 struct qmp_combo *qmp = phy_get_drvdata(phy); 3860 const struct qmp_phy_cfg *cfg = qmp->cfg; 3861 void __iomem *serdes = qmp->serdes; 3862 void __iomem *tx = qmp->tx; 3863 void __iomem *rx = qmp->rx; 3864 void __iomem *tx2 = qmp->tx2; 3865 void __iomem *rx2 = qmp->rx2; 3866 void __iomem *pcs = qmp->pcs; 3867 void __iomem *pcs_usb = qmp->pcs_usb; 3868 void __iomem *status; 3869 unsigned int val; 3870 int ret; 3871 3872 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 3873 3874 ret = clk_prepare_enable(qmp->pipe_clk); 3875 if (ret) { 3876 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 3877 return ret; 3878 } 3879 3880 /* Tx, Rx, and PCS configurations */ 3881 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 3882 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 3883 3884 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 3885 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 3886 3887 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 3888 qmp_configure(qmp->dev, qmp->pcs_misc, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); 3889 3890 3891 if (pcs_usb) 3892 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, 3893 cfg->pcs_usb_tbl_num); 3894 3895 if (cfg->has_pwrdn_delay) 3896 usleep_range(10, 20); 3897 3898 /* Pull PHY out of reset state */ 3899 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3900 3901 /* start SerDes and Phy-Coding-Sublayer */ 3902 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 3903 3904 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 3905 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 3906 PHY_INIT_COMPLETE_TIMEOUT); 3907 if (ret) { 3908 dev_err(qmp->dev, "phy initialization timed-out\n"); 3909 goto err_disable_pipe_clk; 3910 } 3911 3912 return 0; 3913 3914 err_disable_pipe_clk: 3915 clk_disable_unprepare(qmp->pipe_clk); 3916 3917 return ret; 3918 } 3919 3920 static int qmp_combo_usb_power_off(struct phy *phy) 3921 { 3922 struct qmp_combo *qmp = phy_get_drvdata(phy); 3923 const struct qmp_phy_cfg *cfg = qmp->cfg; 3924 3925 clk_disable_unprepare(qmp->pipe_clk); 3926 3927 /* PHY reset */ 3928 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 3929 3930 /* stop SerDes and Phy-Coding-Sublayer */ 3931 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 3932 SERDES_START | PCS_START); 3933 3934 /* Put PHY into POWER DOWN state: active low */ 3935 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 3936 SW_PWRDN); 3937 3938 return 0; 3939 } 3940 3941 static int qmp_combo_usb_init(struct phy *phy) 3942 { 3943 struct qmp_combo *qmp = phy_get_drvdata(phy); 3944 int ret; 3945 3946 mutex_lock(&qmp->phy_mutex); 3947 ret = qmp_combo_com_init(qmp, false); 3948 if (ret) 3949 goto out_unlock; 3950 3951 ret = qmp_combo_usb_power_on(phy); 3952 if (ret) { 3953 qmp_combo_com_exit(qmp, false); 3954 goto out_unlock; 3955 } 3956 3957 qmp->usb_init_count++; 3958 3959 out_unlock: 3960 mutex_unlock(&qmp->phy_mutex); 3961 return ret; 3962 } 3963 3964 static int qmp_combo_usb_exit(struct phy *phy) 3965 { 3966 struct qmp_combo *qmp = phy_get_drvdata(phy); 3967 int ret; 3968 3969 mutex_lock(&qmp->phy_mutex); 3970 ret = qmp_combo_usb_power_off(phy); 3971 if (ret) 3972 goto out_unlock; 3973 3974 ret = qmp_combo_com_exit(qmp, false); 3975 if (ret) 3976 goto out_unlock; 3977 3978 qmp->usb_init_count--; 3979 3980 out_unlock: 3981 mutex_unlock(&qmp->phy_mutex); 3982 return ret; 3983 } 3984 3985 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 3986 { 3987 struct qmp_combo *qmp = phy_get_drvdata(phy); 3988 3989 qmp->phy_mode = mode; 3990 3991 return 0; 3992 } 3993 3994 static const struct phy_ops qmp_combo_usb_phy_ops = { 3995 .init = qmp_combo_usb_init, 3996 .exit = qmp_combo_usb_exit, 3997 .set_mode = qmp_combo_usb_set_mode, 3998 .owner = THIS_MODULE, 3999 }; 4000 4001 static const struct phy_ops qmp_combo_dp_phy_ops = { 4002 .init = qmp_combo_dp_init, 4003 .configure = qmp_combo_dp_configure, 4004 .power_on = qmp_combo_dp_power_on, 4005 .calibrate = qmp_combo_dp_calibrate, 4006 .power_off = qmp_combo_dp_power_off, 4007 .exit = qmp_combo_dp_exit, 4008 .owner = THIS_MODULE, 4009 }; 4010 4011 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 4012 { 4013 const struct qmp_phy_cfg *cfg = qmp->cfg; 4014 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 4015 void __iomem *pcs_misc = qmp->pcs_misc; 4016 void __iomem *pcs_aon = qmp->pcs_aon; 4017 u32 intr_mask; 4018 4019 if (qmp->phy_mode == PHY_MODE_USB_HOST_SS || 4020 qmp->phy_mode == PHY_MODE_USB_DEVICE_SS) 4021 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 4022 else 4023 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 4024 4025 /* Clear any pending interrupts status */ 4026 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4027 /* Writing 1 followed by 0 clears the interrupt */ 4028 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4029 4030 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 4031 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 4032 4033 /* Enable required PHY autonomous mode interrupts */ 4034 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 4035 4036 /* 4037 * Enable i/o clamp_n for autonomous mode 4038 * V6 and later versions use pcs aon clamp register 4039 */ 4040 if (pcs_aon) 4041 qphy_clrbits(pcs_aon, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4042 else if (pcs_misc) 4043 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4044 } 4045 4046 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 4047 { 4048 const struct qmp_phy_cfg *cfg = qmp->cfg; 4049 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 4050 void __iomem *pcs_misc = qmp->pcs_misc; 4051 void __iomem *pcs_aon = qmp->pcs_aon; 4052 4053 /* Disable i/o clamp_n on resume for normal mode */ 4054 if (pcs_aon) 4055 qphy_setbits(pcs_aon, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4056 else if (pcs_misc) 4057 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4058 4059 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 4060 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 4061 4062 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4063 /* Writing 1 followed by 0 clears the interrupt */ 4064 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4065 } 4066 4067 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 4068 { 4069 struct qmp_combo *qmp = dev_get_drvdata(dev); 4070 4071 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->phy_mode); 4072 4073 if (!qmp->init_count) { 4074 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 4075 return 0; 4076 } 4077 4078 qmp_combo_enable_autonomous_mode(qmp); 4079 4080 clk_disable_unprepare(qmp->pipe_clk); 4081 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 4082 4083 return 0; 4084 } 4085 4086 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 4087 { 4088 struct qmp_combo *qmp = dev_get_drvdata(dev); 4089 int ret = 0; 4090 4091 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->phy_mode); 4092 4093 if (!qmp->init_count) { 4094 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 4095 return 0; 4096 } 4097 4098 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 4099 if (ret) 4100 return ret; 4101 4102 ret = clk_prepare_enable(qmp->pipe_clk); 4103 if (ret) { 4104 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 4105 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 4106 return ret; 4107 } 4108 4109 qmp_combo_disable_autonomous_mode(qmp); 4110 4111 return 0; 4112 } 4113 4114 static const struct dev_pm_ops qmp_combo_pm_ops = { 4115 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 4116 qmp_combo_runtime_resume, NULL) 4117 }; 4118 4119 static int qmp_combo_reset_init(struct qmp_combo *qmp) 4120 { 4121 const struct qmp_phy_cfg *cfg = qmp->cfg; 4122 struct device *dev = qmp->dev; 4123 int i; 4124 int ret; 4125 4126 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 4127 sizeof(*qmp->resets), GFP_KERNEL); 4128 if (!qmp->resets) 4129 return -ENOMEM; 4130 4131 for (i = 0; i < cfg->num_resets; i++) 4132 qmp->resets[i].id = cfg->reset_list[i]; 4133 4134 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 4135 if (ret) 4136 return dev_err_probe(dev, ret, "failed to get resets\n"); 4137 4138 return 0; 4139 } 4140 4141 static int qmp_combo_clk_init(struct qmp_combo *qmp) 4142 { 4143 struct device *dev = qmp->dev; 4144 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 4145 int i; 4146 4147 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 4148 if (!qmp->clks) 4149 return -ENOMEM; 4150 4151 for (i = 0; i < num; i++) 4152 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 4153 4154 qmp->num_clks = num; 4155 4156 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 4157 } 4158 4159 static void phy_clk_release_provider(void *res) 4160 { 4161 of_clk_del_provider(res); 4162 } 4163 4164 /* 4165 * Register a fixed rate pipe clock. 4166 * 4167 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 4168 * controls it. The <s>_pipe_clk coming out of the GCC is requested 4169 * by the PHY driver for its operations. 4170 * We register the <s>_pipe_clksrc here. The gcc driver takes care 4171 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 4172 * Below picture shows this relationship. 4173 * 4174 * +---------------+ 4175 * | PHY block |<<---------------------------------------+ 4176 * | | | 4177 * | +-------+ | +-----+ | 4178 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 4179 * clk | +-------+ | +-----+ 4180 * +---------------+ 4181 */ 4182 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 4183 { 4184 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 4185 struct clk_init_data init = { }; 4186 char name[64]; 4187 4188 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 4189 init.name = name; 4190 init.ops = &clk_fixed_rate_ops; 4191 4192 /* controllers using QMP phys use 125MHz pipe clock interface */ 4193 fixed->fixed_rate = 125000000; 4194 fixed->hw.init = &init; 4195 4196 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4197 } 4198 4199 /* 4200 * Display Port PLL driver block diagram for branch clocks 4201 * 4202 * +------------------------------+ 4203 * | DP_VCO_CLK | 4204 * | | 4205 * | +-------------------+ | 4206 * | | (DP PLL/VCO) | | 4207 * | +---------+---------+ | 4208 * | v | 4209 * | +----------+-----------+ | 4210 * | | hsclk_divsel_clk_src | | 4211 * | +----------+-----------+ | 4212 * +------------------------------+ 4213 * | 4214 * +---------<---------v------------>----------+ 4215 * | | 4216 * +--------v----------------+ | 4217 * | dp_phy_pll_link_clk | | 4218 * | link_clk | | 4219 * +--------+----------------+ | 4220 * | | 4221 * | | 4222 * v v 4223 * Input to DISPCC block | 4224 * for link clk, crypto clk | 4225 * and interface clock | 4226 * | 4227 * | 4228 * +--------<------------+-----------------+---<---+ 4229 * | | | 4230 * +----v---------+ +--------v-----+ +--------v------+ 4231 * | vco_divided | | vco_divided | | vco_divided | 4232 * | _clk_src | | _clk_src | | _clk_src | 4233 * | | | | | | 4234 * |divsel_six | | divsel_two | | divsel_four | 4235 * +-------+------+ +-----+--------+ +--------+------+ 4236 * | | | 4237 * v---->----------v-------------<------v 4238 * | 4239 * +----------+-----------------+ 4240 * | dp_phy_pll_vco_div_clk | 4241 * +---------+------------------+ 4242 * | 4243 * v 4244 * Input to DISPCC block 4245 * for DP pixel clock 4246 * 4247 */ 4248 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 4249 { 4250 switch (req->rate) { 4251 case 1620000000UL / 2: 4252 case 2700000000UL / 2: 4253 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 4254 return 0; 4255 default: 4256 return -EINVAL; 4257 } 4258 } 4259 4260 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 4261 { 4262 const struct qmp_combo *qmp; 4263 const struct phy_configure_opts_dp *dp_opts; 4264 4265 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 4266 dp_opts = &qmp->dp_opts; 4267 4268 switch (dp_opts->link_rate) { 4269 case 1620: 4270 return 1620000000UL / 2; 4271 case 2700: 4272 return 2700000000UL / 2; 4273 case 5400: 4274 return 5400000000UL / 4; 4275 case 8100: 4276 return 8100000000UL / 6; 4277 default: 4278 return 0; 4279 } 4280 } 4281 4282 static const struct clk_ops qmp_dp_pixel_clk_ops = { 4283 .determine_rate = qmp_dp_pixel_clk_determine_rate, 4284 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 4285 }; 4286 4287 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 4288 { 4289 switch (req->rate) { 4290 case 162000000: 4291 case 270000000: 4292 case 540000000: 4293 case 810000000: 4294 return 0; 4295 default: 4296 return -EINVAL; 4297 } 4298 } 4299 4300 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 4301 { 4302 const struct qmp_combo *qmp; 4303 const struct phy_configure_opts_dp *dp_opts; 4304 4305 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 4306 dp_opts = &qmp->dp_opts; 4307 4308 switch (dp_opts->link_rate) { 4309 case 1620: 4310 case 2700: 4311 case 5400: 4312 case 8100: 4313 return dp_opts->link_rate * 100000; 4314 default: 4315 return 0; 4316 } 4317 } 4318 4319 static const struct clk_ops qmp_dp_link_clk_ops = { 4320 .determine_rate = qmp_dp_link_clk_determine_rate, 4321 .recalc_rate = qmp_dp_link_clk_recalc_rate, 4322 }; 4323 4324 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 4325 { 4326 struct qmp_combo *qmp = data; 4327 unsigned int idx = clkspec->args[0]; 4328 4329 if (idx >= 2) { 4330 pr_err("%s: invalid index %u\n", __func__, idx); 4331 return ERR_PTR(-EINVAL); 4332 } 4333 4334 if (idx == 0) 4335 return &qmp->dp_link_hw; 4336 4337 return &qmp->dp_pixel_hw; 4338 } 4339 4340 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 4341 { 4342 struct clk_init_data init = { }; 4343 char name[64]; 4344 int ret; 4345 4346 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 4347 init.ops = &qmp_dp_link_clk_ops; 4348 init.name = name; 4349 qmp->dp_link_hw.init = &init; 4350 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 4351 if (ret) 4352 return ret; 4353 4354 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 4355 init.ops = &qmp_dp_pixel_clk_ops; 4356 init.name = name; 4357 qmp->dp_pixel_hw.init = &init; 4358 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 4359 if (ret) 4360 return ret; 4361 4362 return 0; 4363 } 4364 4365 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 4366 { 4367 struct qmp_combo *qmp = data; 4368 4369 switch (clkspec->args[0]) { 4370 case QMP_USB43DP_USB3_PIPE_CLK: 4371 return &qmp->pipe_clk_fixed.hw; 4372 case QMP_USB43DP_DP_LINK_CLK: 4373 return &qmp->dp_link_hw; 4374 case QMP_USB43DP_DP_VCO_DIV_CLK: 4375 return &qmp->dp_pixel_hw; 4376 } 4377 4378 return ERR_PTR(-EINVAL); 4379 } 4380 4381 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 4382 struct device_node *dp_np) 4383 { 4384 int ret; 4385 4386 ret = phy_pipe_clk_register(qmp, usb_np); 4387 if (ret) 4388 return ret; 4389 4390 ret = phy_dp_clks_register(qmp, dp_np); 4391 if (ret) 4392 return ret; 4393 4394 /* 4395 * Register a single provider for bindings without child nodes. 4396 */ 4397 if (usb_np == qmp->dev->of_node) 4398 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 4399 4400 /* 4401 * Register multiple providers for legacy bindings with child nodes. 4402 */ 4403 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 4404 &qmp->pipe_clk_fixed.hw); 4405 if (ret) 4406 return ret; 4407 4408 /* 4409 * Roll a devm action because the clock provider is the child node, but 4410 * the child node is not actually a device. 4411 */ 4412 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 4413 if (ret) 4414 return ret; 4415 4416 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 4417 if (ret) 4418 return ret; 4419 4420 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 4421 } 4422 4423 #if IS_ENABLED(CONFIG_TYPEC) 4424 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 4425 enum typec_orientation orientation) 4426 { 4427 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 4428 const struct qmp_phy_cfg *cfg = qmp->cfg; 4429 4430 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 4431 return 0; 4432 4433 mutex_lock(&qmp->phy_mutex); 4434 qmp->orientation = orientation; 4435 4436 if (qmp->init_count) { 4437 if (qmp->usb_init_count) 4438 qmp_combo_usb_power_off(qmp->usb_phy); 4439 qmp_combo_com_exit(qmp, true); 4440 4441 qmp_combo_com_init(qmp, true); 4442 if (qmp->usb_init_count) 4443 qmp_combo_usb_power_on(qmp->usb_phy); 4444 if (qmp->dp_init_count) 4445 cfg->dp_aux_init(qmp); 4446 } 4447 mutex_unlock(&qmp->phy_mutex); 4448 4449 return 0; 4450 } 4451 4452 static int qmp_combo_typec_mux_set(struct typec_mux_dev *mux, struct typec_mux_state *state) 4453 { 4454 struct qmp_combo *qmp = typec_mux_get_drvdata(mux); 4455 const struct qmp_phy_cfg *cfg = qmp->cfg; 4456 enum qmpphy_mode new_mode; 4457 unsigned int svid; 4458 4459 guard(mutex)(&qmp->phy_mutex); 4460 4461 if (state->alt) 4462 svid = state->alt->svid; 4463 else 4464 svid = 0; 4465 4466 if (svid == USB_TYPEC_DP_SID) { 4467 switch (state->mode) { 4468 /* DP Only */ 4469 case TYPEC_DP_STATE_C: 4470 case TYPEC_DP_STATE_E: 4471 new_mode = QMPPHY_MODE_DP_ONLY; 4472 break; 4473 4474 /* DP + USB */ 4475 case TYPEC_DP_STATE_D: 4476 case TYPEC_DP_STATE_F: 4477 4478 /* Safe fallback...*/ 4479 default: 4480 new_mode = QMPPHY_MODE_USB3DP; 4481 break; 4482 } 4483 } else { 4484 /* No DP SVID => don't care, assume it's just USB3 */ 4485 new_mode = QMPPHY_MODE_USB3_ONLY; 4486 } 4487 4488 if (new_mode == qmp->qmpphy_mode) { 4489 dev_dbg(qmp->dev, "typec_mux_set: same qmpphy mode, bail out\n"); 4490 return 0; 4491 } 4492 4493 if (qmp->qmpphy_mode != QMPPHY_MODE_USB3_ONLY && qmp->dp_powered_on) { 4494 dev_dbg(qmp->dev, "typec_mux_set: DP PHY is still in use, delaying switch\n"); 4495 return 0; 4496 } 4497 4498 dev_dbg(qmp->dev, "typec_mux_set: switching from qmpphy mode %d to %d\n", 4499 qmp->qmpphy_mode, new_mode); 4500 4501 qmp->qmpphy_mode = new_mode; 4502 4503 if (qmp->init_count) { 4504 if (qmp->usb_init_count) 4505 qmp_combo_usb_power_off(qmp->usb_phy); 4506 4507 if (qmp->dp_init_count) 4508 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 4509 4510 qmp_combo_com_exit(qmp, true); 4511 4512 /* Now everything's powered down, power up the right PHYs */ 4513 qmp_combo_com_init(qmp, true); 4514 4515 if (new_mode == QMPPHY_MODE_DP_ONLY) { 4516 if (qmp->usb_init_count) 4517 qmp->usb_init_count--; 4518 } 4519 4520 if (new_mode == QMPPHY_MODE_USB3DP || new_mode == QMPPHY_MODE_USB3_ONLY) { 4521 qmp_combo_usb_power_on(qmp->usb_phy); 4522 if (!qmp->usb_init_count) 4523 qmp->usb_init_count++; 4524 } 4525 4526 if (new_mode == QMPPHY_MODE_DP_ONLY || new_mode == QMPPHY_MODE_USB3DP) { 4527 if (qmp->dp_init_count) 4528 cfg->dp_aux_init(qmp); 4529 } 4530 } 4531 4532 return 0; 4533 } 4534 4535 static void qmp_combo_typec_switch_unregister(void *data) 4536 { 4537 struct qmp_combo *qmp = data; 4538 4539 typec_switch_unregister(qmp->sw); 4540 } 4541 4542 static void qmp_combo_typec_mux_unregister(void *data) 4543 { 4544 struct qmp_combo *qmp = data; 4545 4546 typec_mux_unregister(qmp->mux); 4547 } 4548 4549 static int qmp_combo_typec_register(struct qmp_combo *qmp) 4550 { 4551 struct typec_switch_desc sw_desc = {}; 4552 struct typec_mux_desc mux_desc = { }; 4553 struct device *dev = qmp->dev; 4554 int ret; 4555 4556 sw_desc.drvdata = qmp; 4557 sw_desc.fwnode = dev->fwnode; 4558 sw_desc.set = qmp_combo_typec_switch_set; 4559 qmp->sw = typec_switch_register(dev, &sw_desc); 4560 if (IS_ERR(qmp->sw)) { 4561 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 4562 return PTR_ERR(qmp->sw); 4563 } 4564 4565 ret = devm_add_action_or_reset(dev, qmp_combo_typec_switch_unregister, qmp); 4566 if (ret) 4567 return ret; 4568 4569 mux_desc.drvdata = qmp; 4570 mux_desc.fwnode = dev->fwnode; 4571 mux_desc.set = qmp_combo_typec_mux_set; 4572 qmp->mux = typec_mux_register(dev, &mux_desc); 4573 if (IS_ERR(qmp->mux)) { 4574 dev_err(dev, "Unable to register typec mux: %pe\n", qmp->mux); 4575 return PTR_ERR(qmp->mux); 4576 } 4577 4578 return devm_add_action_or_reset(dev, qmp_combo_typec_mux_unregister, qmp); 4579 } 4580 #else 4581 static int qmp_combo_typec_register(struct qmp_combo *qmp) 4582 { 4583 return 0; 4584 } 4585 #endif 4586 4587 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np) 4588 { 4589 struct device *dev = qmp->dev; 4590 4591 /* 4592 * Get memory resources from the DP child node: 4593 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 4594 * tx2 -> 3; rx2 -> 4 4595 * 4596 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 4597 * implementation. 4598 */ 4599 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 4600 if (IS_ERR(qmp->dp_tx)) 4601 return PTR_ERR(qmp->dp_tx); 4602 4603 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 4604 if (IS_ERR(qmp->dp_dp_phy)) 4605 return PTR_ERR(qmp->dp_dp_phy); 4606 4607 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 4608 if (IS_ERR(qmp->dp_tx2)) 4609 return PTR_ERR(qmp->dp_tx2); 4610 4611 return 0; 4612 } 4613 4614 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np) 4615 { 4616 const struct qmp_phy_cfg *cfg = qmp->cfg; 4617 struct device *dev = qmp->dev; 4618 4619 /* 4620 * Get memory resources from the USB child node: 4621 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 4622 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 4623 */ 4624 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 4625 if (IS_ERR(qmp->tx)) 4626 return PTR_ERR(qmp->tx); 4627 4628 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 4629 if (IS_ERR(qmp->rx)) 4630 return PTR_ERR(qmp->rx); 4631 4632 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 4633 if (IS_ERR(qmp->pcs)) 4634 return PTR_ERR(qmp->pcs); 4635 4636 if (cfg->pcs_usb_offset) 4637 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 4638 4639 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 4640 if (IS_ERR(qmp->tx2)) 4641 return PTR_ERR(qmp->tx2); 4642 4643 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 4644 if (IS_ERR(qmp->rx2)) 4645 return PTR_ERR(qmp->rx2); 4646 4647 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 4648 if (IS_ERR(qmp->pcs_misc)) { 4649 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 4650 qmp->pcs_misc = NULL; 4651 } 4652 4653 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 4654 if (IS_ERR(qmp->pipe_clk)) { 4655 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 4656 "failed to get pipe clock\n"); 4657 } 4658 4659 return 0; 4660 } 4661 4662 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 4663 struct device_node *dp_np) 4664 { 4665 struct platform_device *pdev = to_platform_device(qmp->dev); 4666 int ret; 4667 4668 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 4669 if (IS_ERR(qmp->serdes)) 4670 return PTR_ERR(qmp->serdes); 4671 4672 qmp->com = devm_platform_ioremap_resource(pdev, 1); 4673 if (IS_ERR(qmp->com)) 4674 return PTR_ERR(qmp->com); 4675 4676 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 4677 if (IS_ERR(qmp->dp_serdes)) 4678 return PTR_ERR(qmp->dp_serdes); 4679 4680 ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np); 4681 if (ret) 4682 return ret; 4683 4684 ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np); 4685 if (ret) 4686 return ret; 4687 4688 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 4689 if (ret < 0) 4690 return ret; 4691 4692 qmp->num_clks = ret; 4693 4694 return 0; 4695 } 4696 4697 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 4698 { 4699 struct platform_device *pdev = to_platform_device(qmp->dev); 4700 const struct qmp_phy_cfg *cfg = qmp->cfg; 4701 const struct qmp_combo_offsets *offs = cfg->offsets; 4702 struct device *dev = qmp->dev; 4703 void __iomem *base; 4704 int ret; 4705 4706 if (!offs) 4707 return -EINVAL; 4708 4709 base = devm_platform_ioremap_resource(pdev, 0); 4710 if (IS_ERR(base)) 4711 return PTR_ERR(base); 4712 4713 qmp->com = base + offs->com; 4714 qmp->tx = base + offs->txa; 4715 qmp->rx = base + offs->rxa; 4716 qmp->tx2 = base + offs->txb; 4717 qmp->rx2 = base + offs->rxb; 4718 4719 qmp->serdes = base + offs->usb3_serdes; 4720 qmp->pcs_misc = base + offs->usb3_pcs_misc; 4721 qmp->pcs = base + offs->usb3_pcs; 4722 if (offs->usb3_pcs_aon) 4723 qmp->pcs_aon = base + offs->usb3_pcs_aon; 4724 qmp->pcs_usb = base + offs->usb3_pcs_usb; 4725 4726 qmp->dp_serdes = base + offs->dp_serdes; 4727 if (offs->dp_txa) { 4728 qmp->dp_tx = base + offs->dp_txa; 4729 qmp->dp_tx2 = base + offs->dp_txb; 4730 } else { 4731 qmp->dp_tx = base + offs->txa; 4732 qmp->dp_tx2 = base + offs->txb; 4733 } 4734 qmp->dp_dp_phy = base + offs->dp_dp_phy; 4735 4736 ret = qmp_combo_clk_init(qmp); 4737 if (ret) 4738 return ret; 4739 4740 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 4741 if (IS_ERR(qmp->pipe_clk)) { 4742 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 4743 "failed to get usb3_pipe clock\n"); 4744 } 4745 4746 return 0; 4747 } 4748 4749 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 4750 { 4751 struct qmp_combo *qmp = dev_get_drvdata(dev); 4752 4753 if (args->args_count == 0) 4754 return ERR_PTR(-EINVAL); 4755 4756 switch (args->args[0]) { 4757 case QMP_USB43DP_USB3_PHY: 4758 return qmp->usb_phy; 4759 case QMP_USB43DP_DP_PHY: 4760 return qmp->dp_phy; 4761 } 4762 4763 return ERR_PTR(-EINVAL); 4764 } 4765 4766 static void qmp_combo_find_lanes_orientation(const struct qmp_combo_lane_mapping *mapping, 4767 unsigned int mapping_count, 4768 u32 *lanes, unsigned int lanes_count, 4769 enum typec_orientation *orientation) 4770 { 4771 int i; 4772 4773 for (i = 0; i < mapping_count; i++) { 4774 if (mapping[i].lanes_count != lanes_count) 4775 continue; 4776 if (!memcmp(mapping[i].lanes, lanes, sizeof(u32) * lanes_count)) { 4777 *orientation = mapping[i].orientation; 4778 return; 4779 } 4780 } 4781 } 4782 4783 static int qmp_combo_get_dt_lanes_mapping(struct device *dev, unsigned int endpoint, 4784 u32 *data_lanes, unsigned int max, 4785 unsigned int *count) 4786 { 4787 struct device_node *ep __free(device_node) = NULL; 4788 int ret; 4789 4790 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, endpoint); 4791 if (!ep) 4792 return -EINVAL; 4793 4794 ret = of_property_count_u32_elems(ep, "data-lanes"); 4795 if (ret < 0) 4796 return ret; 4797 4798 *count = ret; 4799 if (*count > max) 4800 return -EINVAL; 4801 4802 return of_property_read_u32_array(ep, "data-lanes", data_lanes, 4803 min_t(unsigned int, *count, max)); 4804 } 4805 4806 static int qmp_combo_get_dt_dp_orientation(struct device *dev, 4807 enum typec_orientation *orientation) 4808 { 4809 unsigned int count; 4810 u32 data_lanes[4]; 4811 int ret; 4812 4813 /* DP is described on the first endpoint of the first port */ 4814 ret = qmp_combo_get_dt_lanes_mapping(dev, 0, data_lanes, 4, &count); 4815 if (ret < 0) 4816 return ret == -EINVAL ? 0 : ret; 4817 4818 /* Search for a match and only update orientation if found */ 4819 qmp_combo_find_lanes_orientation(dp_data_lanes, ARRAY_SIZE(dp_data_lanes), 4820 data_lanes, count, orientation); 4821 4822 return 0; 4823 } 4824 4825 static int qmp_combo_get_dt_usb3_orientation(struct device *dev, 4826 enum typec_orientation *orientation) 4827 { 4828 unsigned int count; 4829 u32 data_lanes[2]; 4830 int ret; 4831 4832 /* USB3 is described on the second endpoint of the first port */ 4833 ret = qmp_combo_get_dt_lanes_mapping(dev, 1, data_lanes, 2, &count); 4834 if (ret < 0) 4835 return ret == -EINVAL ? 0 : ret; 4836 4837 /* Search for a match and only update orientation if found */ 4838 qmp_combo_find_lanes_orientation(usb3_data_lanes, ARRAY_SIZE(usb3_data_lanes), 4839 data_lanes, count, orientation); 4840 4841 return 0; 4842 } 4843 4844 static int qmp_combo_probe(struct platform_device *pdev) 4845 { 4846 struct qmp_combo *qmp; 4847 struct device *dev = &pdev->dev; 4848 struct device_node *dp_np, *usb_np; 4849 struct phy_provider *phy_provider; 4850 int ret; 4851 4852 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 4853 if (!qmp) 4854 return -ENOMEM; 4855 4856 qmp->dev = dev; 4857 dev_set_drvdata(dev, qmp); 4858 4859 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 4860 4861 qmp->cfg = of_device_get_match_data(dev); 4862 if (!qmp->cfg) 4863 return -EINVAL; 4864 4865 mutex_init(&qmp->phy_mutex); 4866 4867 ret = qmp_combo_reset_init(qmp); 4868 if (ret) 4869 return ret; 4870 4871 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 4872 qmp->cfg->vreg_list, &qmp->vregs); 4873 if (ret) 4874 return ret; 4875 4876 /* Check for legacy binding with child nodes. */ 4877 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 4878 if (usb_np) { 4879 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 4880 if (!dp_np) { 4881 of_node_put(usb_np); 4882 return -EINVAL; 4883 } 4884 4885 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 4886 } else { 4887 usb_np = of_node_get(dev->of_node); 4888 dp_np = of_node_get(dev->of_node); 4889 4890 ret = qmp_combo_parse_dt(qmp); 4891 } 4892 if (ret) 4893 goto err_node_put; 4894 4895 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 4896 4897 if (of_property_present(dev->of_node, "mode-switch") || 4898 of_property_present(dev->of_node, "orientation-switch")) { 4899 ret = qmp_combo_typec_register(qmp); 4900 if (ret) 4901 goto err_node_put; 4902 } else { 4903 enum typec_orientation dp_orientation = TYPEC_ORIENTATION_NONE; 4904 enum typec_orientation usb3_orientation = TYPEC_ORIENTATION_NONE; 4905 4906 ret = qmp_combo_get_dt_dp_orientation(dev, &dp_orientation); 4907 if (ret) 4908 goto err_node_put; 4909 4910 ret = qmp_combo_get_dt_usb3_orientation(dev, &usb3_orientation); 4911 if (ret) 4912 goto err_node_put; 4913 4914 if (dp_orientation == TYPEC_ORIENTATION_NONE && 4915 usb3_orientation != TYPEC_ORIENTATION_NONE) { 4916 qmp->qmpphy_mode = QMPPHY_MODE_USB3_ONLY; 4917 qmp->orientation = usb3_orientation; 4918 } else if (usb3_orientation == TYPEC_ORIENTATION_NONE && 4919 dp_orientation != TYPEC_ORIENTATION_NONE) { 4920 qmp->qmpphy_mode = QMPPHY_MODE_DP_ONLY; 4921 qmp->orientation = dp_orientation; 4922 } else if (dp_orientation != TYPEC_ORIENTATION_NONE && 4923 dp_orientation == usb3_orientation) { 4924 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 4925 qmp->orientation = dp_orientation; 4926 } else { 4927 dev_warn(dev, "unable to determine orientation & mode from data-lanes"); 4928 } 4929 } 4930 4931 ret = drm_aux_bridge_register(dev); 4932 if (ret) 4933 goto err_node_put; 4934 4935 pm_runtime_set_active(dev); 4936 ret = devm_pm_runtime_enable(dev); 4937 if (ret) 4938 goto err_node_put; 4939 /* 4940 * Prevent runtime pm from being ON by default. Users can enable 4941 * it using power/control in sysfs. 4942 */ 4943 pm_runtime_forbid(dev); 4944 4945 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 4946 if (ret) 4947 goto err_node_put; 4948 4949 4950 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 4951 if (IS_ERR(qmp->usb_phy)) { 4952 ret = PTR_ERR(qmp->usb_phy); 4953 dev_err(dev, "failed to create USB PHY: %d\n", ret); 4954 goto err_node_put; 4955 } 4956 4957 phy_set_drvdata(qmp->usb_phy, qmp); 4958 4959 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 4960 if (IS_ERR(qmp->dp_phy)) { 4961 ret = PTR_ERR(qmp->dp_phy); 4962 dev_err(dev, "failed to create DP PHY: %d\n", ret); 4963 goto err_node_put; 4964 } 4965 4966 phy_set_drvdata(qmp->dp_phy, qmp); 4967 4968 if (usb_np == dev->of_node) 4969 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 4970 else 4971 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 4972 4973 of_node_put(usb_np); 4974 of_node_put(dp_np); 4975 4976 return PTR_ERR_OR_ZERO(phy_provider); 4977 4978 err_node_put: 4979 of_node_put(usb_np); 4980 of_node_put(dp_np); 4981 return ret; 4982 } 4983 4984 static const struct of_device_id qmp_combo_of_match_table[] = { 4985 { 4986 .compatible = "qcom,glymur-qmp-usb3-dp-phy", 4987 .data = &glymur_usb3dpphy_cfg, 4988 }, 4989 { 4990 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 4991 .data = &sar2130p_usb3dpphy_cfg, 4992 }, 4993 { 4994 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 4995 .data = &sc7180_usb3dpphy_cfg, 4996 }, 4997 { 4998 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 4999 .data = &sm8250_usb3dpphy_cfg, 5000 }, 5001 { 5002 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 5003 .data = &sc8180x_usb3dpphy_cfg, 5004 }, 5005 { 5006 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 5007 .data = &sc8280xp_usb43dpphy_cfg, 5008 }, 5009 { 5010 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 5011 .data = &sdm845_usb3dpphy_cfg, 5012 }, 5013 { 5014 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 5015 .data = &sm6350_usb3dpphy_cfg, 5016 }, 5017 { 5018 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 5019 .data = &sc8180x_usb3dpphy_cfg, 5020 }, 5021 { 5022 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 5023 .data = &sm8250_usb3dpphy_cfg, 5024 }, 5025 { 5026 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 5027 .data = &sm8350_usb3dpphy_cfg, 5028 }, 5029 { 5030 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 5031 .data = &sm8350_usb3dpphy_cfg, 5032 }, 5033 { 5034 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 5035 .data = &sm8550_usb3dpphy_cfg, 5036 }, 5037 { 5038 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 5039 .data = &sm8650_usb3dpphy_cfg, 5040 }, 5041 { 5042 .compatible = "qcom,sm8750-qmp-usb3-dp-phy", 5043 .data = &sm8750_usb3dpphy_cfg, 5044 }, 5045 { 5046 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 5047 .data = &x1e80100_usb3dpphy_cfg, 5048 }, 5049 { } 5050 }; 5051 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 5052 5053 static struct platform_driver qmp_combo_driver = { 5054 .probe = qmp_combo_probe, 5055 .driver = { 5056 .name = "qcom-qmp-combo-phy", 5057 .pm = &qmp_combo_pm_ops, 5058 .of_match_table = qmp_combo_of_match_table, 5059 }, 5060 }; 5061 5062 module_platform_driver(qmp_combo_driver); 5063 5064 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 5065 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 5066 MODULE_LICENSE("GPL v2"); 5067