1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_graph.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/usb/typec.h> 23 #include <linux/usb/typec_dp.h> 24 #include <linux/usb/typec_mux.h> 25 26 #include <drm/bridge/aux-bridge.h> 27 28 #include <dt-bindings/phy/phy-qcom-qmp.h> 29 30 #include "phy-qcom-qmp-common.h" 31 32 #include "phy-qcom-qmp.h" 33 #include "phy-qcom-qmp-pcs-aon-v6.h" 34 #include "phy-qcom-qmp-pcs-aon-v8.h" 35 #include "phy-qcom-qmp-pcs-aon-v10.h" 36 #include "phy-qcom-qmp-pcs-misc-v3.h" 37 #include "phy-qcom-qmp-pcs-misc-v4.h" 38 #include "phy-qcom-qmp-pcs-misc-v5.h" 39 #include "phy-qcom-qmp-pcs-misc-v8.h" 40 #include "phy-qcom-qmp-pcs-usb-v4.h" 41 #include "phy-qcom-qmp-pcs-usb-v5.h" 42 #include "phy-qcom-qmp-pcs-usb-v6.h" 43 #include "phy-qcom-qmp-pcs-usb-v8.h" 44 #include "phy-qcom-qmp-pcs-usb-v10.h" 45 46 #include "phy-qcom-qmp-dp-com-v3.h" 47 48 #include "phy-qcom-qmp-dp-phy.h" 49 #include "phy-qcom-qmp-dp-phy-v3.h" 50 #include "phy-qcom-qmp-dp-phy-v4.h" 51 #include "phy-qcom-qmp-dp-phy-v5.h" 52 #include "phy-qcom-qmp-dp-phy-v6.h" 53 #include "phy-qcom-qmp-dp-phy-v8.h" 54 #include "phy-qcom-qmp-dp-phy-v10.h" 55 56 #include "phy-qcom-qmp-usb43-pcs-v8.h" 57 58 #include "phy-qcom-qmp-com-aon-v10.h" 59 60 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 61 /* DP PHY soft reset */ 62 #define SW_DPPHY_RESET BIT(0) 63 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 64 #define SW_DPPHY_RESET_MUX BIT(1) 65 /* USB3 PHY soft reset */ 66 #define SW_USB3PHY_RESET BIT(2) 67 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 68 #define SW_USB3PHY_RESET_MUX BIT(3) 69 70 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 71 #define USB3_MODE BIT(0) /* enables USB3 mode */ 72 #define DP_MODE BIT(1) /* enables DP mode */ 73 74 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 75 #define SW_PORTSELECT_VAL BIT(0) 76 #define SW_PORTSELECT_MUX BIT(1) 77 #define INVERT_CC_POLARITY BIT(2) 78 79 #define PHY_INIT_COMPLETE_TIMEOUT 10000 80 81 enum qmpphy_mode { 82 QMPPHY_MODE_USB3DP = 0, 83 QMPPHY_MODE_DP_ONLY, 84 QMPPHY_MODE_USB3_ONLY, 85 }; 86 87 /* set of registers with offsets different per-PHY */ 88 enum qphy_reg_layout { 89 /* PCS registers */ 90 QPHY_SW_RESET, 91 QPHY_START_CTRL, 92 QPHY_PCS_STATUS, 93 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 94 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 95 QPHY_PCS_POWER_DOWN_CONTROL, 96 QPHY_PCS_CLAMP_ENABLE, 97 98 QPHY_COM_RESETSM_CNTRL, 99 QPHY_COM_C_READY_STATUS, 100 QPHY_COM_CMN_STATUS, 101 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 102 103 QPHY_DP_PHY_STATUS, 104 QPHY_DP_PHY_VCO_DIV, 105 106 QPHY_TX_TX_POL_INV, 107 QPHY_TX_TX_DRV_LVL, 108 QPHY_TX_TX_EMP_POST1_LVL, 109 QPHY_TX_HIGHZ_DRVR_EN, 110 QPHY_TX_TRANSCEIVER_BIAS_EN, 111 112 QPHY_AON_TOGGLE_ENABLE, 113 QPHY_DP_AON_TOGGLE_ENABLE, 114 /* Keep last to ensure regs_layout arrays are properly initialized */ 115 QPHY_LAYOUT_SIZE 116 }; 117 118 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 119 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 120 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 121 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 122 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 123 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 124 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 125 126 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE, 127 128 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 129 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 130 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 131 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 132 133 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 134 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 135 136 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 137 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 138 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 139 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 140 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 141 }; 142 143 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 144 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 145 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 146 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 147 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 148 149 /* In PCS_USB */ 150 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 151 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 152 153 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE, 154 155 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 156 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 157 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 158 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 159 160 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 161 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 162 163 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 164 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 165 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 166 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 167 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 168 }; 169 170 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 171 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 172 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 173 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 174 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 175 176 /* In PCS_USB */ 177 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 178 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 179 180 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V5_PCS_MISC_CLAMP_ENABLE, 181 182 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 183 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 184 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 185 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 186 187 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 188 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 189 190 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 191 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 192 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 193 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 194 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 195 }; 196 197 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 198 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 199 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 200 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 201 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 202 203 /* In PCS_USB */ 204 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 205 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 206 207 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V6_PCS_AON_CLAMP_ENABLE, 208 209 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 210 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 211 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 212 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 213 214 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 215 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 216 217 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 218 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 219 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 220 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 221 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 222 }; 223 224 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 225 [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET, 226 [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL, 227 [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1, 228 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL, 229 230 /* In PCS_USB */ 231 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 232 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 233 234 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V6_PCS_AON_CLAMP_ENABLE, 235 236 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 237 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 238 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 239 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 240 241 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 242 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 243 244 [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV, 245 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL, 246 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL, 247 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN, 248 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN, 249 }; 250 251 static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 252 [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET, 253 [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL, 254 [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1, 255 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL, 256 257 /* In PCS_USB */ 258 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 259 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 260 261 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 262 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 263 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 264 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 265 266 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 267 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 268 269 [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV, 270 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL, 271 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL, 272 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN, 273 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN, 274 }; 275 276 static const unsigned int qmp_v10_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 277 [QPHY_SW_RESET] = QPHY_V10_PCS_SW_RESET, 278 [QPHY_START_CTRL] = QPHY_V10_PCS_START_CONTROL, 279 [QPHY_PCS_STATUS] = QPHY_V10_PCS_PCS_STATUS1, 280 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V10_PCS_POWER_DOWN_CONTROL, 281 282 /* In PCS_USB */ 283 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V10_PCS_USB3_AUTONOMOUS_MODE_CTRL, 284 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V10_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 285 286 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V10_PCS_AON_CLAMP_ENABLE, 287 288 [QPHY_AON_TOGGLE_ENABLE] = QPHY_V10_COM_AON_USB3_AON_TOGGLE_ENABLE, 289 [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V10_COM_AON_DP_AON_TOGGLE_ENABLE, 290 291 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V10_COM_RESETSM_CNTRL, 292 [QPHY_COM_C_READY_STATUS] = QSERDES_V10_COM_C_READY_STATUS, 293 [QPHY_COM_CMN_STATUS] = QSERDES_V10_COM_CMN_STATUS, 294 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V10_COM_BIAS_EN_CLKBUFLR_EN, 295 296 [QPHY_DP_PHY_STATUS] = QSERDES_V10_DP_PHY_STATUS, 297 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V10_DP_PHY_VCO_DIV, 298 299 [QPHY_TX_TX_POL_INV] = QSERDES_V10_TX_TX_POL_INV, 300 [QPHY_TX_TX_DRV_LVL] = QSERDES_V10_TX_TX_DRV_LVL, 301 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V10_TX_TX_EMP_POST1_LVL, 302 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V10_TX_HIGHZ_DRVR_EN, 303 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V10_TX_TRANSCEIVER_BIAS_EN, 304 }; 305 306 static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = { 307 [QPHY_SW_RESET] = QPHY_V8_USB43_PCS_SW_RESET, 308 [QPHY_START_CTRL] = QPHY_V8_USB43_PCS_START_CONTROL, 309 [QPHY_PCS_STATUS] = QPHY_V8_USB43_PCS_PCS_STATUS1, 310 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_USB43_PCS_POWER_DOWN_CONTROL, 311 312 /* In PCS_USB */ 313 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL, 314 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR, 315 316 [QPHY_PCS_CLAMP_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_CLAMP_ENABLE, 317 [QPHY_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_USB3_AON_TOGGLE_ENABLE, 318 [QPHY_DP_AON_TOGGLE_ENABLE] = QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE, 319 320 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL, 321 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS, 322 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS, 323 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, 324 325 [QPHY_DP_PHY_STATUS] = QSERDES_V8_DP_PHY_STATUS, 326 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V8_DP_PHY_VCO_DIV, 327 328 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_LALB_TX0_DRV_LVL, 329 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 330 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_LALB_HIGHZ_DRVR_EN, 331 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 332 }; 333 334 static const struct qmp_phy_init_tbl glymur_usb43dp_serdes_tbl[] = { 335 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE1, 0xe1), 336 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE1, 0x01), 337 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE1, 0x06), 338 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x16), 339 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x36), 340 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE1, 0x02), 341 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE1, 0x1a), 342 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE1, 0x41), 343 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE1, 0x41), 344 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE1, 0x00), 345 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE1, 0xab), 346 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE1, 0xaa), 347 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE1, 0x01), 348 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x13), 349 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 350 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE1, 0x4d), 351 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE1, 0x03), 352 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x95), 353 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 354 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x4b), 355 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 356 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0xe1), 357 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x01), 358 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 359 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 360 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 361 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x05), 362 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x0a), 363 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x1a), 364 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x41), 365 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MSB_MODE0, 0x00), 366 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0xab), 367 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xaa), 368 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01), 369 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 370 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 371 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0x4d), 372 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x03), 373 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a), 374 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00), 375 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x62), 376 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02), 377 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x0a), 378 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x0f), 379 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO_MODE1, 0x0f), 380 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x1a), 381 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x04), 382 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_CFG, 0x04), 383 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 384 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x14), 385 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0xa0), 386 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x76), 387 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x0a), 388 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x01), 389 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_SPARE_FOR_ECO, 0x40), 390 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), 391 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_2, 0x01), 392 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60), 393 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x05), 394 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x33), 395 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xaf), 396 }; 397 398 static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_misc_tbl[] = { 399 QMP_PHY_INIT_CFG(QPHY_V8_PCS_MISC_PCS_MISC_CONFIG1, 0x01), 400 }; 401 402 static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_tbl[] = { 403 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1, 0xc4), 404 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2, 0x89), 405 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3, 0x20), 406 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6, 0x13), 407 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1, 0x21), 408 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_SIGDET_LVL, 0x55), 409 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 410 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 411 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME, 0xa4), 412 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_CONFIG, 0x0a), 413 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_DLY_TIME, 0x04), 414 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 415 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2, 0x30), 416 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG, 0x0c), 417 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG1, 0x4b), 418 QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG5, 0x10), 419 }; 420 421 static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_usb_tbl[] = { 422 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 423 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 424 }; 425 426 static const struct qmp_phy_init_tbl glymur_usb43dp_lalb_tbl[] = { 427 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x81), 428 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0d), 429 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL1, 0x00), 430 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL2, 0x00), 431 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL3, 0x80), 432 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCIE5_TOP_LDO_CODE_CTRL4, 0x8D), 433 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x13), 434 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0c), 435 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x00), 436 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x11), 437 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_4, 0x11), 438 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), 439 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), 440 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), 441 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_VREF_SEL, 0x00), 442 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_VREF_SEL, 0x00), 443 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x00), 444 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x00), 445 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B0, 0xa4), 446 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B1, 0xa2), 447 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B2, 0x6e), 448 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B3, 0x51), 449 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B4, 0x0a), 450 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B5, 0x26), 451 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B6, 0x12), 452 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE_0_1_B7, 0x2a), 453 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B0, 0x4c), 454 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B1, 0xc4), 455 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B2, 0x38), 456 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B3, 0x64), 457 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B4, 0x0c), 458 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B5, 0x4b), 459 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B6, 0x12), 460 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_MODE_RATE2_B7, 0x0a), 461 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x0c), 462 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE1, 0x26), 463 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE1, 0x26), 464 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT1_RATE2, 0x26), 465 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CTUNE_MEAS_CNT2_RATE2, 0x26), 466 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_0_1, 0x11), 467 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_INIT_RATE_2_3, 0x11), 468 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE1, 0x03), 469 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_CODE_OVRD_RATE2, 0x03), 470 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE1, 0x15), 471 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE1, 0x00), 472 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF1_RATE2, 0x22), 473 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KVCO_IDEAL_FREQ_DIFF2_RATE2, 0x00), 474 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CODE_OVRD_RATE_2_3, 0x22), 475 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE1, 0xff), 476 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE1, 0x00), 477 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND1_RATE2, 0xff), 478 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_UPPER_FREQ_DIFF_BND2_RATE2, 0x00), 479 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE1, 0x07), 480 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_KP_CAL_LOWER_FREQ_DIFF_BND_RATE2, 0x09), 481 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_SUMMER_CAL_SPD_MODE_RATE_0123, 0x2f), 482 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE1, 0x00), 483 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CODE_OVERRIDE_RATE2, 0x00), 484 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL2, 0x85), 485 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_CAL_CTRL3, 0x45), 486 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE1, 0x00), 487 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_IVCM_POSTCAL_OFFSET_RATE2, 0x00), 488 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_ENABLES, 0x0c), 489 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CNTRL, 0xa3), 490 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_LVL, 0x04), 491 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_DEGLITCH_CNTRL, 0x0e), 492 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL1, 0x14), 493 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_CTRL2_AND_CDR_LOCK_EDGE, 0x00), 494 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_SIGDET_CAL_TRIM, 0x66), 495 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE1, 0xff), 496 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_FREQ_LOCK_DET_DLY_RATE2, 0x32), 497 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE1, 0x07), 498 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_FLL_RATE2, 0x0a), 499 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE1, 0x02), 500 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_CP_CUR_PLL_RATE2, 0x04), 501 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_01, 0x76), 502 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_CCODE_RATE_23, 0x67), 503 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_0_1, 0x20), 504 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FAST_RATE_2_3, 0x02), 505 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_0_1, 0x33), 506 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_FLL_RATE_2_3, 0x43), 507 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_0_1, 0x00), 508 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_RCODE_PLL_RATE_2_3, 0x51), 509 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_FLL_DIV_RATIO_RATE_0123, 0xe5), 510 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_RATE_0123, 0xf5), 511 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_TYPE_CONFIG, 0x1f), 512 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_EN_LOWFREQ, 0x07), 513 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_LOOP_FUNC_CTRL, 0xd0), 514 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_EN, 0x1f), 515 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE0_1, 0x88), 516 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_GM_CAL_RES_RATE2_3, 0x88), 517 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_AUX_CLK_CTRL, 0x20), 518 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_EOM_CTRL1, 0x10), 519 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 520 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL3, 0x0a), 521 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RX_EQU_ADAPTOR_CNTRL4, 0xaa), 522 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CTLE_POST_CAL_OFFSET_RATE_0_1_2, 0x77), 523 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_CNTRL1, 0x00), 524 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE0_1, 0xdd), 525 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VGA_CAL_MAN_VAL_RATE2_3, 0xd8), 526 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP1_DAC_ENABLE, 0x1c), 527 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP2_DAC_ENABLE, 0x1c), 528 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP345_DAC_ENABLE, 0x18), 529 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DFE_TAP67_DAC_ENABLE, 0x10), 530 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_CTRL, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_MAN_INDEX, 0x10), 532 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_IQTUNE_DIV2_CTRL_RATE0123, 0x1C), 533 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CDR_VCO_CAP_CODE_OVRD_MUXES, 0x00), 534 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_DIG_BKUP_CTRL16, 0x37), 535 }; 536 537 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 562 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 563 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 564 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 565 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 566 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 567 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 568 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 569 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 570 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 571 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 572 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 573 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 574 }; 575 576 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 577 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 578 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 579 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 580 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 581 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 582 }; 583 584 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 585 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 586 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 587 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 588 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 589 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 590 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 591 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 592 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 593 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 601 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 602 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 603 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 606 }; 607 608 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 609 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 611 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 612 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 614 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 615 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 616 }; 617 618 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 619 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 620 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 621 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 622 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 623 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 624 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 625 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 626 }; 627 628 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 629 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 630 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 631 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 632 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 633 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 634 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 635 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 636 }; 637 638 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 639 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 640 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 641 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 642 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 643 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 644 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 645 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 646 }; 647 648 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 649 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 650 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 651 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 652 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 653 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 654 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 655 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 656 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 658 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 659 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 660 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 661 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 662 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 663 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 664 }; 665 666 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 667 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 668 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 669 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 670 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 671 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 672 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 673 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 674 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 675 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 676 }; 677 678 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 679 /* FLL settings */ 680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 681 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 682 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 683 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 684 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 685 686 /* Lock Det settings */ 687 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 688 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 689 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 690 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 691 692 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 693 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 694 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 695 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 696 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 697 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 698 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 699 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 700 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 701 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 702 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 703 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 704 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 705 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 706 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 707 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 708 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 709 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 710 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 711 712 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 713 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 714 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 715 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 716 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 717 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 718 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 719 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 720 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 721 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 722 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 723 }; 724 725 static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = { 726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55), 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05), 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12), 752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34), 753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04), 754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01), 755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5), 757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04), 770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 774 }; 775 776 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 777 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 778 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 779 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 780 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 781 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 782 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 783 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 784 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 785 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 786 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 787 }; 788 789 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 790 /* FLL settings */ 791 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 792 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 793 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 794 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 795 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 796 797 /* Lock Det settings */ 798 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 799 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 800 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 801 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 802 803 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 804 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 805 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 806 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 807 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 808 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 809 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 810 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 811 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 812 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 813 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 814 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 815 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 816 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 817 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 818 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 819 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 820 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 821 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 822 823 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 824 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 825 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 826 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 827 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 828 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 829 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 830 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 831 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 832 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 833 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 834 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 835 836 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 837 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 838 }; 839 840 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 881 }; 882 883 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 884 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 885 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 886 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 887 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 888 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 889 }; 890 891 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 893 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 894 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 895 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 896 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 897 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 898 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 899 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 900 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 901 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 902 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 903 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 928 }; 929 930 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 931 /* Lock Det settings */ 932 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 933 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 934 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 935 936 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 937 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 938 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 939 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 940 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 941 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 942 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 943 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 944 }; 945 946 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 947 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 948 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 949 }; 950 951 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 952 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 953 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 954 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 955 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 956 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 957 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 958 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 959 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 960 }; 961 962 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 963 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 968 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 969 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 970 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 971 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 972 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 973 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 974 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 975 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 976 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 977 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 978 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 979 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 980 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 981 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 982 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 983 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 984 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 985 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 986 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 987 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 988 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 989 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 990 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 991 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 992 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 1001 }; 1002 1003 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 1004 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1005 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1006 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1007 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1008 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1009 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 1010 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1011 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1012 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1013 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1014 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1015 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1016 }; 1017 1018 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 1019 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1020 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1021 }; 1022 1023 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 1024 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 1026 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1034 }; 1035 1036 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 1061 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 1062 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 1075 }; 1076 1077 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 1078 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1079 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1080 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1081 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1085 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1086 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1087 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1088 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1089 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1090 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1091 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1092 }; 1093 1094 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 1095 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1096 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1097 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1098 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1099 }; 1100 1101 static const struct qmp_phy_init_tbl sm8475_usb3_rx_tbl[] = { 1102 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 1103 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 1104 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1105 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1106 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1107 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1108 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 1109 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 1110 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 1111 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 1112 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x08), 1113 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1114 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 1115 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 1116 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 1117 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1118 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1119 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1120 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1121 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1122 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1123 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 1124 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1125 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), 1126 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xff), 1127 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff), 1128 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf), 1129 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfe), 1130 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 1131 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 1132 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 1133 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 1134 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 1135 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 1136 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1137 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 1138 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 1139 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 1140 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1141 }; 1142 1143 static const struct qmp_phy_init_tbl sm8475_usb3_pcs_usb_tbl[] = { 1144 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1145 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1146 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1147 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1148 }; 1149 1150 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 1151 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 1152 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 1153 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1154 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1155 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1156 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1157 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1158 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1159 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 1160 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1161 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1162 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 1163 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 1164 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1165 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 1166 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 1167 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 1168 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 1169 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 1170 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 1171 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 1172 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1173 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1174 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1175 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1176 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 1184 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 1185 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 1196 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 1197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 1199 }; 1200 1201 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 1202 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 1203 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 1208 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 1209 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 1210 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 1211 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 1212 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 1213 }; 1214 1215 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 1216 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 1217 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 1218 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1219 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1220 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 1225 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 1226 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 1227 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1228 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 1229 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 1230 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1234 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 1235 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1236 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1237 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 1238 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 1242 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 1243 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 1244 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 1245 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1246 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 1247 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 1248 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 1249 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 1250 1251 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 1252 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 1253 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 1254 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 1255 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 1256 1257 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 1258 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 1259 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 1260 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 1261 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 1262 }; 1263 1264 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 1265 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1266 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 1267 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 1268 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 1269 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 1270 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 1271 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1272 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1273 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 1274 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1275 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1276 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 1277 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 1278 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 1279 }; 1280 1281 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 1282 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1283 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1284 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1285 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1286 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 1287 }; 1288 1289 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 1290 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1291 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1292 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1293 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1294 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1295 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1296 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1297 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1298 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1299 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1300 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1301 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1302 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1303 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 1304 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1305 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1306 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1307 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1308 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1309 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1310 }; 1311 1312 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 1313 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 1314 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1315 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1316 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1317 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 1318 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 1319 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 1320 }; 1321 1322 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 1323 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 1324 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1325 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1326 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1327 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 1328 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 1329 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1330 }; 1331 1332 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 1333 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1334 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 1335 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 1336 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 1337 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 1338 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 1339 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1340 }; 1341 1342 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 1343 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 1344 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 1345 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 1346 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 1347 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 1348 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 1349 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 1350 }; 1351 1352 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 1353 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 1354 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1355 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 1356 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 1357 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 1358 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1359 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1360 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 1361 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1362 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1363 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 1364 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 1365 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 1366 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 1367 }; 1368 1369 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 1370 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 1371 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 1372 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 1373 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 1374 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 1375 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 1376 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1377 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1378 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1379 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1380 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1381 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1382 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1383 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 1384 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1385 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1386 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1387 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 1388 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 1389 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 1390 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 1391 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 1392 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 1393 }; 1394 1395 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 1396 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1398 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 1399 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 1400 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 1401 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 1402 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1403 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 1404 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1405 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 1407 }; 1408 1409 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 1410 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1412 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 1413 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 1414 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 1415 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 1416 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1417 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1418 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1419 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1420 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1421 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1422 }; 1423 1424 static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl[] = { 1425 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1426 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), 1441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1445 }; 1446 1447 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1468 }; 1469 1470 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = { 1471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), 1478 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1481 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1482 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1483 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1484 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1485 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1486 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1487 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1488 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1489 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1490 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1491 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1492 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1493 }; 1494 1495 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl[] = { 1496 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x00), 1497 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 1498 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE1, 0x10), 1499 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE1, 0x01), 1500 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), 1501 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), 1502 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1503 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1504 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BG_TIMER, 0x0a), 1505 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_EN_CENTER, 0x00), 1506 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_ADJ_PER1, 0x00), 1507 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x00), 1508 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x00), 1509 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_ENABLE1, 0x0c), 1510 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), 1511 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), 1512 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), 1513 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x3b), 1514 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP_EN, 0x00), 1515 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 1516 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), 1517 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), 1518 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), 1519 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x56), 1520 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), 1521 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), 1522 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_1, 0x40), 1523 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DCC_CAL_3, 0x60), 1524 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PSM_CAL_EN, 0x01), 1525 }; 1526 1527 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1528 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1529 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1530 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1531 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1532 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1533 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1534 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1535 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1536 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1537 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1538 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1539 }; 1540 1541 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = { 1542 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40), 1543 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00), 1544 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff), 1545 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f), 1546 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03), 1547 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f), 1548 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1549 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1550 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1551 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1), 1552 }; 1553 1554 static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx_tbl[] = { 1555 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRANSMITTER_EN_CTRL, 0x3f), 1556 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_VMODE_CTRL1, 0x40), 1557 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT1, 0x07), 1558 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_ANA_INTERFACE_SELECT2, 0x18), 1559 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_PCS_INTERFACE_SELECT1, 0x50), 1560 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_1, 0x0d), 1561 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_CLKBUF_ENABLE, 0x07), 1562 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_RESET_TSYNC_EN_CTRL, 0x0a), 1563 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_LVL_UPDATE_CTRL, 0x0f), 1564 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TRAN_DRVR_EMP_EN, 0x5f), 1565 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_EMP_POST1_LVL, 0x20), 1566 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_EMP_POST1_LVL, 0x20), 1567 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_PRE1_EMPH, 0x20), 1568 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_PRE1_EMPH, 0x20), 1569 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_DRV_LVL, 0x00), 1570 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_DRV_LVL, 0x00), 1571 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_HIGHZ_DRVR_EN, 0x30), 1572 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_2, 0x50), 1573 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_LANE_MODE_3, 0x51), 1574 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX_DCC_ANA_CTRL2, 0x00), 1575 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_CAL_CTRL, 0x20), 1576 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_CAL_CTRL, 0x02), 1577 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX0_RESTRIM_POST_CAL_OFFSET, 0x10), 1578 QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET, 0x10), 1579 }; 1580 1581 static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_rbr[] = { 1582 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1583 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), 1584 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), 1585 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), 1586 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x6f), 1587 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x08), 1588 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1589 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), 1590 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), 1591 }; 1592 1593 static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr[] = { 1594 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1595 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), 1596 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), 1597 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), 1598 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1599 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1600 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1601 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), 1602 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), 1603 }; 1604 1605 static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr2[] = { 1606 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1607 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x8c), 1608 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1609 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0a), 1610 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x1f), 1611 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1c), 1612 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1613 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x2e), 1614 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x21), 1615 }; 1616 1617 static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr3[] = { 1618 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1619 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), 1620 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), 1621 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), 1622 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x2f), 1623 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x2a), 1624 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1625 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), 1626 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), 1627 }; 1628 1629 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1630 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1631 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1632 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1633 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1634 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1635 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1636 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1637 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1638 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1639 }; 1640 1641 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1642 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1643 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1644 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1645 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1646 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1647 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1648 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1649 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1650 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1651 }; 1652 1653 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1654 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1655 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1656 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1657 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1658 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1659 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1660 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1661 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1662 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1663 }; 1664 1665 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1666 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1667 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1668 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1669 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1670 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1671 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1672 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1673 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1674 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1675 }; 1676 1677 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = { 1678 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1679 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1680 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1681 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1682 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1683 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1684 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1685 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1686 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1687 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1688 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1689 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1690 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1691 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1692 }; 1693 1694 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = { 1695 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1696 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1697 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1698 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1699 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1700 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1701 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1702 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1703 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1709 }; 1710 1711 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = { 1712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1724 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1725 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1726 }; 1727 1728 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = { 1729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00), 1739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b), 1740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92), 1742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 1743 }; 1744 1745 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_rbr[] = { 1746 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x05), 1747 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x7a), 1748 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x02), 1749 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x83), 1750 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x37), 1751 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x04), 1752 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x54), 1753 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1754 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x06), 1755 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xfe), 1756 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x00), 1757 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x05), 1758 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), 1759 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), 1760 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa4), 1761 }; 1762 1763 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr[] = { 1764 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x04), 1765 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x21), 1766 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x04), 1767 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x18), 1768 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x07), 1769 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x07), 1770 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), 1771 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1772 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), 1773 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), 1774 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), 1775 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x04), 1776 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x07), 1777 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), 1778 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xa3), 1779 }; 1780 1781 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr2[] = { 1782 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x03), 1783 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xf6), 1784 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x20), 1785 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x0), 1786 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 1787 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 1788 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x10), 1789 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x0e), 1790 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x46), 1791 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0x00), 1792 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x05), 1793 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xae), 1794 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x02), 1795 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x00), 1796 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0xbf), 1797 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 1798 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_RESETSM_CNTRL, 0x20), 1799 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x03), 1800 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x3f), 1801 }; 1802 1803 static const struct qmp_phy_init_tbl qmp_v8_dp_serdes_tbl_hbr3[] = { 1804 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_HSCLK_SEL_1, 0x02), 1805 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x63), 1806 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1807 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE1_MODE0, 0x5b), 1808 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_STEP_SIZE2_MODE0, 0x02), 1809 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CP_CTRL_MODE0, 0x06), 1810 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_RCTRL_MODE0, 0x16), 1811 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_CCTRL_MODE0, 0x36), 1812 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORECLK_DIV_MODE0, 0x0a), 1813 1814 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP1_MODE0, 0x17), 1815 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_LOCK_CMP2_MODE0, 0x15), 1816 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DEC_START_MODE0, 0x4f), 1817 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START1_MODE0, 0x00), 1818 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START2_MODE0, 0xa0), 1819 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_DIV_FRAC_START3_MODE0, 0x01), 1820 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1821 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1822 1823 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE1_MODE0, 0xa0), 1824 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE2_MODE0, 0x01), 1825 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_ADJ_PER1, 0x00), 1826 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER1, 0x6b), 1827 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SSC_PER2, 0x02), 1828 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_ENABLE1, 0x0c), 1829 1830 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYS_CLK_CTRL, 0x02), 1831 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_BUF_ENABLE, 0x06), 1832 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_PLL_IVCO, 0x07), 1833 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SYSCLK_EN_SEL, 0x04), 1834 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_CTRL, 0x00), 1835 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_VCO_TUNE_MAP, 0x00), 1836 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_SELECT, 0x30), 1837 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CORE_CLK_EN, 0x00), 1838 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_CONFIG_1, 0x16), 1839 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_SVS_MODE_CLK_SEL, 0x15), 1840 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CLK_FWD_CONFIG_1, 0x30), 1841 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIAS_EN_CLKBUFLR_EN, 0x10), 1842 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD3, 0x05), 1843 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_CMN_MODE_CONTD1, 0x24), 1844 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_BIN_VCOCAL_HSCLK_SEL_1, 0x02), 1845 QMP_PHY_INIT_CFG(QSERDES_V8_USB43_COM_IP_CTRL_AND_DP_SEL, 0x84), 1846 }; 1847 1848 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1883 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1884 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1885 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1886 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1887 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1888 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1889 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1890 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1891 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1892 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1893 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1894 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1895 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1896 }; 1897 1898 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1899 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1900 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1901 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1902 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1903 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1904 }; 1905 1906 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1907 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1908 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1909 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1910 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1911 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1912 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1913 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1914 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1915 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1916 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1917 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1918 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1919 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1920 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1921 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1922 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1923 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1924 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1925 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1926 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1927 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1928 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1929 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1930 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1931 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1932 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1933 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1934 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1935 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1936 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1937 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1938 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1939 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1940 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1941 }; 1942 1943 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1944 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1945 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1946 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1947 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1948 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1949 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1950 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1951 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1952 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1953 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1954 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1955 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1956 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1957 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1958 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1959 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1960 }; 1961 1962 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1963 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1964 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1965 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1966 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1967 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1968 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1969 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1970 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1971 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1972 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1973 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1995 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1996 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1997 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1998 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1999 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 2000 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 2001 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 2002 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 2003 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 2004 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 2005 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 2006 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 2007 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 2008 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 2009 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 2010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 2011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 2012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 2013 }; 2014 2015 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 2016 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 2017 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 2018 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 2019 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2020 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 2021 }; 2022 2023 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 2024 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 2025 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 2026 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 2027 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 2028 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 2029 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 2030 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 2031 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 2032 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 2033 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 2034 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 2035 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 2036 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 2037 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 2038 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 2039 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 2040 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 2041 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 2042 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 2043 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 2044 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 2045 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 2046 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 2047 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 2048 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 2049 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 2050 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 2051 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 2052 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 2053 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 2054 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 2055 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 2056 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 2057 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 2058 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 2059 }; 2060 2061 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 2062 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 2063 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 2064 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4), 2065 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89), 2066 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20), 2067 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13), 2068 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21), 2069 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55), 2070 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a), 2071 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 2072 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30), 2073 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c), 2074 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b), 2075 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10), 2076 }; 2077 2078 static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = { 2079 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 2080 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2081 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02), 2082 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16), 2083 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36), 2084 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04), 2085 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16), 2086 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41), 2087 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41), 2088 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00), 2089 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55), 2090 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75), 2091 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01), 2092 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01), 2093 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25), 2094 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02), 2095 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 2096 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 2097 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 2098 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 2099 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 2100 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2101 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02), 2102 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16), 2103 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36), 2104 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08), 2105 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a), 2106 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41), 2107 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00), 2108 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55), 2109 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75), 2110 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01), 2111 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25), 2112 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02), 2113 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a), 2114 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01), 2115 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62), 2116 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02), 2117 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c), 2118 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a), 2119 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14), 2120 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04), 2121 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20), 2122 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16), 2123 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 2124 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 2125 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 2126 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c), 2127 }; 2128 2129 static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = { 2130 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00), 2131 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00), 2132 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2133 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 2134 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5), 2135 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11), 2136 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31), 2137 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f), 2138 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12), 2139 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1), 2140 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2), 2141 }; 2142 2143 static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = { 2144 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a), 2145 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06), 2146 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 2147 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 2148 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 2149 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 2150 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99), 2151 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08), 2152 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08), 2153 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00), 2154 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a), 2155 QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 2156 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54), 2157 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f), 2158 QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13), 2159 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 2160 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 2161 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 2162 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2163 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 2164 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 2165 2166 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c), 2167 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04), 2168 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 2169 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f), 2170 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf), 2171 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff), 2172 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf), 2173 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed), 2174 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19), 2175 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09), 2176 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91), 2177 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7), 2178 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa), 2179 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04), 2180 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2181 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c), 2182 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10), 2183 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14), 2184 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08), 2185 }; 2186 2187 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = { 2188 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4), 2189 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89), 2190 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20), 2191 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13), 2192 QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21), 2193 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55), 2194 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 2195 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 2196 QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a), 2197 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88), 2198 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13), 2199 QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c), 2200 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b), 2201 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10), 2202 }; 2203 2204 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = { 2205 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 2206 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), 2207 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40), 2208 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00), 2209 }; 2210 2211 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 2212 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 2213 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 2214 }; 2215 2216 static const struct qmp_phy_init_tbl hawi_usb3_serdes_tbl[] = { 2217 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 2218 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1, 0x01), 2219 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE1, 0x02), 2220 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE1, 0x16), 2221 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE1, 0x36), 2222 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORECLK_DIV_MODE1, 0x04), 2223 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE1, 0x16), 2224 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE1, 0x41), 2225 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE1, 0x41), 2226 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MSB_MODE1, 0x00), 2227 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE1, 0x55), 2228 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE1, 0x75), 2229 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE1, 0x01), 2230 QMP_PHY_INIT_CFG(QSERDES_V10_COM_HSCLK_SEL_1, 0x01), 2231 QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE1_MODE1, 0x25), 2232 QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE2_MODE1, 0x02), 2233 QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 2234 QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 2235 QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 2236 QMP_PHY_INIT_CFG(QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 2237 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 2238 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0, 0x01), 2239 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE0, 0x02), 2240 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE0, 0x16), 2241 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE0, 0x36), 2242 QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 2243 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE0, 0x08), 2244 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE0, 0x1a), 2245 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE0, 0x41), 2246 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MSB_MODE0, 0x00), 2247 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE0, 0x55), 2248 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE0, 0x75), 2249 QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE0, 0x01), 2250 QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE1_MODE0, 0x25), 2251 QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE2_MODE0, 0x02), 2252 QMP_PHY_INIT_CFG(QSERDES_V10_COM_BG_TIMER, 0x0a), 2253 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_EN_CENTER, 0x01), 2254 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER1, 0x62), 2255 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER2, 0x02), 2256 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_BUF_ENABLE, 0x0c), 2257 QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_EN_SEL, 0x1a), 2258 QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP_CFG, 0x14), 2259 QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE_MAP, 0x04), 2260 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORE_CLK_EN, 0x20), 2261 QMP_PHY_INIT_CFG(QSERDES_V10_COM_CMN_CONFIG_1, 0x16), 2262 QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 2263 QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a), 2264 QMP_PHY_INIT_CFG(QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36), 2265 QMP_PHY_INIT_CFG(QSERDES_V10_COM_ADDITIONAL_MISC, 0x0c), 2266 }; 2267 2268 static const struct qmp_phy_init_tbl hawi_usb3_tx_tbl[] = { 2269 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_TX, 0x00), 2270 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_RX, 0x00), 2271 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 2272 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 2273 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_1, 0xe5), 2274 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_2, 0x02), 2275 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_3, 0x11), 2276 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_4, 0x31), 2277 QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_5, 0x5d), 2278 QMP_PHY_INIT_CFG(QSERDES_V10_TX_RCV_DETECT_LVL_2, 0x12), 2279 QMP_PHY_INIT_CFG_LANE(QSERDES_V10_TX_PI_QEC_CTRL, 0x21, 1), 2280 QMP_PHY_INIT_CFG_LANE(QSERDES_V10_TX_PI_QEC_CTRL, 0x05, 2), 2281 }; 2282 2283 static const struct qmp_phy_init_tbl hawi_usb3_rx_tbl[] = { 2284 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FO_GAIN, 0x0a), 2285 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_GAIN, 0x06), 2286 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 2287 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 2288 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 2289 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 2290 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_PI_CONTROLS, 0x99), 2291 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH1, 0x08), 2292 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH2, 0x08), 2293 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_GAIN1, 0x00), 2294 QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_GAIN2, 0x0a), 2295 QMP_PHY_INIT_CFG(QSERDES_V10_RX_AUX_DATA_TCOARSE_TFINE, 0x20), 2296 QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL1, 0x54), 2297 QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL2, 0x0f), 2298 QMP_PHY_INIT_CFG(QSERDES_V10_RX_GM_CAL, 0x13), 2299 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 2300 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 2301 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 2302 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW, 0x07), 2303 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 2304 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 2305 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x0c), 2306 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CNTRL, 0x04), 2307 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 2308 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_LOW, 0x3f), 2309 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH, 0xbf), 2310 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH2, 0xff), 2311 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH3, 0xdf), 2312 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH4, 0xed), 2313 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_LOW, 0x19), 2314 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH, 0x09), 2315 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH2, 0x91), 2316 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH3, 0xb7), 2317 QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH4, 0xaa), 2318 QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_EN_TIMER, 0x04), 2319 QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 2320 QMP_PHY_INIT_CFG(QSERDES_V10_RX_DCC_CTRL1, 0x0c), 2321 QMP_PHY_INIT_CFG(QSERDES_V10_RX_VTH_CODE, 0x10), 2322 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_CTRL1, 0x14), 2323 QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_TRIM, 0x08), 2324 }; 2325 2326 static const struct qmp_phy_init_tbl hawi_usb3_pcs_tbl[] = { 2327 QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG1, 0xc4), 2328 QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG2, 0x89), 2329 QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG3, 0x20), 2330 QMP_PHY_INIT_CFG(QPHY_V10_PCS_LOCK_DETECT_CONFIG6, 0x13), 2331 QMP_PHY_INIT_CFG(QPHY_V10_PCS_REFGEN_REQ_CONFIG1, 0x21), 2332 QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_SIGDET_LVL, 0x55), 2333 QMP_PHY_INIT_CFG(QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 2334 QMP_PHY_INIT_CFG(QPHY_V10_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 2335 QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_CONFIG, 0x0a), 2336 QMP_PHY_INIT_CFG(QPHY_V10_PCS_ALIGN_DETECT_CONFIG1, 0x88), 2337 QMP_PHY_INIT_CFG(QPHY_V10_PCS_ALIGN_DETECT_CONFIG2, 0x13), 2338 QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG, 0x04), 2339 QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG2, 0x01), 2340 QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG1, 0x4b), 2341 QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG5, 0x10), 2342 }; 2343 2344 static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = { 2345 QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 2346 QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 2347 QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 2348 QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 2349 }; 2350 2351 /* list of regulators */ 2352 static struct regulator_bulk_data qmp_phy_vreg_l[] = { 2353 { .supply = "vdda-phy", .init_load_uA = 21800, }, 2354 { .supply = "vdda-pll", .init_load_uA = 36000, }, 2355 }; 2356 2357 static struct regulator_bulk_data qmp_phy_vreg_refgen[] = { 2358 { .supply = "vdda-phy", .init_load_uA = 21800 }, 2359 { .supply = "vdda-pll", .init_load_uA = 36000 }, 2360 { .supply = "refgen", .init_load_uA = 3270 }, 2361 }; 2362 2363 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 2364 { 0x00, 0x0c, 0x15, 0x1a }, 2365 { 0x02, 0x0e, 0x16, 0xff }, 2366 { 0x02, 0x11, 0xff, 0xff }, 2367 { 0x04, 0xff, 0xff, 0xff } 2368 }; 2369 2370 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 2371 { 0x02, 0x12, 0x16, 0x1a }, 2372 { 0x09, 0x19, 0x1f, 0xff }, 2373 { 0x10, 0x1f, 0xff, 0xff }, 2374 { 0x1f, 0xff, 0xff, 0xff } 2375 }; 2376 2377 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 2378 { 0x00, 0x0c, 0x14, 0x19 }, 2379 { 0x00, 0x0b, 0x12, 0xff }, 2380 { 0x00, 0x0b, 0xff, 0xff }, 2381 { 0x04, 0xff, 0xff, 0xff } 2382 }; 2383 2384 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 2385 { 0x08, 0x0f, 0x16, 0x1f }, 2386 { 0x11, 0x1e, 0x1f, 0xff }, 2387 { 0x19, 0x1f, 0xff, 0xff }, 2388 { 0x1f, 0xff, 0xff, 0xff } 2389 }; 2390 2391 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 2392 { 0x00, 0x0c, 0x15, 0x1b }, 2393 { 0x02, 0x0e, 0x16, 0xff }, 2394 { 0x02, 0x11, 0xff, 0xff }, 2395 { 0x04, 0xff, 0xff, 0xff } 2396 }; 2397 2398 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 2399 { 0x00, 0x0d, 0x14, 0x1a }, 2400 { 0x00, 0x0e, 0x15, 0xff }, 2401 { 0x00, 0x0e, 0xff, 0xff }, 2402 { 0x03, 0xff, 0xff, 0xff } 2403 }; 2404 2405 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 2406 { 0x08, 0x0f, 0x16, 0x1f }, 2407 { 0x11, 0x1e, 0x1f, 0xff }, 2408 { 0x16, 0x1f, 0xff, 0xff }, 2409 { 0x1f, 0xff, 0xff, 0xff } 2410 }; 2411 2412 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 2413 { 0x20, 0x2c, 0x35, 0x3b }, 2414 { 0x22, 0x2e, 0x36, 0xff }, 2415 { 0x22, 0x31, 0xff, 0xff }, 2416 { 0x24, 0xff, 0xff, 0xff } 2417 }; 2418 2419 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 2420 { 0x22, 0x32, 0x36, 0x3a }, 2421 { 0x29, 0x39, 0x3f, 0xff }, 2422 { 0x30, 0x3f, 0xff, 0xff }, 2423 { 0x3f, 0xff, 0xff, 0xff } 2424 }; 2425 2426 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 2427 { 0x20, 0x2d, 0x34, 0x3a }, 2428 { 0x20, 0x2e, 0x35, 0xff }, 2429 { 0x20, 0x2e, 0xff, 0xff }, 2430 { 0x24, 0xff, 0xff, 0xff } 2431 }; 2432 2433 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 2434 { 0x28, 0x2f, 0x36, 0x3f }, 2435 { 0x31, 0x3e, 0x3f, 0xff }, 2436 { 0x36, 0x3f, 0xff, 0xff }, 2437 { 0x3f, 0xff, 0xff, 0xff } 2438 }; 2439 2440 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = { 2441 { 0x27, 0x2f, 0x36, 0x3f }, 2442 { 0x31, 0x3e, 0x3f, 0xff }, 2443 { 0x36, 0x3f, 0xff, 0xff }, 2444 { 0x3f, 0xff, 0xff, 0xff } 2445 }; 2446 2447 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 2448 { 0x20, 0x2d, 0x34, 0x3a }, 2449 { 0x20, 0x2e, 0x35, 0xff }, 2450 { 0x20, 0x2e, 0xff, 0xff }, 2451 { 0x22, 0xff, 0xff, 0xff } 2452 }; 2453 2454 struct qmp_combo_lane_mapping { 2455 unsigned int lanes_count; 2456 enum typec_orientation orientation; 2457 u32 lanes[4]; 2458 }; 2459 2460 static const struct qmp_combo_lane_mapping usb3_data_lanes[] = { 2461 { 2, TYPEC_ORIENTATION_NORMAL, { 1, 0 }}, 2462 { 2, TYPEC_ORIENTATION_REVERSE, { 2, 3 }}, 2463 }; 2464 2465 static const struct qmp_combo_lane_mapping dp_data_lanes[] = { 2466 { 1, TYPEC_ORIENTATION_NORMAL, { 3 }}, 2467 { 1, TYPEC_ORIENTATION_REVERSE, { 0 }}, 2468 { 2, TYPEC_ORIENTATION_NORMAL, { 3, 2 }}, 2469 { 2, TYPEC_ORIENTATION_REVERSE, { 0, 1 }}, 2470 { 4, TYPEC_ORIENTATION_NORMAL, { 3, 2, 1, 0 }}, 2471 { 4, TYPEC_ORIENTATION_REVERSE, { 0, 1, 2, 3 }}, 2472 }; 2473 2474 struct qmp_combo; 2475 2476 struct qmp_combo_offsets { 2477 u16 com; 2478 u16 txa; 2479 u16 rxa; 2480 u16 txb; 2481 u16 rxb; 2482 u16 usb3_serdes; 2483 u16 usb3_pcs_misc; 2484 u16 usb3_pcs; 2485 u16 usb3_pcs_aon; 2486 u16 usb3_pcs_usb; 2487 u16 dp_serdes; 2488 u16 dp_txa; 2489 u16 dp_txb; 2490 u16 dp_dp_phy; 2491 u16 aon_toggle; 2492 }; 2493 2494 struct qmp_phy_cfg { 2495 const struct qmp_combo_offsets *offsets; 2496 2497 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 2498 const struct qmp_phy_init_tbl *serdes_tbl; 2499 int serdes_tbl_num; 2500 const struct qmp_phy_init_tbl *tx_tbl; 2501 int tx_tbl_num; 2502 const struct qmp_phy_init_tbl *rx_tbl; 2503 int rx_tbl_num; 2504 const struct qmp_phy_init_tbl *pcs_tbl; 2505 int pcs_tbl_num; 2506 const struct qmp_phy_init_tbl *pcs_usb_tbl; 2507 int pcs_usb_tbl_num; 2508 const struct qmp_phy_init_tbl *pcs_misc_tbl; 2509 int pcs_misc_tbl_num; 2510 2511 const struct qmp_phy_init_tbl *dp_serdes_tbl; 2512 int dp_serdes_tbl_num; 2513 const struct qmp_phy_init_tbl *dp_tx_tbl; 2514 int dp_tx_tbl_num; 2515 2516 /* Init sequence for DP PHY block link rates */ 2517 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 2518 int serdes_tbl_rbr_num; 2519 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 2520 int serdes_tbl_hbr_num; 2521 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 2522 int serdes_tbl_hbr2_num; 2523 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 2524 int serdes_tbl_hbr3_num; 2525 2526 /* DP PHY swing and pre_emphasis tables */ 2527 const u8 (*swing_hbr_rbr)[4][4]; 2528 const u8 (*swing_hbr3_hbr2)[4][4]; 2529 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 2530 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 2531 2532 /* DP PHY callbacks */ 2533 int (*configure_dp_clocks)(struct qmp_combo *qmp); 2534 int (*configure_dp_phy)(struct qmp_combo *qmp); 2535 void (*configure_dp_tx)(struct qmp_combo *qmp); 2536 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 2537 void (*dp_aux_init)(struct qmp_combo *qmp); 2538 2539 /* resets to be requested */ 2540 const char * const *reset_list; 2541 int num_resets; 2542 /* regulators to be requested */ 2543 const struct regulator_bulk_data *vreg_list; 2544 int num_vregs; 2545 2546 /* array of registers with different offsets */ 2547 const unsigned int *regs; 2548 2549 /* true, if PHY needs delay after POWER_DOWN */ 2550 bool has_pwrdn_delay; 2551 2552 /* Offset from PCS to PCS_USB region */ 2553 unsigned int pcs_usb_offset; 2554 2555 bool invert_cc_polarity; 2556 }; 2557 2558 struct qmp_combo { 2559 struct device *dev; 2560 2561 const struct qmp_phy_cfg *cfg; 2562 2563 void __iomem *com; 2564 void __iomem *aon_toggle; 2565 2566 void __iomem *serdes; 2567 void __iomem *tx; 2568 void __iomem *rx; 2569 void __iomem *pcs; 2570 void __iomem *tx2; 2571 void __iomem *rx2; 2572 void __iomem *pcs_misc; 2573 void __iomem *pcs_aon; 2574 void __iomem *pcs_usb; 2575 2576 void __iomem *dp_serdes; 2577 void __iomem *dp_tx; 2578 void __iomem *dp_tx2; 2579 void __iomem *dp_dp_phy; 2580 2581 struct clk *pipe_clk; 2582 struct clk_bulk_data *clks; 2583 int num_clks; 2584 struct reset_control_bulk_data *resets; 2585 struct regulator_bulk_data *vregs; 2586 2587 struct mutex phy_mutex; 2588 int init_count; 2589 enum qmpphy_mode qmpphy_mode; 2590 2591 struct phy *usb_phy; 2592 enum phy_mode phy_mode; 2593 unsigned int usb_init_count; 2594 2595 struct phy *dp_phy; 2596 unsigned int dp_aux_cfg; 2597 struct phy_configure_opts_dp dp_opts; 2598 unsigned int dp_init_count; 2599 bool dp_powered_on; 2600 2601 struct clk_fixed_rate pipe_clk_fixed; 2602 struct clk_hw dp_link_hw; 2603 struct clk_hw dp_pixel_hw; 2604 2605 struct typec_switch_dev *sw; 2606 enum typec_orientation orientation; 2607 2608 struct typec_mux_dev *mux; 2609 }; 2610 2611 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 2612 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 2613 static int qmp_v3_configure_dp_clocks(struct qmp_combo *qmp); 2614 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 2615 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 2616 2617 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 2618 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 2619 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 2620 2621 static void qmp_v8_dp_aux_init(struct qmp_combo *qmp); 2622 static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp); 2623 static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp); 2624 2625 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 2626 { 2627 u32 reg; 2628 2629 reg = readl(base + offset); 2630 reg |= val; 2631 writel(reg, base + offset); 2632 2633 /* ensure that above write is through */ 2634 readl(base + offset); 2635 } 2636 2637 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 2638 { 2639 u32 reg; 2640 2641 reg = readl(base + offset); 2642 reg &= ~val; 2643 writel(reg, base + offset); 2644 2645 /* ensure that above write is through */ 2646 readl(base + offset); 2647 } 2648 2649 /* list of clocks required by phy */ 2650 static const char * const qmp_combo_phy_clk_l[] = { 2651 "aux", "cfg_ahb", "ref", "com_aux", 2652 }; 2653 2654 /* list of resets */ 2655 static const char * const msm8996_usb3phy_reset_l[] = { 2656 "phy", "common", 2657 }; 2658 2659 static const char * const sc7180_usb3phy_reset_l[] = { 2660 "phy", 2661 }; 2662 2663 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 2664 .com = 0x0000, 2665 .txa = 0x1200, 2666 .rxa = 0x1400, 2667 .txb = 0x1600, 2668 .rxb = 0x1800, 2669 .usb3_serdes = 0x1000, 2670 .usb3_pcs_misc = 0x1a00, 2671 .usb3_pcs = 0x1c00, 2672 .usb3_pcs_usb = 0x1f00, 2673 .dp_serdes = 0x2000, 2674 .dp_txa = 0x2200, 2675 .dp_txb = 0x2600, 2676 .dp_dp_phy = 0x2a00, 2677 }; 2678 2679 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 2680 .com = 0x0000, 2681 .txa = 0x0400, 2682 .rxa = 0x0600, 2683 .txb = 0x0a00, 2684 .rxb = 0x0c00, 2685 .usb3_serdes = 0x1000, 2686 .usb3_pcs_misc = 0x1200, 2687 .usb3_pcs = 0x1400, 2688 .usb3_pcs_usb = 0x1700, 2689 .dp_serdes = 0x2000, 2690 .dp_dp_phy = 0x2200, 2691 }; 2692 2693 static const struct qmp_combo_offsets qmp_combo_offsets_v8 = { 2694 .com = 0x0000, 2695 .txa = 0x1400, 2696 .rxa = 0x1600, 2697 .txb = 0x1800, 2698 .rxb = 0x1a00, 2699 .usb3_serdes = 0x1000, 2700 .usb3_pcs_misc = 0x1c00, 2701 .usb3_pcs = 0x1e00, 2702 .usb3_pcs_aon = 0x2000, 2703 .usb3_pcs_usb = 0x2100, 2704 .dp_serdes = 0x3000, 2705 .dp_txa = 0x3400, 2706 .dp_txb = 0x3800, 2707 .dp_dp_phy = 0x3c00, 2708 }; 2709 2710 static const struct qmp_combo_offsets qmp_combo_offsets_v10 = { 2711 .com = 0x0000, 2712 .aon_toggle = 0x0400, 2713 .txa = 0x1400, 2714 .rxa = 0x1600, 2715 .txb = 0x1800, 2716 .rxb = 0x1a00, 2717 .usb3_serdes = 0x1000, 2718 .usb3_pcs_misc = 0x1c00, 2719 .usb3_pcs = 0x1e00, 2720 .usb3_pcs_aon = 0x2000, 2721 .usb3_pcs_usb = 0x2100, 2722 .dp_serdes = 0x3000, 2723 .dp_txa = 0x3400, 2724 .dp_txb = 0x3800, 2725 .dp_dp_phy = 0x3c00, 2726 }; 2727 2728 static const struct qmp_combo_offsets qmp_combo_usb43dp_offsets_v8 = { 2729 .com = 0x0000, 2730 .usb3_pcs_aon = 0x0100, 2731 .usb3_serdes = 0x1000, 2732 .usb3_pcs_misc = 0x1400, 2733 .usb3_pcs = 0x1600, 2734 .usb3_pcs_usb = 0x1900, 2735 .dp_serdes = 0x2000, 2736 .dp_dp_phy = 0x2400, 2737 .txa = 0x4000, 2738 .txb = 0x5000, 2739 }; 2740 2741 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = { 2742 .offsets = &qmp_combo_offsets_v3, 2743 2744 .serdes_tbl = sar2130p_usb3_serdes_tbl, 2745 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 2746 .tx_tbl = sm8550_usb3_tx_tbl, 2747 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2748 .rx_tbl = sm8550_usb3_rx_tbl, 2749 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2750 .pcs_tbl = sm8550_usb3_pcs_tbl, 2751 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2752 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2753 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2754 2755 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2756 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2757 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2758 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2759 2760 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2761 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2762 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2763 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2764 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2765 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2766 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2767 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2768 2769 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2770 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2771 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2772 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2773 2774 .dp_aux_init = qmp_v4_dp_aux_init, 2775 .configure_dp_tx = qmp_v4_configure_dp_tx, 2776 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2777 .configure_dp_phy = qmp_v4_configure_dp_phy, 2778 2779 .regs = qmp_v6_usb3phy_regs_layout, 2780 .reset_list = msm8996_usb3phy_reset_l, 2781 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2782 .vreg_list = qmp_phy_vreg_l, 2783 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2784 .invert_cc_polarity = true, 2785 }; 2786 2787 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 2788 .offsets = &qmp_combo_offsets_v3, 2789 2790 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2791 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2792 .tx_tbl = qmp_v3_usb3_tx_tbl, 2793 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2794 .rx_tbl = qmp_v3_usb3_rx_tbl, 2795 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2796 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2797 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2798 2799 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2800 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2801 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2802 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2803 2804 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2805 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2806 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2807 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2808 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2809 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2810 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2811 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2812 2813 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2814 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2815 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2816 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2817 2818 .dp_aux_init = qmp_v3_dp_aux_init, 2819 .configure_dp_tx = qmp_v3_configure_dp_tx, 2820 .configure_dp_phy = qmp_v3_configure_dp_phy, 2821 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2822 2823 .reset_list = sc7180_usb3phy_reset_l, 2824 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 2825 .vreg_list = qmp_phy_vreg_l, 2826 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2827 .regs = qmp_v3_usb3phy_regs_layout, 2828 2829 .has_pwrdn_delay = true, 2830 }; 2831 2832 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 2833 .offsets = &qmp_combo_offsets_v3, 2834 2835 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 2836 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 2837 .tx_tbl = qmp_v3_usb3_tx_tbl, 2838 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 2839 .rx_tbl = qmp_v3_usb3_rx_tbl, 2840 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 2841 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 2842 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 2843 2844 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 2845 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 2846 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 2847 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 2848 2849 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 2850 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 2851 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 2852 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 2853 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 2854 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 2855 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 2856 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 2857 2858 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2859 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2860 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2861 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2862 2863 .dp_aux_init = qmp_v3_dp_aux_init, 2864 .configure_dp_tx = qmp_v3_configure_dp_tx, 2865 .configure_dp_phy = qmp_v3_configure_dp_phy, 2866 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 2867 2868 .reset_list = msm8996_usb3phy_reset_l, 2869 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2870 .vreg_list = qmp_phy_vreg_l, 2871 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2872 .regs = qmp_v3_usb3phy_regs_layout, 2873 2874 .has_pwrdn_delay = true, 2875 }; 2876 2877 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 2878 .offsets = &qmp_combo_offsets_v3, 2879 2880 .serdes_tbl = sm8150_usb3_serdes_tbl, 2881 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2882 .tx_tbl = sm8150_usb3_tx_tbl, 2883 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 2884 .rx_tbl = sm8150_usb3_rx_tbl, 2885 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 2886 .pcs_tbl = sm8150_usb3_pcs_tbl, 2887 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 2888 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 2889 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 2890 2891 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 2892 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 2893 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 2894 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 2895 2896 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2897 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2898 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2899 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2900 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2901 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2902 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2903 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2904 2905 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 2906 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 2907 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 2908 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 2909 2910 .dp_aux_init = qmp_v4_dp_aux_init, 2911 .configure_dp_tx = qmp_v4_configure_dp_tx, 2912 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2913 .configure_dp_phy = qmp_v4_configure_dp_phy, 2914 2915 .reset_list = msm8996_usb3phy_reset_l, 2916 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2917 .vreg_list = qmp_phy_vreg_l, 2918 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2919 .regs = qmp_v45_usb3phy_regs_layout, 2920 .pcs_usb_offset = 0x300, 2921 2922 .has_pwrdn_delay = true, 2923 }; 2924 2925 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 2926 .offsets = &qmp_combo_offsets_v5, 2927 2928 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 2929 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 2930 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 2931 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 2932 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 2933 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 2934 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 2935 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 2936 2937 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 2938 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 2939 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 2940 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 2941 2942 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 2943 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 2944 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 2945 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 2946 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 2947 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 2948 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 2949 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 2950 2951 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 2952 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 2953 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2954 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2955 2956 .dp_aux_init = qmp_v4_dp_aux_init, 2957 .configure_dp_tx = qmp_v4_configure_dp_tx, 2958 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 2959 .configure_dp_phy = qmp_v4_configure_dp_phy, 2960 2961 .reset_list = msm8996_usb3phy_reset_l, 2962 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2963 .vreg_list = qmp_phy_vreg_l, 2964 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2965 .regs = qmp_v5_5nm_usb3phy_regs_layout, 2966 }; 2967 2968 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 2969 .offsets = &qmp_combo_offsets_v5, 2970 2971 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 2972 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 2973 .tx_tbl = x1e80100_usb43dp_tx_tbl, 2974 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 2975 .rx_tbl = x1e80100_usb43dp_rx_tbl, 2976 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 2977 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 2978 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 2979 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 2980 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 2981 2982 .dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl, 2983 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl), 2984 .dp_tx_tbl = qmp_v6_n4_dp_tx_tbl, 2985 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl), 2986 2987 .serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr, 2988 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr), 2989 .serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr, 2990 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr), 2991 .serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2, 2992 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2), 2993 .serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3, 2994 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3), 2995 2996 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2997 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2998 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2999 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3000 3001 .dp_aux_init = qmp_v4_dp_aux_init, 3002 .configure_dp_tx = qmp_v4_configure_dp_tx, 3003 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3004 .configure_dp_phy = qmp_v4_configure_dp_phy, 3005 3006 .reset_list = msm8996_usb3phy_reset_l, 3007 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3008 .vreg_list = qmp_phy_vreg_l, 3009 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3010 .regs = qmp_v6_n4_usb3phy_regs_layout, 3011 }; 3012 3013 static const struct qmp_phy_cfg hawi_usb3dpphy_cfg = { 3014 .offsets = &qmp_combo_offsets_v10, 3015 3016 .serdes_tbl = hawi_usb3_serdes_tbl, 3017 .serdes_tbl_num = ARRAY_SIZE(hawi_usb3_serdes_tbl), 3018 .tx_tbl = hawi_usb3_tx_tbl, 3019 .tx_tbl_num = ARRAY_SIZE(hawi_usb3_tx_tbl), 3020 .rx_tbl = hawi_usb3_rx_tbl, 3021 .rx_tbl_num = ARRAY_SIZE(hawi_usb3_rx_tbl), 3022 .pcs_tbl = hawi_usb3_pcs_tbl, 3023 .pcs_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_tbl), 3024 .pcs_usb_tbl = hawi_usb3_pcs_usb_tbl, 3025 .pcs_usb_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_usb_tbl), 3026 3027 .regs = qmp_v10_usb3phy_regs_layout, 3028 .reset_list = msm8996_usb3phy_reset_l, 3029 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3030 .vreg_list = qmp_phy_vreg_l, 3031 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3032 }; 3033 3034 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 3035 .offsets = &qmp_combo_offsets_v3, 3036 3037 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 3038 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 3039 .tx_tbl = qmp_v3_usb3_tx_tbl, 3040 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 3041 .rx_tbl = sm6350_usb3_rx_tbl, 3042 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 3043 .pcs_tbl = sm6350_usb3_pcs_tbl, 3044 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 3045 3046 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 3047 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 3048 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 3049 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 3050 3051 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 3052 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 3053 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 3054 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 3055 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 3056 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 3057 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 3058 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 3059 3060 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 3061 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 3062 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 3063 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 3064 3065 .dp_aux_init = qmp_v3_dp_aux_init, 3066 .configure_dp_tx = qmp_v3_configure_dp_tx, 3067 .configure_dp_phy = qmp_v3_configure_dp_phy, 3068 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 3069 3070 .reset_list = msm8996_usb3phy_reset_l, 3071 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3072 .vreg_list = qmp_phy_vreg_l, 3073 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3074 .regs = qmp_v3_usb3phy_regs_layout, 3075 }; 3076 3077 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 3078 .offsets = &qmp_combo_offsets_v3, 3079 3080 .serdes_tbl = sm8150_usb3_serdes_tbl, 3081 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 3082 .tx_tbl = sm8250_usb3_tx_tbl, 3083 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 3084 .rx_tbl = sm8250_usb3_rx_tbl, 3085 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 3086 .pcs_tbl = sm8250_usb3_pcs_tbl, 3087 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 3088 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 3089 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 3090 3091 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 3092 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 3093 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 3094 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 3095 3096 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 3097 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 3098 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 3099 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 3100 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 3101 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 3102 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 3103 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 3104 3105 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 3106 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 3107 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 3108 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 3109 3110 .dp_aux_init = qmp_v4_dp_aux_init, 3111 .configure_dp_tx = qmp_v4_configure_dp_tx, 3112 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3113 .configure_dp_phy = qmp_v4_configure_dp_phy, 3114 3115 .reset_list = msm8996_usb3phy_reset_l, 3116 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3117 .vreg_list = qmp_phy_vreg_l, 3118 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3119 .regs = qmp_v45_usb3phy_regs_layout, 3120 .pcs_usb_offset = 0x300, 3121 3122 .has_pwrdn_delay = true, 3123 }; 3124 3125 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 3126 .offsets = &qmp_combo_offsets_v3, 3127 3128 .serdes_tbl = sm8150_usb3_serdes_tbl, 3129 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 3130 .tx_tbl = sm8350_usb3_tx_tbl, 3131 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 3132 .rx_tbl = sm8350_usb3_rx_tbl, 3133 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 3134 .pcs_tbl = sm8350_usb3_pcs_tbl, 3135 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 3136 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 3137 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 3138 3139 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 3140 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 3141 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 3142 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 3143 3144 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 3145 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 3146 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 3147 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 3148 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 3149 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 3150 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 3151 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 3152 3153 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 3154 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 3155 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 3156 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 3157 3158 .dp_aux_init = qmp_v4_dp_aux_init, 3159 .configure_dp_tx = qmp_v4_configure_dp_tx, 3160 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3161 .configure_dp_phy = qmp_v4_configure_dp_phy, 3162 3163 .reset_list = msm8996_usb3phy_reset_l, 3164 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3165 .vreg_list = qmp_phy_vreg_l, 3166 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3167 .regs = qmp_v45_usb3phy_regs_layout, 3168 3169 .has_pwrdn_delay = true, 3170 }; 3171 3172 static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg = { 3173 .offsets = &qmp_combo_offsets_v3, 3174 3175 .serdes_tbl = sar2130p_usb3_serdes_tbl, 3176 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl), 3177 .tx_tbl = sm8550_usb3_tx_tbl, 3178 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 3179 .rx_tbl = sm8475_usb3_rx_tbl, 3180 .rx_tbl_num = ARRAY_SIZE(sm8475_usb3_rx_tbl), 3181 .pcs_tbl = sm8550_usb3_pcs_tbl, 3182 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 3183 .pcs_usb_tbl = sm8475_usb3_pcs_usb_tbl, 3184 .pcs_usb_tbl_num = ARRAY_SIZE(sm8475_usb3_pcs_usb_tbl), 3185 3186 .dp_serdes_tbl = qmp_v6_dp_v1_serdes_tbl, 3187 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl), 3188 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 3189 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 3190 3191 .serdes_tbl_rbr = qmp_v6_dp_v1_serdes_tbl_rbr, 3192 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_rbr), 3193 .serdes_tbl_hbr = qmp_v6_dp_v1_serdes_tbl_hbr, 3194 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr), 3195 .serdes_tbl_hbr2 = qmp_v6_dp_v1_serdes_tbl_hbr2, 3196 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr2), 3197 .serdes_tbl_hbr3 = qmp_v6_dp_v1_serdes_tbl_hbr3, 3198 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr3), 3199 3200 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 3201 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 3202 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 3203 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3204 3205 .dp_aux_init = qmp_v4_dp_aux_init, 3206 .configure_dp_tx = qmp_v4_configure_dp_tx, 3207 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3208 .configure_dp_phy = qmp_v4_configure_dp_phy, 3209 3210 .regs = qmp_v6_usb3phy_regs_layout, 3211 .reset_list = msm8996_usb3phy_reset_l, 3212 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3213 .vreg_list = qmp_phy_vreg_l, 3214 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3215 }; 3216 3217 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 3218 .offsets = &qmp_combo_offsets_v3, 3219 3220 .serdes_tbl = sm8550_usb3_serdes_tbl, 3221 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 3222 .tx_tbl = sm8550_usb3_tx_tbl, 3223 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 3224 .rx_tbl = sm8550_usb3_rx_tbl, 3225 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 3226 .pcs_tbl = sm8550_usb3_pcs_tbl, 3227 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 3228 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 3229 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 3230 3231 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 3232 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 3233 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 3234 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 3235 3236 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 3237 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 3238 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 3239 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 3240 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 3241 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 3242 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 3243 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 3244 3245 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 3246 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 3247 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 3248 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3249 3250 .dp_aux_init = qmp_v4_dp_aux_init, 3251 .configure_dp_tx = qmp_v4_configure_dp_tx, 3252 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3253 .configure_dp_phy = qmp_v4_configure_dp_phy, 3254 3255 .regs = qmp_v6_usb3phy_regs_layout, 3256 .reset_list = msm8996_usb3phy_reset_l, 3257 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3258 .vreg_list = qmp_phy_vreg_l, 3259 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3260 }; 3261 3262 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = { 3263 .offsets = &qmp_combo_offsets_v3, 3264 3265 .serdes_tbl = sm8550_usb3_serdes_tbl, 3266 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 3267 .tx_tbl = sm8550_usb3_tx_tbl, 3268 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 3269 .rx_tbl = sm8550_usb3_rx_tbl, 3270 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 3271 .pcs_tbl = sm8550_usb3_pcs_tbl, 3272 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 3273 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 3274 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 3275 3276 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 3277 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 3278 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 3279 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 3280 3281 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 3282 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 3283 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 3284 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 3285 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 3286 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 3287 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 3288 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 3289 3290 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 3291 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 3292 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 3293 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3294 3295 .dp_aux_init = qmp_v4_dp_aux_init, 3296 .configure_dp_tx = qmp_v4_configure_dp_tx, 3297 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3298 .configure_dp_phy = qmp_v4_configure_dp_phy, 3299 3300 .regs = qmp_v6_usb3phy_regs_layout, 3301 .reset_list = msm8996_usb3phy_reset_l, 3302 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3303 .vreg_list = qmp_phy_vreg_l, 3304 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3305 }; 3306 3307 static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = { 3308 .offsets = &qmp_combo_offsets_v8, 3309 3310 .serdes_tbl = sm8750_usb3_serdes_tbl, 3311 .serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl), 3312 .tx_tbl = sm8750_usb3_tx_tbl, 3313 .tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl), 3314 .rx_tbl = sm8750_usb3_rx_tbl, 3315 .rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl), 3316 .pcs_tbl = sm8750_usb3_pcs_tbl, 3317 .pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl), 3318 .pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl, 3319 .pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), 3320 3321 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 3322 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 3323 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 3324 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 3325 3326 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 3327 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 3328 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 3329 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 3330 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 3331 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 3332 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 3333 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 3334 3335 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 3336 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 3337 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 3338 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3339 3340 .dp_aux_init = qmp_v4_dp_aux_init, 3341 .configure_dp_tx = qmp_v4_configure_dp_tx, 3342 .configure_dp_clocks = qmp_v3_configure_dp_clocks, 3343 .configure_dp_phy = qmp_v4_configure_dp_phy, 3344 3345 .regs = qmp_v8_usb3phy_regs_layout, 3346 .reset_list = msm8996_usb3phy_reset_l, 3347 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3348 .vreg_list = qmp_phy_vreg_l, 3349 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 3350 }; 3351 3352 static const struct qmp_phy_cfg glymur_usb3dpphy_cfg = { 3353 .offsets = &qmp_combo_usb43dp_offsets_v8, 3354 3355 .serdes_tbl = glymur_usb43dp_serdes_tbl, 3356 .serdes_tbl_num = ARRAY_SIZE(glymur_usb43dp_serdes_tbl), 3357 .tx_tbl = glymur_usb43dp_lalb_tbl, 3358 .tx_tbl_num = ARRAY_SIZE(glymur_usb43dp_lalb_tbl), 3359 .pcs_tbl = glymur_usb43dp_pcs_tbl, 3360 .pcs_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_tbl), 3361 .pcs_usb_tbl = glymur_usb43dp_pcs_usb_tbl, 3362 .pcs_usb_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_usb_tbl), 3363 .pcs_misc_tbl = glymur_usb43dp_pcs_misc_tbl, 3364 .pcs_misc_tbl_num = ARRAY_SIZE(glymur_usb43dp_pcs_misc_tbl), 3365 3366 .dp_serdes_tbl = qmp_v8_dp_serdes_tbl, 3367 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl), 3368 .dp_tx_tbl = qmp_v8_n3p_dp_tx_tbl, 3369 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v8_n3p_dp_tx_tbl), 3370 3371 .serdes_tbl_rbr = qmp_v8_dp_serdes_tbl_rbr, 3372 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_rbr), 3373 .serdes_tbl_hbr = qmp_v8_dp_serdes_tbl_hbr, 3374 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr), 3375 .serdes_tbl_hbr2 = qmp_v8_dp_serdes_tbl_hbr2, 3376 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr2), 3377 .serdes_tbl_hbr3 = qmp_v8_dp_serdes_tbl_hbr3, 3378 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v8_dp_serdes_tbl_hbr3), 3379 3380 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 3381 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 3382 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 3383 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 3384 3385 .dp_aux_init = qmp_v8_dp_aux_init, 3386 .configure_dp_tx = qmp_v4_configure_dp_tx, 3387 .configure_dp_clocks = qmp_v8_configure_dp_clocks, 3388 .configure_dp_phy = qmp_v8_configure_dp_phy, 3389 3390 .regs = qmp_v8_n3_usb43dpphy_regs_layout, 3391 .reset_list = msm8996_usb3phy_reset_l, 3392 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 3393 .vreg_list = qmp_phy_vreg_refgen, 3394 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_refgen), 3395 }; 3396 3397 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 3398 { 3399 const struct qmp_phy_cfg *cfg = qmp->cfg; 3400 void __iomem *serdes = qmp->dp_serdes; 3401 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3402 3403 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, 3404 cfg->dp_serdes_tbl_num); 3405 3406 switch (dp_opts->link_rate) { 3407 case 1620: 3408 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, 3409 cfg->serdes_tbl_rbr_num); 3410 break; 3411 case 2700: 3412 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, 3413 cfg->serdes_tbl_hbr_num); 3414 break; 3415 case 5400: 3416 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, 3417 cfg->serdes_tbl_hbr2_num); 3418 break; 3419 case 8100: 3420 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3, 3421 cfg->serdes_tbl_hbr3_num); 3422 break; 3423 default: 3424 /* Other link rates aren't supported */ 3425 return -EINVAL; 3426 } 3427 3428 return 0; 3429 } 3430 3431 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 3432 { 3433 const struct qmp_phy_cfg *cfg = qmp->cfg; 3434 3435 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3436 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3437 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3438 3439 /* Turn on BIAS current for PHY/PLL */ 3440 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 3441 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 3442 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3443 3444 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3445 3446 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3447 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 3448 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 3449 DP_PHY_PD_CTL_DP_CLAMP_EN, 3450 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3451 3452 writel(QSERDES_V3_COM_BIAS_EN | 3453 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 3454 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 3455 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 3456 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3457 3458 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3459 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3460 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3461 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3462 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3463 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3464 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3465 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3466 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3467 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3468 qmp->dp_aux_cfg = 0; 3469 3470 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3471 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3472 PHY_AUX_REQ_ERR_MASK, 3473 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 3474 } 3475 3476 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 3477 { 3478 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3479 const struct qmp_phy_cfg *cfg = qmp->cfg; 3480 unsigned int v_level = 0, p_level = 0; 3481 u8 voltage_swing_cfg, pre_emphasis_cfg; 3482 int i; 3483 3484 for (i = 0; i < dp_opts->lanes; i++) { 3485 v_level = max(v_level, dp_opts->voltage[i]); 3486 p_level = max(p_level, dp_opts->pre[i]); 3487 } 3488 3489 if (dp_opts->link_rate <= 2700) { 3490 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 3491 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 3492 } else { 3493 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 3494 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 3495 } 3496 3497 /* TODO: Move check to config check */ 3498 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 3499 return -EINVAL; 3500 3501 /* Enable MUX to use Cursor values from these registers */ 3502 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 3503 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 3504 3505 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3506 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3507 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3508 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3509 3510 return 0; 3511 } 3512 3513 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 3514 { 3515 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3516 u32 bias_en, drvr_en; 3517 3518 if (qmp_combo_configure_dp_swing(qmp) < 0) 3519 return; 3520 3521 if (dp_opts->lanes == 1) { 3522 bias_en = 0x3e; 3523 drvr_en = 0x13; 3524 } else { 3525 bias_en = 0x3f; 3526 drvr_en = 0x10; 3527 } 3528 3529 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 3530 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 3531 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 3532 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 3533 } 3534 3535 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 3536 { 3537 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3538 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3539 u32 val; 3540 3541 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3542 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 3543 3544 if (dp_opts->lanes == 4 || reverse) 3545 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 3546 if (dp_opts->lanes == 4 || !reverse) 3547 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 3548 3549 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3550 3551 if (reverse) 3552 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 3553 else 3554 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 3555 3556 return reverse; 3557 } 3558 3559 static int qmp_v3_configure_dp_clocks(struct qmp_combo *qmp) 3560 { 3561 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3562 u32 phy_vco_div; 3563 unsigned long pixel_freq; 3564 const struct qmp_phy_cfg *cfg = qmp->cfg; 3565 3566 switch (dp_opts->link_rate) { 3567 case 1620: 3568 phy_vco_div = 0x1; 3569 pixel_freq = 1620000000UL / 2; 3570 break; 3571 case 2700: 3572 phy_vco_div = 0x1; 3573 pixel_freq = 2700000000UL / 2; 3574 break; 3575 case 5400: 3576 phy_vco_div = 0x2; 3577 pixel_freq = 5400000000UL / 4; 3578 break; 3579 case 8100: 3580 phy_vco_div = 0x0; 3581 pixel_freq = 8100000000UL / 6; 3582 break; 3583 default: 3584 /* Other link rates aren't supported */ 3585 return -EINVAL; 3586 } 3587 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 3588 3589 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 3590 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 3591 3592 return 0; 3593 } 3594 3595 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 3596 { 3597 const struct qmp_phy_cfg *cfg = qmp->cfg; 3598 u32 status; 3599 int ret; 3600 3601 qmp_combo_configure_dp_mode(qmp); 3602 3603 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 3604 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 3605 3606 ret = qmp_v3_configure_dp_clocks(qmp); 3607 if (ret) 3608 return ret; 3609 3610 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3611 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3612 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3613 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3614 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3615 3616 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 3617 3618 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 3619 status, 3620 ((status & BIT(0)) > 0), 3621 500, 3622 10000)) 3623 return -ETIMEDOUT; 3624 3625 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3626 3627 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3628 status, 3629 ((status & BIT(1)) > 0), 3630 500, 3631 10000)) 3632 return -ETIMEDOUT; 3633 3634 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3635 udelay(2000); 3636 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3637 3638 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3639 status, 3640 ((status & BIT(1)) > 0), 3641 500, 3642 10000); 3643 } 3644 3645 /* 3646 * We need to calibrate the aux setting here as many times 3647 * as the caller tries 3648 */ 3649 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 3650 { 3651 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 3652 u8 val; 3653 3654 qmp->dp_aux_cfg++; 3655 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 3656 val = cfg1_settings[qmp->dp_aux_cfg]; 3657 3658 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3659 3660 return 0; 3661 } 3662 3663 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 3664 { 3665 const struct qmp_phy_cfg *cfg = qmp->cfg; 3666 3667 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3668 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3669 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3670 3671 /* Turn on BIAS current for PHY/PLL */ 3672 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3673 3674 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3675 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3676 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3677 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3678 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3679 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3680 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3681 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3682 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3683 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3684 3685 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3686 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3687 PHY_AUX_REQ_ERR_MASK, 3688 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 3689 } 3690 3691 static void qmp_v8_dp_aux_init(struct qmp_combo *qmp) 3692 { 3693 const struct qmp_phy_cfg *cfg = qmp->cfg; 3694 3695 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 3696 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 3697 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 3698 3699 /* Turn on BIAS current for PHY/PLL */ 3700 writel(0x1c, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 3701 3702 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 3703 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3704 writel(0x06, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3705 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 3706 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 3707 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 3708 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 3709 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 3710 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 3711 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 3712 3713 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 3714 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 3715 PHY_AUX_REQ_ERR_MASK, 3716 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 3717 } 3718 3719 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 3720 { 3721 const struct qmp_phy_cfg *cfg = qmp->cfg; 3722 3723 /* Program default values before writing proper values */ 3724 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3725 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3726 3727 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3728 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3729 3730 qmp_combo_configure_dp_swing(qmp); 3731 } 3732 3733 static int qmp_v8_configure_dp_clocks(struct qmp_combo *qmp) 3734 { 3735 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3736 u32 phy_vco_div; 3737 unsigned long pixel_freq; 3738 const struct qmp_phy_cfg *cfg = qmp->cfg; 3739 3740 switch (dp_opts->link_rate) { 3741 case 1620: 3742 phy_vco_div = 0x4; 3743 pixel_freq = 1620000000UL / 2; 3744 break; 3745 case 2700: 3746 phy_vco_div = 0x2; 3747 pixel_freq = 2700000000UL / 2; 3748 break; 3749 case 5400: 3750 phy_vco_div = 0x4; 3751 pixel_freq = 5400000000UL / 4; 3752 break; 3753 case 8100: 3754 phy_vco_div = 0x3; 3755 pixel_freq = 8100000000UL / 6; 3756 break; 3757 default: 3758 /* Other link rates aren't supported */ 3759 return -EINVAL; 3760 } 3761 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 3762 3763 /* disable core reset tsync */ 3764 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3765 3766 writel(0x04, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SETUP_CYC); 3767 writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_SILENCE_CYC); 3768 writel(0x08, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_CYC); 3769 writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); 3770 3771 writel(0x3e, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TSYNC_OVRD); 3772 writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX2_TX3_LANE_CTL); 3773 writel(0x05, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_TX0_TX1_LANE_CTL); 3774 writel(0x01, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_AUXLESS_CFG1); 3775 writel(0x11, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LFPS_PERIOD); 3776 writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN0_DRV_LVL); 3777 writel(0x1f, qmp->dp_dp_phy + QSERDES_V8_DP_PHY_LN1_DRV_LVL); 3778 3779 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 3780 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 3781 3782 return 0; 3783 } 3784 3785 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 3786 { 3787 const struct qmp_phy_cfg *cfg = qmp->cfg; 3788 u32 status; 3789 int ret; 3790 3791 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 3792 3793 qmp_combo_configure_dp_mode(qmp); 3794 3795 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 3796 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 3797 3798 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 3799 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 3800 3801 ret = qmp->cfg->configure_dp_clocks(qmp); 3802 if (ret) 3803 return ret; 3804 3805 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3806 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3807 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3808 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3809 3810 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 3811 3812 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 3813 status, 3814 ((status & BIT(0)) > 0), 3815 500, 3816 10000)) 3817 return -ETIMEDOUT; 3818 3819 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 3820 status, 3821 ((status & BIT(0)) > 0), 3822 500, 3823 10000)) 3824 return -ETIMEDOUT; 3825 3826 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 3827 status, 3828 ((status & BIT(1)) > 0), 3829 500, 3830 10000)) 3831 return -ETIMEDOUT; 3832 3833 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3834 3835 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3836 status, 3837 ((status & BIT(0)) > 0), 3838 500, 3839 10000)) 3840 return -ETIMEDOUT; 3841 3842 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3843 status, 3844 ((status & BIT(1)) > 0), 3845 500, 3846 10000)) 3847 return -ETIMEDOUT; 3848 3849 return 0; 3850 } 3851 3852 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 3853 { 3854 const struct qmp_phy_cfg *cfg = qmp->cfg; 3855 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3856 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3857 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 3858 u32 status; 3859 int ret; 3860 3861 ret = qmp_v456_configure_dp_phy(qmp); 3862 if (ret < 0) 3863 return ret; 3864 3865 /* 3866 * At least for 7nm DP PHY this has to be done after enabling link 3867 * clock. 3868 */ 3869 3870 if (dp_opts->lanes == 1) { 3871 bias0_en = reverse ? 0x3e : 0x15; 3872 bias1_en = reverse ? 0x15 : 0x3e; 3873 drvr0_en = reverse ? 0x13 : 0x10; 3874 drvr1_en = reverse ? 0x10 : 0x13; 3875 } else if (dp_opts->lanes == 2) { 3876 bias0_en = reverse ? 0x3f : 0x15; 3877 bias1_en = reverse ? 0x15 : 0x3f; 3878 drvr0_en = 0x10; 3879 drvr1_en = 0x10; 3880 } else { 3881 bias0_en = 0x3f; 3882 bias1_en = 0x3f; 3883 drvr0_en = 0x10; 3884 drvr1_en = 0x10; 3885 } 3886 3887 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3888 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3889 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3890 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3891 3892 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3893 udelay(2000); 3894 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3895 3896 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3897 status, 3898 ((status & BIT(1)) > 0), 3899 500, 3900 10000)) 3901 return -ETIMEDOUT; 3902 3903 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 3904 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 3905 3906 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3907 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3908 3909 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3910 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3911 3912 return 0; 3913 } 3914 3915 static int qmp_v8_configure_dp_phy(struct qmp_combo *qmp) 3916 { 3917 const struct qmp_phy_cfg *cfg = qmp->cfg; 3918 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 3919 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 3920 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 3921 u32 status; 3922 int ret; 3923 3924 ret = qmp_v456_configure_dp_phy(qmp); 3925 if (ret < 0) 3926 return ret; 3927 3928 if (dp_opts->lanes == 1) { 3929 bias0_en = reverse ? 0x3e : 0x15; 3930 bias1_en = reverse ? 0x15 : 0x3e; 3931 drvr0_en = reverse ? 0x13 : 0x10; 3932 drvr1_en = reverse ? 0x10 : 0x13; 3933 } else if (dp_opts->lanes == 2) { 3934 bias0_en = reverse ? 0x3f : 0x15; 3935 bias1_en = reverse ? 0x15 : 0x3f; 3936 drvr0_en = 0x10; 3937 drvr1_en = 0x10; 3938 } else { 3939 bias0_en = 0x3f; 3940 bias1_en = 0x3f; 3941 drvr0_en = 0x34; 3942 drvr1_en = 0x34; 3943 } 3944 3945 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3946 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3947 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 3948 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 3949 3950 writel(0x08, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3951 udelay(100); 3952 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 3953 udelay(500); 3954 3955 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 3956 status, 3957 ((status & BIT(1)) > 0), 3958 500, 3959 10000)) 3960 return -ETIMEDOUT; 3961 3962 writel(0x00, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3963 writel(0x00, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 3964 3965 writel(0x2b, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3966 writel(0x2b, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 3967 3968 return 0; 3969 } 3970 3971 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 3972 { 3973 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 3974 struct qmp_combo *qmp = phy_get_drvdata(phy); 3975 const struct qmp_phy_cfg *cfg = qmp->cfg; 3976 3977 mutex_lock(&qmp->phy_mutex); 3978 3979 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 3980 if (qmp->dp_opts.set_voltages) { 3981 cfg->configure_dp_tx(qmp); 3982 qmp->dp_opts.set_voltages = 0; 3983 } 3984 3985 mutex_unlock(&qmp->phy_mutex); 3986 3987 return 0; 3988 } 3989 3990 static int qmp_combo_dp_calibrate(struct phy *phy) 3991 { 3992 struct qmp_combo *qmp = phy_get_drvdata(phy); 3993 const struct qmp_phy_cfg *cfg = qmp->cfg; 3994 int ret = 0; 3995 3996 mutex_lock(&qmp->phy_mutex); 3997 3998 if (cfg->calibrate_dp_phy) 3999 ret = cfg->calibrate_dp_phy(qmp); 4000 4001 mutex_unlock(&qmp->phy_mutex); 4002 4003 return ret; 4004 } 4005 4006 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 4007 { 4008 const struct qmp_phy_cfg *cfg = qmp->cfg; 4009 void __iomem *com = qmp->com; 4010 void __iomem *aon_toggle; 4011 int ret; 4012 u32 val; 4013 4014 if (!force && qmp->init_count++) 4015 return 0; 4016 4017 if (qmp->aon_toggle) 4018 aon_toggle = qmp->aon_toggle; 4019 else 4020 aon_toggle = qmp->pcs_aon; 4021 4022 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 4023 if (ret) { 4024 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 4025 goto err_decrement_count; 4026 } 4027 4028 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4029 if (ret) { 4030 dev_err(qmp->dev, "reset assert failed\n"); 4031 goto err_disable_regulators; 4032 } 4033 4034 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 4035 if (ret) { 4036 dev_err(qmp->dev, "reset deassert failed\n"); 4037 goto err_disable_regulators; 4038 } 4039 4040 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 4041 if (ret) 4042 goto err_assert_reset; 4043 4044 /* In DP-only mode, the pipe clk is still required for USB2 */ 4045 ret = clk_prepare_enable(qmp->pipe_clk); 4046 if (ret) { 4047 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 4048 goto err_disable_clocks; 4049 } 4050 4051 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 4052 4053 /* override hardware control for reset of qmp phy */ 4054 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 4055 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 4056 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 4057 4058 /* override hardware control for reset of qmp phy */ 4059 if (aon_toggle && cfg->regs[QPHY_AON_TOGGLE_ENABLE]) { 4060 qphy_clrbits(aon_toggle, cfg->regs[QPHY_AON_TOGGLE_ENABLE], 0x1); 4061 qphy_clrbits(aon_toggle, cfg->regs[QPHY_DP_AON_TOGGLE_ENABLE], 0x1); 4062 } 4063 4064 /* Use software based port select and switch on typec orientation */ 4065 val = SW_PORTSELECT_MUX; 4066 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 4067 val |= SW_PORTSELECT_VAL; 4068 4069 if (cfg->invert_cc_polarity) 4070 val |= INVERT_CC_POLARITY; 4071 4072 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 4073 4074 switch (qmp->qmpphy_mode) { 4075 case QMPPHY_MODE_USB3DP: 4076 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 4077 4078 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 4079 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 4080 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 4081 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 4082 break; 4083 4084 case QMPPHY_MODE_DP_ONLY: 4085 writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 4086 4087 /* bring QMP DP PHY PCS block out of reset */ 4088 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 4089 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET); 4090 break; 4091 4092 case QMPPHY_MODE_USB3_ONLY: 4093 writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 4094 4095 /* bring QMP USB PHY PCS block out of reset */ 4096 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 4097 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 4098 break; 4099 } 4100 4101 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 4102 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 4103 4104 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4105 SW_PWRDN); 4106 4107 return 0; 4108 4109 err_disable_clocks: 4110 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 4111 err_assert_reset: 4112 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4113 err_disable_regulators: 4114 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4115 err_decrement_count: 4116 qmp->init_count--; 4117 4118 return ret; 4119 } 4120 4121 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 4122 { 4123 const struct qmp_phy_cfg *cfg = qmp->cfg; 4124 4125 if (!force && --qmp->init_count) 4126 return 0; 4127 4128 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 4129 4130 clk_disable_unprepare(qmp->pipe_clk); 4131 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 4132 4133 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 4134 4135 return 0; 4136 } 4137 4138 static int qmp_combo_dp_init(struct phy *phy) 4139 { 4140 struct qmp_combo *qmp = phy_get_drvdata(phy); 4141 const struct qmp_phy_cfg *cfg = qmp->cfg; 4142 int ret; 4143 4144 mutex_lock(&qmp->phy_mutex); 4145 4146 ret = qmp_combo_com_init(qmp, false); 4147 if (ret) 4148 goto out_unlock; 4149 4150 cfg->dp_aux_init(qmp); 4151 4152 qmp->dp_init_count++; 4153 4154 out_unlock: 4155 mutex_unlock(&qmp->phy_mutex); 4156 return ret; 4157 } 4158 4159 static int qmp_combo_dp_exit(struct phy *phy) 4160 { 4161 struct qmp_combo *qmp = phy_get_drvdata(phy); 4162 4163 mutex_lock(&qmp->phy_mutex); 4164 4165 qmp_combo_com_exit(qmp, false); 4166 4167 qmp->dp_init_count--; 4168 4169 mutex_unlock(&qmp->phy_mutex); 4170 4171 return 0; 4172 } 4173 4174 static int qmp_combo_dp_power_on(struct phy *phy) 4175 { 4176 struct qmp_combo *qmp = phy_get_drvdata(phy); 4177 const struct qmp_phy_cfg *cfg = qmp->cfg; 4178 void __iomem *tx = qmp->dp_tx; 4179 void __iomem *tx2 = qmp->dp_tx2; 4180 4181 mutex_lock(&qmp->phy_mutex); 4182 4183 qmp_combo_dp_serdes_init(qmp); 4184 4185 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 4186 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 4187 4188 /* Configure special DP tx tunings */ 4189 cfg->configure_dp_tx(qmp); 4190 4191 /* Configure link rate, swing, etc. */ 4192 cfg->configure_dp_phy(qmp); 4193 4194 qmp->dp_powered_on = true; 4195 4196 mutex_unlock(&qmp->phy_mutex); 4197 4198 return 0; 4199 } 4200 4201 static int qmp_combo_dp_power_off(struct phy *phy) 4202 { 4203 struct qmp_combo *qmp = phy_get_drvdata(phy); 4204 4205 mutex_lock(&qmp->phy_mutex); 4206 4207 /* Assert DP PHY power down */ 4208 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 4209 4210 qmp->dp_powered_on = false; 4211 4212 mutex_unlock(&qmp->phy_mutex); 4213 4214 return 0; 4215 } 4216 4217 static int qmp_combo_usb_power_on(struct phy *phy) 4218 { 4219 struct qmp_combo *qmp = phy_get_drvdata(phy); 4220 const struct qmp_phy_cfg *cfg = qmp->cfg; 4221 void __iomem *serdes = qmp->serdes; 4222 void __iomem *tx = qmp->tx; 4223 void __iomem *rx = qmp->rx; 4224 void __iomem *tx2 = qmp->tx2; 4225 void __iomem *rx2 = qmp->rx2; 4226 void __iomem *pcs = qmp->pcs; 4227 void __iomem *pcs_usb = qmp->pcs_usb; 4228 void __iomem *status; 4229 unsigned int val; 4230 int ret; 4231 4232 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 4233 4234 /* Tx, Rx, and PCS configurations */ 4235 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 4236 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 4237 4238 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 4239 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 4240 4241 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 4242 qmp_configure(qmp->dev, qmp->pcs_misc, cfg->pcs_misc_tbl, cfg->pcs_misc_tbl_num); 4243 4244 4245 if (pcs_usb) 4246 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, 4247 cfg->pcs_usb_tbl_num); 4248 4249 if (cfg->has_pwrdn_delay) 4250 usleep_range(10, 20); 4251 4252 /* Pull PHY out of reset state */ 4253 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4254 4255 /* start SerDes and Phy-Coding-Sublayer */ 4256 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 4257 4258 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 4259 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 4260 PHY_INIT_COMPLETE_TIMEOUT); 4261 if (ret) { 4262 dev_err(qmp->dev, "phy initialization timed-out\n"); 4263 goto err_disable_pipe_clk; 4264 } 4265 4266 return 0; 4267 4268 err_disable_pipe_clk: 4269 clk_disable_unprepare(qmp->pipe_clk); 4270 4271 return ret; 4272 } 4273 4274 static int qmp_combo_usb_power_off(struct phy *phy) 4275 { 4276 struct qmp_combo *qmp = phy_get_drvdata(phy); 4277 const struct qmp_phy_cfg *cfg = qmp->cfg; 4278 4279 /* PHY reset */ 4280 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 4281 4282 /* stop SerDes and Phy-Coding-Sublayer */ 4283 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 4284 SERDES_START | PCS_START); 4285 4286 /* Put PHY into POWER DOWN state: active low */ 4287 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 4288 SW_PWRDN); 4289 4290 return 0; 4291 } 4292 4293 static int qmp_combo_usb_init(struct phy *phy) 4294 { 4295 struct qmp_combo *qmp = phy_get_drvdata(phy); 4296 int ret; 4297 4298 mutex_lock(&qmp->phy_mutex); 4299 ret = qmp_combo_com_init(qmp, false); 4300 if (ret) 4301 goto out_unlock; 4302 4303 ret = qmp_combo_usb_power_on(phy); 4304 if (ret) { 4305 qmp_combo_com_exit(qmp, false); 4306 goto out_unlock; 4307 } 4308 4309 qmp->usb_init_count++; 4310 4311 out_unlock: 4312 mutex_unlock(&qmp->phy_mutex); 4313 return ret; 4314 } 4315 4316 static int qmp_combo_usb_exit(struct phy *phy) 4317 { 4318 struct qmp_combo *qmp = phy_get_drvdata(phy); 4319 int ret; 4320 4321 mutex_lock(&qmp->phy_mutex); 4322 ret = qmp_combo_usb_power_off(phy); 4323 if (ret) 4324 goto out_unlock; 4325 4326 ret = qmp_combo_com_exit(qmp, false); 4327 if (ret) 4328 goto out_unlock; 4329 4330 qmp->usb_init_count--; 4331 4332 out_unlock: 4333 mutex_unlock(&qmp->phy_mutex); 4334 return ret; 4335 } 4336 4337 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 4338 { 4339 struct qmp_combo *qmp = phy_get_drvdata(phy); 4340 4341 qmp->phy_mode = mode; 4342 4343 return 0; 4344 } 4345 4346 static const struct phy_ops qmp_combo_usb_phy_ops = { 4347 .init = qmp_combo_usb_init, 4348 .exit = qmp_combo_usb_exit, 4349 .set_mode = qmp_combo_usb_set_mode, 4350 .owner = THIS_MODULE, 4351 }; 4352 4353 static const struct phy_ops qmp_combo_dp_phy_ops = { 4354 .init = qmp_combo_dp_init, 4355 .configure = qmp_combo_dp_configure, 4356 .power_on = qmp_combo_dp_power_on, 4357 .calibrate = qmp_combo_dp_calibrate, 4358 .power_off = qmp_combo_dp_power_off, 4359 .exit = qmp_combo_dp_exit, 4360 .owner = THIS_MODULE, 4361 }; 4362 4363 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 4364 { 4365 const struct qmp_phy_cfg *cfg = qmp->cfg; 4366 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 4367 void __iomem *pcs_misc = qmp->pcs_misc; 4368 void __iomem *pcs_aon = qmp->pcs_aon; 4369 u32 intr_mask; 4370 4371 if (qmp->phy_mode == PHY_MODE_USB_HOST_SS || 4372 qmp->phy_mode == PHY_MODE_USB_DEVICE_SS) 4373 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 4374 else 4375 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 4376 4377 /* Clear any pending interrupts status */ 4378 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4379 /* Writing 1 followed by 0 clears the interrupt */ 4380 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4381 4382 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 4383 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 4384 4385 /* Enable required PHY autonomous mode interrupts */ 4386 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 4387 4388 /* 4389 * Enable i/o clamp_n for autonomous mode 4390 * V6 and later versions use pcs aon clamp register 4391 */ 4392 if (pcs_aon) 4393 qphy_clrbits(pcs_aon, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4394 else if (pcs_misc) 4395 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4396 } 4397 4398 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 4399 { 4400 const struct qmp_phy_cfg *cfg = qmp->cfg; 4401 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 4402 void __iomem *pcs_misc = qmp->pcs_misc; 4403 void __iomem *pcs_aon = qmp->pcs_aon; 4404 4405 /* Disable i/o clamp_n on resume for normal mode */ 4406 if (pcs_aon) 4407 qphy_setbits(pcs_aon, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4408 else if (pcs_misc) 4409 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_CLAMP_ENABLE], CLAMP_EN); 4410 4411 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 4412 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 4413 4414 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4415 /* Writing 1 followed by 0 clears the interrupt */ 4416 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 4417 } 4418 4419 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 4420 { 4421 struct qmp_combo *qmp = dev_get_drvdata(dev); 4422 4423 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->phy_mode); 4424 4425 if (!qmp->init_count) { 4426 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 4427 return 0; 4428 } 4429 4430 qmp_combo_enable_autonomous_mode(qmp); 4431 4432 clk_disable_unprepare(qmp->pipe_clk); 4433 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 4434 4435 return 0; 4436 } 4437 4438 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 4439 { 4440 struct qmp_combo *qmp = dev_get_drvdata(dev); 4441 int ret = 0; 4442 4443 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->phy_mode); 4444 4445 if (!qmp->init_count) { 4446 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 4447 return 0; 4448 } 4449 4450 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 4451 if (ret) 4452 return ret; 4453 4454 ret = clk_prepare_enable(qmp->pipe_clk); 4455 if (ret) { 4456 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 4457 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 4458 return ret; 4459 } 4460 4461 qmp_combo_disable_autonomous_mode(qmp); 4462 4463 return 0; 4464 } 4465 4466 static const struct dev_pm_ops qmp_combo_pm_ops = { 4467 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 4468 qmp_combo_runtime_resume, NULL) 4469 }; 4470 4471 static int qmp_combo_reset_init(struct qmp_combo *qmp) 4472 { 4473 const struct qmp_phy_cfg *cfg = qmp->cfg; 4474 struct device *dev = qmp->dev; 4475 int i; 4476 int ret; 4477 4478 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 4479 sizeof(*qmp->resets), GFP_KERNEL); 4480 if (!qmp->resets) 4481 return -ENOMEM; 4482 4483 for (i = 0; i < cfg->num_resets; i++) 4484 qmp->resets[i].id = cfg->reset_list[i]; 4485 4486 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 4487 if (ret) 4488 return dev_err_probe(dev, ret, "failed to get resets\n"); 4489 4490 return 0; 4491 } 4492 4493 static int qmp_combo_clk_init(struct qmp_combo *qmp) 4494 { 4495 struct device *dev = qmp->dev; 4496 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 4497 int i; 4498 4499 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 4500 if (!qmp->clks) 4501 return -ENOMEM; 4502 4503 for (i = 0; i < num; i++) 4504 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 4505 4506 qmp->num_clks = num; 4507 4508 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 4509 } 4510 4511 static void phy_clk_release_provider(void *res) 4512 { 4513 of_clk_del_provider(res); 4514 } 4515 4516 /* 4517 * Register a fixed rate pipe clock. 4518 * 4519 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 4520 * controls it. The <s>_pipe_clk coming out of the GCC is requested 4521 * by the PHY driver for its operations. 4522 * We register the <s>_pipe_clksrc here. The gcc driver takes care 4523 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 4524 * Below picture shows this relationship. 4525 * 4526 * +---------------+ 4527 * | PHY block |<<---------------------------------------+ 4528 * | | | 4529 * | +-------+ | +-----+ | 4530 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 4531 * clk | +-------+ | +-----+ 4532 * +---------------+ 4533 */ 4534 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 4535 { 4536 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 4537 struct clk_init_data init = { }; 4538 char name[64]; 4539 4540 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 4541 init.name = name; 4542 init.ops = &clk_fixed_rate_ops; 4543 4544 /* controllers using QMP phys use 125MHz pipe clock interface */ 4545 fixed->fixed_rate = 125000000; 4546 fixed->hw.init = &init; 4547 4548 return devm_clk_hw_register(qmp->dev, &fixed->hw); 4549 } 4550 4551 /* 4552 * Display Port PLL driver block diagram for branch clocks 4553 * 4554 * +------------------------------+ 4555 * | DP_VCO_CLK | 4556 * | | 4557 * | +-------------------+ | 4558 * | | (DP PLL/VCO) | | 4559 * | +---------+---------+ | 4560 * | v | 4561 * | +----------+-----------+ | 4562 * | | hsclk_divsel_clk_src | | 4563 * | +----------+-----------+ | 4564 * +------------------------------+ 4565 * | 4566 * +---------<---------v------------>----------+ 4567 * | | 4568 * +--------v----------------+ | 4569 * | dp_phy_pll_link_clk | | 4570 * | link_clk | | 4571 * +--------+----------------+ | 4572 * | | 4573 * | | 4574 * v v 4575 * Input to DISPCC block | 4576 * for link clk, crypto clk | 4577 * and interface clock | 4578 * | 4579 * | 4580 * +--------<------------+-----------------+---<---+ 4581 * | | | 4582 * +----v---------+ +--------v-----+ +--------v------+ 4583 * | vco_divided | | vco_divided | | vco_divided | 4584 * | _clk_src | | _clk_src | | _clk_src | 4585 * | | | | | | 4586 * |divsel_six | | divsel_two | | divsel_four | 4587 * +-------+------+ +-----+--------+ +--------+------+ 4588 * | | | 4589 * v---->----------v-------------<------v 4590 * | 4591 * +----------+-----------------+ 4592 * | dp_phy_pll_vco_div_clk | 4593 * +---------+------------------+ 4594 * | 4595 * v 4596 * Input to DISPCC block 4597 * for DP pixel clock 4598 * 4599 */ 4600 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 4601 { 4602 switch (req->rate) { 4603 case 1620000000UL / 2: 4604 case 2700000000UL / 2: 4605 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 4606 return 0; 4607 default: 4608 return -EINVAL; 4609 } 4610 } 4611 4612 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 4613 { 4614 const struct qmp_combo *qmp; 4615 const struct phy_configure_opts_dp *dp_opts; 4616 4617 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 4618 dp_opts = &qmp->dp_opts; 4619 4620 switch (dp_opts->link_rate) { 4621 case 1620: 4622 return 1620000000UL / 2; 4623 case 2700: 4624 return 2700000000UL / 2; 4625 case 5400: 4626 return 5400000000UL / 4; 4627 case 8100: 4628 return 8100000000UL / 6; 4629 default: 4630 return 0; 4631 } 4632 } 4633 4634 static const struct clk_ops qmp_dp_pixel_clk_ops = { 4635 .determine_rate = qmp_dp_pixel_clk_determine_rate, 4636 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 4637 }; 4638 4639 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 4640 { 4641 switch (req->rate) { 4642 case 162000000: 4643 case 270000000: 4644 case 540000000: 4645 case 810000000: 4646 return 0; 4647 default: 4648 return -EINVAL; 4649 } 4650 } 4651 4652 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 4653 { 4654 const struct qmp_combo *qmp; 4655 const struct phy_configure_opts_dp *dp_opts; 4656 4657 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 4658 dp_opts = &qmp->dp_opts; 4659 4660 switch (dp_opts->link_rate) { 4661 case 1620: 4662 case 2700: 4663 case 5400: 4664 case 8100: 4665 return dp_opts->link_rate * 100000; 4666 default: 4667 return 0; 4668 } 4669 } 4670 4671 static const struct clk_ops qmp_dp_link_clk_ops = { 4672 .determine_rate = qmp_dp_link_clk_determine_rate, 4673 .recalc_rate = qmp_dp_link_clk_recalc_rate, 4674 }; 4675 4676 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 4677 { 4678 struct qmp_combo *qmp = data; 4679 unsigned int idx = clkspec->args[0]; 4680 4681 if (idx >= 2) { 4682 pr_err("%s: invalid index %u\n", __func__, idx); 4683 return ERR_PTR(-EINVAL); 4684 } 4685 4686 if (idx == 0) 4687 return &qmp->dp_link_hw; 4688 4689 return &qmp->dp_pixel_hw; 4690 } 4691 4692 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 4693 { 4694 struct clk_init_data init = { }; 4695 char name[64]; 4696 int ret; 4697 4698 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 4699 init.ops = &qmp_dp_link_clk_ops; 4700 init.name = name; 4701 qmp->dp_link_hw.init = &init; 4702 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 4703 if (ret) 4704 return ret; 4705 4706 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 4707 init.ops = &qmp_dp_pixel_clk_ops; 4708 init.name = name; 4709 qmp->dp_pixel_hw.init = &init; 4710 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 4711 if (ret) 4712 return ret; 4713 4714 return 0; 4715 } 4716 4717 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 4718 { 4719 struct qmp_combo *qmp = data; 4720 4721 switch (clkspec->args[0]) { 4722 case QMP_USB43DP_USB3_PIPE_CLK: 4723 return &qmp->pipe_clk_fixed.hw; 4724 case QMP_USB43DP_DP_LINK_CLK: 4725 return &qmp->dp_link_hw; 4726 case QMP_USB43DP_DP_VCO_DIV_CLK: 4727 return &qmp->dp_pixel_hw; 4728 } 4729 4730 return ERR_PTR(-EINVAL); 4731 } 4732 4733 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 4734 struct device_node *dp_np) 4735 { 4736 int ret; 4737 4738 ret = phy_pipe_clk_register(qmp, usb_np); 4739 if (ret) 4740 return ret; 4741 4742 ret = phy_dp_clks_register(qmp, dp_np); 4743 if (ret) 4744 return ret; 4745 4746 /* 4747 * Register a single provider for bindings without child nodes. 4748 */ 4749 if (usb_np == qmp->dev->of_node) 4750 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 4751 4752 /* 4753 * Register multiple providers for legacy bindings with child nodes. 4754 */ 4755 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 4756 &qmp->pipe_clk_fixed.hw); 4757 if (ret) 4758 return ret; 4759 4760 /* 4761 * Roll a devm action because the clock provider is the child node, but 4762 * the child node is not actually a device. 4763 */ 4764 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 4765 if (ret) 4766 return ret; 4767 4768 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 4769 if (ret) 4770 return ret; 4771 4772 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 4773 } 4774 4775 #if IS_ENABLED(CONFIG_TYPEC) 4776 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 4777 enum typec_orientation orientation) 4778 { 4779 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 4780 const struct qmp_phy_cfg *cfg = qmp->cfg; 4781 4782 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 4783 return 0; 4784 4785 mutex_lock(&qmp->phy_mutex); 4786 qmp->orientation = orientation; 4787 4788 if (qmp->init_count) { 4789 if (qmp->usb_init_count) 4790 qmp_combo_usb_power_off(qmp->usb_phy); 4791 qmp_combo_com_exit(qmp, true); 4792 4793 qmp_combo_com_init(qmp, true); 4794 if (qmp->usb_init_count) 4795 qmp_combo_usb_power_on(qmp->usb_phy); 4796 if (qmp->dp_init_count) 4797 cfg->dp_aux_init(qmp); 4798 } 4799 mutex_unlock(&qmp->phy_mutex); 4800 4801 return 0; 4802 } 4803 4804 static int qmp_combo_typec_mux_set(struct typec_mux_dev *mux, struct typec_mux_state *state) 4805 { 4806 struct qmp_combo *qmp = typec_mux_get_drvdata(mux); 4807 const struct qmp_phy_cfg *cfg = qmp->cfg; 4808 enum qmpphy_mode new_mode; 4809 unsigned int svid; 4810 4811 guard(mutex)(&qmp->phy_mutex); 4812 4813 if (state->alt) 4814 svid = state->alt->svid; 4815 else 4816 svid = 0; 4817 4818 if (svid == USB_TYPEC_DP_SID) { 4819 switch (state->mode) { 4820 /* DP Only */ 4821 case TYPEC_DP_STATE_C: 4822 case TYPEC_DP_STATE_E: 4823 new_mode = QMPPHY_MODE_DP_ONLY; 4824 break; 4825 4826 /* DP + USB */ 4827 case TYPEC_DP_STATE_D: 4828 case TYPEC_DP_STATE_F: 4829 4830 /* Safe fallback...*/ 4831 default: 4832 new_mode = QMPPHY_MODE_USB3DP; 4833 break; 4834 } 4835 } else { 4836 /* No DP SVID => don't care, assume it's just USB3 */ 4837 new_mode = QMPPHY_MODE_USB3_ONLY; 4838 } 4839 4840 if (new_mode == qmp->qmpphy_mode) { 4841 dev_dbg(qmp->dev, "typec_mux_set: same qmpphy mode, bail out\n"); 4842 return 0; 4843 } 4844 4845 if (qmp->qmpphy_mode != QMPPHY_MODE_USB3_ONLY && qmp->dp_powered_on) { 4846 dev_dbg(qmp->dev, "typec_mux_set: DP PHY is still in use, delaying switch\n"); 4847 return 0; 4848 } 4849 4850 dev_dbg(qmp->dev, "typec_mux_set: switching from qmpphy mode %d to %d\n", 4851 qmp->qmpphy_mode, new_mode); 4852 4853 qmp->qmpphy_mode = new_mode; 4854 4855 if (qmp->init_count) { 4856 if (qmp->usb_init_count) 4857 qmp_combo_usb_power_off(qmp->usb_phy); 4858 4859 if (qmp->dp_init_count) 4860 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 4861 4862 qmp_combo_com_exit(qmp, true); 4863 4864 /* Now everything's powered down, power up the right PHYs */ 4865 qmp_combo_com_init(qmp, true); 4866 4867 if (new_mode == QMPPHY_MODE_DP_ONLY) { 4868 if (qmp->usb_init_count) 4869 qmp->usb_init_count--; 4870 } 4871 4872 if (new_mode == QMPPHY_MODE_USB3DP || new_mode == QMPPHY_MODE_USB3_ONLY) { 4873 qmp_combo_usb_power_on(qmp->usb_phy); 4874 if (!qmp->usb_init_count) 4875 qmp->usb_init_count++; 4876 } 4877 4878 if (new_mode == QMPPHY_MODE_DP_ONLY || new_mode == QMPPHY_MODE_USB3DP) { 4879 if (qmp->dp_init_count) 4880 cfg->dp_aux_init(qmp); 4881 } 4882 } 4883 4884 return 0; 4885 } 4886 4887 static void qmp_combo_typec_switch_unregister(void *data) 4888 { 4889 struct qmp_combo *qmp = data; 4890 4891 typec_switch_unregister(qmp->sw); 4892 } 4893 4894 static void qmp_combo_typec_mux_unregister(void *data) 4895 { 4896 struct qmp_combo *qmp = data; 4897 4898 typec_mux_unregister(qmp->mux); 4899 } 4900 4901 static int qmp_combo_typec_register(struct qmp_combo *qmp) 4902 { 4903 struct typec_switch_desc sw_desc = {}; 4904 struct typec_mux_desc mux_desc = { }; 4905 struct device *dev = qmp->dev; 4906 int ret; 4907 4908 sw_desc.drvdata = qmp; 4909 sw_desc.fwnode = dev->fwnode; 4910 sw_desc.set = qmp_combo_typec_switch_set; 4911 qmp->sw = typec_switch_register(dev, &sw_desc); 4912 if (IS_ERR(qmp->sw)) { 4913 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 4914 return PTR_ERR(qmp->sw); 4915 } 4916 4917 ret = devm_add_action_or_reset(dev, qmp_combo_typec_switch_unregister, qmp); 4918 if (ret) 4919 return ret; 4920 4921 mux_desc.drvdata = qmp; 4922 mux_desc.fwnode = dev->fwnode; 4923 mux_desc.set = qmp_combo_typec_mux_set; 4924 qmp->mux = typec_mux_register(dev, &mux_desc); 4925 if (IS_ERR(qmp->mux)) { 4926 dev_err(dev, "Unable to register typec mux: %pe\n", qmp->mux); 4927 return PTR_ERR(qmp->mux); 4928 } 4929 4930 return devm_add_action_or_reset(dev, qmp_combo_typec_mux_unregister, qmp); 4931 } 4932 #else 4933 static int qmp_combo_typec_register(struct qmp_combo *qmp) 4934 { 4935 return 0; 4936 } 4937 #endif 4938 4939 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np) 4940 { 4941 struct device *dev = qmp->dev; 4942 4943 /* 4944 * Get memory resources from the DP child node: 4945 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 4946 * tx2 -> 3; rx2 -> 4 4947 * 4948 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 4949 * implementation. 4950 */ 4951 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 4952 if (IS_ERR(qmp->dp_tx)) 4953 return PTR_ERR(qmp->dp_tx); 4954 4955 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 4956 if (IS_ERR(qmp->dp_dp_phy)) 4957 return PTR_ERR(qmp->dp_dp_phy); 4958 4959 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 4960 if (IS_ERR(qmp->dp_tx2)) 4961 return PTR_ERR(qmp->dp_tx2); 4962 4963 return 0; 4964 } 4965 4966 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np) 4967 { 4968 const struct qmp_phy_cfg *cfg = qmp->cfg; 4969 struct device *dev = qmp->dev; 4970 4971 /* 4972 * Get memory resources from the USB child node: 4973 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 4974 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 4975 */ 4976 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 4977 if (IS_ERR(qmp->tx)) 4978 return PTR_ERR(qmp->tx); 4979 4980 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 4981 if (IS_ERR(qmp->rx)) 4982 return PTR_ERR(qmp->rx); 4983 4984 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 4985 if (IS_ERR(qmp->pcs)) 4986 return PTR_ERR(qmp->pcs); 4987 4988 if (cfg->pcs_usb_offset) 4989 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 4990 4991 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 4992 if (IS_ERR(qmp->tx2)) 4993 return PTR_ERR(qmp->tx2); 4994 4995 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 4996 if (IS_ERR(qmp->rx2)) 4997 return PTR_ERR(qmp->rx2); 4998 4999 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 5000 if (IS_ERR(qmp->pcs_misc)) { 5001 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 5002 qmp->pcs_misc = NULL; 5003 } 5004 5005 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 5006 if (IS_ERR(qmp->pipe_clk)) { 5007 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 5008 "failed to get pipe clock\n"); 5009 } 5010 5011 return 0; 5012 } 5013 5014 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 5015 struct device_node *dp_np) 5016 { 5017 struct platform_device *pdev = to_platform_device(qmp->dev); 5018 int ret; 5019 5020 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 5021 if (IS_ERR(qmp->serdes)) 5022 return PTR_ERR(qmp->serdes); 5023 5024 qmp->com = devm_platform_ioremap_resource(pdev, 1); 5025 if (IS_ERR(qmp->com)) 5026 return PTR_ERR(qmp->com); 5027 5028 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 5029 if (IS_ERR(qmp->dp_serdes)) 5030 return PTR_ERR(qmp->dp_serdes); 5031 5032 ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np); 5033 if (ret) 5034 return ret; 5035 5036 ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np); 5037 if (ret) 5038 return ret; 5039 5040 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 5041 if (ret < 0) 5042 return ret; 5043 5044 qmp->num_clks = ret; 5045 5046 return 0; 5047 } 5048 5049 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 5050 { 5051 struct platform_device *pdev = to_platform_device(qmp->dev); 5052 const struct qmp_phy_cfg *cfg = qmp->cfg; 5053 const struct qmp_combo_offsets *offs = cfg->offsets; 5054 struct device *dev = qmp->dev; 5055 void __iomem *base; 5056 int ret; 5057 5058 if (!offs) 5059 return -EINVAL; 5060 5061 base = devm_platform_ioremap_resource(pdev, 0); 5062 if (IS_ERR(base)) 5063 return PTR_ERR(base); 5064 5065 qmp->com = base + offs->com; 5066 qmp->tx = base + offs->txa; 5067 qmp->rx = base + offs->rxa; 5068 qmp->tx2 = base + offs->txb; 5069 qmp->rx2 = base + offs->rxb; 5070 5071 qmp->serdes = base + offs->usb3_serdes; 5072 qmp->pcs_misc = base + offs->usb3_pcs_misc; 5073 qmp->pcs = base + offs->usb3_pcs; 5074 if (offs->usb3_pcs_aon) 5075 qmp->pcs_aon = base + offs->usb3_pcs_aon; 5076 qmp->pcs_usb = base + offs->usb3_pcs_usb; 5077 5078 qmp->dp_serdes = base + offs->dp_serdes; 5079 if (offs->dp_txa) { 5080 qmp->dp_tx = base + offs->dp_txa; 5081 qmp->dp_tx2 = base + offs->dp_txb; 5082 } else { 5083 qmp->dp_tx = base + offs->txa; 5084 qmp->dp_tx2 = base + offs->txb; 5085 } 5086 qmp->dp_dp_phy = base + offs->dp_dp_phy; 5087 5088 if (offs->aon_toggle) 5089 qmp->aon_toggle = base + offs->aon_toggle; 5090 5091 ret = qmp_combo_clk_init(qmp); 5092 if (ret) 5093 return ret; 5094 5095 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 5096 if (IS_ERR(qmp->pipe_clk)) { 5097 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 5098 "failed to get usb3_pipe clock\n"); 5099 } 5100 5101 return 0; 5102 } 5103 5104 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 5105 { 5106 struct qmp_combo *qmp = dev_get_drvdata(dev); 5107 5108 if (args->args_count == 0) 5109 return ERR_PTR(-EINVAL); 5110 5111 switch (args->args[0]) { 5112 case QMP_USB43DP_USB3_PHY: 5113 return qmp->usb_phy; 5114 case QMP_USB43DP_DP_PHY: 5115 return qmp->dp_phy; 5116 } 5117 5118 return ERR_PTR(-EINVAL); 5119 } 5120 5121 static void qmp_combo_find_lanes_orientation(const struct qmp_combo_lane_mapping *mapping, 5122 unsigned int mapping_count, 5123 u32 *lanes, unsigned int lanes_count, 5124 enum typec_orientation *orientation) 5125 { 5126 int i; 5127 5128 for (i = 0; i < mapping_count; i++) { 5129 if (mapping[i].lanes_count != lanes_count) 5130 continue; 5131 if (!memcmp(mapping[i].lanes, lanes, sizeof(u32) * lanes_count)) { 5132 *orientation = mapping[i].orientation; 5133 return; 5134 } 5135 } 5136 } 5137 5138 static int qmp_combo_get_dt_lanes_mapping(struct device *dev, unsigned int endpoint, 5139 u32 *data_lanes, unsigned int max, 5140 unsigned int *count) 5141 { 5142 struct device_node *ep __free(device_node) = NULL; 5143 int ret; 5144 5145 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, endpoint); 5146 if (!ep) 5147 return -EINVAL; 5148 5149 ret = of_property_count_u32_elems(ep, "data-lanes"); 5150 if (ret < 0) 5151 return ret; 5152 5153 *count = ret; 5154 if (*count > max) 5155 return -EINVAL; 5156 5157 return of_property_read_u32_array(ep, "data-lanes", data_lanes, 5158 min_t(unsigned int, *count, max)); 5159 } 5160 5161 static int qmp_combo_get_dt_dp_orientation(struct device *dev, 5162 enum typec_orientation *orientation) 5163 { 5164 unsigned int count; 5165 u32 data_lanes[4]; 5166 int ret; 5167 5168 /* DP is described on the first endpoint of the first port */ 5169 ret = qmp_combo_get_dt_lanes_mapping(dev, 0, data_lanes, 4, &count); 5170 if (ret < 0) 5171 return ret == -EINVAL ? 0 : ret; 5172 5173 /* Search for a match and only update orientation if found */ 5174 qmp_combo_find_lanes_orientation(dp_data_lanes, ARRAY_SIZE(dp_data_lanes), 5175 data_lanes, count, orientation); 5176 5177 return 0; 5178 } 5179 5180 static int qmp_combo_get_dt_usb3_orientation(struct device *dev, 5181 enum typec_orientation *orientation) 5182 { 5183 unsigned int count; 5184 u32 data_lanes[2]; 5185 int ret; 5186 5187 /* USB3 is described on the second endpoint of the first port */ 5188 ret = qmp_combo_get_dt_lanes_mapping(dev, 1, data_lanes, 2, &count); 5189 if (ret < 0) 5190 return ret == -EINVAL ? 0 : ret; 5191 5192 /* Search for a match and only update orientation if found */ 5193 qmp_combo_find_lanes_orientation(usb3_data_lanes, ARRAY_SIZE(usb3_data_lanes), 5194 data_lanes, count, orientation); 5195 5196 return 0; 5197 } 5198 5199 static int qmp_combo_probe(struct platform_device *pdev) 5200 { 5201 struct qmp_combo *qmp; 5202 struct device *dev = &pdev->dev; 5203 struct device_node *dp_np, *usb_np; 5204 struct phy_provider *phy_provider; 5205 int ret; 5206 5207 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 5208 if (!qmp) 5209 return -ENOMEM; 5210 5211 qmp->dev = dev; 5212 dev_set_drvdata(dev, qmp); 5213 5214 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 5215 5216 qmp->cfg = of_device_get_match_data(dev); 5217 if (!qmp->cfg) 5218 return -EINVAL; 5219 5220 mutex_init(&qmp->phy_mutex); 5221 5222 ret = qmp_combo_reset_init(qmp); 5223 if (ret) 5224 return ret; 5225 5226 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 5227 qmp->cfg->vreg_list, &qmp->vregs); 5228 if (ret) 5229 return ret; 5230 5231 /* Check for legacy binding with child nodes. */ 5232 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 5233 if (usb_np) { 5234 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 5235 if (!dp_np) { 5236 of_node_put(usb_np); 5237 return -EINVAL; 5238 } 5239 5240 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 5241 } else { 5242 usb_np = of_node_get(dev->of_node); 5243 dp_np = of_node_get(dev->of_node); 5244 5245 ret = qmp_combo_parse_dt(qmp); 5246 } 5247 if (ret) 5248 goto err_node_put; 5249 5250 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 5251 5252 if (of_property_present(dev->of_node, "mode-switch") || 5253 of_property_present(dev->of_node, "orientation-switch")) { 5254 ret = qmp_combo_typec_register(qmp); 5255 if (ret) 5256 goto err_node_put; 5257 } else { 5258 enum typec_orientation dp_orientation = TYPEC_ORIENTATION_NONE; 5259 enum typec_orientation usb3_orientation = TYPEC_ORIENTATION_NONE; 5260 5261 ret = qmp_combo_get_dt_dp_orientation(dev, &dp_orientation); 5262 if (ret) 5263 goto err_node_put; 5264 5265 ret = qmp_combo_get_dt_usb3_orientation(dev, &usb3_orientation); 5266 if (ret) 5267 goto err_node_put; 5268 5269 if (dp_orientation == TYPEC_ORIENTATION_NONE && 5270 usb3_orientation != TYPEC_ORIENTATION_NONE) { 5271 qmp->qmpphy_mode = QMPPHY_MODE_USB3_ONLY; 5272 qmp->orientation = usb3_orientation; 5273 } else if (usb3_orientation == TYPEC_ORIENTATION_NONE && 5274 dp_orientation != TYPEC_ORIENTATION_NONE) { 5275 qmp->qmpphy_mode = QMPPHY_MODE_DP_ONLY; 5276 qmp->orientation = dp_orientation; 5277 } else if (dp_orientation != TYPEC_ORIENTATION_NONE && 5278 dp_orientation == usb3_orientation) { 5279 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP; 5280 qmp->orientation = dp_orientation; 5281 } else { 5282 dev_warn(dev, "unable to determine orientation & mode from data-lanes"); 5283 } 5284 } 5285 5286 ret = drm_aux_bridge_register(dev); 5287 if (ret) 5288 goto err_node_put; 5289 5290 /* 5291 * Enable runtime PM before creating the PHYs, phy_create() only enables 5292 * it on the PHY devices if already enabled on the parent. Hold a usage 5293 * reference so callbacks cannot run until the PHY is ready. 5294 */ 5295 pm_runtime_get_noresume(dev); 5296 pm_runtime_set_active(dev); 5297 ret = devm_pm_runtime_enable(dev); 5298 if (ret) 5299 goto err_pm_put; 5300 /* 5301 * Prevent runtime pm from being ON by default. Users can enable 5302 * it using power/control in sysfs. 5303 */ 5304 pm_runtime_forbid(dev); 5305 5306 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 5307 if (ret) 5308 goto err_pm_put; 5309 5310 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 5311 if (IS_ERR(qmp->usb_phy)) { 5312 ret = PTR_ERR(qmp->usb_phy); 5313 dev_err(dev, "failed to create USB PHY: %d\n", ret); 5314 goto err_pm_put; 5315 } 5316 5317 phy_set_drvdata(qmp->usb_phy, qmp); 5318 5319 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 5320 if (IS_ERR(qmp->dp_phy)) { 5321 ret = PTR_ERR(qmp->dp_phy); 5322 dev_err(dev, "failed to create DP PHY: %d\n", ret); 5323 goto err_pm_put; 5324 } 5325 5326 phy_set_drvdata(qmp->dp_phy, qmp); 5327 5328 if (usb_np == dev->of_node) 5329 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 5330 else 5331 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 5332 5333 if (IS_ERR(phy_provider)) { 5334 ret = PTR_ERR(phy_provider); 5335 goto err_pm_put; 5336 } 5337 5338 of_node_put(usb_np); 5339 of_node_put(dp_np); 5340 5341 pm_runtime_put(dev); 5342 5343 return 0; 5344 5345 err_pm_put: 5346 pm_runtime_put_noidle(dev); 5347 err_node_put: 5348 of_node_put(usb_np); 5349 of_node_put(dp_np); 5350 return ret; 5351 } 5352 5353 static const struct of_device_id qmp_combo_of_match_table[] = { 5354 { 5355 .compatible = "qcom,glymur-qmp-usb3-dp-phy", 5356 .data = &glymur_usb3dpphy_cfg, 5357 }, 5358 { 5359 .compatible = "qcom,hawi-qmp-usb3-dp-phy", 5360 .data = &hawi_usb3dpphy_cfg, 5361 }, 5362 { 5363 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy", 5364 .data = &sar2130p_usb3dpphy_cfg, 5365 }, 5366 { 5367 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 5368 .data = &sc7180_usb3dpphy_cfg, 5369 }, 5370 { 5371 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 5372 .data = &sm8250_usb3dpphy_cfg, 5373 }, 5374 { 5375 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 5376 .data = &sc8180x_usb3dpphy_cfg, 5377 }, 5378 { 5379 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 5380 .data = &sc8280xp_usb43dpphy_cfg, 5381 }, 5382 { 5383 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 5384 .data = &sdm845_usb3dpphy_cfg, 5385 }, 5386 { 5387 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 5388 .data = &sm6350_usb3dpphy_cfg, 5389 }, 5390 { 5391 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 5392 .data = &sc8180x_usb3dpphy_cfg, 5393 }, 5394 { 5395 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 5396 .data = &sm8250_usb3dpphy_cfg, 5397 }, 5398 { 5399 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 5400 .data = &sm8350_usb3dpphy_cfg, 5401 }, 5402 { 5403 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 5404 .data = &sm8350_usb3dpphy_cfg, 5405 }, 5406 { 5407 .compatible = "qcom,sm8475-qmp-usb3-dp-phy", 5408 .data = &sm8475_usb3dpphy_cfg, 5409 }, 5410 { 5411 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 5412 .data = &sm8550_usb3dpphy_cfg, 5413 }, 5414 { 5415 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 5416 .data = &sm8650_usb3dpphy_cfg, 5417 }, 5418 { 5419 .compatible = "qcom,sm8750-qmp-usb3-dp-phy", 5420 .data = &sm8750_usb3dpphy_cfg, 5421 }, 5422 { 5423 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 5424 .data = &x1e80100_usb3dpphy_cfg, 5425 }, 5426 { } 5427 }; 5428 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 5429 5430 static struct platform_driver qmp_combo_driver = { 5431 .probe = qmp_combo_probe, 5432 .driver = { 5433 .name = "qcom-qmp-combo-phy", 5434 .pm = &qmp_combo_pm_ops, 5435 .of_match_table = qmp_combo_of_match_table, 5436 }, 5437 }; 5438 5439 module_platform_driver(qmp_combo_driver); 5440 5441 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 5442 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 5443 MODULE_LICENSE("GPL v2"); 5444