1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/bridge/aux-bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp.h" 29 #include "phy-qcom-qmp-pcs-misc-v3.h" 30 #include "phy-qcom-qmp-pcs-usb-v4.h" 31 #include "phy-qcom-qmp-pcs-usb-v5.h" 32 #include "phy-qcom-qmp-pcs-usb-v6.h" 33 34 /* QPHY_SW_RESET bit */ 35 #define SW_RESET BIT(0) 36 /* QPHY_POWER_DOWN_CONTROL */ 37 #define SW_PWRDN BIT(0) 38 /* QPHY_START_CONTROL bits */ 39 #define SERDES_START BIT(0) 40 #define PCS_START BIT(1) 41 /* QPHY_PCS_STATUS bit */ 42 #define PHYSTATUS BIT(6) 43 44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45 /* DP PHY soft reset */ 46 #define SW_DPPHY_RESET BIT(0) 47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_DPPHY_RESET_MUX BIT(1) 49 /* USB3 PHY soft reset */ 50 #define SW_USB3PHY_RESET BIT(2) 51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52 #define SW_USB3PHY_RESET_MUX BIT(3) 53 54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55 #define USB3_MODE BIT(0) /* enables USB3 mode */ 56 #define DP_MODE BIT(1) /* enables DP mode */ 57 58 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 59 #define ARCVR_DTCT_EN BIT(0) 60 #define ALFPS_DTCT_EN BIT(1) 61 #define ARCVR_DTCT_EVENT_SEL BIT(4) 62 63 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 64 #define IRQ_CLEAR BIT(0) 65 66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 70 #define SW_PORTSELECT_VAL BIT(0) 71 #define SW_PORTSELECT_MUX BIT(1) 72 73 #define PHY_INIT_COMPLETE_TIMEOUT 10000 74 75 struct qmp_phy_init_tbl { 76 unsigned int offset; 77 unsigned int val; 78 /* 79 * mask of lanes for which this register is written 80 * for cases when second lane needs different values 81 */ 82 u8 lane_mask; 83 }; 84 85 #define QMP_PHY_INIT_CFG(o, v) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 .lane_mask = 0xff, \ 90 } 91 92 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 93 { \ 94 .offset = o, \ 95 .val = v, \ 96 .lane_mask = l, \ 97 } 98 99 /* set of registers with offsets different per-PHY */ 100 enum qphy_reg_layout { 101 /* PCS registers */ 102 QPHY_SW_RESET, 103 QPHY_START_CTRL, 104 QPHY_PCS_STATUS, 105 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 106 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 107 QPHY_PCS_POWER_DOWN_CONTROL, 108 109 QPHY_COM_RESETSM_CNTRL, 110 QPHY_COM_C_READY_STATUS, 111 QPHY_COM_CMN_STATUS, 112 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 113 114 QPHY_DP_PHY_STATUS, 115 116 QPHY_TX_TX_POL_INV, 117 QPHY_TX_TX_DRV_LVL, 118 QPHY_TX_TX_EMP_POST1_LVL, 119 QPHY_TX_HIGHZ_DRVR_EN, 120 QPHY_TX_TRANSCEIVER_BIAS_EN, 121 122 /* Keep last to ensure regs_layout arrays are properly initialized */ 123 QPHY_LAYOUT_SIZE 124 }; 125 126 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 127 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 128 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 129 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 130 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 131 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 132 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 133 134 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 135 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 136 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 137 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 138 139 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 140 141 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 142 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 143 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 144 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 145 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 146 }; 147 148 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 149 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 150 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 151 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 152 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 153 154 /* In PCS_USB */ 155 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 156 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 157 158 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 159 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 160 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 161 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 162 163 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 164 165 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 166 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 167 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 168 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 169 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 170 }; 171 172 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 173 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 174 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 175 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 176 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 177 178 /* In PCS_USB */ 179 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 180 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 181 182 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 183 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 184 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 185 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 186 187 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 188 189 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 190 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 191 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 192 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 193 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 194 }; 195 196 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 197 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 198 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 199 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 200 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 201 202 /* In PCS_USB */ 203 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 204 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 205 206 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 207 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 208 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 209 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 210 211 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 212 213 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 214 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 215 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 216 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 217 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 218 }; 219 220 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 257 }; 258 259 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 265 }; 266 267 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 289 }; 290 291 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 299 }; 300 301 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 309 }; 310 311 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 319 }; 320 321 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 329 }; 330 331 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 333 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 342 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 343 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 344 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 345 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 346 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 347 }; 348 349 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 354 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 359 }; 360 361 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 362 /* FLL settings */ 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 368 369 /* Lock Det settings */ 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 374 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 394 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 406 }; 407 408 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 419 }; 420 421 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 422 /* FLL settings */ 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 428 429 /* Lock Det settings */ 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 434 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 454 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 467 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 470 }; 471 472 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 513 }; 514 515 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 516 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 517 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 518 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 521 }; 522 523 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 560 }; 561 562 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 563 /* Lock Det settings */ 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 567 568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 576 }; 577 578 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 579 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 580 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 581 }; 582 583 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 584 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 585 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 590 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 591 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 592 }; 593 594 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 615 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 616 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 617 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 618 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 633 }; 634 635 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 648 }; 649 650 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 653 }; 654 655 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 656 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 658 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 659 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 660 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 661 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 662 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 663 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 664 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 665 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 666 }; 667 668 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 686 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 687 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 688 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 689 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 690 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 691 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 692 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 693 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 694 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 695 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 696 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 697 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 698 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 699 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 700 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 701 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 702 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 707 }; 708 709 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 724 }; 725 726 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 731 }; 732 733 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 782 }; 783 784 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 785 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 786 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 787 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 788 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 789 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 790 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 791 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 792 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 793 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 794 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 795 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 796 }; 797 798 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 803 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 804 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 805 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 806 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 807 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 808 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 833 834 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 835 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 836 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 837 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 838 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 839 840 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 841 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 842 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 843 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 844 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 845 }; 846 847 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 848 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 849 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 850 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 851 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 852 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 853 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 854 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 858 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 859 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 860 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 861 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 862 }; 863 864 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 865 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 866 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 867 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 868 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 869 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 870 }; 871 872 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 893 }; 894 895 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 903 }; 904 905 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 908 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 909 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 910 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 913 }; 914 915 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 916 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 917 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 918 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 923 }; 924 925 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 933 }; 934 935 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 936 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 937 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 938 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 939 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 940 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 941 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 942 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 943 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 944 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 945 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 946 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 947 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 948 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 949 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 950 }; 951 952 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 976 }; 977 978 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 979 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 980 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 981 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 982 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 983 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 984 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 985 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 986 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 987 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 988 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 990 }; 991 992 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 993 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 994 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 995 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 996 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 997 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 998 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 999 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1000 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1001 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1002 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1003 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1004 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1005 }; 1006 1007 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1008 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1009 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1014 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1028 }; 1029 1030 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1031 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1036 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1037 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1038 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1039 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1042 }; 1043 1044 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1054 }; 1055 1056 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1060 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1061 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1062 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1063 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1064 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1065 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1066 }; 1067 1068 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1071 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1073 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1074 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1075 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1076 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1078 }; 1079 1080 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1090 }; 1091 1092 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1140 }; 1141 1142 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1148 }; 1149 1150 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1185 }; 1186 1187 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1188 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1189 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1190 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1191 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1192 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1193 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1194 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1195 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1196 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1197 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1198 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1199 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1200 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1201 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1202 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1203 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1204 }; 1205 1206 /* list of regulators */ 1207 struct qmp_regulator_data { 1208 const char *name; 1209 unsigned int enable_load; 1210 }; 1211 1212 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1213 { .name = "vdda-phy", .enable_load = 21800 }, 1214 { .name = "vdda-pll", .enable_load = 36000 }, 1215 }; 1216 1217 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1218 { 0x00, 0x0c, 0x15, 0x1a }, 1219 { 0x02, 0x0e, 0x16, 0xff }, 1220 { 0x02, 0x11, 0xff, 0xff }, 1221 { 0x04, 0xff, 0xff, 0xff } 1222 }; 1223 1224 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1225 { 0x02, 0x12, 0x16, 0x1a }, 1226 { 0x09, 0x19, 0x1f, 0xff }, 1227 { 0x10, 0x1f, 0xff, 0xff }, 1228 { 0x1f, 0xff, 0xff, 0xff } 1229 }; 1230 1231 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1232 { 0x00, 0x0c, 0x14, 0x19 }, 1233 { 0x00, 0x0b, 0x12, 0xff }, 1234 { 0x00, 0x0b, 0xff, 0xff }, 1235 { 0x04, 0xff, 0xff, 0xff } 1236 }; 1237 1238 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1239 { 0x08, 0x0f, 0x16, 0x1f }, 1240 { 0x11, 0x1e, 0x1f, 0xff }, 1241 { 0x19, 0x1f, 0xff, 0xff }, 1242 { 0x1f, 0xff, 0xff, 0xff } 1243 }; 1244 1245 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1246 { 0x00, 0x0c, 0x15, 0x1b }, 1247 { 0x02, 0x0e, 0x16, 0xff }, 1248 { 0x02, 0x11, 0xff, 0xff }, 1249 { 0x04, 0xff, 0xff, 0xff } 1250 }; 1251 1252 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1253 { 0x00, 0x0d, 0x14, 0x1a }, 1254 { 0x00, 0x0e, 0x15, 0xff }, 1255 { 0x00, 0x0d, 0xff, 0xff }, 1256 { 0x03, 0xff, 0xff, 0xff } 1257 }; 1258 1259 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1260 { 0x08, 0x0f, 0x16, 0x1f }, 1261 { 0x11, 0x1e, 0x1f, 0xff }, 1262 { 0x16, 0x1f, 0xff, 0xff }, 1263 { 0x1f, 0xff, 0xff, 0xff } 1264 }; 1265 1266 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1267 { 0x20, 0x2c, 0x35, 0x3b }, 1268 { 0x22, 0x2e, 0x36, 0xff }, 1269 { 0x22, 0x31, 0xff, 0xff }, 1270 { 0x24, 0xff, 0xff, 0xff } 1271 }; 1272 1273 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1274 { 0x22, 0x32, 0x36, 0x3a }, 1275 { 0x29, 0x39, 0x3f, 0xff }, 1276 { 0x30, 0x3f, 0xff, 0xff }, 1277 { 0x3f, 0xff, 0xff, 0xff } 1278 }; 1279 1280 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1281 { 0x20, 0x2d, 0x34, 0x3a }, 1282 { 0x20, 0x2e, 0x35, 0xff }, 1283 { 0x20, 0x2e, 0xff, 0xff }, 1284 { 0x24, 0xff, 0xff, 0xff } 1285 }; 1286 1287 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1288 { 0x28, 0x2f, 0x36, 0x3f }, 1289 { 0x31, 0x3e, 0x3f, 0xff }, 1290 { 0x36, 0x3f, 0xff, 0xff }, 1291 { 0x3f, 0xff, 0xff, 0xff } 1292 }; 1293 1294 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1295 { 0x20, 0x2d, 0x34, 0x3a }, 1296 { 0x20, 0x2e, 0x35, 0xff }, 1297 { 0x20, 0x2e, 0xff, 0xff }, 1298 { 0x22, 0xff, 0xff, 0xff } 1299 }; 1300 1301 struct qmp_combo; 1302 1303 struct qmp_combo_offsets { 1304 u16 com; 1305 u16 txa; 1306 u16 rxa; 1307 u16 txb; 1308 u16 rxb; 1309 u16 usb3_serdes; 1310 u16 usb3_pcs_misc; 1311 u16 usb3_pcs; 1312 u16 usb3_pcs_usb; 1313 u16 dp_serdes; 1314 u16 dp_txa; 1315 u16 dp_txb; 1316 u16 dp_dp_phy; 1317 }; 1318 1319 struct qmp_phy_cfg { 1320 const struct qmp_combo_offsets *offsets; 1321 1322 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1323 const struct qmp_phy_init_tbl *serdes_tbl; 1324 int serdes_tbl_num; 1325 const struct qmp_phy_init_tbl *tx_tbl; 1326 int tx_tbl_num; 1327 const struct qmp_phy_init_tbl *rx_tbl; 1328 int rx_tbl_num; 1329 const struct qmp_phy_init_tbl *pcs_tbl; 1330 int pcs_tbl_num; 1331 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1332 int pcs_usb_tbl_num; 1333 1334 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1335 int dp_serdes_tbl_num; 1336 const struct qmp_phy_init_tbl *dp_tx_tbl; 1337 int dp_tx_tbl_num; 1338 1339 /* Init sequence for DP PHY block link rates */ 1340 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1341 int serdes_tbl_rbr_num; 1342 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1343 int serdes_tbl_hbr_num; 1344 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1345 int serdes_tbl_hbr2_num; 1346 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1347 int serdes_tbl_hbr3_num; 1348 1349 /* DP PHY swing and pre_emphasis tables */ 1350 const u8 (*swing_hbr_rbr)[4][4]; 1351 const u8 (*swing_hbr3_hbr2)[4][4]; 1352 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1353 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1354 1355 /* DP PHY callbacks */ 1356 int (*configure_dp_phy)(struct qmp_combo *qmp); 1357 void (*configure_dp_tx)(struct qmp_combo *qmp); 1358 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1359 void (*dp_aux_init)(struct qmp_combo *qmp); 1360 1361 /* resets to be requested */ 1362 const char * const *reset_list; 1363 int num_resets; 1364 /* regulators to be requested */ 1365 const struct qmp_regulator_data *vreg_list; 1366 int num_vregs; 1367 1368 /* array of registers with different offsets */ 1369 const unsigned int *regs; 1370 1371 /* true, if PHY needs delay after POWER_DOWN */ 1372 bool has_pwrdn_delay; 1373 1374 /* Offset from PCS to PCS_USB region */ 1375 unsigned int pcs_usb_offset; 1376 1377 }; 1378 1379 struct qmp_combo { 1380 struct device *dev; 1381 1382 const struct qmp_phy_cfg *cfg; 1383 1384 void __iomem *com; 1385 1386 void __iomem *serdes; 1387 void __iomem *tx; 1388 void __iomem *rx; 1389 void __iomem *pcs; 1390 void __iomem *tx2; 1391 void __iomem *rx2; 1392 void __iomem *pcs_misc; 1393 void __iomem *pcs_usb; 1394 1395 void __iomem *dp_serdes; 1396 void __iomem *dp_tx; 1397 void __iomem *dp_tx2; 1398 void __iomem *dp_dp_phy; 1399 1400 struct clk *pipe_clk; 1401 struct clk_bulk_data *clks; 1402 int num_clks; 1403 struct reset_control_bulk_data *resets; 1404 struct regulator_bulk_data *vregs; 1405 1406 struct mutex phy_mutex; 1407 int init_count; 1408 1409 struct phy *usb_phy; 1410 enum phy_mode mode; 1411 unsigned int usb_init_count; 1412 1413 struct phy *dp_phy; 1414 unsigned int dp_aux_cfg; 1415 struct phy_configure_opts_dp dp_opts; 1416 unsigned int dp_init_count; 1417 1418 struct clk_fixed_rate pipe_clk_fixed; 1419 struct clk_hw dp_link_hw; 1420 struct clk_hw dp_pixel_hw; 1421 1422 struct typec_switch_dev *sw; 1423 enum typec_orientation orientation; 1424 }; 1425 1426 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1427 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1428 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1429 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1430 1431 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1432 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1433 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1434 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1435 1436 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1437 { 1438 u32 reg; 1439 1440 reg = readl(base + offset); 1441 reg |= val; 1442 writel(reg, base + offset); 1443 1444 /* ensure that above write is through */ 1445 readl(base + offset); 1446 } 1447 1448 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1449 { 1450 u32 reg; 1451 1452 reg = readl(base + offset); 1453 reg &= ~val; 1454 writel(reg, base + offset); 1455 1456 /* ensure that above write is through */ 1457 readl(base + offset); 1458 } 1459 1460 /* list of clocks required by phy */ 1461 static const char * const qmp_combo_phy_clk_l[] = { 1462 "aux", "cfg_ahb", "ref", "com_aux", 1463 }; 1464 1465 /* list of resets */ 1466 static const char * const msm8996_usb3phy_reset_l[] = { 1467 "phy", "common", 1468 }; 1469 1470 static const char * const sc7180_usb3phy_reset_l[] = { 1471 "phy", 1472 }; 1473 1474 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1475 .com = 0x0000, 1476 .txa = 0x1200, 1477 .rxa = 0x1400, 1478 .txb = 0x1600, 1479 .rxb = 0x1800, 1480 .usb3_serdes = 0x1000, 1481 .usb3_pcs_misc = 0x1a00, 1482 .usb3_pcs = 0x1c00, 1483 .usb3_pcs_usb = 0x1f00, 1484 .dp_serdes = 0x2000, 1485 .dp_txa = 0x2200, 1486 .dp_txb = 0x2600, 1487 .dp_dp_phy = 0x2a00, 1488 }; 1489 1490 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1491 .com = 0x0000, 1492 .txa = 0x0400, 1493 .rxa = 0x0600, 1494 .txb = 0x0a00, 1495 .rxb = 0x0c00, 1496 .usb3_serdes = 0x1000, 1497 .usb3_pcs_misc = 0x1200, 1498 .usb3_pcs = 0x1400, 1499 .usb3_pcs_usb = 0x1700, 1500 .dp_serdes = 0x2000, 1501 .dp_dp_phy = 0x2200, 1502 }; 1503 1504 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1505 .offsets = &qmp_combo_offsets_v3, 1506 1507 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1508 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1509 .tx_tbl = qmp_v3_usb3_tx_tbl, 1510 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1511 .rx_tbl = qmp_v3_usb3_rx_tbl, 1512 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1513 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1514 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1515 1516 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1517 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1518 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1519 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1520 1521 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1522 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1523 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1524 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1525 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1526 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1527 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1528 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1529 1530 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1531 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1532 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1533 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1534 1535 .dp_aux_init = qmp_v3_dp_aux_init, 1536 .configure_dp_tx = qmp_v3_configure_dp_tx, 1537 .configure_dp_phy = qmp_v3_configure_dp_phy, 1538 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1539 1540 .reset_list = sc7180_usb3phy_reset_l, 1541 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1542 .vreg_list = qmp_phy_vreg_l, 1543 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1544 .regs = qmp_v3_usb3phy_regs_layout, 1545 1546 .has_pwrdn_delay = true, 1547 }; 1548 1549 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1550 .offsets = &qmp_combo_offsets_v3, 1551 1552 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1553 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1554 .tx_tbl = qmp_v3_usb3_tx_tbl, 1555 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1556 .rx_tbl = qmp_v3_usb3_rx_tbl, 1557 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1558 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1559 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1560 1561 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1562 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1563 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1564 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1565 1566 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1567 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1568 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1569 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1570 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1571 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1572 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1573 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1574 1575 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1576 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1577 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1578 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1579 1580 .dp_aux_init = qmp_v3_dp_aux_init, 1581 .configure_dp_tx = qmp_v3_configure_dp_tx, 1582 .configure_dp_phy = qmp_v3_configure_dp_phy, 1583 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1584 1585 .reset_list = msm8996_usb3phy_reset_l, 1586 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1587 .vreg_list = qmp_phy_vreg_l, 1588 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1589 .regs = qmp_v3_usb3phy_regs_layout, 1590 1591 .has_pwrdn_delay = true, 1592 }; 1593 1594 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1595 .offsets = &qmp_combo_offsets_v3, 1596 1597 .serdes_tbl = sm8150_usb3_serdes_tbl, 1598 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1599 .tx_tbl = sm8150_usb3_tx_tbl, 1600 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1601 .rx_tbl = sm8150_usb3_rx_tbl, 1602 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1603 .pcs_tbl = sm8150_usb3_pcs_tbl, 1604 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1605 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1606 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1607 1608 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1609 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1610 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1611 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1612 1613 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1614 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1615 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1616 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1617 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1618 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1619 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1620 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1621 1622 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1623 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1624 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1625 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1626 1627 .dp_aux_init = qmp_v4_dp_aux_init, 1628 .configure_dp_tx = qmp_v4_configure_dp_tx, 1629 .configure_dp_phy = qmp_v4_configure_dp_phy, 1630 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1631 1632 .reset_list = msm8996_usb3phy_reset_l, 1633 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1634 .vreg_list = qmp_phy_vreg_l, 1635 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1636 .regs = qmp_v45_usb3phy_regs_layout, 1637 .pcs_usb_offset = 0x300, 1638 1639 .has_pwrdn_delay = true, 1640 }; 1641 1642 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1643 .offsets = &qmp_combo_offsets_v5, 1644 1645 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1646 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1647 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1648 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1649 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1650 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1651 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1652 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1653 1654 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1655 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1656 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1657 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1658 1659 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1660 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1661 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1662 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1663 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1664 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1665 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1666 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1667 1668 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1669 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1670 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1671 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1672 1673 .dp_aux_init = qmp_v4_dp_aux_init, 1674 .configure_dp_tx = qmp_v4_configure_dp_tx, 1675 .configure_dp_phy = qmp_v4_configure_dp_phy, 1676 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1677 1678 .reset_list = msm8996_usb3phy_reset_l, 1679 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1680 .vreg_list = qmp_phy_vreg_l, 1681 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1682 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1683 }; 1684 1685 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1686 .offsets = &qmp_combo_offsets_v3, 1687 1688 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1689 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1690 .tx_tbl = qmp_v3_usb3_tx_tbl, 1691 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1692 .rx_tbl = sm6350_usb3_rx_tbl, 1693 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1694 .pcs_tbl = sm6350_usb3_pcs_tbl, 1695 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1696 1697 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1698 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1699 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1700 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1701 1702 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1703 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1704 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1705 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1706 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1707 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1708 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1709 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1710 1711 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1712 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1713 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1714 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1715 1716 .dp_aux_init = qmp_v3_dp_aux_init, 1717 .configure_dp_tx = qmp_v3_configure_dp_tx, 1718 .configure_dp_phy = qmp_v3_configure_dp_phy, 1719 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1720 1721 .reset_list = msm8996_usb3phy_reset_l, 1722 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1723 .vreg_list = qmp_phy_vreg_l, 1724 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1725 .regs = qmp_v3_usb3phy_regs_layout, 1726 }; 1727 1728 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1729 .offsets = &qmp_combo_offsets_v3, 1730 1731 .serdes_tbl = sm8150_usb3_serdes_tbl, 1732 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1733 .tx_tbl = sm8250_usb3_tx_tbl, 1734 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1735 .rx_tbl = sm8250_usb3_rx_tbl, 1736 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1737 .pcs_tbl = sm8250_usb3_pcs_tbl, 1738 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1739 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1740 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1741 1742 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1743 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1744 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1745 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1746 1747 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1748 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1749 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1750 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1751 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1752 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1753 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1754 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1755 1756 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1757 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1758 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1759 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1760 1761 .dp_aux_init = qmp_v4_dp_aux_init, 1762 .configure_dp_tx = qmp_v4_configure_dp_tx, 1763 .configure_dp_phy = qmp_v4_configure_dp_phy, 1764 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1765 1766 .reset_list = msm8996_usb3phy_reset_l, 1767 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1768 .vreg_list = qmp_phy_vreg_l, 1769 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1770 .regs = qmp_v45_usb3phy_regs_layout, 1771 .pcs_usb_offset = 0x300, 1772 1773 .has_pwrdn_delay = true, 1774 }; 1775 1776 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1777 .offsets = &qmp_combo_offsets_v3, 1778 1779 .serdes_tbl = sm8150_usb3_serdes_tbl, 1780 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1781 .tx_tbl = sm8350_usb3_tx_tbl, 1782 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1783 .rx_tbl = sm8350_usb3_rx_tbl, 1784 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1785 .pcs_tbl = sm8350_usb3_pcs_tbl, 1786 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1787 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1788 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1789 1790 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1791 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1792 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1793 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1794 1795 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1796 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1797 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1798 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1799 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1800 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1801 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1802 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1803 1804 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1805 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1806 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1807 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1808 1809 .dp_aux_init = qmp_v4_dp_aux_init, 1810 .configure_dp_tx = qmp_v4_configure_dp_tx, 1811 .configure_dp_phy = qmp_v4_configure_dp_phy, 1812 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1813 1814 .reset_list = msm8996_usb3phy_reset_l, 1815 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1816 .vreg_list = qmp_phy_vreg_l, 1817 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1818 .regs = qmp_v45_usb3phy_regs_layout, 1819 1820 .has_pwrdn_delay = true, 1821 }; 1822 1823 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1824 .offsets = &qmp_combo_offsets_v3, 1825 1826 .serdes_tbl = sm8550_usb3_serdes_tbl, 1827 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1828 .tx_tbl = sm8550_usb3_tx_tbl, 1829 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1830 .rx_tbl = sm8550_usb3_rx_tbl, 1831 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1832 .pcs_tbl = sm8550_usb3_pcs_tbl, 1833 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1834 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1835 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1836 1837 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1838 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1839 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1840 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1841 1842 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1843 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1844 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1845 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1846 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1847 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1848 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1849 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1850 1851 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1852 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1853 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1854 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1855 1856 .dp_aux_init = qmp_v4_dp_aux_init, 1857 .configure_dp_tx = qmp_v4_configure_dp_tx, 1858 .configure_dp_phy = qmp_v4_configure_dp_phy, 1859 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1860 1861 .regs = qmp_v6_usb3phy_regs_layout, 1862 .reset_list = msm8996_usb3phy_reset_l, 1863 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1864 .vreg_list = qmp_phy_vreg_l, 1865 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1866 }; 1867 1868 static void qmp_combo_configure_lane(void __iomem *base, 1869 const struct qmp_phy_init_tbl tbl[], 1870 int num, 1871 u8 lane_mask) 1872 { 1873 int i; 1874 const struct qmp_phy_init_tbl *t = tbl; 1875 1876 if (!t) 1877 return; 1878 1879 for (i = 0; i < num; i++, t++) { 1880 if (!(t->lane_mask & lane_mask)) 1881 continue; 1882 1883 writel(t->val, base + t->offset); 1884 } 1885 } 1886 1887 static void qmp_combo_configure(void __iomem *base, 1888 const struct qmp_phy_init_tbl tbl[], 1889 int num) 1890 { 1891 qmp_combo_configure_lane(base, tbl, num, 0xff); 1892 } 1893 1894 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1895 { 1896 const struct qmp_phy_cfg *cfg = qmp->cfg; 1897 void __iomem *serdes = qmp->dp_serdes; 1898 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1899 1900 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1901 1902 switch (dp_opts->link_rate) { 1903 case 1620: 1904 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1905 cfg->serdes_tbl_rbr_num); 1906 break; 1907 case 2700: 1908 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1909 cfg->serdes_tbl_hbr_num); 1910 break; 1911 case 5400: 1912 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1913 cfg->serdes_tbl_hbr2_num); 1914 break; 1915 case 8100: 1916 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1917 cfg->serdes_tbl_hbr3_num); 1918 break; 1919 default: 1920 /* Other link rates aren't supported */ 1921 return -EINVAL; 1922 } 1923 1924 return 0; 1925 } 1926 1927 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1928 { 1929 const struct qmp_phy_cfg *cfg = qmp->cfg; 1930 1931 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1932 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1933 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1934 1935 /* Turn on BIAS current for PHY/PLL */ 1936 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1937 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1938 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1939 1940 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1941 1942 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1943 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1944 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1945 DP_PHY_PD_CTL_DP_CLAMP_EN, 1946 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1947 1948 writel(QSERDES_V3_COM_BIAS_EN | 1949 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1950 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1951 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1952 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1953 1954 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1955 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1956 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1957 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1958 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1959 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1960 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1961 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1962 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1963 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1964 qmp->dp_aux_cfg = 0; 1965 1966 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1967 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1968 PHY_AUX_REQ_ERR_MASK, 1969 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1970 } 1971 1972 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 1973 { 1974 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1975 const struct qmp_phy_cfg *cfg = qmp->cfg; 1976 unsigned int v_level = 0, p_level = 0; 1977 u8 voltage_swing_cfg, pre_emphasis_cfg; 1978 int i; 1979 1980 for (i = 0; i < dp_opts->lanes; i++) { 1981 v_level = max(v_level, dp_opts->voltage[i]); 1982 p_level = max(p_level, dp_opts->pre[i]); 1983 } 1984 1985 if (dp_opts->link_rate <= 2700) { 1986 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1987 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1988 } else { 1989 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1990 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1991 } 1992 1993 /* TODO: Move check to config check */ 1994 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1995 return -EINVAL; 1996 1997 /* Enable MUX to use Cursor values from these registers */ 1998 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1999 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2000 2001 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2002 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2003 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2004 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2005 2006 return 0; 2007 } 2008 2009 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2010 { 2011 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2012 u32 bias_en, drvr_en; 2013 2014 if (qmp_combo_configure_dp_swing(qmp) < 0) 2015 return; 2016 2017 if (dp_opts->lanes == 1) { 2018 bias_en = 0x3e; 2019 drvr_en = 0x13; 2020 } else { 2021 bias_en = 0x3f; 2022 drvr_en = 0x10; 2023 } 2024 2025 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2026 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2027 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2028 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2029 } 2030 2031 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2032 { 2033 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2034 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2035 u32 val; 2036 2037 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2038 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2039 2040 if (dp_opts->lanes == 4 || reverse) 2041 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2042 if (dp_opts->lanes == 4 || !reverse) 2043 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2044 2045 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2046 2047 if (reverse) 2048 writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE); 2049 else 2050 writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE); 2051 2052 return reverse; 2053 } 2054 2055 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2056 { 2057 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2058 u32 phy_vco_div; 2059 unsigned long pixel_freq; 2060 2061 switch (dp_opts->link_rate) { 2062 case 1620: 2063 phy_vco_div = 0x1; 2064 pixel_freq = 1620000000UL / 2; 2065 break; 2066 case 2700: 2067 phy_vco_div = 0x1; 2068 pixel_freq = 2700000000UL / 2; 2069 break; 2070 case 5400: 2071 phy_vco_div = 0x2; 2072 pixel_freq = 5400000000UL / 4; 2073 break; 2074 case 8100: 2075 phy_vco_div = 0x0; 2076 pixel_freq = 8100000000UL / 6; 2077 break; 2078 default: 2079 /* Other link rates aren't supported */ 2080 return -EINVAL; 2081 } 2082 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 2083 2084 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2085 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2086 2087 return 0; 2088 } 2089 2090 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2091 { 2092 const struct qmp_phy_cfg *cfg = qmp->cfg; 2093 u32 status; 2094 int ret; 2095 2096 qmp_combo_configure_dp_mode(qmp); 2097 2098 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2099 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2100 2101 ret = qmp_combo_configure_dp_clocks(qmp); 2102 if (ret) 2103 return ret; 2104 2105 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2106 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2107 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2108 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2109 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2110 2111 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2112 2113 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2114 status, 2115 ((status & BIT(0)) > 0), 2116 500, 2117 10000)) 2118 return -ETIMEDOUT; 2119 2120 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2121 2122 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2123 status, 2124 ((status & BIT(1)) > 0), 2125 500, 2126 10000)) 2127 return -ETIMEDOUT; 2128 2129 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2130 udelay(2000); 2131 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2132 2133 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2134 status, 2135 ((status & BIT(1)) > 0), 2136 500, 2137 10000); 2138 } 2139 2140 /* 2141 * We need to calibrate the aux setting here as many times 2142 * as the caller tries 2143 */ 2144 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2145 { 2146 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2147 u8 val; 2148 2149 qmp->dp_aux_cfg++; 2150 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2151 val = cfg1_settings[qmp->dp_aux_cfg]; 2152 2153 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2154 2155 return 0; 2156 } 2157 2158 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2159 { 2160 const struct qmp_phy_cfg *cfg = qmp->cfg; 2161 2162 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2163 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2164 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2165 2166 /* Turn on BIAS current for PHY/PLL */ 2167 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2168 2169 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2170 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2171 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2172 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2173 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2174 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2175 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2176 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2177 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2178 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2179 qmp->dp_aux_cfg = 0; 2180 2181 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2182 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2183 PHY_AUX_REQ_ERR_MASK, 2184 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2185 } 2186 2187 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2188 { 2189 const struct qmp_phy_cfg *cfg = qmp->cfg; 2190 2191 /* Program default values before writing proper values */ 2192 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2193 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2194 2195 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2196 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2197 2198 qmp_combo_configure_dp_swing(qmp); 2199 } 2200 2201 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2202 { 2203 const struct qmp_phy_cfg *cfg = qmp->cfg; 2204 u32 status; 2205 int ret; 2206 2207 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 2208 2209 qmp_combo_configure_dp_mode(qmp); 2210 2211 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2212 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2213 2214 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2215 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2216 2217 ret = qmp_combo_configure_dp_clocks(qmp); 2218 if (ret) 2219 return ret; 2220 2221 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2222 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2223 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2224 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2225 2226 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2227 2228 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2229 status, 2230 ((status & BIT(0)) > 0), 2231 500, 2232 10000)) 2233 return -ETIMEDOUT; 2234 2235 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2236 status, 2237 ((status & BIT(0)) > 0), 2238 500, 2239 10000)) 2240 return -ETIMEDOUT; 2241 2242 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2243 status, 2244 ((status & BIT(1)) > 0), 2245 500, 2246 10000)) 2247 return -ETIMEDOUT; 2248 2249 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2250 2251 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2252 status, 2253 ((status & BIT(0)) > 0), 2254 500, 2255 10000)) 2256 return -ETIMEDOUT; 2257 2258 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2259 status, 2260 ((status & BIT(1)) > 0), 2261 500, 2262 10000)) 2263 return -ETIMEDOUT; 2264 2265 return 0; 2266 } 2267 2268 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2269 { 2270 const struct qmp_phy_cfg *cfg = qmp->cfg; 2271 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2272 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2273 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2274 u32 status; 2275 int ret; 2276 2277 ret = qmp_v456_configure_dp_phy(qmp); 2278 if (ret < 0) 2279 return ret; 2280 2281 /* 2282 * At least for 7nm DP PHY this has to be done after enabling link 2283 * clock. 2284 */ 2285 2286 if (dp_opts->lanes == 1) { 2287 bias0_en = reverse ? 0x3e : 0x15; 2288 bias1_en = reverse ? 0x15 : 0x3e; 2289 drvr0_en = reverse ? 0x13 : 0x10; 2290 drvr1_en = reverse ? 0x10 : 0x13; 2291 } else if (dp_opts->lanes == 2) { 2292 bias0_en = reverse ? 0x3f : 0x15; 2293 bias1_en = reverse ? 0x15 : 0x3f; 2294 drvr0_en = 0x10; 2295 drvr1_en = 0x10; 2296 } else { 2297 bias0_en = 0x3f; 2298 bias1_en = 0x3f; 2299 drvr0_en = 0x10; 2300 drvr1_en = 0x10; 2301 } 2302 2303 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2304 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2305 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2306 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2307 2308 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2309 udelay(2000); 2310 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2311 2312 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2313 status, 2314 ((status & BIT(1)) > 0), 2315 500, 2316 10000)) 2317 return -ETIMEDOUT; 2318 2319 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2320 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2321 2322 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2323 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2324 2325 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2326 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2327 2328 return 0; 2329 2330 return 0; 2331 } 2332 2333 /* 2334 * We need to calibrate the aux setting here as many times 2335 * as the caller tries 2336 */ 2337 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2338 { 2339 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2340 u8 val; 2341 2342 qmp->dp_aux_cfg++; 2343 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2344 val = cfg1_settings[qmp->dp_aux_cfg]; 2345 2346 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2347 2348 return 0; 2349 } 2350 2351 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2352 { 2353 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2354 struct qmp_combo *qmp = phy_get_drvdata(phy); 2355 const struct qmp_phy_cfg *cfg = qmp->cfg; 2356 2357 mutex_lock(&qmp->phy_mutex); 2358 2359 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2360 if (qmp->dp_opts.set_voltages) { 2361 cfg->configure_dp_tx(qmp); 2362 qmp->dp_opts.set_voltages = 0; 2363 } 2364 2365 mutex_unlock(&qmp->phy_mutex); 2366 2367 return 0; 2368 } 2369 2370 static int qmp_combo_dp_calibrate(struct phy *phy) 2371 { 2372 struct qmp_combo *qmp = phy_get_drvdata(phy); 2373 const struct qmp_phy_cfg *cfg = qmp->cfg; 2374 int ret = 0; 2375 2376 mutex_lock(&qmp->phy_mutex); 2377 2378 if (cfg->calibrate_dp_phy) 2379 ret = cfg->calibrate_dp_phy(qmp); 2380 2381 mutex_unlock(&qmp->phy_mutex); 2382 2383 return ret; 2384 } 2385 2386 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2387 { 2388 const struct qmp_phy_cfg *cfg = qmp->cfg; 2389 void __iomem *com = qmp->com; 2390 int ret; 2391 u32 val; 2392 2393 if (!force && qmp->init_count++) 2394 return 0; 2395 2396 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2397 if (ret) { 2398 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2399 goto err_decrement_count; 2400 } 2401 2402 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2403 if (ret) { 2404 dev_err(qmp->dev, "reset assert failed\n"); 2405 goto err_disable_regulators; 2406 } 2407 2408 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2409 if (ret) { 2410 dev_err(qmp->dev, "reset deassert failed\n"); 2411 goto err_disable_regulators; 2412 } 2413 2414 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2415 if (ret) 2416 goto err_assert_reset; 2417 2418 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2419 2420 /* override hardware control for reset of qmp phy */ 2421 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2422 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2423 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2424 2425 /* Use software based port select and switch on typec orientation */ 2426 val = SW_PORTSELECT_MUX; 2427 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2428 val |= SW_PORTSELECT_VAL; 2429 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2430 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2431 2432 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2433 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2434 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2435 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2436 2437 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2438 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2439 2440 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2441 SW_PWRDN); 2442 2443 return 0; 2444 2445 err_assert_reset: 2446 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2447 err_disable_regulators: 2448 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2449 err_decrement_count: 2450 qmp->init_count--; 2451 2452 return ret; 2453 } 2454 2455 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2456 { 2457 const struct qmp_phy_cfg *cfg = qmp->cfg; 2458 2459 if (!force && --qmp->init_count) 2460 return 0; 2461 2462 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2463 2464 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2465 2466 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2467 2468 return 0; 2469 } 2470 2471 static int qmp_combo_dp_init(struct phy *phy) 2472 { 2473 struct qmp_combo *qmp = phy_get_drvdata(phy); 2474 const struct qmp_phy_cfg *cfg = qmp->cfg; 2475 int ret; 2476 2477 mutex_lock(&qmp->phy_mutex); 2478 2479 ret = qmp_combo_com_init(qmp, false); 2480 if (ret) 2481 goto out_unlock; 2482 2483 cfg->dp_aux_init(qmp); 2484 2485 qmp->dp_init_count++; 2486 2487 out_unlock: 2488 mutex_unlock(&qmp->phy_mutex); 2489 return ret; 2490 } 2491 2492 static int qmp_combo_dp_exit(struct phy *phy) 2493 { 2494 struct qmp_combo *qmp = phy_get_drvdata(phy); 2495 2496 mutex_lock(&qmp->phy_mutex); 2497 2498 qmp_combo_com_exit(qmp, false); 2499 2500 qmp->dp_init_count--; 2501 2502 mutex_unlock(&qmp->phy_mutex); 2503 2504 return 0; 2505 } 2506 2507 static int qmp_combo_dp_power_on(struct phy *phy) 2508 { 2509 struct qmp_combo *qmp = phy_get_drvdata(phy); 2510 const struct qmp_phy_cfg *cfg = qmp->cfg; 2511 void __iomem *tx = qmp->dp_tx; 2512 void __iomem *tx2 = qmp->dp_tx2; 2513 2514 mutex_lock(&qmp->phy_mutex); 2515 2516 qmp_combo_dp_serdes_init(qmp); 2517 2518 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2519 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2520 2521 /* Configure special DP tx tunings */ 2522 cfg->configure_dp_tx(qmp); 2523 2524 /* Configure link rate, swing, etc. */ 2525 cfg->configure_dp_phy(qmp); 2526 2527 mutex_unlock(&qmp->phy_mutex); 2528 2529 return 0; 2530 } 2531 2532 static int qmp_combo_dp_power_off(struct phy *phy) 2533 { 2534 struct qmp_combo *qmp = phy_get_drvdata(phy); 2535 2536 mutex_lock(&qmp->phy_mutex); 2537 2538 /* Assert DP PHY power down */ 2539 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2540 2541 mutex_unlock(&qmp->phy_mutex); 2542 2543 return 0; 2544 } 2545 2546 static int qmp_combo_usb_power_on(struct phy *phy) 2547 { 2548 struct qmp_combo *qmp = phy_get_drvdata(phy); 2549 const struct qmp_phy_cfg *cfg = qmp->cfg; 2550 void __iomem *serdes = qmp->serdes; 2551 void __iomem *tx = qmp->tx; 2552 void __iomem *rx = qmp->rx; 2553 void __iomem *tx2 = qmp->tx2; 2554 void __iomem *rx2 = qmp->rx2; 2555 void __iomem *pcs = qmp->pcs; 2556 void __iomem *pcs_usb = qmp->pcs_usb; 2557 void __iomem *status; 2558 unsigned int val; 2559 int ret; 2560 2561 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2562 2563 ret = clk_prepare_enable(qmp->pipe_clk); 2564 if (ret) { 2565 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2566 return ret; 2567 } 2568 2569 /* Tx, Rx, and PCS configurations */ 2570 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2571 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2572 2573 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2574 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2575 2576 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2577 2578 if (pcs_usb) 2579 qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 2580 2581 if (cfg->has_pwrdn_delay) 2582 usleep_range(10, 20); 2583 2584 /* Pull PHY out of reset state */ 2585 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2586 2587 /* start SerDes and Phy-Coding-Sublayer */ 2588 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2589 2590 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2591 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2592 PHY_INIT_COMPLETE_TIMEOUT); 2593 if (ret) { 2594 dev_err(qmp->dev, "phy initialization timed-out\n"); 2595 goto err_disable_pipe_clk; 2596 } 2597 2598 return 0; 2599 2600 err_disable_pipe_clk: 2601 clk_disable_unprepare(qmp->pipe_clk); 2602 2603 return ret; 2604 } 2605 2606 static int qmp_combo_usb_power_off(struct phy *phy) 2607 { 2608 struct qmp_combo *qmp = phy_get_drvdata(phy); 2609 const struct qmp_phy_cfg *cfg = qmp->cfg; 2610 2611 clk_disable_unprepare(qmp->pipe_clk); 2612 2613 /* PHY reset */ 2614 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2615 2616 /* stop SerDes and Phy-Coding-Sublayer */ 2617 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2618 SERDES_START | PCS_START); 2619 2620 /* Put PHY into POWER DOWN state: active low */ 2621 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2622 SW_PWRDN); 2623 2624 return 0; 2625 } 2626 2627 static int qmp_combo_usb_init(struct phy *phy) 2628 { 2629 struct qmp_combo *qmp = phy_get_drvdata(phy); 2630 int ret; 2631 2632 mutex_lock(&qmp->phy_mutex); 2633 ret = qmp_combo_com_init(qmp, false); 2634 if (ret) 2635 goto out_unlock; 2636 2637 ret = qmp_combo_usb_power_on(phy); 2638 if (ret) { 2639 qmp_combo_com_exit(qmp, false); 2640 goto out_unlock; 2641 } 2642 2643 qmp->usb_init_count++; 2644 2645 out_unlock: 2646 mutex_unlock(&qmp->phy_mutex); 2647 return ret; 2648 } 2649 2650 static int qmp_combo_usb_exit(struct phy *phy) 2651 { 2652 struct qmp_combo *qmp = phy_get_drvdata(phy); 2653 int ret; 2654 2655 mutex_lock(&qmp->phy_mutex); 2656 ret = qmp_combo_usb_power_off(phy); 2657 if (ret) 2658 goto out_unlock; 2659 2660 ret = qmp_combo_com_exit(qmp, false); 2661 if (ret) 2662 goto out_unlock; 2663 2664 qmp->usb_init_count--; 2665 2666 out_unlock: 2667 mutex_unlock(&qmp->phy_mutex); 2668 return ret; 2669 } 2670 2671 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2672 { 2673 struct qmp_combo *qmp = phy_get_drvdata(phy); 2674 2675 qmp->mode = mode; 2676 2677 return 0; 2678 } 2679 2680 static const struct phy_ops qmp_combo_usb_phy_ops = { 2681 .init = qmp_combo_usb_init, 2682 .exit = qmp_combo_usb_exit, 2683 .set_mode = qmp_combo_usb_set_mode, 2684 .owner = THIS_MODULE, 2685 }; 2686 2687 static const struct phy_ops qmp_combo_dp_phy_ops = { 2688 .init = qmp_combo_dp_init, 2689 .configure = qmp_combo_dp_configure, 2690 .power_on = qmp_combo_dp_power_on, 2691 .calibrate = qmp_combo_dp_calibrate, 2692 .power_off = qmp_combo_dp_power_off, 2693 .exit = qmp_combo_dp_exit, 2694 .owner = THIS_MODULE, 2695 }; 2696 2697 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2698 { 2699 const struct qmp_phy_cfg *cfg = qmp->cfg; 2700 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2701 void __iomem *pcs_misc = qmp->pcs_misc; 2702 u32 intr_mask; 2703 2704 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2705 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2706 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2707 else 2708 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2709 2710 /* Clear any pending interrupts status */ 2711 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2712 /* Writing 1 followed by 0 clears the interrupt */ 2713 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2714 2715 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2716 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2717 2718 /* Enable required PHY autonomous mode interrupts */ 2719 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2720 2721 /* Enable i/o clamp_n for autonomous mode */ 2722 if (pcs_misc) 2723 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2724 } 2725 2726 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2727 { 2728 const struct qmp_phy_cfg *cfg = qmp->cfg; 2729 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2730 void __iomem *pcs_misc = qmp->pcs_misc; 2731 2732 /* Disable i/o clamp_n on resume for normal mode */ 2733 if (pcs_misc) 2734 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2735 2736 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2737 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2738 2739 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2740 /* Writing 1 followed by 0 clears the interrupt */ 2741 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2742 } 2743 2744 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2745 { 2746 struct qmp_combo *qmp = dev_get_drvdata(dev); 2747 2748 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2749 2750 if (!qmp->init_count) { 2751 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2752 return 0; 2753 } 2754 2755 qmp_combo_enable_autonomous_mode(qmp); 2756 2757 clk_disable_unprepare(qmp->pipe_clk); 2758 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2759 2760 return 0; 2761 } 2762 2763 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2764 { 2765 struct qmp_combo *qmp = dev_get_drvdata(dev); 2766 int ret = 0; 2767 2768 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2769 2770 if (!qmp->init_count) { 2771 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2772 return 0; 2773 } 2774 2775 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2776 if (ret) 2777 return ret; 2778 2779 ret = clk_prepare_enable(qmp->pipe_clk); 2780 if (ret) { 2781 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2782 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2783 return ret; 2784 } 2785 2786 qmp_combo_disable_autonomous_mode(qmp); 2787 2788 return 0; 2789 } 2790 2791 static const struct dev_pm_ops qmp_combo_pm_ops = { 2792 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2793 qmp_combo_runtime_resume, NULL) 2794 }; 2795 2796 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2797 { 2798 const struct qmp_phy_cfg *cfg = qmp->cfg; 2799 struct device *dev = qmp->dev; 2800 int num = cfg->num_vregs; 2801 int ret, i; 2802 2803 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2804 if (!qmp->vregs) 2805 return -ENOMEM; 2806 2807 for (i = 0; i < num; i++) 2808 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2809 2810 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2811 if (ret) { 2812 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2813 return ret; 2814 } 2815 2816 for (i = 0; i < num; i++) { 2817 ret = regulator_set_load(qmp->vregs[i].consumer, 2818 cfg->vreg_list[i].enable_load); 2819 if (ret) { 2820 dev_err(dev, "failed to set load at %s\n", 2821 qmp->vregs[i].supply); 2822 return ret; 2823 } 2824 } 2825 2826 return 0; 2827 } 2828 2829 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2830 { 2831 const struct qmp_phy_cfg *cfg = qmp->cfg; 2832 struct device *dev = qmp->dev; 2833 int i; 2834 int ret; 2835 2836 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2837 sizeof(*qmp->resets), GFP_KERNEL); 2838 if (!qmp->resets) 2839 return -ENOMEM; 2840 2841 for (i = 0; i < cfg->num_resets; i++) 2842 qmp->resets[i].id = cfg->reset_list[i]; 2843 2844 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2845 if (ret) 2846 return dev_err_probe(dev, ret, "failed to get resets\n"); 2847 2848 return 0; 2849 } 2850 2851 static int qmp_combo_clk_init(struct qmp_combo *qmp) 2852 { 2853 struct device *dev = qmp->dev; 2854 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 2855 int i; 2856 2857 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2858 if (!qmp->clks) 2859 return -ENOMEM; 2860 2861 for (i = 0; i < num; i++) 2862 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 2863 2864 qmp->num_clks = num; 2865 2866 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 2867 } 2868 2869 static void phy_clk_release_provider(void *res) 2870 { 2871 of_clk_del_provider(res); 2872 } 2873 2874 /* 2875 * Register a fixed rate pipe clock. 2876 * 2877 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2878 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2879 * by the PHY driver for its operations. 2880 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2881 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2882 * Below picture shows this relationship. 2883 * 2884 * +---------------+ 2885 * | PHY block |<<---------------------------------------+ 2886 * | | | 2887 * | +-------+ | +-----+ | 2888 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2889 * clk | +-------+ | +-----+ 2890 * +---------------+ 2891 */ 2892 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2893 { 2894 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2895 struct clk_init_data init = { }; 2896 char name[64]; 2897 2898 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2899 init.name = name; 2900 init.ops = &clk_fixed_rate_ops; 2901 2902 /* controllers using QMP phys use 125MHz pipe clock interface */ 2903 fixed->fixed_rate = 125000000; 2904 fixed->hw.init = &init; 2905 2906 return devm_clk_hw_register(qmp->dev, &fixed->hw); 2907 } 2908 2909 /* 2910 * Display Port PLL driver block diagram for branch clocks 2911 * 2912 * +------------------------------+ 2913 * | DP_VCO_CLK | 2914 * | | 2915 * | +-------------------+ | 2916 * | | (DP PLL/VCO) | | 2917 * | +---------+---------+ | 2918 * | v | 2919 * | +----------+-----------+ | 2920 * | | hsclk_divsel_clk_src | | 2921 * | +----------+-----------+ | 2922 * +------------------------------+ 2923 * | 2924 * +---------<---------v------------>----------+ 2925 * | | 2926 * +--------v----------------+ | 2927 * | dp_phy_pll_link_clk | | 2928 * | link_clk | | 2929 * +--------+----------------+ | 2930 * | | 2931 * | | 2932 * v v 2933 * Input to DISPCC block | 2934 * for link clk, crypto clk | 2935 * and interface clock | 2936 * | 2937 * | 2938 * +--------<------------+-----------------+---<---+ 2939 * | | | 2940 * +----v---------+ +--------v-----+ +--------v------+ 2941 * | vco_divided | | vco_divided | | vco_divided | 2942 * | _clk_src | | _clk_src | | _clk_src | 2943 * | | | | | | 2944 * |divsel_six | | divsel_two | | divsel_four | 2945 * +-------+------+ +-----+--------+ +--------+------+ 2946 * | | | 2947 * v---->----------v-------------<------v 2948 * | 2949 * +----------+-----------------+ 2950 * | dp_phy_pll_vco_div_clk | 2951 * +---------+------------------+ 2952 * | 2953 * v 2954 * Input to DISPCC block 2955 * for DP pixel clock 2956 * 2957 */ 2958 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2959 { 2960 switch (req->rate) { 2961 case 1620000000UL / 2: 2962 case 2700000000UL / 2: 2963 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2964 return 0; 2965 default: 2966 return -EINVAL; 2967 } 2968 } 2969 2970 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2971 { 2972 const struct qmp_combo *qmp; 2973 const struct phy_configure_opts_dp *dp_opts; 2974 2975 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 2976 dp_opts = &qmp->dp_opts; 2977 2978 switch (dp_opts->link_rate) { 2979 case 1620: 2980 return 1620000000UL / 2; 2981 case 2700: 2982 return 2700000000UL / 2; 2983 case 5400: 2984 return 5400000000UL / 4; 2985 case 8100: 2986 return 8100000000UL / 6; 2987 default: 2988 return 0; 2989 } 2990 } 2991 2992 static const struct clk_ops qmp_dp_pixel_clk_ops = { 2993 .determine_rate = qmp_dp_pixel_clk_determine_rate, 2994 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 2995 }; 2996 2997 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2998 { 2999 switch (req->rate) { 3000 case 162000000: 3001 case 270000000: 3002 case 540000000: 3003 case 810000000: 3004 return 0; 3005 default: 3006 return -EINVAL; 3007 } 3008 } 3009 3010 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3011 { 3012 const struct qmp_combo *qmp; 3013 const struct phy_configure_opts_dp *dp_opts; 3014 3015 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3016 dp_opts = &qmp->dp_opts; 3017 3018 switch (dp_opts->link_rate) { 3019 case 1620: 3020 case 2700: 3021 case 5400: 3022 case 8100: 3023 return dp_opts->link_rate * 100000; 3024 default: 3025 return 0; 3026 } 3027 } 3028 3029 static const struct clk_ops qmp_dp_link_clk_ops = { 3030 .determine_rate = qmp_dp_link_clk_determine_rate, 3031 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3032 }; 3033 3034 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3035 { 3036 struct qmp_combo *qmp = data; 3037 unsigned int idx = clkspec->args[0]; 3038 3039 if (idx >= 2) { 3040 pr_err("%s: invalid index %u\n", __func__, idx); 3041 return ERR_PTR(-EINVAL); 3042 } 3043 3044 if (idx == 0) 3045 return &qmp->dp_link_hw; 3046 3047 return &qmp->dp_pixel_hw; 3048 } 3049 3050 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3051 { 3052 struct clk_init_data init = { }; 3053 char name[64]; 3054 int ret; 3055 3056 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3057 init.ops = &qmp_dp_link_clk_ops; 3058 init.name = name; 3059 qmp->dp_link_hw.init = &init; 3060 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3061 if (ret) 3062 return ret; 3063 3064 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3065 init.ops = &qmp_dp_pixel_clk_ops; 3066 init.name = name; 3067 qmp->dp_pixel_hw.init = &init; 3068 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3069 if (ret) 3070 return ret; 3071 3072 return 0; 3073 } 3074 3075 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3076 { 3077 struct qmp_combo *qmp = data; 3078 3079 switch (clkspec->args[0]) { 3080 case QMP_USB43DP_USB3_PIPE_CLK: 3081 return &qmp->pipe_clk_fixed.hw; 3082 case QMP_USB43DP_DP_LINK_CLK: 3083 return &qmp->dp_link_hw; 3084 case QMP_USB43DP_DP_VCO_DIV_CLK: 3085 return &qmp->dp_pixel_hw; 3086 } 3087 3088 return ERR_PTR(-EINVAL); 3089 } 3090 3091 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3092 struct device_node *dp_np) 3093 { 3094 int ret; 3095 3096 ret = phy_pipe_clk_register(qmp, usb_np); 3097 if (ret) 3098 return ret; 3099 3100 ret = phy_dp_clks_register(qmp, dp_np); 3101 if (ret) 3102 return ret; 3103 3104 /* 3105 * Register a single provider for bindings without child nodes. 3106 */ 3107 if (usb_np == qmp->dev->of_node) 3108 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3109 3110 /* 3111 * Register multiple providers for legacy bindings with child nodes. 3112 */ 3113 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3114 &qmp->pipe_clk_fixed.hw); 3115 if (ret) 3116 return ret; 3117 3118 /* 3119 * Roll a devm action because the clock provider is the child node, but 3120 * the child node is not actually a device. 3121 */ 3122 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3123 if (ret) 3124 return ret; 3125 3126 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3127 if (ret) 3128 return ret; 3129 3130 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3131 } 3132 3133 #if IS_ENABLED(CONFIG_TYPEC) 3134 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3135 enum typec_orientation orientation) 3136 { 3137 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3138 const struct qmp_phy_cfg *cfg = qmp->cfg; 3139 3140 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3141 return 0; 3142 3143 mutex_lock(&qmp->phy_mutex); 3144 qmp->orientation = orientation; 3145 3146 if (qmp->init_count) { 3147 if (qmp->usb_init_count) 3148 qmp_combo_usb_power_off(qmp->usb_phy); 3149 qmp_combo_com_exit(qmp, true); 3150 3151 qmp_combo_com_init(qmp, true); 3152 if (qmp->usb_init_count) 3153 qmp_combo_usb_power_on(qmp->usb_phy); 3154 if (qmp->dp_init_count) 3155 cfg->dp_aux_init(qmp); 3156 } 3157 mutex_unlock(&qmp->phy_mutex); 3158 3159 return 0; 3160 } 3161 3162 static void qmp_combo_typec_unregister(void *data) 3163 { 3164 struct qmp_combo *qmp = data; 3165 3166 typec_switch_unregister(qmp->sw); 3167 } 3168 3169 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3170 { 3171 struct typec_switch_desc sw_desc = {}; 3172 struct device *dev = qmp->dev; 3173 3174 sw_desc.drvdata = qmp; 3175 sw_desc.fwnode = dev->fwnode; 3176 sw_desc.set = qmp_combo_typec_switch_set; 3177 qmp->sw = typec_switch_register(dev, &sw_desc); 3178 if (IS_ERR(qmp->sw)) { 3179 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3180 return PTR_ERR(qmp->sw); 3181 } 3182 3183 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3184 } 3185 #else 3186 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3187 { 3188 return 0; 3189 } 3190 #endif 3191 3192 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3193 { 3194 struct device *dev = qmp->dev; 3195 3196 /* 3197 * Get memory resources from the DP child node: 3198 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3199 * tx2 -> 3; rx2 -> 4 3200 * 3201 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3202 * implementation. 3203 */ 3204 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3205 if (IS_ERR(qmp->dp_tx)) 3206 return PTR_ERR(qmp->dp_tx); 3207 3208 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3209 if (IS_ERR(qmp->dp_dp_phy)) 3210 return PTR_ERR(qmp->dp_dp_phy); 3211 3212 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3213 if (IS_ERR(qmp->dp_tx2)) 3214 return PTR_ERR(qmp->dp_tx2); 3215 3216 return 0; 3217 } 3218 3219 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3220 { 3221 const struct qmp_phy_cfg *cfg = qmp->cfg; 3222 struct device *dev = qmp->dev; 3223 3224 /* 3225 * Get memory resources from the USB child node: 3226 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3227 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3228 */ 3229 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3230 if (IS_ERR(qmp->tx)) 3231 return PTR_ERR(qmp->tx); 3232 3233 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3234 if (IS_ERR(qmp->rx)) 3235 return PTR_ERR(qmp->rx); 3236 3237 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3238 if (IS_ERR(qmp->pcs)) 3239 return PTR_ERR(qmp->pcs); 3240 3241 if (cfg->pcs_usb_offset) 3242 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3243 3244 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3245 if (IS_ERR(qmp->tx2)) 3246 return PTR_ERR(qmp->tx2); 3247 3248 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3249 if (IS_ERR(qmp->rx2)) 3250 return PTR_ERR(qmp->rx2); 3251 3252 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3253 if (IS_ERR(qmp->pcs_misc)) { 3254 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3255 qmp->pcs_misc = NULL; 3256 } 3257 3258 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3259 if (IS_ERR(qmp->pipe_clk)) { 3260 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3261 "failed to get pipe clock\n"); 3262 } 3263 3264 return 0; 3265 } 3266 3267 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3268 struct device_node *dp_np) 3269 { 3270 struct platform_device *pdev = to_platform_device(qmp->dev); 3271 int ret; 3272 3273 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3274 if (IS_ERR(qmp->serdes)) 3275 return PTR_ERR(qmp->serdes); 3276 3277 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3278 if (IS_ERR(qmp->com)) 3279 return PTR_ERR(qmp->com); 3280 3281 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3282 if (IS_ERR(qmp->dp_serdes)) 3283 return PTR_ERR(qmp->dp_serdes); 3284 3285 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3286 if (ret) 3287 return ret; 3288 3289 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3290 if (ret) 3291 return ret; 3292 3293 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3294 if (ret < 0) 3295 return ret; 3296 3297 qmp->num_clks = ret; 3298 3299 return 0; 3300 } 3301 3302 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3303 { 3304 struct platform_device *pdev = to_platform_device(qmp->dev); 3305 const struct qmp_phy_cfg *cfg = qmp->cfg; 3306 const struct qmp_combo_offsets *offs = cfg->offsets; 3307 struct device *dev = qmp->dev; 3308 void __iomem *base; 3309 int ret; 3310 3311 if (!offs) 3312 return -EINVAL; 3313 3314 base = devm_platform_ioremap_resource(pdev, 0); 3315 if (IS_ERR(base)) 3316 return PTR_ERR(base); 3317 3318 qmp->com = base + offs->com; 3319 qmp->tx = base + offs->txa; 3320 qmp->rx = base + offs->rxa; 3321 qmp->tx2 = base + offs->txb; 3322 qmp->rx2 = base + offs->rxb; 3323 3324 qmp->serdes = base + offs->usb3_serdes; 3325 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3326 qmp->pcs = base + offs->usb3_pcs; 3327 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3328 3329 qmp->dp_serdes = base + offs->dp_serdes; 3330 if (offs->dp_txa) { 3331 qmp->dp_tx = base + offs->dp_txa; 3332 qmp->dp_tx2 = base + offs->dp_txb; 3333 } else { 3334 qmp->dp_tx = base + offs->txa; 3335 qmp->dp_tx2 = base + offs->txb; 3336 } 3337 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3338 3339 ret = qmp_combo_clk_init(qmp); 3340 if (ret) 3341 return ret; 3342 3343 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3344 if (IS_ERR(qmp->pipe_clk)) { 3345 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3346 "failed to get usb3_pipe clock\n"); 3347 } 3348 3349 return 0; 3350 } 3351 3352 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 3353 { 3354 struct qmp_combo *qmp = dev_get_drvdata(dev); 3355 3356 if (args->args_count == 0) 3357 return ERR_PTR(-EINVAL); 3358 3359 switch (args->args[0]) { 3360 case QMP_USB43DP_USB3_PHY: 3361 return qmp->usb_phy; 3362 case QMP_USB43DP_DP_PHY: 3363 return qmp->dp_phy; 3364 } 3365 3366 return ERR_PTR(-EINVAL); 3367 } 3368 3369 static int qmp_combo_probe(struct platform_device *pdev) 3370 { 3371 struct qmp_combo *qmp; 3372 struct device *dev = &pdev->dev; 3373 struct device_node *dp_np, *usb_np; 3374 struct phy_provider *phy_provider; 3375 int ret; 3376 3377 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3378 if (!qmp) 3379 return -ENOMEM; 3380 3381 qmp->dev = dev; 3382 3383 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3384 3385 qmp->cfg = of_device_get_match_data(dev); 3386 if (!qmp->cfg) 3387 return -EINVAL; 3388 3389 mutex_init(&qmp->phy_mutex); 3390 3391 ret = qmp_combo_reset_init(qmp); 3392 if (ret) 3393 return ret; 3394 3395 ret = qmp_combo_vreg_init(qmp); 3396 if (ret) 3397 return ret; 3398 3399 ret = qmp_combo_typec_switch_register(qmp); 3400 if (ret) 3401 return ret; 3402 3403 ret = drm_aux_bridge_register(dev); 3404 if (ret) 3405 return ret; 3406 3407 /* Check for legacy binding with child nodes. */ 3408 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3409 if (usb_np) { 3410 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3411 if (!dp_np) { 3412 of_node_put(usb_np); 3413 return -EINVAL; 3414 } 3415 3416 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3417 } else { 3418 usb_np = of_node_get(dev->of_node); 3419 dp_np = of_node_get(dev->of_node); 3420 3421 ret = qmp_combo_parse_dt(qmp); 3422 } 3423 if (ret) 3424 goto err_node_put; 3425 3426 pm_runtime_set_active(dev); 3427 ret = devm_pm_runtime_enable(dev); 3428 if (ret) 3429 goto err_node_put; 3430 /* 3431 * Prevent runtime pm from being ON by default. Users can enable 3432 * it using power/control in sysfs. 3433 */ 3434 pm_runtime_forbid(dev); 3435 3436 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3437 if (ret) 3438 goto err_node_put; 3439 3440 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3441 if (IS_ERR(qmp->usb_phy)) { 3442 ret = PTR_ERR(qmp->usb_phy); 3443 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3444 goto err_node_put; 3445 } 3446 3447 phy_set_drvdata(qmp->usb_phy, qmp); 3448 3449 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3450 if (IS_ERR(qmp->dp_phy)) { 3451 ret = PTR_ERR(qmp->dp_phy); 3452 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3453 goto err_node_put; 3454 } 3455 3456 phy_set_drvdata(qmp->dp_phy, qmp); 3457 3458 dev_set_drvdata(dev, qmp); 3459 3460 if (usb_np == dev->of_node) 3461 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3462 else 3463 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3464 3465 of_node_put(usb_np); 3466 of_node_put(dp_np); 3467 3468 return PTR_ERR_OR_ZERO(phy_provider); 3469 3470 err_node_put: 3471 of_node_put(usb_np); 3472 of_node_put(dp_np); 3473 return ret; 3474 } 3475 3476 static const struct of_device_id qmp_combo_of_match_table[] = { 3477 { 3478 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3479 .data = &sc7180_usb3dpphy_cfg, 3480 }, 3481 { 3482 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3483 .data = &sm8250_usb3dpphy_cfg, 3484 }, 3485 { 3486 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3487 .data = &sc8180x_usb3dpphy_cfg, 3488 }, 3489 { 3490 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3491 .data = &sc8280xp_usb43dpphy_cfg, 3492 }, 3493 { 3494 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3495 .data = &sdm845_usb3dpphy_cfg, 3496 }, 3497 { 3498 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3499 .data = &sm6350_usb3dpphy_cfg, 3500 }, 3501 { 3502 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3503 .data = &sc8180x_usb3dpphy_cfg, 3504 }, 3505 { 3506 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3507 .data = &sm8250_usb3dpphy_cfg, 3508 }, 3509 { 3510 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3511 .data = &sm8350_usb3dpphy_cfg, 3512 }, 3513 { 3514 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3515 .data = &sm8350_usb3dpphy_cfg, 3516 }, 3517 { 3518 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3519 .data = &sm8550_usb3dpphy_cfg, 3520 }, 3521 { } 3522 }; 3523 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3524 3525 static struct platform_driver qmp_combo_driver = { 3526 .probe = qmp_combo_probe, 3527 .driver = { 3528 .name = "qcom-qmp-combo-phy", 3529 .pm = &qmp_combo_pm_ops, 3530 .of_match_table = qmp_combo_of_match_table, 3531 }, 3532 }; 3533 3534 module_platform_driver(qmp_combo_driver); 3535 3536 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3537 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3538 MODULE_LICENSE("GPL v2"); 3539