1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy-qcom-qmp.h> 24 25 #include "phy-qcom-qmp.h" 26 #include "phy-qcom-qmp-pcs-misc-v3.h" 27 #include "phy-qcom-qmp-pcs-usb-v4.h" 28 #include "phy-qcom-qmp-pcs-usb-v5.h" 29 #include "phy-qcom-qmp-pcs-usb-v6.h" 30 31 /* QPHY_SW_RESET bit */ 32 #define SW_RESET BIT(0) 33 /* QPHY_POWER_DOWN_CONTROL */ 34 #define SW_PWRDN BIT(0) 35 /* QPHY_START_CONTROL bits */ 36 #define SERDES_START BIT(0) 37 #define PCS_START BIT(1) 38 /* QPHY_PCS_STATUS bit */ 39 #define PHYSTATUS BIT(6) 40 41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 42 /* DP PHY soft reset */ 43 #define SW_DPPHY_RESET BIT(0) 44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 45 #define SW_DPPHY_RESET_MUX BIT(1) 46 /* USB3 PHY soft reset */ 47 #define SW_USB3PHY_RESET BIT(2) 48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 49 #define SW_USB3PHY_RESET_MUX BIT(3) 50 51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 52 #define USB3_MODE BIT(0) /* enables USB3 mode */ 53 #define DP_MODE BIT(1) /* enables DP mode */ 54 55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 56 #define ARCVR_DTCT_EN BIT(0) 57 #define ALFPS_DTCT_EN BIT(1) 58 #define ARCVR_DTCT_EVENT_SEL BIT(4) 59 60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 61 #define IRQ_CLEAR BIT(0) 62 63 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 64 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 65 66 #define PHY_INIT_COMPLETE_TIMEOUT 10000 67 68 struct qmp_phy_init_tbl { 69 unsigned int offset; 70 unsigned int val; 71 /* 72 * mask of lanes for which this register is written 73 * for cases when second lane needs different values 74 */ 75 u8 lane_mask; 76 }; 77 78 #define QMP_PHY_INIT_CFG(o, v) \ 79 { \ 80 .offset = o, \ 81 .val = v, \ 82 .lane_mask = 0xff, \ 83 } 84 85 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 .lane_mask = l, \ 90 } 91 92 /* set of registers with offsets different per-PHY */ 93 enum qphy_reg_layout { 94 /* PCS registers */ 95 QPHY_SW_RESET, 96 QPHY_START_CTRL, 97 QPHY_PCS_STATUS, 98 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 99 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 100 QPHY_PCS_POWER_DOWN_CONTROL, 101 /* Keep last to ensure regs_layout arrays are properly initialized */ 102 QPHY_LAYOUT_SIZE 103 }; 104 105 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 107 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 108 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 109 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 110 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 111 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 112 }; 113 114 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 115 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 116 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 117 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 118 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 119 120 /* In PCS_USB */ 121 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 122 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 123 }; 124 125 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 162 }; 163 164 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 165 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 170 }; 171 172 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 173 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 174 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 175 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 176 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 177 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 178 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 179 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 180 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 181 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 182 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 183 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 186 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 194 }; 195 196 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 204 }; 205 206 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 214 }; 215 216 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 224 }; 225 226 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 234 }; 235 236 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 237 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 238 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 239 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 240 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 241 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 242 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 243 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 244 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 245 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 247 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 248 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 249 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 250 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 251 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 252 }; 253 254 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 255 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 256 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 257 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 258 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 259 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 260 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 264 }; 265 266 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 267 /* FLL settings */ 268 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 269 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 270 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 271 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 272 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 273 274 /* Lock Det settings */ 275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 279 280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 299 300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 304 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 305 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 306 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 307 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 308 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 309 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 311 }; 312 313 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 314 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 315 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 316 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 317 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 318 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 319 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 320 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 321 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 322 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 324 }; 325 326 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 327 /* FLL settings */ 328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 333 334 /* Lock Det settings */ 335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 338 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 339 340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 344 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 359 360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 372 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 375 }; 376 377 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 378 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 379 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 380 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 381 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 382 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 383 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 384 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 385 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 386 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 387 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 388 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 389 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 390 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 391 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 392 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 393 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 394 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 395 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 396 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 397 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 398 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 399 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 400 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 401 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 402 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 403 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 404 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 405 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 406 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 407 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 408 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 409 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 410 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 411 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 412 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 413 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 414 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 415 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 416 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 417 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 418 }; 419 420 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 421 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 422 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 423 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 424 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 425 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 426 }; 427 428 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 429 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 430 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 431 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 432 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 433 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 434 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 435 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 436 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 437 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 438 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 439 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 440 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 441 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 442 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 443 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 444 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 445 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 446 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 447 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 465 }; 466 467 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 468 /* Lock Det settings */ 469 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 470 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 471 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 472 473 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 474 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 475 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 476 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 477 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 478 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 479 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 480 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 481 }; 482 483 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 486 }; 487 488 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 489 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 490 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 491 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 492 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 493 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 494 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 495 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 496 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 497 }; 498 499 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 500 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 501 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 502 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 503 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 504 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 520 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 521 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 522 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 523 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 538 }; 539 540 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 541 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 542 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 543 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 544 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 546 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 547 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 548 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 549 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 550 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 551 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 552 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 553 }; 554 555 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 556 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 557 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 558 }; 559 560 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 561 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 562 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 563 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 564 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 565 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 566 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 567 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 568 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 569 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 570 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 571 }; 572 573 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 574 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 575 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 576 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 577 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 578 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 579 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 580 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 581 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 582 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 583 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 584 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 585 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 586 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 587 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 588 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 589 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 590 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 591 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 592 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 593 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 594 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 595 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 596 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 597 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 598 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 599 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 600 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 601 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 602 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 603 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 604 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 605 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 606 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 607 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 608 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 609 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 610 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 611 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 612 }; 613 614 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 617 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 618 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 619 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 620 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 621 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 622 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 623 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 624 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 625 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 626 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 627 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 628 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 629 }; 630 631 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 632 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 633 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 634 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 635 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 636 }; 637 638 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 639 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 640 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 641 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 642 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 643 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 644 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 645 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 646 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 647 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 648 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 649 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 650 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 651 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 652 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 653 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 654 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 655 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 656 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 657 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 658 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 659 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 660 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 661 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 662 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 663 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 664 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 665 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 666 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 667 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 668 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 669 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 670 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 671 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 672 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 673 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 674 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 675 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 676 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 677 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 678 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 679 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 680 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 681 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 682 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 683 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 684 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 685 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 686 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 687 }; 688 689 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 690 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 691 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 692 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 693 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 694 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 695 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 696 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 697 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 698 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 699 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 700 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 701 }; 702 703 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 704 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 705 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 706 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 707 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 708 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 709 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 710 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 711 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 712 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 713 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 714 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 715 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 716 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 717 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 718 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 719 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 720 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 721 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 722 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 723 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 724 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 725 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 726 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 727 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 728 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 729 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 730 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 731 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 732 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 733 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 734 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 735 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 736 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 737 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 738 739 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 740 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 741 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 742 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 743 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 744 745 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 746 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 747 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 748 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 749 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 750 }; 751 752 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 753 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 754 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 755 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 756 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 757 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 758 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99), 759 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 760 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 761 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a), 762 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 763 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 764 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 765 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b), 766 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10), 767 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 768 }; 769 770 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 771 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 772 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 773 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 774 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 775 }; 776 777 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 794 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 795 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 796 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 797 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 798 }; 799 800 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 801 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 802 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 803 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 804 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 805 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 806 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 807 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 808 }; 809 810 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 818 }; 819 820 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 828 }; 829 830 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 838 }; 839 840 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 841 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 842 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 843 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 844 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 845 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 846 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 847 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 848 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 849 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 850 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 851 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 852 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 853 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 854 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 855 }; 856 857 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 881 }; 882 883 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 884 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 885 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 886 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 887 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 888 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 889 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 890 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 891 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 892 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 893 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 894 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 895 }; 896 897 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 898 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 899 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 900 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 901 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 902 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 903 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 904 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 905 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 906 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 907 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 908 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 909 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 910 }; 911 912 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 913 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 914 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 915 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 916 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 933 }; 934 935 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 936 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 937 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 938 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 939 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 940 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 941 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 942 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 943 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 944 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 945 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 946 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 947 }; 948 949 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 950 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 951 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 952 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 953 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 954 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 955 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 956 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 957 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 958 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 959 }; 960 961 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 962 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 963 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 964 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 965 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 966 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 967 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 968 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 969 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 970 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 971 }; 972 973 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 983 }; 984 985 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 995 }; 996 997 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 998 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 999 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1000 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1001 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1002 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1003 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1004 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1005 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1006 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1007 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1008 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1009 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1010 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1011 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1012 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1013 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1014 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1015 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1016 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1017 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1018 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1019 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1020 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1021 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1022 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1023 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1024 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1026 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1034 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1036 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1045 }; 1046 1047 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1048 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1053 }; 1054 1055 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1056 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1090 }; 1091 1092 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1093 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1094 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1095 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1096 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1097 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1098 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1099 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1100 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1101 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1102 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1103 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1104 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1105 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1106 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1107 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1108 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1109 }; 1110 1111 /* list of regulators */ 1112 struct qmp_regulator_data { 1113 const char *name; 1114 unsigned int enable_load; 1115 }; 1116 1117 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1118 { .name = "vdda-phy", .enable_load = 21800 }, 1119 { .name = "vdda-pll", .enable_load = 36000 }, 1120 }; 1121 1122 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1123 { 0x00, 0x0c, 0x15, 0x1a }, 1124 { 0x02, 0x0e, 0x16, 0xff }, 1125 { 0x02, 0x11, 0xff, 0xff }, 1126 { 0x04, 0xff, 0xff, 0xff } 1127 }; 1128 1129 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1130 { 0x02, 0x12, 0x16, 0x1a }, 1131 { 0x09, 0x19, 0x1f, 0xff }, 1132 { 0x10, 0x1f, 0xff, 0xff }, 1133 { 0x1f, 0xff, 0xff, 0xff } 1134 }; 1135 1136 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1137 { 0x00, 0x0c, 0x14, 0x19 }, 1138 { 0x00, 0x0b, 0x12, 0xff }, 1139 { 0x00, 0x0b, 0xff, 0xff }, 1140 { 0x04, 0xff, 0xff, 0xff } 1141 }; 1142 1143 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1144 { 0x08, 0x0f, 0x16, 0x1f }, 1145 { 0x11, 0x1e, 0x1f, 0xff }, 1146 { 0x19, 0x1f, 0xff, 0xff }, 1147 { 0x1f, 0xff, 0xff, 0xff } 1148 }; 1149 1150 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1151 { 0x00, 0x0c, 0x15, 0x1b }, 1152 { 0x02, 0x0e, 0x16, 0xff }, 1153 { 0x02, 0x11, 0xff, 0xff }, 1154 { 0x04, 0xff, 0xff, 0xff } 1155 }; 1156 1157 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1158 { 0x00, 0x0d, 0x14, 0x1a }, 1159 { 0x00, 0x0e, 0x15, 0xff }, 1160 { 0x00, 0x0d, 0xff, 0xff }, 1161 { 0x03, 0xff, 0xff, 0xff } 1162 }; 1163 1164 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1165 { 0x08, 0x0f, 0x16, 0x1f }, 1166 { 0x11, 0x1e, 0x1f, 0xff }, 1167 { 0x16, 0x1f, 0xff, 0xff }, 1168 { 0x1f, 0xff, 0xff, 0xff } 1169 }; 1170 1171 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1172 { 0x20, 0x2c, 0x35, 0x3b }, 1173 { 0x22, 0x2e, 0x36, 0xff }, 1174 { 0x22, 0x31, 0xff, 0xff }, 1175 { 0x24, 0xff, 0xff, 0xff } 1176 }; 1177 1178 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1179 { 0x22, 0x32, 0x36, 0x3a }, 1180 { 0x29, 0x39, 0x3f, 0xff }, 1181 { 0x30, 0x3f, 0xff, 0xff }, 1182 { 0x3f, 0xff, 0xff, 0xff } 1183 }; 1184 1185 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1186 { 0x20, 0x2d, 0x34, 0x3a }, 1187 { 0x20, 0x2e, 0x35, 0xff }, 1188 { 0x20, 0x2e, 0xff, 0xff }, 1189 { 0x24, 0xff, 0xff, 0xff } 1190 }; 1191 1192 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1193 { 0x28, 0x2f, 0x36, 0x3f }, 1194 { 0x31, 0x3e, 0x3f, 0xff }, 1195 { 0x36, 0x3f, 0xff, 0xff }, 1196 { 0x3f, 0xff, 0xff, 0xff } 1197 }; 1198 1199 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1200 { 0x20, 0x2d, 0x34, 0x3a }, 1201 { 0x20, 0x2e, 0x35, 0xff }, 1202 { 0x20, 0x2e, 0xff, 0xff }, 1203 { 0x22, 0xff, 0xff, 0xff } 1204 }; 1205 1206 struct qmp_combo; 1207 1208 struct qmp_combo_offsets { 1209 u16 com; 1210 u16 txa; 1211 u16 rxa; 1212 u16 txb; 1213 u16 rxb; 1214 u16 usb3_serdes; 1215 u16 usb3_pcs_misc; 1216 u16 usb3_pcs; 1217 u16 usb3_pcs_usb; 1218 u16 dp_serdes; 1219 u16 dp_txa; 1220 u16 dp_txb; 1221 u16 dp_dp_phy; 1222 }; 1223 1224 struct qmp_phy_cfg { 1225 const struct qmp_combo_offsets *offsets; 1226 1227 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1228 const struct qmp_phy_init_tbl *serdes_tbl; 1229 int serdes_tbl_num; 1230 const struct qmp_phy_init_tbl *tx_tbl; 1231 int tx_tbl_num; 1232 const struct qmp_phy_init_tbl *rx_tbl; 1233 int rx_tbl_num; 1234 const struct qmp_phy_init_tbl *pcs_tbl; 1235 int pcs_tbl_num; 1236 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1237 int pcs_usb_tbl_num; 1238 1239 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1240 int dp_serdes_tbl_num; 1241 const struct qmp_phy_init_tbl *dp_tx_tbl; 1242 int dp_tx_tbl_num; 1243 1244 /* Init sequence for DP PHY block link rates */ 1245 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1246 int serdes_tbl_rbr_num; 1247 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1248 int serdes_tbl_hbr_num; 1249 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1250 int serdes_tbl_hbr2_num; 1251 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1252 int serdes_tbl_hbr3_num; 1253 1254 /* DP PHY swing and pre_emphasis tables */ 1255 const u8 (*swing_hbr_rbr)[4][4]; 1256 const u8 (*swing_hbr3_hbr2)[4][4]; 1257 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1258 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1259 1260 /* DP PHY callbacks */ 1261 int (*configure_dp_phy)(struct qmp_combo *qmp); 1262 void (*configure_dp_tx)(struct qmp_combo *qmp); 1263 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1264 void (*dp_aux_init)(struct qmp_combo *qmp); 1265 1266 /* clock ids to be requested */ 1267 const char * const *clk_list; 1268 int num_clks; 1269 /* resets to be requested */ 1270 const char * const *reset_list; 1271 int num_resets; 1272 /* regulators to be requested */ 1273 const struct qmp_regulator_data *vreg_list; 1274 int num_vregs; 1275 1276 /* array of registers with different offsets */ 1277 const unsigned int *regs; 1278 1279 /* true, if PHY needs delay after POWER_DOWN */ 1280 bool has_pwrdn_delay; 1281 1282 /* Offset from PCS to PCS_USB region */ 1283 unsigned int pcs_usb_offset; 1284 1285 }; 1286 1287 struct qmp_combo { 1288 struct device *dev; 1289 1290 const struct qmp_phy_cfg *cfg; 1291 1292 void __iomem *com; 1293 1294 void __iomem *serdes; 1295 void __iomem *tx; 1296 void __iomem *rx; 1297 void __iomem *pcs; 1298 void __iomem *tx2; 1299 void __iomem *rx2; 1300 void __iomem *pcs_misc; 1301 void __iomem *pcs_usb; 1302 1303 void __iomem *dp_serdes; 1304 void __iomem *dp_tx; 1305 void __iomem *dp_tx2; 1306 void __iomem *dp_dp_phy; 1307 1308 struct clk *pipe_clk; 1309 struct clk_bulk_data *clks; 1310 struct reset_control_bulk_data *resets; 1311 struct regulator_bulk_data *vregs; 1312 1313 struct mutex phy_mutex; 1314 int init_count; 1315 1316 struct phy *usb_phy; 1317 enum phy_mode mode; 1318 1319 struct phy *dp_phy; 1320 unsigned int dp_aux_cfg; 1321 struct phy_configure_opts_dp dp_opts; 1322 1323 struct clk_fixed_rate pipe_clk_fixed; 1324 struct clk_hw dp_link_hw; 1325 struct clk_hw dp_pixel_hw; 1326 }; 1327 1328 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1329 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1330 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1331 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1332 1333 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1334 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1335 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1336 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1337 1338 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp); 1339 1340 static void qmp_v6_dp_aux_init(struct qmp_combo *qmp); 1341 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp); 1342 1343 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1344 { 1345 u32 reg; 1346 1347 reg = readl(base + offset); 1348 reg |= val; 1349 writel(reg, base + offset); 1350 1351 /* ensure that above write is through */ 1352 readl(base + offset); 1353 } 1354 1355 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1356 { 1357 u32 reg; 1358 1359 reg = readl(base + offset); 1360 reg &= ~val; 1361 writel(reg, base + offset); 1362 1363 /* ensure that above write is through */ 1364 readl(base + offset); 1365 } 1366 1367 /* list of clocks required by phy */ 1368 static const char * const qmp_v3_phy_clk_l[] = { 1369 "aux", "cfg_ahb", "ref", "com_aux", 1370 }; 1371 1372 static const char * const qmp_v4_phy_clk_l[] = { 1373 "aux", "ref", "com_aux", 1374 }; 1375 1376 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1377 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1378 "aux", "ref_clk_src", "com_aux" 1379 }; 1380 1381 /* list of resets */ 1382 static const char * const msm8996_usb3phy_reset_l[] = { 1383 "phy", "common", 1384 }; 1385 1386 static const char * const sc7180_usb3phy_reset_l[] = { 1387 "phy", 1388 }; 1389 1390 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1391 .com = 0x0000, 1392 .txa = 0x1200, 1393 .rxa = 0x1400, 1394 .txb = 0x1600, 1395 .rxb = 0x1800, 1396 .usb3_serdes = 0x1000, 1397 .usb3_pcs_misc = 0x1a00, 1398 .usb3_pcs = 0x1c00, 1399 .dp_serdes = 0x2000, 1400 .dp_txa = 0x2200, 1401 .dp_txb = 0x2600, 1402 .dp_dp_phy = 0x2a00, 1403 }; 1404 1405 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1406 .com = 0x0000, 1407 .txa = 0x0400, 1408 .rxa = 0x0600, 1409 .txb = 0x0a00, 1410 .rxb = 0x0c00, 1411 .usb3_serdes = 0x1000, 1412 .usb3_pcs_misc = 0x1200, 1413 .usb3_pcs = 0x1400, 1414 .usb3_pcs_usb = 0x1700, 1415 .dp_serdes = 0x2000, 1416 .dp_dp_phy = 0x2200, 1417 }; 1418 1419 static const struct qmp_combo_offsets qmp_combo_offsets_v6 = { 1420 .com = 0x0000, 1421 .txa = 0x1200, 1422 .rxa = 0x1400, 1423 .txb = 0x1600, 1424 .rxb = 0x1800, 1425 .usb3_serdes = 0x1000, 1426 .usb3_pcs_misc = 0x1a00, 1427 .usb3_pcs = 0x1c00, 1428 .usb3_pcs_usb = 0x1f00, 1429 .dp_serdes = 0x2000, 1430 .dp_txa = 0x2200, 1431 .dp_txb = 0x2600, 1432 .dp_dp_phy = 0x2a00, 1433 }; 1434 1435 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1436 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1437 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1438 .tx_tbl = qmp_v3_usb3_tx_tbl, 1439 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1440 .rx_tbl = qmp_v3_usb3_rx_tbl, 1441 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1442 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1443 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1444 1445 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1446 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1447 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1448 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1449 1450 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1451 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1452 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1453 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1454 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1455 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1456 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1457 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1458 1459 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1460 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1461 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1462 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1463 1464 .dp_aux_init = qmp_v3_dp_aux_init, 1465 .configure_dp_tx = qmp_v3_configure_dp_tx, 1466 .configure_dp_phy = qmp_v3_configure_dp_phy, 1467 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1468 1469 .clk_list = qmp_v3_phy_clk_l, 1470 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1471 .reset_list = sc7180_usb3phy_reset_l, 1472 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1473 .vreg_list = qmp_phy_vreg_l, 1474 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1475 .regs = qmp_v3_usb3phy_regs_layout, 1476 1477 .has_pwrdn_delay = true, 1478 }; 1479 1480 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1481 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1482 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1483 .tx_tbl = qmp_v3_usb3_tx_tbl, 1484 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1485 .rx_tbl = qmp_v3_usb3_rx_tbl, 1486 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1487 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1488 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1489 1490 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1491 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1492 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1493 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1494 1495 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1496 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1497 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1498 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1499 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1500 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1501 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1502 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1503 1504 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1505 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1506 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1507 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1508 1509 .dp_aux_init = qmp_v3_dp_aux_init, 1510 .configure_dp_tx = qmp_v3_configure_dp_tx, 1511 .configure_dp_phy = qmp_v3_configure_dp_phy, 1512 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1513 1514 .clk_list = qmp_v3_phy_clk_l, 1515 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1516 .reset_list = msm8996_usb3phy_reset_l, 1517 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1518 .vreg_list = qmp_phy_vreg_l, 1519 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1520 .regs = qmp_v3_usb3phy_regs_layout, 1521 1522 .has_pwrdn_delay = true, 1523 }; 1524 1525 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1526 .serdes_tbl = sm8150_usb3_serdes_tbl, 1527 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1528 .tx_tbl = sm8150_usb3_tx_tbl, 1529 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1530 .rx_tbl = sm8150_usb3_rx_tbl, 1531 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1532 .pcs_tbl = sm8150_usb3_pcs_tbl, 1533 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1534 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1535 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1536 1537 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1538 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1539 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1540 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1541 1542 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1543 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1544 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1545 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1546 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1547 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1548 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1549 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1550 1551 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1552 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1553 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1554 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1555 1556 .dp_aux_init = qmp_v4_dp_aux_init, 1557 .configure_dp_tx = qmp_v4_configure_dp_tx, 1558 .configure_dp_phy = qmp_v4_configure_dp_phy, 1559 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1560 1561 .clk_list = qmp_v4_phy_clk_l, 1562 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1563 .reset_list = msm8996_usb3phy_reset_l, 1564 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1565 .vreg_list = qmp_phy_vreg_l, 1566 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1567 .regs = qmp_v4_usb3phy_regs_layout, 1568 .pcs_usb_offset = 0x300, 1569 1570 .has_pwrdn_delay = true, 1571 }; 1572 1573 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1574 .offsets = &qmp_combo_offsets_v5, 1575 1576 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1577 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1578 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1579 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1580 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1581 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1582 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1583 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1584 1585 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1586 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1587 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1588 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1589 1590 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1591 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1592 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1593 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1594 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1595 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1596 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1597 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1598 1599 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1600 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1601 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1602 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1603 1604 .dp_aux_init = qmp_v4_dp_aux_init, 1605 .configure_dp_tx = qmp_v4_configure_dp_tx, 1606 .configure_dp_phy = qmp_v5_configure_dp_phy, 1607 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1608 1609 .clk_list = qmp_v4_phy_clk_l, 1610 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1611 .reset_list = msm8996_usb3phy_reset_l, 1612 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1613 .vreg_list = qmp_phy_vreg_l, 1614 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1615 .regs = qmp_v4_usb3phy_regs_layout, 1616 }; 1617 1618 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1619 .offsets = &qmp_combo_offsets_v3, 1620 1621 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1622 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1623 .tx_tbl = qmp_v3_usb3_tx_tbl, 1624 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1625 .rx_tbl = sm6350_usb3_rx_tbl, 1626 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1627 .pcs_tbl = sm6350_usb3_pcs_tbl, 1628 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1629 1630 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1631 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1632 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1633 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1634 1635 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1636 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1637 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1638 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1639 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1640 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1641 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1642 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1643 1644 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1645 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1646 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1647 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1648 1649 .dp_aux_init = qmp_v3_dp_aux_init, 1650 .configure_dp_tx = qmp_v3_configure_dp_tx, 1651 .configure_dp_phy = qmp_v3_configure_dp_phy, 1652 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1653 1654 .clk_list = qmp_v4_phy_clk_l, 1655 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1656 .reset_list = msm8996_usb3phy_reset_l, 1657 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1658 .vreg_list = qmp_phy_vreg_l, 1659 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1660 .regs = qmp_v3_usb3phy_regs_layout, 1661 }; 1662 1663 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1664 .serdes_tbl = sm8150_usb3_serdes_tbl, 1665 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1666 .tx_tbl = sm8250_usb3_tx_tbl, 1667 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1668 .rx_tbl = sm8250_usb3_rx_tbl, 1669 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1670 .pcs_tbl = sm8250_usb3_pcs_tbl, 1671 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1672 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1673 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1674 1675 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1676 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1677 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1678 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1679 1680 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1681 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1682 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1683 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1684 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1685 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1686 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1687 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1688 1689 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1690 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1691 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1692 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1693 1694 .dp_aux_init = qmp_v4_dp_aux_init, 1695 .configure_dp_tx = qmp_v4_configure_dp_tx, 1696 .configure_dp_phy = qmp_v4_configure_dp_phy, 1697 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1698 1699 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1700 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1701 .reset_list = msm8996_usb3phy_reset_l, 1702 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1703 .vreg_list = qmp_phy_vreg_l, 1704 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1705 .regs = qmp_v4_usb3phy_regs_layout, 1706 .pcs_usb_offset = 0x300, 1707 1708 .has_pwrdn_delay = true, 1709 }; 1710 1711 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1712 .offsets = &qmp_combo_offsets_v3, 1713 1714 .serdes_tbl = sm8150_usb3_serdes_tbl, 1715 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1716 .tx_tbl = sm8350_usb3_tx_tbl, 1717 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1718 .rx_tbl = sm8350_usb3_rx_tbl, 1719 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1720 .pcs_tbl = sm8350_usb3_pcs_tbl, 1721 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1722 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1723 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1724 1725 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1726 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1727 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1728 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1729 1730 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1731 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1732 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1733 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1734 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1735 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1736 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1737 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1738 1739 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1740 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1741 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1742 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1743 1744 .dp_aux_init = qmp_v4_dp_aux_init, 1745 .configure_dp_tx = qmp_v4_configure_dp_tx, 1746 .configure_dp_phy = qmp_v4_configure_dp_phy, 1747 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1748 1749 .clk_list = qmp_v4_phy_clk_l, 1750 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1751 .reset_list = msm8996_usb3phy_reset_l, 1752 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1753 .vreg_list = qmp_phy_vreg_l, 1754 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1755 .regs = qmp_v4_usb3phy_regs_layout, 1756 1757 .has_pwrdn_delay = true, 1758 }; 1759 1760 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1761 .offsets = &qmp_combo_offsets_v6, 1762 1763 .serdes_tbl = sm8550_usb3_serdes_tbl, 1764 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1765 .tx_tbl = sm8550_usb3_tx_tbl, 1766 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1767 .rx_tbl = sm8550_usb3_rx_tbl, 1768 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1769 .pcs_tbl = sm8550_usb3_pcs_tbl, 1770 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1771 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1772 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1773 1774 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1775 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1776 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1777 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1778 1779 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1780 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1781 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1782 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1783 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1784 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1785 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1786 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1787 1788 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1789 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1790 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1791 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1792 1793 .dp_aux_init = qmp_v6_dp_aux_init, 1794 .configure_dp_tx = qmp_v4_configure_dp_tx, 1795 .configure_dp_phy = qmp_v6_configure_dp_phy, 1796 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1797 1798 .regs = qmp_v4_usb3phy_regs_layout, 1799 .clk_list = qmp_v4_phy_clk_l, 1800 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1801 .reset_list = msm8996_usb3phy_reset_l, 1802 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1803 .vreg_list = qmp_phy_vreg_l, 1804 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1805 }; 1806 1807 static void qmp_combo_configure_lane(void __iomem *base, 1808 const struct qmp_phy_init_tbl tbl[], 1809 int num, 1810 u8 lane_mask) 1811 { 1812 int i; 1813 const struct qmp_phy_init_tbl *t = tbl; 1814 1815 if (!t) 1816 return; 1817 1818 for (i = 0; i < num; i++, t++) { 1819 if (!(t->lane_mask & lane_mask)) 1820 continue; 1821 1822 writel(t->val, base + t->offset); 1823 } 1824 } 1825 1826 static void qmp_combo_configure(void __iomem *base, 1827 const struct qmp_phy_init_tbl tbl[], 1828 int num) 1829 { 1830 qmp_combo_configure_lane(base, tbl, num, 0xff); 1831 } 1832 1833 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1834 { 1835 const struct qmp_phy_cfg *cfg = qmp->cfg; 1836 void __iomem *serdes = qmp->dp_serdes; 1837 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1838 1839 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1840 1841 switch (dp_opts->link_rate) { 1842 case 1620: 1843 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1844 cfg->serdes_tbl_rbr_num); 1845 break; 1846 case 2700: 1847 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1848 cfg->serdes_tbl_hbr_num); 1849 break; 1850 case 5400: 1851 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1852 cfg->serdes_tbl_hbr2_num); 1853 break; 1854 case 8100: 1855 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1856 cfg->serdes_tbl_hbr3_num); 1857 break; 1858 default: 1859 /* Other link rates aren't supported */ 1860 return -EINVAL; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1867 { 1868 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1869 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1870 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1871 1872 /* Turn on BIAS current for PHY/PLL */ 1873 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1874 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1875 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1876 1877 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1878 1879 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1880 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1881 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1882 DP_PHY_PD_CTL_DP_CLAMP_EN, 1883 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1884 1885 writel(QSERDES_V3_COM_BIAS_EN | 1886 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1887 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1888 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1889 qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN); 1890 1891 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1892 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1893 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1894 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1895 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1896 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1897 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1898 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1899 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1900 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1901 qmp->dp_aux_cfg = 0; 1902 1903 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1904 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1905 PHY_AUX_REQ_ERR_MASK, 1906 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1907 } 1908 1909 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp, 1910 unsigned int drv_lvl_reg, unsigned int emp_post_reg) 1911 { 1912 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1913 const struct qmp_phy_cfg *cfg = qmp->cfg; 1914 unsigned int v_level = 0, p_level = 0; 1915 u8 voltage_swing_cfg, pre_emphasis_cfg; 1916 int i; 1917 1918 for (i = 0; i < dp_opts->lanes; i++) { 1919 v_level = max(v_level, dp_opts->voltage[i]); 1920 p_level = max(p_level, dp_opts->pre[i]); 1921 } 1922 1923 if (dp_opts->link_rate <= 2700) { 1924 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1925 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1926 } else { 1927 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1928 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1929 } 1930 1931 /* TODO: Move check to config check */ 1932 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1933 return -EINVAL; 1934 1935 /* Enable MUX to use Cursor values from these registers */ 1936 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 1937 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 1938 1939 writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg); 1940 writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg); 1941 writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg); 1942 writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg); 1943 1944 return 0; 1945 } 1946 1947 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 1948 { 1949 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1950 u32 bias_en, drvr_en; 1951 1952 if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL, 1953 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0) 1954 return; 1955 1956 if (dp_opts->lanes == 1) { 1957 bias_en = 0x3e; 1958 drvr_en = 0x13; 1959 } else { 1960 bias_en = 0x3f; 1961 drvr_en = 0x10; 1962 } 1963 1964 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1965 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1966 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 1967 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 1968 } 1969 1970 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 1971 { 1972 u32 val; 1973 bool reverse = false; 1974 1975 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1976 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 1977 1978 /* 1979 * TODO: Assume orientation is CC1 for now and two lanes, need to 1980 * use type-c connector to understand orientation and lanes. 1981 * 1982 * Otherwise val changes to be like below if this code understood 1983 * the orientation of the type-c cable. 1984 * 1985 * if (lane_cnt == 4 || orientation == ORIENTATION_CC2) 1986 * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 1987 * if (lane_cnt == 4 || orientation == ORIENTATION_CC1) 1988 * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1989 * if (orientation == ORIENTATION_CC2) 1990 * writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE); 1991 */ 1992 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 1993 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1994 1995 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 1996 1997 return reverse; 1998 } 1999 2000 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2001 { 2002 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2003 u32 phy_vco_div, status; 2004 unsigned long pixel_freq; 2005 2006 qmp_combo_configure_dp_mode(qmp); 2007 2008 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2009 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2010 2011 switch (dp_opts->link_rate) { 2012 case 1620: 2013 phy_vco_div = 0x1; 2014 pixel_freq = 1620000000UL / 2; 2015 break; 2016 case 2700: 2017 phy_vco_div = 0x1; 2018 pixel_freq = 2700000000UL / 2; 2019 break; 2020 case 5400: 2021 phy_vco_div = 0x2; 2022 pixel_freq = 5400000000UL / 4; 2023 break; 2024 case 8100: 2025 phy_vco_div = 0x0; 2026 pixel_freq = 8100000000UL / 6; 2027 break; 2028 default: 2029 /* Other link rates aren't supported */ 2030 return -EINVAL; 2031 } 2032 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV); 2033 2034 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2035 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2036 2037 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2038 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2039 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2040 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2041 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2042 2043 writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL); 2044 2045 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V3_COM_C_READY_STATUS, 2046 status, 2047 ((status & BIT(0)) > 0), 2048 500, 2049 10000)) 2050 return -ETIMEDOUT; 2051 2052 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2053 2054 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 2055 status, 2056 ((status & BIT(1)) > 0), 2057 500, 2058 10000)) 2059 return -ETIMEDOUT; 2060 2061 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2062 udelay(2000); 2063 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2064 2065 return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, 2066 status, 2067 ((status & BIT(1)) > 0), 2068 500, 2069 10000); 2070 } 2071 2072 /* 2073 * We need to calibrate the aux setting here as many times 2074 * as the caller tries 2075 */ 2076 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2077 { 2078 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2079 u8 val; 2080 2081 qmp->dp_aux_cfg++; 2082 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2083 val = cfg1_settings[qmp->dp_aux_cfg]; 2084 2085 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2086 2087 return 0; 2088 } 2089 2090 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2091 { 2092 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2093 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2094 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2095 2096 /* Turn on BIAS current for PHY/PLL */ 2097 writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 2098 2099 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2100 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2101 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2102 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2103 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2104 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2105 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2106 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2107 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2108 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2109 qmp->dp_aux_cfg = 0; 2110 2111 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2112 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2113 PHY_AUX_REQ_ERR_MASK, 2114 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2115 } 2116 2117 static void qmp_v6_dp_aux_init(struct qmp_combo *qmp) 2118 { 2119 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2120 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2121 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2122 2123 /* Turn on BIAS current for PHY/PLL */ 2124 writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN); 2125 2126 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2127 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2128 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2129 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2130 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2131 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2132 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2133 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2134 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2135 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2136 qmp->dp_aux_cfg = 0; 2137 2138 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2139 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2140 PHY_AUX_REQ_ERR_MASK, 2141 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2142 } 2143 2144 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2145 { 2146 /* Program default values before writing proper values */ 2147 writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 2148 writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 2149 2150 writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 2151 writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 2152 2153 qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL, 2154 QSERDES_V4_TX_TX_EMP_POST1_LVL); 2155 } 2156 2157 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp, 2158 unsigned int com_resetm_ctrl_reg, 2159 unsigned int com_c_ready_status_reg, 2160 unsigned int dp_phy_status_reg) 2161 { 2162 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2163 u32 phy_vco_div, status; 2164 unsigned long pixel_freq; 2165 2166 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 2167 2168 qmp_combo_configure_dp_mode(qmp); 2169 2170 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2171 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2172 2173 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2174 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2175 2176 switch (dp_opts->link_rate) { 2177 case 1620: 2178 phy_vco_div = 0x1; 2179 pixel_freq = 1620000000UL / 2; 2180 break; 2181 case 2700: 2182 phy_vco_div = 0x1; 2183 pixel_freq = 2700000000UL / 2; 2184 break; 2185 case 5400: 2186 phy_vco_div = 0x2; 2187 pixel_freq = 5400000000UL / 4; 2188 break; 2189 case 8100: 2190 phy_vco_div = 0x0; 2191 pixel_freq = 8100000000UL / 6; 2192 break; 2193 default: 2194 /* Other link rates aren't supported */ 2195 return -EINVAL; 2196 } 2197 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 2198 2199 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2200 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2201 2202 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2203 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2204 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2205 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2206 2207 writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg); 2208 2209 if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg, 2210 status, 2211 ((status & BIT(0)) > 0), 2212 500, 2213 10000)) 2214 return -ETIMEDOUT; 2215 2216 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS, 2217 status, 2218 ((status & BIT(0)) > 0), 2219 500, 2220 10000)) 2221 return -ETIMEDOUT; 2222 2223 if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS, 2224 status, 2225 ((status & BIT(1)) > 0), 2226 500, 2227 10000)) 2228 return -ETIMEDOUT; 2229 2230 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2231 2232 if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg, 2233 status, 2234 ((status & BIT(0)) > 0), 2235 500, 2236 10000)) 2237 return -ETIMEDOUT; 2238 2239 if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg, 2240 status, 2241 ((status & BIT(1)) > 0), 2242 500, 2243 10000)) 2244 return -ETIMEDOUT; 2245 2246 return 0; 2247 } 2248 2249 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2250 { 2251 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2252 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2253 bool reverse = false; 2254 u32 status; 2255 int ret; 2256 2257 ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL, 2258 QSERDES_V4_COM_C_READY_STATUS, 2259 QSERDES_V4_DP_PHY_STATUS); 2260 if (ret < 0) 2261 return ret; 2262 2263 /* 2264 * At least for 7nm DP PHY this has to be done after enabling link 2265 * clock. 2266 */ 2267 2268 if (dp_opts->lanes == 1) { 2269 bias0_en = reverse ? 0x3e : 0x15; 2270 bias1_en = reverse ? 0x15 : 0x3e; 2271 drvr0_en = reverse ? 0x13 : 0x10; 2272 drvr1_en = reverse ? 0x10 : 0x13; 2273 } else if (dp_opts->lanes == 2) { 2274 bias0_en = reverse ? 0x3f : 0x15; 2275 bias1_en = reverse ? 0x15 : 0x3f; 2276 drvr0_en = 0x10; 2277 drvr1_en = 0x10; 2278 } else { 2279 bias0_en = 0x3f; 2280 bias1_en = 0x3f; 2281 drvr0_en = 0x10; 2282 drvr1_en = 0x10; 2283 } 2284 2285 writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2286 writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2287 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2288 writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2289 2290 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2291 udelay(2000); 2292 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2293 2294 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 2295 status, 2296 ((status & BIT(1)) > 0), 2297 500, 2298 10000)) 2299 return -ETIMEDOUT; 2300 2301 writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV); 2302 writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV); 2303 2304 writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 2305 writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 2306 2307 writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 2308 writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 2309 2310 return 0; 2311 } 2312 2313 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp) 2314 { 2315 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2316 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2317 bool reverse = false; 2318 u32 status; 2319 int ret; 2320 2321 ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL, 2322 QSERDES_V4_COM_C_READY_STATUS, 2323 QSERDES_V4_DP_PHY_STATUS); 2324 if (ret < 0) 2325 return ret; 2326 2327 if (dp_opts->lanes == 1) { 2328 bias0_en = reverse ? 0x3e : 0x1a; 2329 drvr0_en = reverse ? 0x13 : 0x10; 2330 bias1_en = reverse ? 0x15 : 0x3e; 2331 drvr1_en = reverse ? 0x10 : 0x13; 2332 } else if (dp_opts->lanes == 2) { 2333 bias0_en = reverse ? 0x3f : 0x15; 2334 drvr0_en = 0x10; 2335 bias1_en = reverse ? 0x15 : 0x3f; 2336 drvr1_en = 0x10; 2337 } else { 2338 bias0_en = 0x3f; 2339 bias1_en = 0x3f; 2340 drvr0_en = 0x10; 2341 drvr1_en = 0x10; 2342 } 2343 2344 writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 2345 writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 2346 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 2347 writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 2348 2349 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2350 udelay(2000); 2351 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2352 2353 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS, 2354 status, 2355 ((status & BIT(1)) > 0), 2356 500, 2357 10000)) 2358 return -ETIMEDOUT; 2359 2360 writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV); 2361 writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV); 2362 2363 writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL); 2364 writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL); 2365 2366 writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 2367 writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL); 2368 2369 return 0; 2370 } 2371 2372 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp) 2373 { 2374 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2375 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2376 bool reverse = false; 2377 u32 status; 2378 int ret; 2379 2380 ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL, 2381 QSERDES_V6_COM_C_READY_STATUS, 2382 QSERDES_V6_DP_PHY_STATUS); 2383 if (ret < 0) 2384 return ret; 2385 2386 if (dp_opts->lanes == 1) { 2387 bias0_en = reverse ? 0x3e : 0x1a; 2388 drvr0_en = reverse ? 0x13 : 0x10; 2389 bias1_en = reverse ? 0x15 : 0x3e; 2390 drvr1_en = reverse ? 0x10 : 0x13; 2391 } else if (dp_opts->lanes == 2) { 2392 bias0_en = reverse ? 0x3f : 0x15; 2393 drvr0_en = 0x10; 2394 bias1_en = reverse ? 0x15 : 0x3f; 2395 drvr1_en = 0x10; 2396 } else { 2397 bias0_en = 0x3f; 2398 bias1_en = 0x3f; 2399 drvr0_en = 0x10; 2400 drvr1_en = 0x10; 2401 } 2402 2403 writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2404 writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2405 writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2406 writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2407 2408 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2409 udelay(2000); 2410 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2411 2412 if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS, 2413 status, 2414 ((status & BIT(1)) > 0), 2415 500, 2416 10000)) 2417 return -ETIMEDOUT; 2418 2419 writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV); 2420 writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV); 2421 2422 writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL); 2423 writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL); 2424 2425 writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL); 2426 writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL); 2427 2428 return 0; 2429 } 2430 2431 /* 2432 * We need to calibrate the aux setting here as many times 2433 * as the caller tries 2434 */ 2435 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2436 { 2437 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2438 u8 val; 2439 2440 qmp->dp_aux_cfg++; 2441 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2442 val = cfg1_settings[qmp->dp_aux_cfg]; 2443 2444 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2445 2446 return 0; 2447 } 2448 2449 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2450 { 2451 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2452 struct qmp_combo *qmp = phy_get_drvdata(phy); 2453 const struct qmp_phy_cfg *cfg = qmp->cfg; 2454 2455 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2456 if (qmp->dp_opts.set_voltages) { 2457 cfg->configure_dp_tx(qmp); 2458 qmp->dp_opts.set_voltages = 0; 2459 } 2460 2461 return 0; 2462 } 2463 2464 static int qmp_combo_dp_calibrate(struct phy *phy) 2465 { 2466 struct qmp_combo *qmp = phy_get_drvdata(phy); 2467 const struct qmp_phy_cfg *cfg = qmp->cfg; 2468 2469 if (cfg->calibrate_dp_phy) 2470 return cfg->calibrate_dp_phy(qmp); 2471 2472 return 0; 2473 } 2474 2475 static int qmp_combo_com_init(struct qmp_combo *qmp) 2476 { 2477 const struct qmp_phy_cfg *cfg = qmp->cfg; 2478 void __iomem *com = qmp->com; 2479 int ret; 2480 2481 mutex_lock(&qmp->phy_mutex); 2482 if (qmp->init_count++) { 2483 mutex_unlock(&qmp->phy_mutex); 2484 return 0; 2485 } 2486 2487 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2488 if (ret) { 2489 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2490 goto err_unlock; 2491 } 2492 2493 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2494 if (ret) { 2495 dev_err(qmp->dev, "reset assert failed\n"); 2496 goto err_disable_regulators; 2497 } 2498 2499 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2500 if (ret) { 2501 dev_err(qmp->dev, "reset deassert failed\n"); 2502 goto err_disable_regulators; 2503 } 2504 2505 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2506 if (ret) 2507 goto err_assert_reset; 2508 2509 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2510 2511 /* override hardware control for reset of qmp phy */ 2512 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2513 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2514 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2515 2516 /* Default type-c orientation, i.e CC1 */ 2517 qphy_setbits(com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 2518 2519 qphy_setbits(com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE); 2520 2521 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2522 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2523 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2524 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2525 2526 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2527 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2528 2529 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2530 SW_PWRDN); 2531 2532 mutex_unlock(&qmp->phy_mutex); 2533 2534 return 0; 2535 2536 err_assert_reset: 2537 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2538 err_disable_regulators: 2539 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2540 err_unlock: 2541 mutex_unlock(&qmp->phy_mutex); 2542 2543 return ret; 2544 } 2545 2546 static int qmp_combo_com_exit(struct qmp_combo *qmp) 2547 { 2548 const struct qmp_phy_cfg *cfg = qmp->cfg; 2549 2550 mutex_lock(&qmp->phy_mutex); 2551 if (--qmp->init_count) { 2552 mutex_unlock(&qmp->phy_mutex); 2553 return 0; 2554 } 2555 2556 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2557 2558 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2559 2560 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2561 2562 mutex_unlock(&qmp->phy_mutex); 2563 2564 return 0; 2565 } 2566 2567 static int qmp_combo_dp_init(struct phy *phy) 2568 { 2569 struct qmp_combo *qmp = phy_get_drvdata(phy); 2570 const struct qmp_phy_cfg *cfg = qmp->cfg; 2571 int ret; 2572 2573 ret = qmp_combo_com_init(qmp); 2574 if (ret) 2575 return ret; 2576 2577 cfg->dp_aux_init(qmp); 2578 2579 return 0; 2580 } 2581 2582 static int qmp_combo_dp_exit(struct phy *phy) 2583 { 2584 struct qmp_combo *qmp = phy_get_drvdata(phy); 2585 2586 qmp_combo_com_exit(qmp); 2587 2588 return 0; 2589 } 2590 2591 static int qmp_combo_dp_power_on(struct phy *phy) 2592 { 2593 struct qmp_combo *qmp = phy_get_drvdata(phy); 2594 const struct qmp_phy_cfg *cfg = qmp->cfg; 2595 void __iomem *tx = qmp->dp_tx; 2596 void __iomem *tx2 = qmp->dp_tx2; 2597 2598 qmp_combo_dp_serdes_init(qmp); 2599 2600 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2601 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2602 2603 /* Configure special DP tx tunings */ 2604 cfg->configure_dp_tx(qmp); 2605 2606 /* Configure link rate, swing, etc. */ 2607 cfg->configure_dp_phy(qmp); 2608 2609 return 0; 2610 } 2611 2612 static int qmp_combo_dp_power_off(struct phy *phy) 2613 { 2614 struct qmp_combo *qmp = phy_get_drvdata(phy); 2615 2616 /* Assert DP PHY power down */ 2617 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2618 2619 return 0; 2620 } 2621 2622 static int qmp_combo_usb_power_on(struct phy *phy) 2623 { 2624 struct qmp_combo *qmp = phy_get_drvdata(phy); 2625 const struct qmp_phy_cfg *cfg = qmp->cfg; 2626 void __iomem *serdes = qmp->serdes; 2627 void __iomem *tx = qmp->tx; 2628 void __iomem *rx = qmp->rx; 2629 void __iomem *tx2 = qmp->tx2; 2630 void __iomem *rx2 = qmp->rx2; 2631 void __iomem *pcs = qmp->pcs; 2632 void __iomem *status; 2633 unsigned int val; 2634 int ret; 2635 2636 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2637 2638 ret = clk_prepare_enable(qmp->pipe_clk); 2639 if (ret) { 2640 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2641 return ret; 2642 } 2643 2644 /* Tx, Rx, and PCS configurations */ 2645 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2646 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2647 2648 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2649 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2650 2651 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2652 2653 if (cfg->has_pwrdn_delay) 2654 usleep_range(10, 20); 2655 2656 /* Pull PHY out of reset state */ 2657 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2658 2659 /* start SerDes and Phy-Coding-Sublayer */ 2660 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2661 2662 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2663 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2664 PHY_INIT_COMPLETE_TIMEOUT); 2665 if (ret) { 2666 dev_err(qmp->dev, "phy initialization timed-out\n"); 2667 goto err_disable_pipe_clk; 2668 } 2669 2670 return 0; 2671 2672 err_disable_pipe_clk: 2673 clk_disable_unprepare(qmp->pipe_clk); 2674 2675 return ret; 2676 } 2677 2678 static int qmp_combo_usb_power_off(struct phy *phy) 2679 { 2680 struct qmp_combo *qmp = phy_get_drvdata(phy); 2681 const struct qmp_phy_cfg *cfg = qmp->cfg; 2682 2683 clk_disable_unprepare(qmp->pipe_clk); 2684 2685 /* PHY reset */ 2686 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2687 2688 /* stop SerDes and Phy-Coding-Sublayer */ 2689 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2690 SERDES_START | PCS_START); 2691 2692 /* Put PHY into POWER DOWN state: active low */ 2693 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2694 SW_PWRDN); 2695 2696 return 0; 2697 } 2698 2699 static int qmp_combo_usb_init(struct phy *phy) 2700 { 2701 struct qmp_combo *qmp = phy_get_drvdata(phy); 2702 int ret; 2703 2704 ret = qmp_combo_com_init(qmp); 2705 if (ret) 2706 return ret; 2707 2708 ret = qmp_combo_usb_power_on(phy); 2709 if (ret) 2710 qmp_combo_com_exit(qmp); 2711 2712 return ret; 2713 } 2714 2715 static int qmp_combo_usb_exit(struct phy *phy) 2716 { 2717 struct qmp_combo *qmp = phy_get_drvdata(phy); 2718 int ret; 2719 2720 ret = qmp_combo_usb_power_off(phy); 2721 if (ret) 2722 return ret; 2723 2724 return qmp_combo_com_exit(qmp); 2725 } 2726 2727 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2728 { 2729 struct qmp_combo *qmp = phy_get_drvdata(phy); 2730 2731 qmp->mode = mode; 2732 2733 return 0; 2734 } 2735 2736 static const struct phy_ops qmp_combo_usb_phy_ops = { 2737 .init = qmp_combo_usb_init, 2738 .exit = qmp_combo_usb_exit, 2739 .set_mode = qmp_combo_usb_set_mode, 2740 .owner = THIS_MODULE, 2741 }; 2742 2743 static const struct phy_ops qmp_combo_dp_phy_ops = { 2744 .init = qmp_combo_dp_init, 2745 .configure = qmp_combo_dp_configure, 2746 .power_on = qmp_combo_dp_power_on, 2747 .calibrate = qmp_combo_dp_calibrate, 2748 .power_off = qmp_combo_dp_power_off, 2749 .exit = qmp_combo_dp_exit, 2750 .owner = THIS_MODULE, 2751 }; 2752 2753 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2754 { 2755 const struct qmp_phy_cfg *cfg = qmp->cfg; 2756 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2757 void __iomem *pcs_misc = qmp->pcs_misc; 2758 u32 intr_mask; 2759 2760 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2761 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2762 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2763 else 2764 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2765 2766 /* Clear any pending interrupts status */ 2767 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2768 /* Writing 1 followed by 0 clears the interrupt */ 2769 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2770 2771 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2772 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2773 2774 /* Enable required PHY autonomous mode interrupts */ 2775 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2776 2777 /* Enable i/o clamp_n for autonomous mode */ 2778 if (pcs_misc) 2779 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2780 } 2781 2782 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2783 { 2784 const struct qmp_phy_cfg *cfg = qmp->cfg; 2785 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2786 void __iomem *pcs_misc = qmp->pcs_misc; 2787 2788 /* Disable i/o clamp_n on resume for normal mode */ 2789 if (pcs_misc) 2790 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2791 2792 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2793 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2794 2795 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2796 /* Writing 1 followed by 0 clears the interrupt */ 2797 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2798 } 2799 2800 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2801 { 2802 struct qmp_combo *qmp = dev_get_drvdata(dev); 2803 const struct qmp_phy_cfg *cfg = qmp->cfg; 2804 2805 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2806 2807 if (!qmp->init_count) { 2808 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2809 return 0; 2810 } 2811 2812 qmp_combo_enable_autonomous_mode(qmp); 2813 2814 clk_disable_unprepare(qmp->pipe_clk); 2815 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2816 2817 return 0; 2818 } 2819 2820 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2821 { 2822 struct qmp_combo *qmp = dev_get_drvdata(dev); 2823 const struct qmp_phy_cfg *cfg = qmp->cfg; 2824 int ret = 0; 2825 2826 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2827 2828 if (!qmp->init_count) { 2829 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2830 return 0; 2831 } 2832 2833 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2834 if (ret) 2835 return ret; 2836 2837 ret = clk_prepare_enable(qmp->pipe_clk); 2838 if (ret) { 2839 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2840 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2841 return ret; 2842 } 2843 2844 qmp_combo_disable_autonomous_mode(qmp); 2845 2846 return 0; 2847 } 2848 2849 static const struct dev_pm_ops qmp_combo_pm_ops = { 2850 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2851 qmp_combo_runtime_resume, NULL) 2852 }; 2853 2854 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2855 { 2856 const struct qmp_phy_cfg *cfg = qmp->cfg; 2857 struct device *dev = qmp->dev; 2858 int num = cfg->num_vregs; 2859 int ret, i; 2860 2861 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2862 if (!qmp->vregs) 2863 return -ENOMEM; 2864 2865 for (i = 0; i < num; i++) 2866 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2867 2868 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2869 if (ret) { 2870 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2871 return ret; 2872 } 2873 2874 for (i = 0; i < num; i++) { 2875 ret = regulator_set_load(qmp->vregs[i].consumer, 2876 cfg->vreg_list[i].enable_load); 2877 if (ret) { 2878 dev_err(dev, "failed to set load at %s\n", 2879 qmp->vregs[i].supply); 2880 return ret; 2881 } 2882 } 2883 2884 return 0; 2885 } 2886 2887 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2888 { 2889 const struct qmp_phy_cfg *cfg = qmp->cfg; 2890 struct device *dev = qmp->dev; 2891 int i; 2892 int ret; 2893 2894 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2895 sizeof(*qmp->resets), GFP_KERNEL); 2896 if (!qmp->resets) 2897 return -ENOMEM; 2898 2899 for (i = 0; i < cfg->num_resets; i++) 2900 qmp->resets[i].id = cfg->reset_list[i]; 2901 2902 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2903 if (ret) 2904 return dev_err_probe(dev, ret, "failed to get resets\n"); 2905 2906 return 0; 2907 } 2908 2909 static int qmp_combo_clk_init(struct qmp_combo *qmp) 2910 { 2911 const struct qmp_phy_cfg *cfg = qmp->cfg; 2912 struct device *dev = qmp->dev; 2913 int num = cfg->num_clks; 2914 int i; 2915 2916 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2917 if (!qmp->clks) 2918 return -ENOMEM; 2919 2920 for (i = 0; i < num; i++) 2921 qmp->clks[i].id = cfg->clk_list[i]; 2922 2923 return devm_clk_bulk_get(dev, num, qmp->clks); 2924 } 2925 2926 static void phy_clk_release_provider(void *res) 2927 { 2928 of_clk_del_provider(res); 2929 } 2930 2931 /* 2932 * Register a fixed rate pipe clock. 2933 * 2934 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2935 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2936 * by the PHY driver for its operations. 2937 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2938 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2939 * Below picture shows this relationship. 2940 * 2941 * +---------------+ 2942 * | PHY block |<<---------------------------------------+ 2943 * | | | 2944 * | +-------+ | +-----+ | 2945 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2946 * clk | +-------+ | +-----+ 2947 * +---------------+ 2948 */ 2949 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2950 { 2951 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2952 struct clk_init_data init = { }; 2953 char name[64]; 2954 2955 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2956 init.name = name; 2957 init.ops = &clk_fixed_rate_ops; 2958 2959 /* controllers using QMP phys use 125MHz pipe clock interface */ 2960 fixed->fixed_rate = 125000000; 2961 fixed->hw.init = &init; 2962 2963 return devm_clk_hw_register(qmp->dev, &fixed->hw); 2964 } 2965 2966 /* 2967 * Display Port PLL driver block diagram for branch clocks 2968 * 2969 * +------------------------------+ 2970 * | DP_VCO_CLK | 2971 * | | 2972 * | +-------------------+ | 2973 * | | (DP PLL/VCO) | | 2974 * | +---------+---------+ | 2975 * | v | 2976 * | +----------+-----------+ | 2977 * | | hsclk_divsel_clk_src | | 2978 * | +----------+-----------+ | 2979 * +------------------------------+ 2980 * | 2981 * +---------<---------v------------>----------+ 2982 * | | 2983 * +--------v----------------+ | 2984 * | dp_phy_pll_link_clk | | 2985 * | link_clk | | 2986 * +--------+----------------+ | 2987 * | | 2988 * | | 2989 * v v 2990 * Input to DISPCC block | 2991 * for link clk, crypto clk | 2992 * and interface clock | 2993 * | 2994 * | 2995 * +--------<------------+-----------------+---<---+ 2996 * | | | 2997 * +----v---------+ +--------v-----+ +--------v------+ 2998 * | vco_divided | | vco_divided | | vco_divided | 2999 * | _clk_src | | _clk_src | | _clk_src | 3000 * | | | | | | 3001 * |divsel_six | | divsel_two | | divsel_four | 3002 * +-------+------+ +-----+--------+ +--------+------+ 3003 * | | | 3004 * v---->----------v-------------<------v 3005 * | 3006 * +----------+-----------------+ 3007 * | dp_phy_pll_vco_div_clk | 3008 * +---------+------------------+ 3009 * | 3010 * v 3011 * Input to DISPCC block 3012 * for DP pixel clock 3013 * 3014 */ 3015 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3016 { 3017 switch (req->rate) { 3018 case 1620000000UL / 2: 3019 case 2700000000UL / 2: 3020 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3021 return 0; 3022 default: 3023 return -EINVAL; 3024 } 3025 } 3026 3027 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3028 { 3029 const struct qmp_combo *qmp; 3030 const struct phy_configure_opts_dp *dp_opts; 3031 3032 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 3033 dp_opts = &qmp->dp_opts; 3034 3035 switch (dp_opts->link_rate) { 3036 case 1620: 3037 return 1620000000UL / 2; 3038 case 2700: 3039 return 2700000000UL / 2; 3040 case 5400: 3041 return 5400000000UL / 4; 3042 case 8100: 3043 return 8100000000UL / 6; 3044 default: 3045 return 0; 3046 } 3047 } 3048 3049 static const struct clk_ops qmp_dp_pixel_clk_ops = { 3050 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3051 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3052 }; 3053 3054 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3055 { 3056 switch (req->rate) { 3057 case 162000000: 3058 case 270000000: 3059 case 540000000: 3060 case 810000000: 3061 return 0; 3062 default: 3063 return -EINVAL; 3064 } 3065 } 3066 3067 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3068 { 3069 const struct qmp_combo *qmp; 3070 const struct phy_configure_opts_dp *dp_opts; 3071 3072 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3073 dp_opts = &qmp->dp_opts; 3074 3075 switch (dp_opts->link_rate) { 3076 case 1620: 3077 case 2700: 3078 case 5400: 3079 case 8100: 3080 return dp_opts->link_rate * 100000; 3081 default: 3082 return 0; 3083 } 3084 } 3085 3086 static const struct clk_ops qmp_dp_link_clk_ops = { 3087 .determine_rate = qmp_dp_link_clk_determine_rate, 3088 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3089 }; 3090 3091 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3092 { 3093 struct qmp_combo *qmp = data; 3094 unsigned int idx = clkspec->args[0]; 3095 3096 if (idx >= 2) { 3097 pr_err("%s: invalid index %u\n", __func__, idx); 3098 return ERR_PTR(-EINVAL); 3099 } 3100 3101 if (idx == 0) 3102 return &qmp->dp_link_hw; 3103 3104 return &qmp->dp_pixel_hw; 3105 } 3106 3107 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3108 { 3109 struct clk_init_data init = { }; 3110 char name[64]; 3111 int ret; 3112 3113 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3114 init.ops = &qmp_dp_link_clk_ops; 3115 init.name = name; 3116 qmp->dp_link_hw.init = &init; 3117 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3118 if (ret) 3119 return ret; 3120 3121 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3122 init.ops = &qmp_dp_pixel_clk_ops; 3123 init.name = name; 3124 qmp->dp_pixel_hw.init = &init; 3125 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3126 if (ret) 3127 return ret; 3128 3129 return 0; 3130 } 3131 3132 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3133 { 3134 struct qmp_combo *qmp = data; 3135 3136 switch (clkspec->args[0]) { 3137 case QMP_USB43DP_USB3_PIPE_CLK: 3138 return &qmp->pipe_clk_fixed.hw; 3139 case QMP_USB43DP_DP_LINK_CLK: 3140 return &qmp->dp_link_hw; 3141 case QMP_USB43DP_DP_VCO_DIV_CLK: 3142 return &qmp->dp_pixel_hw; 3143 } 3144 3145 return ERR_PTR(-EINVAL); 3146 } 3147 3148 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3149 struct device_node *dp_np) 3150 { 3151 int ret; 3152 3153 ret = phy_pipe_clk_register(qmp, usb_np); 3154 if (ret) 3155 return ret; 3156 3157 ret = phy_dp_clks_register(qmp, dp_np); 3158 if (ret) 3159 return ret; 3160 3161 /* 3162 * Register a single provider for bindings without child nodes. 3163 */ 3164 if (usb_np == qmp->dev->of_node) 3165 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3166 3167 /* 3168 * Register multiple providers for legacy bindings with child nodes. 3169 */ 3170 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3171 &qmp->pipe_clk_fixed.hw); 3172 if (ret) 3173 return ret; 3174 3175 /* 3176 * Roll a devm action because the clock provider is the child node, but 3177 * the child node is not actually a device. 3178 */ 3179 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3180 if (ret) 3181 return ret; 3182 3183 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3184 if (ret) 3185 return ret; 3186 3187 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3188 } 3189 3190 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3191 { 3192 struct device *dev = qmp->dev; 3193 3194 /* 3195 * Get memory resources from the DP child node: 3196 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3197 * tx2 -> 3; rx2 -> 4 3198 * 3199 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3200 * implementation. 3201 */ 3202 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3203 if (IS_ERR(qmp->dp_tx)) 3204 return PTR_ERR(qmp->dp_tx); 3205 3206 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3207 if (IS_ERR(qmp->dp_dp_phy)) 3208 return PTR_ERR(qmp->dp_dp_phy); 3209 3210 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3211 if (IS_ERR(qmp->dp_tx2)) 3212 return PTR_ERR(qmp->dp_tx2); 3213 3214 return 0; 3215 } 3216 3217 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3218 { 3219 const struct qmp_phy_cfg *cfg = qmp->cfg; 3220 struct device *dev = qmp->dev; 3221 3222 /* 3223 * Get memory resources from the USB child node: 3224 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3225 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3226 */ 3227 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3228 if (IS_ERR(qmp->tx)) 3229 return PTR_ERR(qmp->tx); 3230 3231 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3232 if (IS_ERR(qmp->rx)) 3233 return PTR_ERR(qmp->rx); 3234 3235 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3236 if (IS_ERR(qmp->pcs)) 3237 return PTR_ERR(qmp->pcs); 3238 3239 if (cfg->pcs_usb_offset) 3240 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3241 3242 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3243 if (IS_ERR(qmp->tx2)) 3244 return PTR_ERR(qmp->tx2); 3245 3246 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3247 if (IS_ERR(qmp->rx2)) 3248 return PTR_ERR(qmp->rx2); 3249 3250 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3251 if (IS_ERR(qmp->pcs_misc)) { 3252 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3253 qmp->pcs_misc = NULL; 3254 } 3255 3256 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3257 if (IS_ERR(qmp->pipe_clk)) { 3258 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3259 "failed to get pipe clock\n"); 3260 } 3261 3262 return 0; 3263 } 3264 3265 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3266 struct device_node *dp_np) 3267 { 3268 struct platform_device *pdev = to_platform_device(qmp->dev); 3269 int ret; 3270 3271 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3272 if (IS_ERR(qmp->serdes)) 3273 return PTR_ERR(qmp->serdes); 3274 3275 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3276 if (IS_ERR(qmp->com)) 3277 return PTR_ERR(qmp->com); 3278 3279 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3280 if (IS_ERR(qmp->dp_serdes)) 3281 return PTR_ERR(qmp->dp_serdes); 3282 3283 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3284 if (ret) 3285 return ret; 3286 3287 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3288 if (ret) 3289 return ret; 3290 3291 return 0; 3292 } 3293 3294 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3295 { 3296 struct platform_device *pdev = to_platform_device(qmp->dev); 3297 const struct qmp_phy_cfg *cfg = qmp->cfg; 3298 const struct qmp_combo_offsets *offs = cfg->offsets; 3299 struct device *dev = qmp->dev; 3300 void __iomem *base; 3301 3302 if (!offs) 3303 return -EINVAL; 3304 3305 base = devm_platform_ioremap_resource(pdev, 0); 3306 if (IS_ERR(base)) 3307 return PTR_ERR(base); 3308 3309 qmp->com = base + offs->com; 3310 qmp->tx = base + offs->txa; 3311 qmp->rx = base + offs->rxa; 3312 qmp->tx2 = base + offs->txb; 3313 qmp->rx2 = base + offs->rxb; 3314 3315 qmp->serdes = base + offs->usb3_serdes; 3316 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3317 qmp->pcs = base + offs->usb3_pcs; 3318 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3319 3320 qmp->dp_serdes = base + offs->dp_serdes; 3321 if (offs->dp_txa) { 3322 qmp->dp_tx = base + offs->dp_txa; 3323 qmp->dp_tx2 = base + offs->dp_txb; 3324 } else { 3325 qmp->dp_tx = base + offs->txa; 3326 qmp->dp_tx2 = base + offs->txb; 3327 } 3328 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3329 3330 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3331 if (IS_ERR(qmp->pipe_clk)) { 3332 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3333 "failed to get usb3_pipe clock\n"); 3334 } 3335 3336 return 0; 3337 } 3338 3339 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 3340 { 3341 struct qmp_combo *qmp = dev_get_drvdata(dev); 3342 3343 if (args->args_count == 0) 3344 return ERR_PTR(-EINVAL); 3345 3346 switch (args->args[0]) { 3347 case QMP_USB43DP_USB3_PHY: 3348 return qmp->usb_phy; 3349 case QMP_USB43DP_DP_PHY: 3350 return qmp->dp_phy; 3351 } 3352 3353 return ERR_PTR(-EINVAL); 3354 } 3355 3356 static int qmp_combo_probe(struct platform_device *pdev) 3357 { 3358 struct qmp_combo *qmp; 3359 struct device *dev = &pdev->dev; 3360 struct device_node *dp_np, *usb_np; 3361 struct phy_provider *phy_provider; 3362 int ret; 3363 3364 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3365 if (!qmp) 3366 return -ENOMEM; 3367 3368 qmp->dev = dev; 3369 3370 qmp->cfg = of_device_get_match_data(dev); 3371 if (!qmp->cfg) 3372 return -EINVAL; 3373 3374 mutex_init(&qmp->phy_mutex); 3375 3376 ret = qmp_combo_clk_init(qmp); 3377 if (ret) 3378 return ret; 3379 3380 ret = qmp_combo_reset_init(qmp); 3381 if (ret) 3382 return ret; 3383 3384 ret = qmp_combo_vreg_init(qmp); 3385 if (ret) 3386 return ret; 3387 3388 /* Check for legacy binding with child nodes. */ 3389 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3390 if (usb_np) { 3391 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3392 if (!dp_np) { 3393 of_node_put(usb_np); 3394 return -EINVAL; 3395 } 3396 3397 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3398 } else { 3399 usb_np = of_node_get(dev->of_node); 3400 dp_np = of_node_get(dev->of_node); 3401 3402 ret = qmp_combo_parse_dt(qmp); 3403 } 3404 if (ret) 3405 goto err_node_put; 3406 3407 pm_runtime_set_active(dev); 3408 ret = devm_pm_runtime_enable(dev); 3409 if (ret) 3410 goto err_node_put; 3411 /* 3412 * Prevent runtime pm from being ON by default. Users can enable 3413 * it using power/control in sysfs. 3414 */ 3415 pm_runtime_forbid(dev); 3416 3417 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3418 if (ret) 3419 goto err_node_put; 3420 3421 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3422 if (IS_ERR(qmp->usb_phy)) { 3423 ret = PTR_ERR(qmp->usb_phy); 3424 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3425 goto err_node_put; 3426 } 3427 3428 phy_set_drvdata(qmp->usb_phy, qmp); 3429 3430 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3431 if (IS_ERR(qmp->dp_phy)) { 3432 ret = PTR_ERR(qmp->dp_phy); 3433 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3434 goto err_node_put; 3435 } 3436 3437 phy_set_drvdata(qmp->dp_phy, qmp); 3438 3439 dev_set_drvdata(dev, qmp); 3440 3441 if (usb_np == dev->of_node) 3442 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3443 else 3444 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3445 3446 of_node_put(usb_np); 3447 of_node_put(dp_np); 3448 3449 return PTR_ERR_OR_ZERO(phy_provider); 3450 3451 err_node_put: 3452 of_node_put(usb_np); 3453 of_node_put(dp_np); 3454 return ret; 3455 } 3456 3457 static const struct of_device_id qmp_combo_of_match_table[] = { 3458 { 3459 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3460 .data = &sc7180_usb3dpphy_cfg, 3461 }, 3462 { 3463 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3464 .data = &sc8180x_usb3dpphy_cfg, 3465 }, 3466 { 3467 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3468 .data = &sc8280xp_usb43dpphy_cfg, 3469 }, 3470 { 3471 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3472 .data = &sdm845_usb3dpphy_cfg, 3473 }, 3474 { 3475 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3476 .data = &sm6350_usb3dpphy_cfg, 3477 }, 3478 { 3479 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3480 .data = &sm8250_usb3dpphy_cfg, 3481 }, 3482 { 3483 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3484 .data = &sm8350_usb3dpphy_cfg, 3485 }, 3486 { 3487 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3488 .data = &sm8350_usb3dpphy_cfg, 3489 }, 3490 { 3491 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3492 .data = &sm8550_usb3dpphy_cfg, 3493 }, 3494 { } 3495 }; 3496 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3497 3498 static struct platform_driver qmp_combo_driver = { 3499 .probe = qmp_combo_probe, 3500 .driver = { 3501 .name = "qcom-qmp-combo-phy", 3502 .pm = &qmp_combo_pm_ops, 3503 .of_match_table = qmp_combo_of_match_table, 3504 }, 3505 }; 3506 3507 module_platform_driver(qmp_combo_driver); 3508 3509 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3510 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3511 MODULE_LICENSE("GPL v2"); 3512