1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/drm_bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp.h" 29 #include "phy-qcom-qmp-pcs-misc-v3.h" 30 #include "phy-qcom-qmp-pcs-usb-v4.h" 31 #include "phy-qcom-qmp-pcs-usb-v5.h" 32 #include "phy-qcom-qmp-pcs-usb-v6.h" 33 34 /* QPHY_SW_RESET bit */ 35 #define SW_RESET BIT(0) 36 /* QPHY_POWER_DOWN_CONTROL */ 37 #define SW_PWRDN BIT(0) 38 /* QPHY_START_CONTROL bits */ 39 #define SERDES_START BIT(0) 40 #define PCS_START BIT(1) 41 /* QPHY_PCS_STATUS bit */ 42 #define PHYSTATUS BIT(6) 43 44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45 /* DP PHY soft reset */ 46 #define SW_DPPHY_RESET BIT(0) 47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_DPPHY_RESET_MUX BIT(1) 49 /* USB3 PHY soft reset */ 50 #define SW_USB3PHY_RESET BIT(2) 51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52 #define SW_USB3PHY_RESET_MUX BIT(3) 53 54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55 #define USB3_MODE BIT(0) /* enables USB3 mode */ 56 #define DP_MODE BIT(1) /* enables DP mode */ 57 58 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 59 #define ARCVR_DTCT_EN BIT(0) 60 #define ALFPS_DTCT_EN BIT(1) 61 #define ARCVR_DTCT_EVENT_SEL BIT(4) 62 63 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 64 #define IRQ_CLEAR BIT(0) 65 66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 70 #define SW_PORTSELECT_VAL BIT(0) 71 #define SW_PORTSELECT_MUX BIT(1) 72 73 #define PHY_INIT_COMPLETE_TIMEOUT 10000 74 75 struct qmp_phy_init_tbl { 76 unsigned int offset; 77 unsigned int val; 78 /* 79 * mask of lanes for which this register is written 80 * for cases when second lane needs different values 81 */ 82 u8 lane_mask; 83 }; 84 85 #define QMP_PHY_INIT_CFG(o, v) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 .lane_mask = 0xff, \ 90 } 91 92 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 93 { \ 94 .offset = o, \ 95 .val = v, \ 96 .lane_mask = l, \ 97 } 98 99 /* set of registers with offsets different per-PHY */ 100 enum qphy_reg_layout { 101 /* PCS registers */ 102 QPHY_SW_RESET, 103 QPHY_START_CTRL, 104 QPHY_PCS_STATUS, 105 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 106 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 107 QPHY_PCS_POWER_DOWN_CONTROL, 108 109 QPHY_COM_RESETSM_CNTRL, 110 QPHY_COM_C_READY_STATUS, 111 QPHY_COM_CMN_STATUS, 112 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 113 114 QPHY_DP_PHY_STATUS, 115 116 QPHY_TX_TX_POL_INV, 117 QPHY_TX_TX_DRV_LVL, 118 QPHY_TX_TX_EMP_POST1_LVL, 119 QPHY_TX_HIGHZ_DRVR_EN, 120 QPHY_TX_TRANSCEIVER_BIAS_EN, 121 122 /* Keep last to ensure regs_layout arrays are properly initialized */ 123 QPHY_LAYOUT_SIZE 124 }; 125 126 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 127 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 128 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 129 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 130 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 131 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 132 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 133 134 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 135 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 136 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 137 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 138 139 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 140 141 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 142 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 143 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 144 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 145 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 146 }; 147 148 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 149 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 150 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 151 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 152 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 153 154 /* In PCS_USB */ 155 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 156 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 157 158 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 159 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 160 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 161 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 162 163 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 164 165 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 166 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 167 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 168 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 169 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 170 }; 171 172 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 173 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 174 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 175 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 176 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 177 178 /* In PCS_USB */ 179 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 180 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 181 182 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 183 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 184 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 185 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 186 187 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 188 189 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 190 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 191 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 192 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 193 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 194 }; 195 196 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 197 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 198 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 199 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 200 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 201 202 /* In PCS_USB */ 203 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 204 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 205 206 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 207 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 208 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 209 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 210 211 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 212 213 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 214 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 215 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 216 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 217 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 218 }; 219 220 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 257 }; 258 259 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 260 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 261 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 262 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 263 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 264 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 265 }; 266 267 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 289 }; 290 291 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 299 }; 300 301 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 309 }; 310 311 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 319 }; 320 321 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 329 }; 330 331 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 333 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 334 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 335 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 336 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 342 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 343 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 344 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 345 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 346 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 347 }; 348 349 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 354 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 359 }; 360 361 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 362 /* FLL settings */ 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 368 369 /* Lock Det settings */ 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 374 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 394 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 406 }; 407 408 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 419 }; 420 421 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 422 /* FLL settings */ 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 428 429 /* Lock Det settings */ 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 434 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 454 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 467 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 470 }; 471 472 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 513 }; 514 515 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 516 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 517 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 518 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 521 }; 522 523 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 560 }; 561 562 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 563 /* Lock Det settings */ 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 567 568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 576 }; 577 578 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 579 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 580 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 581 }; 582 583 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 584 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 585 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 590 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 591 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 592 }; 593 594 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 615 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 616 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 617 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 618 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 633 }; 634 635 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 648 }; 649 650 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 653 }; 654 655 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 656 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 658 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 659 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 660 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 661 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 662 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 663 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 664 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 665 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 666 }; 667 668 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 686 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 687 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 688 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 689 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 690 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 691 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 692 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 693 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 694 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 695 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 696 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 697 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 698 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 699 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 700 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 701 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 702 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 707 }; 708 709 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 724 }; 725 726 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 727 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 728 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 729 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 730 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 731 }; 732 733 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 782 }; 783 784 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 785 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 786 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 787 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 788 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 789 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 790 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 791 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 792 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 793 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 794 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 795 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 796 }; 797 798 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 803 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 804 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 805 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 806 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 807 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 808 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 833 834 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 835 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 836 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 837 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 838 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 839 840 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 841 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 842 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 843 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 844 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 845 }; 846 847 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 848 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 849 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 850 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 851 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 852 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 853 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99), 854 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 855 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 856 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a), 857 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 858 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 859 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 860 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b), 861 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10), 862 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 863 }; 864 865 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 866 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 867 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 868 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 869 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 870 }; 871 872 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 893 }; 894 895 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 903 }; 904 905 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 908 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 909 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 910 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 913 }; 914 915 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 916 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 917 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 918 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 923 }; 924 925 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 933 }; 934 935 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 936 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 937 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 938 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 939 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 940 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 941 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 942 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 943 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 944 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 945 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 946 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 947 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 948 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 949 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 950 }; 951 952 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 976 }; 977 978 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 979 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 980 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 981 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 982 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 983 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 984 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 985 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 986 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 987 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 988 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 990 }; 991 992 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 993 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 994 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 995 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 996 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 997 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 998 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 999 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1000 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1001 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1002 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1003 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1004 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1005 }; 1006 1007 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1008 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1009 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1014 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1028 }; 1029 1030 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1031 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1036 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1037 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1038 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1039 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1042 }; 1043 1044 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1054 }; 1055 1056 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1060 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1061 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1062 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1063 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1064 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1065 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1066 }; 1067 1068 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1071 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1073 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1074 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1075 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1076 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1078 }; 1079 1080 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1083 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1084 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1085 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1090 }; 1091 1092 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1140 }; 1141 1142 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1148 }; 1149 1150 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1185 }; 1186 1187 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1188 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1189 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1190 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1191 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1192 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1193 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1194 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1195 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1196 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1197 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1198 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1199 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1200 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1201 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1202 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1203 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1204 }; 1205 1206 /* list of regulators */ 1207 struct qmp_regulator_data { 1208 const char *name; 1209 unsigned int enable_load; 1210 }; 1211 1212 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1213 { .name = "vdda-phy", .enable_load = 21800 }, 1214 { .name = "vdda-pll", .enable_load = 36000 }, 1215 }; 1216 1217 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1218 { 0x00, 0x0c, 0x15, 0x1a }, 1219 { 0x02, 0x0e, 0x16, 0xff }, 1220 { 0x02, 0x11, 0xff, 0xff }, 1221 { 0x04, 0xff, 0xff, 0xff } 1222 }; 1223 1224 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1225 { 0x02, 0x12, 0x16, 0x1a }, 1226 { 0x09, 0x19, 0x1f, 0xff }, 1227 { 0x10, 0x1f, 0xff, 0xff }, 1228 { 0x1f, 0xff, 0xff, 0xff } 1229 }; 1230 1231 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1232 { 0x00, 0x0c, 0x14, 0x19 }, 1233 { 0x00, 0x0b, 0x12, 0xff }, 1234 { 0x00, 0x0b, 0xff, 0xff }, 1235 { 0x04, 0xff, 0xff, 0xff } 1236 }; 1237 1238 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1239 { 0x08, 0x0f, 0x16, 0x1f }, 1240 { 0x11, 0x1e, 0x1f, 0xff }, 1241 { 0x19, 0x1f, 0xff, 0xff }, 1242 { 0x1f, 0xff, 0xff, 0xff } 1243 }; 1244 1245 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1246 { 0x00, 0x0c, 0x15, 0x1b }, 1247 { 0x02, 0x0e, 0x16, 0xff }, 1248 { 0x02, 0x11, 0xff, 0xff }, 1249 { 0x04, 0xff, 0xff, 0xff } 1250 }; 1251 1252 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1253 { 0x00, 0x0d, 0x14, 0x1a }, 1254 { 0x00, 0x0e, 0x15, 0xff }, 1255 { 0x00, 0x0d, 0xff, 0xff }, 1256 { 0x03, 0xff, 0xff, 0xff } 1257 }; 1258 1259 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1260 { 0x08, 0x0f, 0x16, 0x1f }, 1261 { 0x11, 0x1e, 0x1f, 0xff }, 1262 { 0x16, 0x1f, 0xff, 0xff }, 1263 { 0x1f, 0xff, 0xff, 0xff } 1264 }; 1265 1266 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1267 { 0x20, 0x2c, 0x35, 0x3b }, 1268 { 0x22, 0x2e, 0x36, 0xff }, 1269 { 0x22, 0x31, 0xff, 0xff }, 1270 { 0x24, 0xff, 0xff, 0xff } 1271 }; 1272 1273 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1274 { 0x22, 0x32, 0x36, 0x3a }, 1275 { 0x29, 0x39, 0x3f, 0xff }, 1276 { 0x30, 0x3f, 0xff, 0xff }, 1277 { 0x3f, 0xff, 0xff, 0xff } 1278 }; 1279 1280 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1281 { 0x20, 0x2d, 0x34, 0x3a }, 1282 { 0x20, 0x2e, 0x35, 0xff }, 1283 { 0x20, 0x2e, 0xff, 0xff }, 1284 { 0x24, 0xff, 0xff, 0xff } 1285 }; 1286 1287 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1288 { 0x28, 0x2f, 0x36, 0x3f }, 1289 { 0x31, 0x3e, 0x3f, 0xff }, 1290 { 0x36, 0x3f, 0xff, 0xff }, 1291 { 0x3f, 0xff, 0xff, 0xff } 1292 }; 1293 1294 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1295 { 0x20, 0x2d, 0x34, 0x3a }, 1296 { 0x20, 0x2e, 0x35, 0xff }, 1297 { 0x20, 0x2e, 0xff, 0xff }, 1298 { 0x22, 0xff, 0xff, 0xff } 1299 }; 1300 1301 struct qmp_combo; 1302 1303 struct qmp_combo_offsets { 1304 u16 com; 1305 u16 txa; 1306 u16 rxa; 1307 u16 txb; 1308 u16 rxb; 1309 u16 usb3_serdes; 1310 u16 usb3_pcs_misc; 1311 u16 usb3_pcs; 1312 u16 usb3_pcs_usb; 1313 u16 dp_serdes; 1314 u16 dp_txa; 1315 u16 dp_txb; 1316 u16 dp_dp_phy; 1317 }; 1318 1319 struct qmp_phy_cfg { 1320 const struct qmp_combo_offsets *offsets; 1321 1322 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1323 const struct qmp_phy_init_tbl *serdes_tbl; 1324 int serdes_tbl_num; 1325 const struct qmp_phy_init_tbl *tx_tbl; 1326 int tx_tbl_num; 1327 const struct qmp_phy_init_tbl *rx_tbl; 1328 int rx_tbl_num; 1329 const struct qmp_phy_init_tbl *pcs_tbl; 1330 int pcs_tbl_num; 1331 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1332 int pcs_usb_tbl_num; 1333 1334 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1335 int dp_serdes_tbl_num; 1336 const struct qmp_phy_init_tbl *dp_tx_tbl; 1337 int dp_tx_tbl_num; 1338 1339 /* Init sequence for DP PHY block link rates */ 1340 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1341 int serdes_tbl_rbr_num; 1342 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1343 int serdes_tbl_hbr_num; 1344 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1345 int serdes_tbl_hbr2_num; 1346 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1347 int serdes_tbl_hbr3_num; 1348 1349 /* DP PHY swing and pre_emphasis tables */ 1350 const u8 (*swing_hbr_rbr)[4][4]; 1351 const u8 (*swing_hbr3_hbr2)[4][4]; 1352 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1353 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1354 1355 /* DP PHY callbacks */ 1356 int (*configure_dp_phy)(struct qmp_combo *qmp); 1357 void (*configure_dp_tx)(struct qmp_combo *qmp); 1358 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1359 void (*dp_aux_init)(struct qmp_combo *qmp); 1360 1361 /* resets to be requested */ 1362 const char * const *reset_list; 1363 int num_resets; 1364 /* regulators to be requested */ 1365 const struct qmp_regulator_data *vreg_list; 1366 int num_vregs; 1367 1368 /* array of registers with different offsets */ 1369 const unsigned int *regs; 1370 1371 /* true, if PHY needs delay after POWER_DOWN */ 1372 bool has_pwrdn_delay; 1373 1374 /* Offset from PCS to PCS_USB region */ 1375 unsigned int pcs_usb_offset; 1376 1377 }; 1378 1379 struct qmp_combo { 1380 struct device *dev; 1381 1382 const struct qmp_phy_cfg *cfg; 1383 1384 void __iomem *com; 1385 1386 void __iomem *serdes; 1387 void __iomem *tx; 1388 void __iomem *rx; 1389 void __iomem *pcs; 1390 void __iomem *tx2; 1391 void __iomem *rx2; 1392 void __iomem *pcs_misc; 1393 void __iomem *pcs_usb; 1394 1395 void __iomem *dp_serdes; 1396 void __iomem *dp_tx; 1397 void __iomem *dp_tx2; 1398 void __iomem *dp_dp_phy; 1399 1400 struct clk *pipe_clk; 1401 struct clk_bulk_data *clks; 1402 int num_clks; 1403 struct reset_control_bulk_data *resets; 1404 struct regulator_bulk_data *vregs; 1405 1406 struct mutex phy_mutex; 1407 int init_count; 1408 1409 struct phy *usb_phy; 1410 enum phy_mode mode; 1411 unsigned int usb_init_count; 1412 1413 struct phy *dp_phy; 1414 unsigned int dp_aux_cfg; 1415 struct phy_configure_opts_dp dp_opts; 1416 unsigned int dp_init_count; 1417 1418 struct clk_fixed_rate pipe_clk_fixed; 1419 struct clk_hw dp_link_hw; 1420 struct clk_hw dp_pixel_hw; 1421 1422 struct drm_bridge bridge; 1423 1424 struct typec_switch_dev *sw; 1425 enum typec_orientation orientation; 1426 }; 1427 1428 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1429 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1430 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1431 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1432 1433 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1434 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1435 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1436 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1437 1438 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1439 { 1440 u32 reg; 1441 1442 reg = readl(base + offset); 1443 reg |= val; 1444 writel(reg, base + offset); 1445 1446 /* ensure that above write is through */ 1447 readl(base + offset); 1448 } 1449 1450 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1451 { 1452 u32 reg; 1453 1454 reg = readl(base + offset); 1455 reg &= ~val; 1456 writel(reg, base + offset); 1457 1458 /* ensure that above write is through */ 1459 readl(base + offset); 1460 } 1461 1462 /* list of clocks required by phy */ 1463 static const char * const qmp_combo_phy_clk_l[] = { 1464 "aux", "cfg_ahb", "ref", "com_aux", 1465 }; 1466 1467 /* list of resets */ 1468 static const char * const msm8996_usb3phy_reset_l[] = { 1469 "phy", "common", 1470 }; 1471 1472 static const char * const sc7180_usb3phy_reset_l[] = { 1473 "phy", 1474 }; 1475 1476 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1477 .com = 0x0000, 1478 .txa = 0x1200, 1479 .rxa = 0x1400, 1480 .txb = 0x1600, 1481 .rxb = 0x1800, 1482 .usb3_serdes = 0x1000, 1483 .usb3_pcs_misc = 0x1a00, 1484 .usb3_pcs = 0x1c00, 1485 .usb3_pcs_usb = 0x1f00, 1486 .dp_serdes = 0x2000, 1487 .dp_txa = 0x2200, 1488 .dp_txb = 0x2600, 1489 .dp_dp_phy = 0x2a00, 1490 }; 1491 1492 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1493 .com = 0x0000, 1494 .txa = 0x0400, 1495 .rxa = 0x0600, 1496 .txb = 0x0a00, 1497 .rxb = 0x0c00, 1498 .usb3_serdes = 0x1000, 1499 .usb3_pcs_misc = 0x1200, 1500 .usb3_pcs = 0x1400, 1501 .usb3_pcs_usb = 0x1700, 1502 .dp_serdes = 0x2000, 1503 .dp_dp_phy = 0x2200, 1504 }; 1505 1506 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1507 .offsets = &qmp_combo_offsets_v3, 1508 1509 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1510 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1511 .tx_tbl = qmp_v3_usb3_tx_tbl, 1512 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1513 .rx_tbl = qmp_v3_usb3_rx_tbl, 1514 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1515 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1516 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1517 1518 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1519 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1520 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1521 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1522 1523 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1524 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1525 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1526 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1527 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1528 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1529 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1530 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1531 1532 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1533 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1534 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1535 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1536 1537 .dp_aux_init = qmp_v3_dp_aux_init, 1538 .configure_dp_tx = qmp_v3_configure_dp_tx, 1539 .configure_dp_phy = qmp_v3_configure_dp_phy, 1540 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1541 1542 .reset_list = sc7180_usb3phy_reset_l, 1543 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1544 .vreg_list = qmp_phy_vreg_l, 1545 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1546 .regs = qmp_v3_usb3phy_regs_layout, 1547 1548 .has_pwrdn_delay = true, 1549 }; 1550 1551 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1552 .offsets = &qmp_combo_offsets_v3, 1553 1554 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1555 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1556 .tx_tbl = qmp_v3_usb3_tx_tbl, 1557 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1558 .rx_tbl = qmp_v3_usb3_rx_tbl, 1559 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1560 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1561 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1562 1563 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1564 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1565 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1566 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1567 1568 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1569 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1570 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1571 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1572 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1573 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1574 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1575 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1576 1577 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1578 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1579 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1580 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1581 1582 .dp_aux_init = qmp_v3_dp_aux_init, 1583 .configure_dp_tx = qmp_v3_configure_dp_tx, 1584 .configure_dp_phy = qmp_v3_configure_dp_phy, 1585 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1586 1587 .reset_list = msm8996_usb3phy_reset_l, 1588 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1589 .vreg_list = qmp_phy_vreg_l, 1590 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1591 .regs = qmp_v3_usb3phy_regs_layout, 1592 1593 .has_pwrdn_delay = true, 1594 }; 1595 1596 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1597 .offsets = &qmp_combo_offsets_v3, 1598 1599 .serdes_tbl = sm8150_usb3_serdes_tbl, 1600 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1601 .tx_tbl = sm8150_usb3_tx_tbl, 1602 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1603 .rx_tbl = sm8150_usb3_rx_tbl, 1604 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1605 .pcs_tbl = sm8150_usb3_pcs_tbl, 1606 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1607 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1608 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1609 1610 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1611 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1612 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1613 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1614 1615 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1616 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1617 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1618 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1619 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1620 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1621 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1622 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1623 1624 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1625 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1626 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1627 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1628 1629 .dp_aux_init = qmp_v4_dp_aux_init, 1630 .configure_dp_tx = qmp_v4_configure_dp_tx, 1631 .configure_dp_phy = qmp_v4_configure_dp_phy, 1632 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1633 1634 .reset_list = msm8996_usb3phy_reset_l, 1635 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1636 .vreg_list = qmp_phy_vreg_l, 1637 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1638 .regs = qmp_v45_usb3phy_regs_layout, 1639 .pcs_usb_offset = 0x300, 1640 1641 .has_pwrdn_delay = true, 1642 }; 1643 1644 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1645 .offsets = &qmp_combo_offsets_v5, 1646 1647 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1648 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1649 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1650 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1651 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1652 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1653 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1654 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1655 1656 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1657 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1658 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1659 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1660 1661 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1662 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1663 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1664 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1665 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1666 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1667 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1668 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1669 1670 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1671 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1672 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1673 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1674 1675 .dp_aux_init = qmp_v4_dp_aux_init, 1676 .configure_dp_tx = qmp_v4_configure_dp_tx, 1677 .configure_dp_phy = qmp_v4_configure_dp_phy, 1678 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1679 1680 .reset_list = msm8996_usb3phy_reset_l, 1681 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1682 .vreg_list = qmp_phy_vreg_l, 1683 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1684 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1685 }; 1686 1687 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1688 .offsets = &qmp_combo_offsets_v3, 1689 1690 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1691 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1692 .tx_tbl = qmp_v3_usb3_tx_tbl, 1693 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1694 .rx_tbl = sm6350_usb3_rx_tbl, 1695 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1696 .pcs_tbl = sm6350_usb3_pcs_tbl, 1697 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1698 1699 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1700 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1701 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1702 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1703 1704 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1705 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1706 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1707 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1708 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1709 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1710 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1711 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1712 1713 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1714 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1715 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1716 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1717 1718 .dp_aux_init = qmp_v3_dp_aux_init, 1719 .configure_dp_tx = qmp_v3_configure_dp_tx, 1720 .configure_dp_phy = qmp_v3_configure_dp_phy, 1721 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1722 1723 .reset_list = msm8996_usb3phy_reset_l, 1724 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1725 .vreg_list = qmp_phy_vreg_l, 1726 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1727 .regs = qmp_v3_usb3phy_regs_layout, 1728 }; 1729 1730 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1731 .offsets = &qmp_combo_offsets_v3, 1732 1733 .serdes_tbl = sm8150_usb3_serdes_tbl, 1734 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1735 .tx_tbl = sm8250_usb3_tx_tbl, 1736 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1737 .rx_tbl = sm8250_usb3_rx_tbl, 1738 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1739 .pcs_tbl = sm8250_usb3_pcs_tbl, 1740 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1741 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1742 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1743 1744 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1745 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1746 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1747 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1748 1749 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1750 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1751 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1752 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1753 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1754 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1755 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1756 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1757 1758 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1759 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1760 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1761 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1762 1763 .dp_aux_init = qmp_v4_dp_aux_init, 1764 .configure_dp_tx = qmp_v4_configure_dp_tx, 1765 .configure_dp_phy = qmp_v4_configure_dp_phy, 1766 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1767 1768 .reset_list = msm8996_usb3phy_reset_l, 1769 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1770 .vreg_list = qmp_phy_vreg_l, 1771 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1772 .regs = qmp_v45_usb3phy_regs_layout, 1773 .pcs_usb_offset = 0x300, 1774 1775 .has_pwrdn_delay = true, 1776 }; 1777 1778 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1779 .offsets = &qmp_combo_offsets_v3, 1780 1781 .serdes_tbl = sm8150_usb3_serdes_tbl, 1782 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1783 .tx_tbl = sm8350_usb3_tx_tbl, 1784 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1785 .rx_tbl = sm8350_usb3_rx_tbl, 1786 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1787 .pcs_tbl = sm8350_usb3_pcs_tbl, 1788 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1789 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1790 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1791 1792 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1793 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1794 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1795 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1796 1797 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1798 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1799 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1800 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1801 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1802 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1803 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1804 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1805 1806 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1807 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1808 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1809 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1810 1811 .dp_aux_init = qmp_v4_dp_aux_init, 1812 .configure_dp_tx = qmp_v4_configure_dp_tx, 1813 .configure_dp_phy = qmp_v4_configure_dp_phy, 1814 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1815 1816 .reset_list = msm8996_usb3phy_reset_l, 1817 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1818 .vreg_list = qmp_phy_vreg_l, 1819 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1820 .regs = qmp_v45_usb3phy_regs_layout, 1821 1822 .has_pwrdn_delay = true, 1823 }; 1824 1825 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1826 .offsets = &qmp_combo_offsets_v3, 1827 1828 .serdes_tbl = sm8550_usb3_serdes_tbl, 1829 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1830 .tx_tbl = sm8550_usb3_tx_tbl, 1831 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1832 .rx_tbl = sm8550_usb3_rx_tbl, 1833 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1834 .pcs_tbl = sm8550_usb3_pcs_tbl, 1835 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1836 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1837 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1838 1839 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1840 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1841 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1842 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1843 1844 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1845 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1846 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1847 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1848 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1849 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1850 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1851 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1852 1853 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1854 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1855 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1856 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1857 1858 .dp_aux_init = qmp_v4_dp_aux_init, 1859 .configure_dp_tx = qmp_v4_configure_dp_tx, 1860 .configure_dp_phy = qmp_v4_configure_dp_phy, 1861 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1862 1863 .regs = qmp_v6_usb3phy_regs_layout, 1864 .reset_list = msm8996_usb3phy_reset_l, 1865 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1866 .vreg_list = qmp_phy_vreg_l, 1867 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1868 }; 1869 1870 static void qmp_combo_configure_lane(void __iomem *base, 1871 const struct qmp_phy_init_tbl tbl[], 1872 int num, 1873 u8 lane_mask) 1874 { 1875 int i; 1876 const struct qmp_phy_init_tbl *t = tbl; 1877 1878 if (!t) 1879 return; 1880 1881 for (i = 0; i < num; i++, t++) { 1882 if (!(t->lane_mask & lane_mask)) 1883 continue; 1884 1885 writel(t->val, base + t->offset); 1886 } 1887 } 1888 1889 static void qmp_combo_configure(void __iomem *base, 1890 const struct qmp_phy_init_tbl tbl[], 1891 int num) 1892 { 1893 qmp_combo_configure_lane(base, tbl, num, 0xff); 1894 } 1895 1896 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1897 { 1898 const struct qmp_phy_cfg *cfg = qmp->cfg; 1899 void __iomem *serdes = qmp->dp_serdes; 1900 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1901 1902 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1903 1904 switch (dp_opts->link_rate) { 1905 case 1620: 1906 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1907 cfg->serdes_tbl_rbr_num); 1908 break; 1909 case 2700: 1910 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1911 cfg->serdes_tbl_hbr_num); 1912 break; 1913 case 5400: 1914 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1915 cfg->serdes_tbl_hbr2_num); 1916 break; 1917 case 8100: 1918 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1919 cfg->serdes_tbl_hbr3_num); 1920 break; 1921 default: 1922 /* Other link rates aren't supported */ 1923 return -EINVAL; 1924 } 1925 1926 return 0; 1927 } 1928 1929 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1930 { 1931 const struct qmp_phy_cfg *cfg = qmp->cfg; 1932 1933 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1934 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1935 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1936 1937 /* Turn on BIAS current for PHY/PLL */ 1938 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1939 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1940 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1941 1942 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1943 1944 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1945 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1946 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1947 DP_PHY_PD_CTL_DP_CLAMP_EN, 1948 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1949 1950 writel(QSERDES_V3_COM_BIAS_EN | 1951 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1952 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1953 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1954 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1955 1956 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1957 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1958 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1959 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1960 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1961 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1962 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1963 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1964 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1965 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1966 qmp->dp_aux_cfg = 0; 1967 1968 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1969 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1970 PHY_AUX_REQ_ERR_MASK, 1971 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1972 } 1973 1974 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 1975 { 1976 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1977 const struct qmp_phy_cfg *cfg = qmp->cfg; 1978 unsigned int v_level = 0, p_level = 0; 1979 u8 voltage_swing_cfg, pre_emphasis_cfg; 1980 int i; 1981 1982 for (i = 0; i < dp_opts->lanes; i++) { 1983 v_level = max(v_level, dp_opts->voltage[i]); 1984 p_level = max(p_level, dp_opts->pre[i]); 1985 } 1986 1987 if (dp_opts->link_rate <= 2700) { 1988 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1989 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1990 } else { 1991 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1992 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1993 } 1994 1995 /* TODO: Move check to config check */ 1996 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 1997 return -EINVAL; 1998 1999 /* Enable MUX to use Cursor values from these registers */ 2000 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2001 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2002 2003 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2004 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2005 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2006 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2007 2008 return 0; 2009 } 2010 2011 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2012 { 2013 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2014 u32 bias_en, drvr_en; 2015 2016 if (qmp_combo_configure_dp_swing(qmp) < 0) 2017 return; 2018 2019 if (dp_opts->lanes == 1) { 2020 bias_en = 0x3e; 2021 drvr_en = 0x13; 2022 } else { 2023 bias_en = 0x3f; 2024 drvr_en = 0x10; 2025 } 2026 2027 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2028 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2029 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2030 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2031 } 2032 2033 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2034 { 2035 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2036 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2037 u32 val; 2038 2039 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2040 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2041 2042 if (dp_opts->lanes == 4 || reverse) 2043 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2044 if (dp_opts->lanes == 4 || !reverse) 2045 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2046 2047 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2048 2049 if (reverse) 2050 writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE); 2051 else 2052 writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE); 2053 2054 return reverse; 2055 } 2056 2057 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2058 { 2059 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2060 u32 phy_vco_div; 2061 unsigned long pixel_freq; 2062 2063 switch (dp_opts->link_rate) { 2064 case 1620: 2065 phy_vco_div = 0x1; 2066 pixel_freq = 1620000000UL / 2; 2067 break; 2068 case 2700: 2069 phy_vco_div = 0x1; 2070 pixel_freq = 2700000000UL / 2; 2071 break; 2072 case 5400: 2073 phy_vco_div = 0x2; 2074 pixel_freq = 5400000000UL / 4; 2075 break; 2076 case 8100: 2077 phy_vco_div = 0x0; 2078 pixel_freq = 8100000000UL / 6; 2079 break; 2080 default: 2081 /* Other link rates aren't supported */ 2082 return -EINVAL; 2083 } 2084 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV); 2085 2086 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2087 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2088 2089 return 0; 2090 } 2091 2092 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2093 { 2094 const struct qmp_phy_cfg *cfg = qmp->cfg; 2095 u32 status; 2096 int ret; 2097 2098 qmp_combo_configure_dp_mode(qmp); 2099 2100 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2101 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2102 2103 ret = qmp_combo_configure_dp_clocks(qmp); 2104 if (ret) 2105 return ret; 2106 2107 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2108 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2109 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2110 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2111 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2112 2113 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2114 2115 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2116 status, 2117 ((status & BIT(0)) > 0), 2118 500, 2119 10000)) 2120 return -ETIMEDOUT; 2121 2122 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2123 2124 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2125 status, 2126 ((status & BIT(1)) > 0), 2127 500, 2128 10000)) 2129 return -ETIMEDOUT; 2130 2131 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2132 udelay(2000); 2133 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2134 2135 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2136 status, 2137 ((status & BIT(1)) > 0), 2138 500, 2139 10000); 2140 } 2141 2142 /* 2143 * We need to calibrate the aux setting here as many times 2144 * as the caller tries 2145 */ 2146 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2147 { 2148 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2149 u8 val; 2150 2151 qmp->dp_aux_cfg++; 2152 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2153 val = cfg1_settings[qmp->dp_aux_cfg]; 2154 2155 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2156 2157 return 0; 2158 } 2159 2160 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2161 { 2162 const struct qmp_phy_cfg *cfg = qmp->cfg; 2163 2164 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2165 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2166 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2167 2168 /* Turn on BIAS current for PHY/PLL */ 2169 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2170 2171 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2172 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2173 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2174 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2175 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2176 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2177 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2178 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2179 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2180 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2181 qmp->dp_aux_cfg = 0; 2182 2183 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2184 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2185 PHY_AUX_REQ_ERR_MASK, 2186 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2187 } 2188 2189 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2190 { 2191 const struct qmp_phy_cfg *cfg = qmp->cfg; 2192 2193 /* Program default values before writing proper values */ 2194 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2195 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2196 2197 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2198 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2199 2200 qmp_combo_configure_dp_swing(qmp); 2201 } 2202 2203 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2204 { 2205 const struct qmp_phy_cfg *cfg = qmp->cfg; 2206 u32 status; 2207 int ret; 2208 2209 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 2210 2211 qmp_combo_configure_dp_mode(qmp); 2212 2213 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2214 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2215 2216 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2217 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2218 2219 ret = qmp_combo_configure_dp_clocks(qmp); 2220 if (ret) 2221 return ret; 2222 2223 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2224 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2225 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2226 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2227 2228 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2229 2230 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2231 status, 2232 ((status & BIT(0)) > 0), 2233 500, 2234 10000)) 2235 return -ETIMEDOUT; 2236 2237 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2238 status, 2239 ((status & BIT(0)) > 0), 2240 500, 2241 10000)) 2242 return -ETIMEDOUT; 2243 2244 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2245 status, 2246 ((status & BIT(1)) > 0), 2247 500, 2248 10000)) 2249 return -ETIMEDOUT; 2250 2251 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2252 2253 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2254 status, 2255 ((status & BIT(0)) > 0), 2256 500, 2257 10000)) 2258 return -ETIMEDOUT; 2259 2260 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2261 status, 2262 ((status & BIT(1)) > 0), 2263 500, 2264 10000)) 2265 return -ETIMEDOUT; 2266 2267 return 0; 2268 } 2269 2270 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2271 { 2272 const struct qmp_phy_cfg *cfg = qmp->cfg; 2273 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2274 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2275 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2276 u32 status; 2277 int ret; 2278 2279 ret = qmp_v456_configure_dp_phy(qmp); 2280 if (ret < 0) 2281 return ret; 2282 2283 /* 2284 * At least for 7nm DP PHY this has to be done after enabling link 2285 * clock. 2286 */ 2287 2288 if (dp_opts->lanes == 1) { 2289 bias0_en = reverse ? 0x3e : 0x15; 2290 bias1_en = reverse ? 0x15 : 0x3e; 2291 drvr0_en = reverse ? 0x13 : 0x10; 2292 drvr1_en = reverse ? 0x10 : 0x13; 2293 } else if (dp_opts->lanes == 2) { 2294 bias0_en = reverse ? 0x3f : 0x15; 2295 bias1_en = reverse ? 0x15 : 0x3f; 2296 drvr0_en = 0x10; 2297 drvr1_en = 0x10; 2298 } else { 2299 bias0_en = 0x3f; 2300 bias1_en = 0x3f; 2301 drvr0_en = 0x10; 2302 drvr1_en = 0x10; 2303 } 2304 2305 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2306 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2307 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2308 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2309 2310 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2311 udelay(2000); 2312 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2313 2314 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2315 status, 2316 ((status & BIT(1)) > 0), 2317 500, 2318 10000)) 2319 return -ETIMEDOUT; 2320 2321 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2322 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2323 2324 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2325 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2326 2327 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2328 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2329 2330 return 0; 2331 2332 return 0; 2333 } 2334 2335 /* 2336 * We need to calibrate the aux setting here as many times 2337 * as the caller tries 2338 */ 2339 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2340 { 2341 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2342 u8 val; 2343 2344 qmp->dp_aux_cfg++; 2345 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2346 val = cfg1_settings[qmp->dp_aux_cfg]; 2347 2348 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2349 2350 return 0; 2351 } 2352 2353 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2354 { 2355 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2356 struct qmp_combo *qmp = phy_get_drvdata(phy); 2357 const struct qmp_phy_cfg *cfg = qmp->cfg; 2358 2359 mutex_lock(&qmp->phy_mutex); 2360 2361 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2362 if (qmp->dp_opts.set_voltages) { 2363 cfg->configure_dp_tx(qmp); 2364 qmp->dp_opts.set_voltages = 0; 2365 } 2366 2367 mutex_unlock(&qmp->phy_mutex); 2368 2369 return 0; 2370 } 2371 2372 static int qmp_combo_dp_calibrate(struct phy *phy) 2373 { 2374 struct qmp_combo *qmp = phy_get_drvdata(phy); 2375 const struct qmp_phy_cfg *cfg = qmp->cfg; 2376 int ret = 0; 2377 2378 mutex_lock(&qmp->phy_mutex); 2379 2380 if (cfg->calibrate_dp_phy) 2381 ret = cfg->calibrate_dp_phy(qmp); 2382 2383 mutex_unlock(&qmp->phy_mutex); 2384 2385 return ret; 2386 } 2387 2388 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2389 { 2390 const struct qmp_phy_cfg *cfg = qmp->cfg; 2391 void __iomem *com = qmp->com; 2392 int ret; 2393 u32 val; 2394 2395 if (!force && qmp->init_count++) 2396 return 0; 2397 2398 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2399 if (ret) { 2400 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2401 goto err_decrement_count; 2402 } 2403 2404 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2405 if (ret) { 2406 dev_err(qmp->dev, "reset assert failed\n"); 2407 goto err_disable_regulators; 2408 } 2409 2410 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2411 if (ret) { 2412 dev_err(qmp->dev, "reset deassert failed\n"); 2413 goto err_disable_regulators; 2414 } 2415 2416 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2417 if (ret) 2418 goto err_assert_reset; 2419 2420 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2421 2422 /* override hardware control for reset of qmp phy */ 2423 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2424 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2425 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2426 2427 /* Use software based port select and switch on typec orientation */ 2428 val = SW_PORTSELECT_MUX; 2429 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2430 val |= SW_PORTSELECT_VAL; 2431 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2432 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2433 2434 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2435 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2436 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2437 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2438 2439 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2440 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2441 2442 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2443 SW_PWRDN); 2444 2445 return 0; 2446 2447 err_assert_reset: 2448 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2449 err_disable_regulators: 2450 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2451 err_decrement_count: 2452 qmp->init_count--; 2453 2454 return ret; 2455 } 2456 2457 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2458 { 2459 const struct qmp_phy_cfg *cfg = qmp->cfg; 2460 2461 if (!force && --qmp->init_count) 2462 return 0; 2463 2464 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2465 2466 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2467 2468 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2469 2470 return 0; 2471 } 2472 2473 static int qmp_combo_dp_init(struct phy *phy) 2474 { 2475 struct qmp_combo *qmp = phy_get_drvdata(phy); 2476 const struct qmp_phy_cfg *cfg = qmp->cfg; 2477 int ret; 2478 2479 mutex_lock(&qmp->phy_mutex); 2480 2481 ret = qmp_combo_com_init(qmp, false); 2482 if (ret) 2483 goto out_unlock; 2484 2485 cfg->dp_aux_init(qmp); 2486 2487 qmp->dp_init_count++; 2488 2489 out_unlock: 2490 mutex_unlock(&qmp->phy_mutex); 2491 return ret; 2492 } 2493 2494 static int qmp_combo_dp_exit(struct phy *phy) 2495 { 2496 struct qmp_combo *qmp = phy_get_drvdata(phy); 2497 2498 mutex_lock(&qmp->phy_mutex); 2499 2500 qmp_combo_com_exit(qmp, false); 2501 2502 qmp->dp_init_count--; 2503 2504 mutex_unlock(&qmp->phy_mutex); 2505 2506 return 0; 2507 } 2508 2509 static int qmp_combo_dp_power_on(struct phy *phy) 2510 { 2511 struct qmp_combo *qmp = phy_get_drvdata(phy); 2512 const struct qmp_phy_cfg *cfg = qmp->cfg; 2513 void __iomem *tx = qmp->dp_tx; 2514 void __iomem *tx2 = qmp->dp_tx2; 2515 2516 mutex_lock(&qmp->phy_mutex); 2517 2518 qmp_combo_dp_serdes_init(qmp); 2519 2520 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2521 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2522 2523 /* Configure special DP tx tunings */ 2524 cfg->configure_dp_tx(qmp); 2525 2526 /* Configure link rate, swing, etc. */ 2527 cfg->configure_dp_phy(qmp); 2528 2529 mutex_unlock(&qmp->phy_mutex); 2530 2531 return 0; 2532 } 2533 2534 static int qmp_combo_dp_power_off(struct phy *phy) 2535 { 2536 struct qmp_combo *qmp = phy_get_drvdata(phy); 2537 2538 mutex_lock(&qmp->phy_mutex); 2539 2540 /* Assert DP PHY power down */ 2541 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2542 2543 mutex_unlock(&qmp->phy_mutex); 2544 2545 return 0; 2546 } 2547 2548 static int qmp_combo_usb_power_on(struct phy *phy) 2549 { 2550 struct qmp_combo *qmp = phy_get_drvdata(phy); 2551 const struct qmp_phy_cfg *cfg = qmp->cfg; 2552 void __iomem *serdes = qmp->serdes; 2553 void __iomem *tx = qmp->tx; 2554 void __iomem *rx = qmp->rx; 2555 void __iomem *tx2 = qmp->tx2; 2556 void __iomem *rx2 = qmp->rx2; 2557 void __iomem *pcs = qmp->pcs; 2558 void __iomem *status; 2559 unsigned int val; 2560 int ret; 2561 2562 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2563 2564 ret = clk_prepare_enable(qmp->pipe_clk); 2565 if (ret) { 2566 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2567 return ret; 2568 } 2569 2570 /* Tx, Rx, and PCS configurations */ 2571 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2572 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2573 2574 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2575 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2576 2577 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2578 2579 if (cfg->has_pwrdn_delay) 2580 usleep_range(10, 20); 2581 2582 /* Pull PHY out of reset state */ 2583 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2584 2585 /* start SerDes and Phy-Coding-Sublayer */ 2586 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2587 2588 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2589 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2590 PHY_INIT_COMPLETE_TIMEOUT); 2591 if (ret) { 2592 dev_err(qmp->dev, "phy initialization timed-out\n"); 2593 goto err_disable_pipe_clk; 2594 } 2595 2596 return 0; 2597 2598 err_disable_pipe_clk: 2599 clk_disable_unprepare(qmp->pipe_clk); 2600 2601 return ret; 2602 } 2603 2604 static int qmp_combo_usb_power_off(struct phy *phy) 2605 { 2606 struct qmp_combo *qmp = phy_get_drvdata(phy); 2607 const struct qmp_phy_cfg *cfg = qmp->cfg; 2608 2609 clk_disable_unprepare(qmp->pipe_clk); 2610 2611 /* PHY reset */ 2612 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2613 2614 /* stop SerDes and Phy-Coding-Sublayer */ 2615 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2616 SERDES_START | PCS_START); 2617 2618 /* Put PHY into POWER DOWN state: active low */ 2619 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2620 SW_PWRDN); 2621 2622 return 0; 2623 } 2624 2625 static int qmp_combo_usb_init(struct phy *phy) 2626 { 2627 struct qmp_combo *qmp = phy_get_drvdata(phy); 2628 int ret; 2629 2630 mutex_lock(&qmp->phy_mutex); 2631 ret = qmp_combo_com_init(qmp, false); 2632 if (ret) 2633 goto out_unlock; 2634 2635 ret = qmp_combo_usb_power_on(phy); 2636 if (ret) { 2637 qmp_combo_com_exit(qmp, false); 2638 goto out_unlock; 2639 } 2640 2641 qmp->usb_init_count++; 2642 2643 out_unlock: 2644 mutex_unlock(&qmp->phy_mutex); 2645 return ret; 2646 } 2647 2648 static int qmp_combo_usb_exit(struct phy *phy) 2649 { 2650 struct qmp_combo *qmp = phy_get_drvdata(phy); 2651 int ret; 2652 2653 mutex_lock(&qmp->phy_mutex); 2654 ret = qmp_combo_usb_power_off(phy); 2655 if (ret) 2656 goto out_unlock; 2657 2658 ret = qmp_combo_com_exit(qmp, false); 2659 if (ret) 2660 goto out_unlock; 2661 2662 qmp->usb_init_count--; 2663 2664 out_unlock: 2665 mutex_unlock(&qmp->phy_mutex); 2666 return ret; 2667 } 2668 2669 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2670 { 2671 struct qmp_combo *qmp = phy_get_drvdata(phy); 2672 2673 qmp->mode = mode; 2674 2675 return 0; 2676 } 2677 2678 static const struct phy_ops qmp_combo_usb_phy_ops = { 2679 .init = qmp_combo_usb_init, 2680 .exit = qmp_combo_usb_exit, 2681 .set_mode = qmp_combo_usb_set_mode, 2682 .owner = THIS_MODULE, 2683 }; 2684 2685 static const struct phy_ops qmp_combo_dp_phy_ops = { 2686 .init = qmp_combo_dp_init, 2687 .configure = qmp_combo_dp_configure, 2688 .power_on = qmp_combo_dp_power_on, 2689 .calibrate = qmp_combo_dp_calibrate, 2690 .power_off = qmp_combo_dp_power_off, 2691 .exit = qmp_combo_dp_exit, 2692 .owner = THIS_MODULE, 2693 }; 2694 2695 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2696 { 2697 const struct qmp_phy_cfg *cfg = qmp->cfg; 2698 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2699 void __iomem *pcs_misc = qmp->pcs_misc; 2700 u32 intr_mask; 2701 2702 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2703 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2704 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2705 else 2706 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2707 2708 /* Clear any pending interrupts status */ 2709 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2710 /* Writing 1 followed by 0 clears the interrupt */ 2711 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2712 2713 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2714 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2715 2716 /* Enable required PHY autonomous mode interrupts */ 2717 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2718 2719 /* Enable i/o clamp_n for autonomous mode */ 2720 if (pcs_misc) 2721 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2722 } 2723 2724 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2725 { 2726 const struct qmp_phy_cfg *cfg = qmp->cfg; 2727 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2728 void __iomem *pcs_misc = qmp->pcs_misc; 2729 2730 /* Disable i/o clamp_n on resume for normal mode */ 2731 if (pcs_misc) 2732 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2733 2734 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2735 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2736 2737 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2738 /* Writing 1 followed by 0 clears the interrupt */ 2739 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2740 } 2741 2742 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2743 { 2744 struct qmp_combo *qmp = dev_get_drvdata(dev); 2745 2746 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2747 2748 if (!qmp->init_count) { 2749 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2750 return 0; 2751 } 2752 2753 qmp_combo_enable_autonomous_mode(qmp); 2754 2755 clk_disable_unprepare(qmp->pipe_clk); 2756 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2757 2758 return 0; 2759 } 2760 2761 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2762 { 2763 struct qmp_combo *qmp = dev_get_drvdata(dev); 2764 int ret = 0; 2765 2766 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2767 2768 if (!qmp->init_count) { 2769 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2770 return 0; 2771 } 2772 2773 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2774 if (ret) 2775 return ret; 2776 2777 ret = clk_prepare_enable(qmp->pipe_clk); 2778 if (ret) { 2779 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2780 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2781 return ret; 2782 } 2783 2784 qmp_combo_disable_autonomous_mode(qmp); 2785 2786 return 0; 2787 } 2788 2789 static const struct dev_pm_ops qmp_combo_pm_ops = { 2790 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2791 qmp_combo_runtime_resume, NULL) 2792 }; 2793 2794 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2795 { 2796 const struct qmp_phy_cfg *cfg = qmp->cfg; 2797 struct device *dev = qmp->dev; 2798 int num = cfg->num_vregs; 2799 int ret, i; 2800 2801 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2802 if (!qmp->vregs) 2803 return -ENOMEM; 2804 2805 for (i = 0; i < num; i++) 2806 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2807 2808 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2809 if (ret) { 2810 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2811 return ret; 2812 } 2813 2814 for (i = 0; i < num; i++) { 2815 ret = regulator_set_load(qmp->vregs[i].consumer, 2816 cfg->vreg_list[i].enable_load); 2817 if (ret) { 2818 dev_err(dev, "failed to set load at %s\n", 2819 qmp->vregs[i].supply); 2820 return ret; 2821 } 2822 } 2823 2824 return 0; 2825 } 2826 2827 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2828 { 2829 const struct qmp_phy_cfg *cfg = qmp->cfg; 2830 struct device *dev = qmp->dev; 2831 int i; 2832 int ret; 2833 2834 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2835 sizeof(*qmp->resets), GFP_KERNEL); 2836 if (!qmp->resets) 2837 return -ENOMEM; 2838 2839 for (i = 0; i < cfg->num_resets; i++) 2840 qmp->resets[i].id = cfg->reset_list[i]; 2841 2842 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2843 if (ret) 2844 return dev_err_probe(dev, ret, "failed to get resets\n"); 2845 2846 return 0; 2847 } 2848 2849 static int qmp_combo_clk_init(struct qmp_combo *qmp) 2850 { 2851 struct device *dev = qmp->dev; 2852 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 2853 int i; 2854 2855 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2856 if (!qmp->clks) 2857 return -ENOMEM; 2858 2859 for (i = 0; i < num; i++) 2860 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 2861 2862 qmp->num_clks = num; 2863 2864 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 2865 } 2866 2867 static void phy_clk_release_provider(void *res) 2868 { 2869 of_clk_del_provider(res); 2870 } 2871 2872 /* 2873 * Register a fixed rate pipe clock. 2874 * 2875 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2876 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2877 * by the PHY driver for its operations. 2878 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2879 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2880 * Below picture shows this relationship. 2881 * 2882 * +---------------+ 2883 * | PHY block |<<---------------------------------------+ 2884 * | | | 2885 * | +-------+ | +-----+ | 2886 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2887 * clk | +-------+ | +-----+ 2888 * +---------------+ 2889 */ 2890 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2891 { 2892 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2893 struct clk_init_data init = { }; 2894 char name[64]; 2895 2896 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2897 init.name = name; 2898 init.ops = &clk_fixed_rate_ops; 2899 2900 /* controllers using QMP phys use 125MHz pipe clock interface */ 2901 fixed->fixed_rate = 125000000; 2902 fixed->hw.init = &init; 2903 2904 return devm_clk_hw_register(qmp->dev, &fixed->hw); 2905 } 2906 2907 /* 2908 * Display Port PLL driver block diagram for branch clocks 2909 * 2910 * +------------------------------+ 2911 * | DP_VCO_CLK | 2912 * | | 2913 * | +-------------------+ | 2914 * | | (DP PLL/VCO) | | 2915 * | +---------+---------+ | 2916 * | v | 2917 * | +----------+-----------+ | 2918 * | | hsclk_divsel_clk_src | | 2919 * | +----------+-----------+ | 2920 * +------------------------------+ 2921 * | 2922 * +---------<---------v------------>----------+ 2923 * | | 2924 * +--------v----------------+ | 2925 * | dp_phy_pll_link_clk | | 2926 * | link_clk | | 2927 * +--------+----------------+ | 2928 * | | 2929 * | | 2930 * v v 2931 * Input to DISPCC block | 2932 * for link clk, crypto clk | 2933 * and interface clock | 2934 * | 2935 * | 2936 * +--------<------------+-----------------+---<---+ 2937 * | | | 2938 * +----v---------+ +--------v-----+ +--------v------+ 2939 * | vco_divided | | vco_divided | | vco_divided | 2940 * | _clk_src | | _clk_src | | _clk_src | 2941 * | | | | | | 2942 * |divsel_six | | divsel_two | | divsel_four | 2943 * +-------+------+ +-----+--------+ +--------+------+ 2944 * | | | 2945 * v---->----------v-------------<------v 2946 * | 2947 * +----------+-----------------+ 2948 * | dp_phy_pll_vco_div_clk | 2949 * +---------+------------------+ 2950 * | 2951 * v 2952 * Input to DISPCC block 2953 * for DP pixel clock 2954 * 2955 */ 2956 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2957 { 2958 switch (req->rate) { 2959 case 1620000000UL / 2: 2960 case 2700000000UL / 2: 2961 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2962 return 0; 2963 default: 2964 return -EINVAL; 2965 } 2966 } 2967 2968 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2969 { 2970 const struct qmp_combo *qmp; 2971 const struct phy_configure_opts_dp *dp_opts; 2972 2973 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 2974 dp_opts = &qmp->dp_opts; 2975 2976 switch (dp_opts->link_rate) { 2977 case 1620: 2978 return 1620000000UL / 2; 2979 case 2700: 2980 return 2700000000UL / 2; 2981 case 5400: 2982 return 5400000000UL / 4; 2983 case 8100: 2984 return 8100000000UL / 6; 2985 default: 2986 return 0; 2987 } 2988 } 2989 2990 static const struct clk_ops qmp_dp_pixel_clk_ops = { 2991 .determine_rate = qmp_dp_pixel_clk_determine_rate, 2992 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 2993 }; 2994 2995 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2996 { 2997 switch (req->rate) { 2998 case 162000000: 2999 case 270000000: 3000 case 540000000: 3001 case 810000000: 3002 return 0; 3003 default: 3004 return -EINVAL; 3005 } 3006 } 3007 3008 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3009 { 3010 const struct qmp_combo *qmp; 3011 const struct phy_configure_opts_dp *dp_opts; 3012 3013 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3014 dp_opts = &qmp->dp_opts; 3015 3016 switch (dp_opts->link_rate) { 3017 case 1620: 3018 case 2700: 3019 case 5400: 3020 case 8100: 3021 return dp_opts->link_rate * 100000; 3022 default: 3023 return 0; 3024 } 3025 } 3026 3027 static const struct clk_ops qmp_dp_link_clk_ops = { 3028 .determine_rate = qmp_dp_link_clk_determine_rate, 3029 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3030 }; 3031 3032 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3033 { 3034 struct qmp_combo *qmp = data; 3035 unsigned int idx = clkspec->args[0]; 3036 3037 if (idx >= 2) { 3038 pr_err("%s: invalid index %u\n", __func__, idx); 3039 return ERR_PTR(-EINVAL); 3040 } 3041 3042 if (idx == 0) 3043 return &qmp->dp_link_hw; 3044 3045 return &qmp->dp_pixel_hw; 3046 } 3047 3048 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3049 { 3050 struct clk_init_data init = { }; 3051 char name[64]; 3052 int ret; 3053 3054 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3055 init.ops = &qmp_dp_link_clk_ops; 3056 init.name = name; 3057 qmp->dp_link_hw.init = &init; 3058 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3059 if (ret) 3060 return ret; 3061 3062 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3063 init.ops = &qmp_dp_pixel_clk_ops; 3064 init.name = name; 3065 qmp->dp_pixel_hw.init = &init; 3066 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3067 if (ret) 3068 return ret; 3069 3070 return 0; 3071 } 3072 3073 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3074 { 3075 struct qmp_combo *qmp = data; 3076 3077 switch (clkspec->args[0]) { 3078 case QMP_USB43DP_USB3_PIPE_CLK: 3079 return &qmp->pipe_clk_fixed.hw; 3080 case QMP_USB43DP_DP_LINK_CLK: 3081 return &qmp->dp_link_hw; 3082 case QMP_USB43DP_DP_VCO_DIV_CLK: 3083 return &qmp->dp_pixel_hw; 3084 } 3085 3086 return ERR_PTR(-EINVAL); 3087 } 3088 3089 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3090 struct device_node *dp_np) 3091 { 3092 int ret; 3093 3094 ret = phy_pipe_clk_register(qmp, usb_np); 3095 if (ret) 3096 return ret; 3097 3098 ret = phy_dp_clks_register(qmp, dp_np); 3099 if (ret) 3100 return ret; 3101 3102 /* 3103 * Register a single provider for bindings without child nodes. 3104 */ 3105 if (usb_np == qmp->dev->of_node) 3106 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3107 3108 /* 3109 * Register multiple providers for legacy bindings with child nodes. 3110 */ 3111 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3112 &qmp->pipe_clk_fixed.hw); 3113 if (ret) 3114 return ret; 3115 3116 /* 3117 * Roll a devm action because the clock provider is the child node, but 3118 * the child node is not actually a device. 3119 */ 3120 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3121 if (ret) 3122 return ret; 3123 3124 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3125 if (ret) 3126 return ret; 3127 3128 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3129 } 3130 3131 #if IS_ENABLED(CONFIG_TYPEC) 3132 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3133 enum typec_orientation orientation) 3134 { 3135 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3136 const struct qmp_phy_cfg *cfg = qmp->cfg; 3137 3138 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3139 return 0; 3140 3141 mutex_lock(&qmp->phy_mutex); 3142 qmp->orientation = orientation; 3143 3144 if (qmp->init_count) { 3145 if (qmp->usb_init_count) 3146 qmp_combo_usb_power_off(qmp->usb_phy); 3147 qmp_combo_com_exit(qmp, true); 3148 3149 qmp_combo_com_init(qmp, true); 3150 if (qmp->usb_init_count) 3151 qmp_combo_usb_power_on(qmp->usb_phy); 3152 if (qmp->dp_init_count) 3153 cfg->dp_aux_init(qmp); 3154 } 3155 mutex_unlock(&qmp->phy_mutex); 3156 3157 return 0; 3158 } 3159 3160 static void qmp_combo_typec_unregister(void *data) 3161 { 3162 struct qmp_combo *qmp = data; 3163 3164 typec_switch_unregister(qmp->sw); 3165 } 3166 3167 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3168 { 3169 struct typec_switch_desc sw_desc = {}; 3170 struct device *dev = qmp->dev; 3171 3172 sw_desc.drvdata = qmp; 3173 sw_desc.fwnode = dev->fwnode; 3174 sw_desc.set = qmp_combo_typec_switch_set; 3175 qmp->sw = typec_switch_register(dev, &sw_desc); 3176 if (IS_ERR(qmp->sw)) { 3177 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3178 return PTR_ERR(qmp->sw); 3179 } 3180 3181 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3182 } 3183 #else 3184 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3185 { 3186 return 0; 3187 } 3188 #endif 3189 3190 #if IS_ENABLED(CONFIG_DRM) 3191 static int qmp_combo_bridge_attach(struct drm_bridge *bridge, 3192 enum drm_bridge_attach_flags flags) 3193 { 3194 struct qmp_combo *qmp = container_of(bridge, struct qmp_combo, bridge); 3195 struct drm_bridge *next_bridge; 3196 3197 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 3198 return -EINVAL; 3199 3200 next_bridge = devm_drm_of_get_bridge(qmp->dev, qmp->dev->of_node, 0, 0); 3201 if (IS_ERR(next_bridge)) { 3202 dev_err(qmp->dev, "failed to acquire drm_bridge: %pe\n", next_bridge); 3203 return PTR_ERR(next_bridge); 3204 } 3205 3206 return drm_bridge_attach(bridge->encoder, next_bridge, bridge, 3207 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 3208 } 3209 3210 static const struct drm_bridge_funcs qmp_combo_bridge_funcs = { 3211 .attach = qmp_combo_bridge_attach, 3212 }; 3213 3214 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp) 3215 { 3216 qmp->bridge.funcs = &qmp_combo_bridge_funcs; 3217 qmp->bridge.of_node = qmp->dev->of_node; 3218 3219 return devm_drm_bridge_add(qmp->dev, &qmp->bridge); 3220 } 3221 #else 3222 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp) 3223 { 3224 return 0; 3225 } 3226 #endif 3227 3228 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3229 { 3230 struct device *dev = qmp->dev; 3231 3232 /* 3233 * Get memory resources from the DP child node: 3234 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3235 * tx2 -> 3; rx2 -> 4 3236 * 3237 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3238 * implementation. 3239 */ 3240 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3241 if (IS_ERR(qmp->dp_tx)) 3242 return PTR_ERR(qmp->dp_tx); 3243 3244 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3245 if (IS_ERR(qmp->dp_dp_phy)) 3246 return PTR_ERR(qmp->dp_dp_phy); 3247 3248 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3249 if (IS_ERR(qmp->dp_tx2)) 3250 return PTR_ERR(qmp->dp_tx2); 3251 3252 return 0; 3253 } 3254 3255 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3256 { 3257 const struct qmp_phy_cfg *cfg = qmp->cfg; 3258 struct device *dev = qmp->dev; 3259 3260 /* 3261 * Get memory resources from the USB child node: 3262 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3263 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3264 */ 3265 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3266 if (IS_ERR(qmp->tx)) 3267 return PTR_ERR(qmp->tx); 3268 3269 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3270 if (IS_ERR(qmp->rx)) 3271 return PTR_ERR(qmp->rx); 3272 3273 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3274 if (IS_ERR(qmp->pcs)) 3275 return PTR_ERR(qmp->pcs); 3276 3277 if (cfg->pcs_usb_offset) 3278 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3279 3280 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3281 if (IS_ERR(qmp->tx2)) 3282 return PTR_ERR(qmp->tx2); 3283 3284 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3285 if (IS_ERR(qmp->rx2)) 3286 return PTR_ERR(qmp->rx2); 3287 3288 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3289 if (IS_ERR(qmp->pcs_misc)) { 3290 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3291 qmp->pcs_misc = NULL; 3292 } 3293 3294 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3295 if (IS_ERR(qmp->pipe_clk)) { 3296 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3297 "failed to get pipe clock\n"); 3298 } 3299 3300 return 0; 3301 } 3302 3303 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3304 struct device_node *dp_np) 3305 { 3306 struct platform_device *pdev = to_platform_device(qmp->dev); 3307 int ret; 3308 3309 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3310 if (IS_ERR(qmp->serdes)) 3311 return PTR_ERR(qmp->serdes); 3312 3313 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3314 if (IS_ERR(qmp->com)) 3315 return PTR_ERR(qmp->com); 3316 3317 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3318 if (IS_ERR(qmp->dp_serdes)) 3319 return PTR_ERR(qmp->dp_serdes); 3320 3321 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3322 if (ret) 3323 return ret; 3324 3325 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3326 if (ret) 3327 return ret; 3328 3329 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3330 if (ret < 0) 3331 return ret; 3332 3333 qmp->num_clks = ret; 3334 3335 return 0; 3336 } 3337 3338 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3339 { 3340 struct platform_device *pdev = to_platform_device(qmp->dev); 3341 const struct qmp_phy_cfg *cfg = qmp->cfg; 3342 const struct qmp_combo_offsets *offs = cfg->offsets; 3343 struct device *dev = qmp->dev; 3344 void __iomem *base; 3345 int ret; 3346 3347 if (!offs) 3348 return -EINVAL; 3349 3350 base = devm_platform_ioremap_resource(pdev, 0); 3351 if (IS_ERR(base)) 3352 return PTR_ERR(base); 3353 3354 qmp->com = base + offs->com; 3355 qmp->tx = base + offs->txa; 3356 qmp->rx = base + offs->rxa; 3357 qmp->tx2 = base + offs->txb; 3358 qmp->rx2 = base + offs->rxb; 3359 3360 qmp->serdes = base + offs->usb3_serdes; 3361 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3362 qmp->pcs = base + offs->usb3_pcs; 3363 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3364 3365 qmp->dp_serdes = base + offs->dp_serdes; 3366 if (offs->dp_txa) { 3367 qmp->dp_tx = base + offs->dp_txa; 3368 qmp->dp_tx2 = base + offs->dp_txb; 3369 } else { 3370 qmp->dp_tx = base + offs->txa; 3371 qmp->dp_tx2 = base + offs->txb; 3372 } 3373 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3374 3375 ret = qmp_combo_clk_init(qmp); 3376 if (ret) 3377 return ret; 3378 3379 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3380 if (IS_ERR(qmp->pipe_clk)) { 3381 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3382 "failed to get usb3_pipe clock\n"); 3383 } 3384 3385 return 0; 3386 } 3387 3388 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 3389 { 3390 struct qmp_combo *qmp = dev_get_drvdata(dev); 3391 3392 if (args->args_count == 0) 3393 return ERR_PTR(-EINVAL); 3394 3395 switch (args->args[0]) { 3396 case QMP_USB43DP_USB3_PHY: 3397 return qmp->usb_phy; 3398 case QMP_USB43DP_DP_PHY: 3399 return qmp->dp_phy; 3400 } 3401 3402 return ERR_PTR(-EINVAL); 3403 } 3404 3405 static int qmp_combo_probe(struct platform_device *pdev) 3406 { 3407 struct qmp_combo *qmp; 3408 struct device *dev = &pdev->dev; 3409 struct device_node *dp_np, *usb_np; 3410 struct phy_provider *phy_provider; 3411 int ret; 3412 3413 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3414 if (!qmp) 3415 return -ENOMEM; 3416 3417 qmp->dev = dev; 3418 3419 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3420 3421 qmp->cfg = of_device_get_match_data(dev); 3422 if (!qmp->cfg) 3423 return -EINVAL; 3424 3425 mutex_init(&qmp->phy_mutex); 3426 3427 ret = qmp_combo_reset_init(qmp); 3428 if (ret) 3429 return ret; 3430 3431 ret = qmp_combo_vreg_init(qmp); 3432 if (ret) 3433 return ret; 3434 3435 ret = qmp_combo_typec_switch_register(qmp); 3436 if (ret) 3437 return ret; 3438 3439 ret = qmp_combo_dp_register_bridge(qmp); 3440 if (ret) 3441 return ret; 3442 3443 /* Check for legacy binding with child nodes. */ 3444 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3445 if (usb_np) { 3446 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3447 if (!dp_np) { 3448 of_node_put(usb_np); 3449 return -EINVAL; 3450 } 3451 3452 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3453 } else { 3454 usb_np = of_node_get(dev->of_node); 3455 dp_np = of_node_get(dev->of_node); 3456 3457 ret = qmp_combo_parse_dt(qmp); 3458 } 3459 if (ret) 3460 goto err_node_put; 3461 3462 pm_runtime_set_active(dev); 3463 ret = devm_pm_runtime_enable(dev); 3464 if (ret) 3465 goto err_node_put; 3466 /* 3467 * Prevent runtime pm from being ON by default. Users can enable 3468 * it using power/control in sysfs. 3469 */ 3470 pm_runtime_forbid(dev); 3471 3472 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3473 if (ret) 3474 goto err_node_put; 3475 3476 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3477 if (IS_ERR(qmp->usb_phy)) { 3478 ret = PTR_ERR(qmp->usb_phy); 3479 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3480 goto err_node_put; 3481 } 3482 3483 phy_set_drvdata(qmp->usb_phy, qmp); 3484 3485 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3486 if (IS_ERR(qmp->dp_phy)) { 3487 ret = PTR_ERR(qmp->dp_phy); 3488 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3489 goto err_node_put; 3490 } 3491 3492 phy_set_drvdata(qmp->dp_phy, qmp); 3493 3494 dev_set_drvdata(dev, qmp); 3495 3496 if (usb_np == dev->of_node) 3497 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3498 else 3499 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3500 3501 of_node_put(usb_np); 3502 of_node_put(dp_np); 3503 3504 return PTR_ERR_OR_ZERO(phy_provider); 3505 3506 err_node_put: 3507 of_node_put(usb_np); 3508 of_node_put(dp_np); 3509 return ret; 3510 } 3511 3512 static const struct of_device_id qmp_combo_of_match_table[] = { 3513 { 3514 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3515 .data = &sc7180_usb3dpphy_cfg, 3516 }, 3517 { 3518 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3519 .data = &sm8250_usb3dpphy_cfg, 3520 }, 3521 { 3522 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3523 .data = &sc8180x_usb3dpphy_cfg, 3524 }, 3525 { 3526 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3527 .data = &sc8280xp_usb43dpphy_cfg, 3528 }, 3529 { 3530 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3531 .data = &sdm845_usb3dpphy_cfg, 3532 }, 3533 { 3534 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3535 .data = &sm6350_usb3dpphy_cfg, 3536 }, 3537 { 3538 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3539 .data = &sc8180x_usb3dpphy_cfg, 3540 }, 3541 { 3542 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3543 .data = &sm8250_usb3dpphy_cfg, 3544 }, 3545 { 3546 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3547 .data = &sm8350_usb3dpphy_cfg, 3548 }, 3549 { 3550 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3551 .data = &sm8350_usb3dpphy_cfg, 3552 }, 3553 { 3554 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3555 .data = &sm8550_usb3dpphy_cfg, 3556 }, 3557 { } 3558 }; 3559 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3560 3561 static struct platform_driver qmp_combo_driver = { 3562 .probe = qmp_combo_probe, 3563 .driver = { 3564 .name = "qcom-qmp-combo-phy", 3565 .pm = &qmp_combo_pm_ops, 3566 .of_match_table = qmp_combo_of_match_table, 3567 }, 3568 }; 3569 3570 module_platform_driver(qmp_combo_driver); 3571 3572 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3573 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3574 MODULE_LICENSE("GPL v2"); 3575