1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/bridge/aux-bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp-common.h" 29 30 #include "phy-qcom-qmp.h" 31 #include "phy-qcom-qmp-pcs-misc-v3.h" 32 #include "phy-qcom-qmp-pcs-usb-v4.h" 33 #include "phy-qcom-qmp-pcs-usb-v5.h" 34 #include "phy-qcom-qmp-pcs-usb-v6.h" 35 36 #include "phy-qcom-qmp-dp-com-v3.h" 37 38 #include "phy-qcom-qmp-dp-phy.h" 39 #include "phy-qcom-qmp-dp-phy-v3.h" 40 #include "phy-qcom-qmp-dp-phy-v4.h" 41 #include "phy-qcom-qmp-dp-phy-v5.h" 42 #include "phy-qcom-qmp-dp-phy-v6.h" 43 44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45 /* DP PHY soft reset */ 46 #define SW_DPPHY_RESET BIT(0) 47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_DPPHY_RESET_MUX BIT(1) 49 /* USB3 PHY soft reset */ 50 #define SW_USB3PHY_RESET BIT(2) 51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52 #define SW_USB3PHY_RESET_MUX BIT(3) 53 54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55 #define USB3_MODE BIT(0) /* enables USB3 mode */ 56 #define DP_MODE BIT(1) /* enables DP mode */ 57 58 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 59 #define SW_PORTSELECT_VAL BIT(0) 60 #define SW_PORTSELECT_MUX BIT(1) 61 62 #define PHY_INIT_COMPLETE_TIMEOUT 10000 63 64 /* set of registers with offsets different per-PHY */ 65 enum qphy_reg_layout { 66 /* PCS registers */ 67 QPHY_SW_RESET, 68 QPHY_START_CTRL, 69 QPHY_PCS_STATUS, 70 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 71 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 72 QPHY_PCS_POWER_DOWN_CONTROL, 73 74 QPHY_COM_RESETSM_CNTRL, 75 QPHY_COM_C_READY_STATUS, 76 QPHY_COM_CMN_STATUS, 77 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 78 79 QPHY_DP_PHY_STATUS, 80 QPHY_DP_PHY_VCO_DIV, 81 82 QPHY_TX_TX_POL_INV, 83 QPHY_TX_TX_DRV_LVL, 84 QPHY_TX_TX_EMP_POST1_LVL, 85 QPHY_TX_HIGHZ_DRVR_EN, 86 QPHY_TX_TRANSCEIVER_BIAS_EN, 87 88 /* Keep last to ensure regs_layout arrays are properly initialized */ 89 QPHY_LAYOUT_SIZE 90 }; 91 92 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 93 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 94 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 95 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 96 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 97 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 98 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 99 100 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 101 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 102 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 103 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 104 105 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 106 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 107 108 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 109 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 110 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 111 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 112 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 113 }; 114 115 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 117 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 118 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 119 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 120 121 /* In PCS_USB */ 122 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 123 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 124 125 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 126 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 127 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 128 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 129 130 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 131 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 132 133 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 134 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 135 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 136 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 137 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 138 }; 139 140 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 141 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 142 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 143 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 144 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 145 146 /* In PCS_USB */ 147 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 148 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 149 150 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 151 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 152 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 153 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 154 155 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 156 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 157 158 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 159 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 160 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 161 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 162 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 163 }; 164 165 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 166 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 167 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 168 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 169 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 170 171 /* In PCS_USB */ 172 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 173 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 174 175 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 176 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 177 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 178 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 179 180 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 181 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 182 183 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 184 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 185 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 186 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 187 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 188 }; 189 190 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 227 }; 228 229 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 230 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 231 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 232 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 233 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 234 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 235 }; 236 237 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 259 }; 260 261 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 269 }; 270 271 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 279 }; 280 281 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 289 }; 290 291 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 299 }; 300 301 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 302 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 303 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 304 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 305 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 306 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 308 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 309 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 310 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 311 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 312 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 313 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 314 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 315 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 316 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 317 }; 318 319 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 320 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 321 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 322 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 324 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 325 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 326 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 327 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 328 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 329 }; 330 331 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 332 /* FLL settings */ 333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 338 339 /* Lock Det settings */ 340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 344 345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 364 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 376 }; 377 378 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 379 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 380 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 381 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 382 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 383 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 384 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 385 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 386 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 387 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 388 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 389 }; 390 391 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 392 /* FLL settings */ 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 398 399 /* Lock Det settings */ 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 404 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 415 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 416 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 417 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 419 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 424 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 437 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 440 }; 441 442 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 443 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 444 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 445 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 446 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 447 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 448 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 449 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 450 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 451 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 452 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 453 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 454 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 455 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 456 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 457 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 458 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 459 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 460 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 483 }; 484 485 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 486 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 487 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 488 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 489 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 490 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 491 }; 492 493 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 494 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 495 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 496 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 497 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 498 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 499 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 500 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 501 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 502 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 503 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 504 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 530 }; 531 532 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 533 /* Lock Det settings */ 534 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 535 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 536 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 537 538 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 539 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 540 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 541 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 542 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 543 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 544 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 546 }; 547 548 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 549 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 550 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 551 }; 552 553 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 554 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 555 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 556 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 557 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 558 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 559 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 560 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 561 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 562 }; 563 564 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 585 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 586 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 587 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 588 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 603 }; 604 605 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 606 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 607 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 608 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 609 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 612 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 613 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 614 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 617 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 618 }; 619 620 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 621 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 622 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 623 }; 624 625 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 626 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 627 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 628 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 629 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 630 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 631 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 632 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 633 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 634 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 635 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 636 }; 637 638 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 639 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 640 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 641 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 642 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 643 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 644 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 645 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 646 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 647 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 663 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 664 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 677 }; 678 679 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 694 }; 695 696 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 697 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 698 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 699 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 700 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 701 }; 702 703 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 724 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 725 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 752 }; 753 754 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 755 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 756 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 757 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 758 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 759 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 760 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 761 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 762 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 763 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 764 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 765 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 766 }; 767 768 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 769 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 770 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 771 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 772 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 773 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 774 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 775 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 776 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 777 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 778 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 779 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 780 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 781 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 782 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 783 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 784 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 785 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 786 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 787 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 788 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 789 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 790 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 791 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 792 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 793 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 794 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 795 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 796 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 797 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 798 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 803 804 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 805 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 806 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 807 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 808 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 809 810 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 811 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 812 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 813 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 814 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 815 }; 816 817 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 818 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 819 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 820 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 821 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 822 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 823 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 824 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 825 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 826 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 827 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 828 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 829 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 830 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 831 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 832 }; 833 834 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 835 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 836 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 837 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 838 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 839 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 840 }; 841 842 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 863 }; 864 865 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 873 }; 874 875 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 883 }; 884 885 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 893 }; 894 895 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 903 }; 904 905 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 907 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 908 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 909 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 910 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 911 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 912 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 913 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 914 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 915 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 916 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 917 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 918 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 920 }; 921 922 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 923 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 924 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 925 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 938 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 939 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 940 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 941 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 942 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 943 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 944 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 945 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 946 }; 947 948 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 949 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 950 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 951 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 952 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 953 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 954 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 955 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 956 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 957 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 958 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 959 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 960 }; 961 962 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 963 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 964 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 965 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 966 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 967 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 968 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 969 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 970 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 971 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 972 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 973 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 974 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 975 }; 976 977 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 995 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 996 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 997 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 998 }; 999 1000 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1001 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1002 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1003 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1004 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1005 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1006 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1007 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1008 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1009 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1010 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1011 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1012 }; 1013 1014 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1024 }; 1025 1026 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1036 }; 1037 1038 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1048 }; 1049 1050 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1055 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1056 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1060 }; 1061 1062 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1110 }; 1111 1112 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1113 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1118 }; 1119 1120 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1121 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1155 }; 1156 1157 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1158 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1159 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1160 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1161 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1162 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1163 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1164 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1165 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1166 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1167 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1168 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1169 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1170 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1171 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1172 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1173 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1174 }; 1175 1176 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1184 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1185 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1196 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1227 }; 1228 1229 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1230 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1234 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1235 }; 1236 1237 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1238 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1242 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1243 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1244 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1245 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1246 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1247 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1248 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1249 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1250 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1251 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1252 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1253 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1254 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1255 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1256 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1257 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1258 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1259 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1260 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1261 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1262 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1263 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1264 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1265 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1266 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1267 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1268 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1269 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1270 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1271 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1272 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1273 }; 1274 1275 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1276 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1277 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1278 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1279 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 1280 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 1281 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 1282 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 1283 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55), 1284 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 1285 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1286 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1287 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 1288 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 1289 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 1290 }; 1291 1292 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1293 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1294 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1295 }; 1296 1297 /* list of regulators */ 1298 struct qmp_regulator_data { 1299 const char *name; 1300 unsigned int enable_load; 1301 }; 1302 1303 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1304 { .name = "vdda-phy", .enable_load = 21800 }, 1305 { .name = "vdda-pll", .enable_load = 36000 }, 1306 }; 1307 1308 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1309 { 0x00, 0x0c, 0x15, 0x1a }, 1310 { 0x02, 0x0e, 0x16, 0xff }, 1311 { 0x02, 0x11, 0xff, 0xff }, 1312 { 0x04, 0xff, 0xff, 0xff } 1313 }; 1314 1315 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1316 { 0x02, 0x12, 0x16, 0x1a }, 1317 { 0x09, 0x19, 0x1f, 0xff }, 1318 { 0x10, 0x1f, 0xff, 0xff }, 1319 { 0x1f, 0xff, 0xff, 0xff } 1320 }; 1321 1322 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1323 { 0x00, 0x0c, 0x14, 0x19 }, 1324 { 0x00, 0x0b, 0x12, 0xff }, 1325 { 0x00, 0x0b, 0xff, 0xff }, 1326 { 0x04, 0xff, 0xff, 0xff } 1327 }; 1328 1329 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1330 { 0x08, 0x0f, 0x16, 0x1f }, 1331 { 0x11, 0x1e, 0x1f, 0xff }, 1332 { 0x19, 0x1f, 0xff, 0xff }, 1333 { 0x1f, 0xff, 0xff, 0xff } 1334 }; 1335 1336 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1337 { 0x00, 0x0c, 0x15, 0x1b }, 1338 { 0x02, 0x0e, 0x16, 0xff }, 1339 { 0x02, 0x11, 0xff, 0xff }, 1340 { 0x04, 0xff, 0xff, 0xff } 1341 }; 1342 1343 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1344 { 0x00, 0x0d, 0x14, 0x1a }, 1345 { 0x00, 0x0e, 0x15, 0xff }, 1346 { 0x00, 0x0d, 0xff, 0xff }, 1347 { 0x03, 0xff, 0xff, 0xff } 1348 }; 1349 1350 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1351 { 0x08, 0x0f, 0x16, 0x1f }, 1352 { 0x11, 0x1e, 0x1f, 0xff }, 1353 { 0x16, 0x1f, 0xff, 0xff }, 1354 { 0x1f, 0xff, 0xff, 0xff } 1355 }; 1356 1357 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1358 { 0x20, 0x2c, 0x35, 0x3b }, 1359 { 0x22, 0x2e, 0x36, 0xff }, 1360 { 0x22, 0x31, 0xff, 0xff }, 1361 { 0x24, 0xff, 0xff, 0xff } 1362 }; 1363 1364 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1365 { 0x22, 0x32, 0x36, 0x3a }, 1366 { 0x29, 0x39, 0x3f, 0xff }, 1367 { 0x30, 0x3f, 0xff, 0xff }, 1368 { 0x3f, 0xff, 0xff, 0xff } 1369 }; 1370 1371 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1372 { 0x20, 0x2d, 0x34, 0x3a }, 1373 { 0x20, 0x2e, 0x35, 0xff }, 1374 { 0x20, 0x2e, 0xff, 0xff }, 1375 { 0x24, 0xff, 0xff, 0xff } 1376 }; 1377 1378 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1379 { 0x28, 0x2f, 0x36, 0x3f }, 1380 { 0x31, 0x3e, 0x3f, 0xff }, 1381 { 0x36, 0x3f, 0xff, 0xff }, 1382 { 0x3f, 0xff, 0xff, 0xff } 1383 }; 1384 1385 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = { 1386 { 0x27, 0x2f, 0x36, 0x3f }, 1387 { 0x31, 0x3e, 0x3f, 0xff }, 1388 { 0x36, 0x3f, 0xff, 0xff }, 1389 { 0x3f, 0xff, 0xff, 0xff } 1390 }; 1391 1392 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1393 { 0x20, 0x2d, 0x34, 0x3a }, 1394 { 0x20, 0x2e, 0x35, 0xff }, 1395 { 0x20, 0x2e, 0xff, 0xff }, 1396 { 0x22, 0xff, 0xff, 0xff } 1397 }; 1398 1399 struct qmp_combo; 1400 1401 struct qmp_combo_offsets { 1402 u16 com; 1403 u16 txa; 1404 u16 rxa; 1405 u16 txb; 1406 u16 rxb; 1407 u16 usb3_serdes; 1408 u16 usb3_pcs_misc; 1409 u16 usb3_pcs; 1410 u16 usb3_pcs_usb; 1411 u16 dp_serdes; 1412 u16 dp_txa; 1413 u16 dp_txb; 1414 u16 dp_dp_phy; 1415 }; 1416 1417 struct qmp_phy_cfg { 1418 const struct qmp_combo_offsets *offsets; 1419 1420 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1421 const struct qmp_phy_init_tbl *serdes_tbl; 1422 int serdes_tbl_num; 1423 const struct qmp_phy_init_tbl *tx_tbl; 1424 int tx_tbl_num; 1425 const struct qmp_phy_init_tbl *rx_tbl; 1426 int rx_tbl_num; 1427 const struct qmp_phy_init_tbl *pcs_tbl; 1428 int pcs_tbl_num; 1429 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1430 int pcs_usb_tbl_num; 1431 1432 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1433 int dp_serdes_tbl_num; 1434 const struct qmp_phy_init_tbl *dp_tx_tbl; 1435 int dp_tx_tbl_num; 1436 1437 /* Init sequence for DP PHY block link rates */ 1438 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1439 int serdes_tbl_rbr_num; 1440 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1441 int serdes_tbl_hbr_num; 1442 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1443 int serdes_tbl_hbr2_num; 1444 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1445 int serdes_tbl_hbr3_num; 1446 1447 /* DP PHY swing and pre_emphasis tables */ 1448 const u8 (*swing_hbr_rbr)[4][4]; 1449 const u8 (*swing_hbr3_hbr2)[4][4]; 1450 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1451 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1452 1453 /* DP PHY callbacks */ 1454 int (*configure_dp_phy)(struct qmp_combo *qmp); 1455 void (*configure_dp_tx)(struct qmp_combo *qmp); 1456 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1457 void (*dp_aux_init)(struct qmp_combo *qmp); 1458 1459 /* resets to be requested */ 1460 const char * const *reset_list; 1461 int num_resets; 1462 /* regulators to be requested */ 1463 const struct qmp_regulator_data *vreg_list; 1464 int num_vregs; 1465 1466 /* array of registers with different offsets */ 1467 const unsigned int *regs; 1468 1469 /* true, if PHY needs delay after POWER_DOWN */ 1470 bool has_pwrdn_delay; 1471 1472 /* Offset from PCS to PCS_USB region */ 1473 unsigned int pcs_usb_offset; 1474 1475 }; 1476 1477 struct qmp_combo { 1478 struct device *dev; 1479 1480 const struct qmp_phy_cfg *cfg; 1481 1482 void __iomem *com; 1483 1484 void __iomem *serdes; 1485 void __iomem *tx; 1486 void __iomem *rx; 1487 void __iomem *pcs; 1488 void __iomem *tx2; 1489 void __iomem *rx2; 1490 void __iomem *pcs_misc; 1491 void __iomem *pcs_usb; 1492 1493 void __iomem *dp_serdes; 1494 void __iomem *dp_tx; 1495 void __iomem *dp_tx2; 1496 void __iomem *dp_dp_phy; 1497 1498 struct clk *pipe_clk; 1499 struct clk_bulk_data *clks; 1500 int num_clks; 1501 struct reset_control_bulk_data *resets; 1502 struct regulator_bulk_data *vregs; 1503 1504 struct mutex phy_mutex; 1505 int init_count; 1506 1507 struct phy *usb_phy; 1508 enum phy_mode mode; 1509 unsigned int usb_init_count; 1510 1511 struct phy *dp_phy; 1512 unsigned int dp_aux_cfg; 1513 struct phy_configure_opts_dp dp_opts; 1514 unsigned int dp_init_count; 1515 1516 struct clk_fixed_rate pipe_clk_fixed; 1517 struct clk_hw dp_link_hw; 1518 struct clk_hw dp_pixel_hw; 1519 1520 struct typec_switch_dev *sw; 1521 enum typec_orientation orientation; 1522 }; 1523 1524 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1525 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1526 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1527 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1528 1529 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1530 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1531 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1532 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1533 1534 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1535 { 1536 u32 reg; 1537 1538 reg = readl(base + offset); 1539 reg |= val; 1540 writel(reg, base + offset); 1541 1542 /* ensure that above write is through */ 1543 readl(base + offset); 1544 } 1545 1546 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1547 { 1548 u32 reg; 1549 1550 reg = readl(base + offset); 1551 reg &= ~val; 1552 writel(reg, base + offset); 1553 1554 /* ensure that above write is through */ 1555 readl(base + offset); 1556 } 1557 1558 /* list of clocks required by phy */ 1559 static const char * const qmp_combo_phy_clk_l[] = { 1560 "aux", "cfg_ahb", "ref", "com_aux", 1561 }; 1562 1563 /* list of resets */ 1564 static const char * const msm8996_usb3phy_reset_l[] = { 1565 "phy", "common", 1566 }; 1567 1568 static const char * const sc7180_usb3phy_reset_l[] = { 1569 "phy", 1570 }; 1571 1572 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1573 .com = 0x0000, 1574 .txa = 0x1200, 1575 .rxa = 0x1400, 1576 .txb = 0x1600, 1577 .rxb = 0x1800, 1578 .usb3_serdes = 0x1000, 1579 .usb3_pcs_misc = 0x1a00, 1580 .usb3_pcs = 0x1c00, 1581 .usb3_pcs_usb = 0x1f00, 1582 .dp_serdes = 0x2000, 1583 .dp_txa = 0x2200, 1584 .dp_txb = 0x2600, 1585 .dp_dp_phy = 0x2a00, 1586 }; 1587 1588 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1589 .com = 0x0000, 1590 .txa = 0x0400, 1591 .rxa = 0x0600, 1592 .txb = 0x0a00, 1593 .rxb = 0x0c00, 1594 .usb3_serdes = 0x1000, 1595 .usb3_pcs_misc = 0x1200, 1596 .usb3_pcs = 0x1400, 1597 .usb3_pcs_usb = 0x1700, 1598 .dp_serdes = 0x2000, 1599 .dp_dp_phy = 0x2200, 1600 }; 1601 1602 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1603 .offsets = &qmp_combo_offsets_v3, 1604 1605 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1606 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1607 .tx_tbl = qmp_v3_usb3_tx_tbl, 1608 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1609 .rx_tbl = qmp_v3_usb3_rx_tbl, 1610 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1611 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1612 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1613 1614 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1615 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1616 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1617 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1618 1619 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1620 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1621 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1622 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1623 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1624 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1625 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1626 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1627 1628 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1629 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1630 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1631 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1632 1633 .dp_aux_init = qmp_v3_dp_aux_init, 1634 .configure_dp_tx = qmp_v3_configure_dp_tx, 1635 .configure_dp_phy = qmp_v3_configure_dp_phy, 1636 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1637 1638 .reset_list = sc7180_usb3phy_reset_l, 1639 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1640 .vreg_list = qmp_phy_vreg_l, 1641 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1642 .regs = qmp_v3_usb3phy_regs_layout, 1643 1644 .has_pwrdn_delay = true, 1645 }; 1646 1647 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1648 .offsets = &qmp_combo_offsets_v3, 1649 1650 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1651 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1652 .tx_tbl = qmp_v3_usb3_tx_tbl, 1653 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1654 .rx_tbl = qmp_v3_usb3_rx_tbl, 1655 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1656 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1657 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1658 1659 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1660 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1661 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1662 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1663 1664 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1665 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1666 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1667 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1668 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1669 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1670 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1671 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1672 1673 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1674 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1675 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1676 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1677 1678 .dp_aux_init = qmp_v3_dp_aux_init, 1679 .configure_dp_tx = qmp_v3_configure_dp_tx, 1680 .configure_dp_phy = qmp_v3_configure_dp_phy, 1681 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1682 1683 .reset_list = msm8996_usb3phy_reset_l, 1684 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1685 .vreg_list = qmp_phy_vreg_l, 1686 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1687 .regs = qmp_v3_usb3phy_regs_layout, 1688 1689 .has_pwrdn_delay = true, 1690 }; 1691 1692 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1693 .offsets = &qmp_combo_offsets_v3, 1694 1695 .serdes_tbl = sm8150_usb3_serdes_tbl, 1696 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1697 .tx_tbl = sm8150_usb3_tx_tbl, 1698 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1699 .rx_tbl = sm8150_usb3_rx_tbl, 1700 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1701 .pcs_tbl = sm8150_usb3_pcs_tbl, 1702 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1703 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1704 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1705 1706 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1707 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1708 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1709 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1710 1711 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1712 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1713 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1714 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1715 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1716 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1717 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1718 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1719 1720 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1721 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1722 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1723 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1724 1725 .dp_aux_init = qmp_v4_dp_aux_init, 1726 .configure_dp_tx = qmp_v4_configure_dp_tx, 1727 .configure_dp_phy = qmp_v4_configure_dp_phy, 1728 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1729 1730 .reset_list = msm8996_usb3phy_reset_l, 1731 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1732 .vreg_list = qmp_phy_vreg_l, 1733 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1734 .regs = qmp_v45_usb3phy_regs_layout, 1735 .pcs_usb_offset = 0x300, 1736 1737 .has_pwrdn_delay = true, 1738 }; 1739 1740 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1741 .offsets = &qmp_combo_offsets_v5, 1742 1743 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1744 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1745 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1746 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1747 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1748 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1749 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1750 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1751 1752 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1753 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1754 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1755 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1756 1757 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1758 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1759 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1760 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1761 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1762 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1763 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1764 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1765 1766 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1767 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1768 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1769 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1770 1771 .dp_aux_init = qmp_v4_dp_aux_init, 1772 .configure_dp_tx = qmp_v4_configure_dp_tx, 1773 .configure_dp_phy = qmp_v4_configure_dp_phy, 1774 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1775 1776 .reset_list = msm8996_usb3phy_reset_l, 1777 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1778 .vreg_list = qmp_phy_vreg_l, 1779 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1780 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1781 }; 1782 1783 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 1784 .offsets = &qmp_combo_offsets_v5, 1785 1786 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 1787 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 1788 .tx_tbl = x1e80100_usb43dp_tx_tbl, 1789 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 1790 .rx_tbl = x1e80100_usb43dp_rx_tbl, 1791 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 1792 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 1793 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 1794 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 1795 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 1796 1797 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1798 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1799 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1800 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1801 1802 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1803 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1804 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1805 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1806 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1807 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1808 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1809 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1810 1811 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1812 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1813 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1814 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1815 1816 .dp_aux_init = qmp_v4_dp_aux_init, 1817 .configure_dp_tx = qmp_v4_configure_dp_tx, 1818 .configure_dp_phy = qmp_v4_configure_dp_phy, 1819 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1820 1821 .reset_list = msm8996_usb3phy_reset_l, 1822 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1823 .vreg_list = qmp_phy_vreg_l, 1824 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1825 .regs = qmp_v45_usb3phy_regs_layout, 1826 }; 1827 1828 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1829 .offsets = &qmp_combo_offsets_v3, 1830 1831 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1832 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1833 .tx_tbl = qmp_v3_usb3_tx_tbl, 1834 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1835 .rx_tbl = sm6350_usb3_rx_tbl, 1836 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1837 .pcs_tbl = sm6350_usb3_pcs_tbl, 1838 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1839 1840 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1841 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1842 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1843 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1844 1845 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1846 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1847 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1848 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1849 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1850 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1851 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1852 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1853 1854 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1855 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1856 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1857 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1858 1859 .dp_aux_init = qmp_v3_dp_aux_init, 1860 .configure_dp_tx = qmp_v3_configure_dp_tx, 1861 .configure_dp_phy = qmp_v3_configure_dp_phy, 1862 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1863 1864 .reset_list = msm8996_usb3phy_reset_l, 1865 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1866 .vreg_list = qmp_phy_vreg_l, 1867 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1868 .regs = qmp_v3_usb3phy_regs_layout, 1869 }; 1870 1871 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1872 .offsets = &qmp_combo_offsets_v3, 1873 1874 .serdes_tbl = sm8150_usb3_serdes_tbl, 1875 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1876 .tx_tbl = sm8250_usb3_tx_tbl, 1877 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1878 .rx_tbl = sm8250_usb3_rx_tbl, 1879 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1880 .pcs_tbl = sm8250_usb3_pcs_tbl, 1881 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1882 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1883 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1884 1885 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1886 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1887 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1888 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1889 1890 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1891 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1892 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1893 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1894 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1895 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1896 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1897 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1898 1899 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1900 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1901 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1902 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1903 1904 .dp_aux_init = qmp_v4_dp_aux_init, 1905 .configure_dp_tx = qmp_v4_configure_dp_tx, 1906 .configure_dp_phy = qmp_v4_configure_dp_phy, 1907 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1908 1909 .reset_list = msm8996_usb3phy_reset_l, 1910 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1911 .vreg_list = qmp_phy_vreg_l, 1912 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1913 .regs = qmp_v45_usb3phy_regs_layout, 1914 .pcs_usb_offset = 0x300, 1915 1916 .has_pwrdn_delay = true, 1917 }; 1918 1919 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1920 .offsets = &qmp_combo_offsets_v3, 1921 1922 .serdes_tbl = sm8150_usb3_serdes_tbl, 1923 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1924 .tx_tbl = sm8350_usb3_tx_tbl, 1925 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1926 .rx_tbl = sm8350_usb3_rx_tbl, 1927 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1928 .pcs_tbl = sm8350_usb3_pcs_tbl, 1929 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1930 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1931 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1932 1933 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1934 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1935 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1936 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1937 1938 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1939 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1940 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1941 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1942 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1943 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1944 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1945 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1946 1947 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1948 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1949 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1950 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1951 1952 .dp_aux_init = qmp_v4_dp_aux_init, 1953 .configure_dp_tx = qmp_v4_configure_dp_tx, 1954 .configure_dp_phy = qmp_v4_configure_dp_phy, 1955 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1956 1957 .reset_list = msm8996_usb3phy_reset_l, 1958 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1959 .vreg_list = qmp_phy_vreg_l, 1960 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1961 .regs = qmp_v45_usb3phy_regs_layout, 1962 1963 .has_pwrdn_delay = true, 1964 }; 1965 1966 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1967 .offsets = &qmp_combo_offsets_v3, 1968 1969 .serdes_tbl = sm8550_usb3_serdes_tbl, 1970 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1971 .tx_tbl = sm8550_usb3_tx_tbl, 1972 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1973 .rx_tbl = sm8550_usb3_rx_tbl, 1974 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1975 .pcs_tbl = sm8550_usb3_pcs_tbl, 1976 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1977 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1978 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1979 1980 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1981 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1982 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1983 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1984 1985 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1986 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1987 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1988 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1989 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1990 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1991 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1992 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1993 1994 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1995 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1996 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1997 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1998 1999 .dp_aux_init = qmp_v4_dp_aux_init, 2000 .configure_dp_tx = qmp_v4_configure_dp_tx, 2001 .configure_dp_phy = qmp_v4_configure_dp_phy, 2002 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2003 2004 .regs = qmp_v6_usb3phy_regs_layout, 2005 .reset_list = msm8996_usb3phy_reset_l, 2006 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2007 .vreg_list = qmp_phy_vreg_l, 2008 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2009 }; 2010 2011 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = { 2012 .offsets = &qmp_combo_offsets_v3, 2013 2014 .serdes_tbl = sm8550_usb3_serdes_tbl, 2015 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 2016 .tx_tbl = sm8550_usb3_tx_tbl, 2017 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 2018 .rx_tbl = sm8550_usb3_rx_tbl, 2019 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 2020 .pcs_tbl = sm8550_usb3_pcs_tbl, 2021 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 2022 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 2023 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 2024 2025 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 2026 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 2027 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 2028 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 2029 2030 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 2031 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 2032 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 2033 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 2034 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 2035 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 2036 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 2037 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 2038 2039 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr, 2040 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 2041 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 2042 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 2043 2044 .dp_aux_init = qmp_v4_dp_aux_init, 2045 .configure_dp_tx = qmp_v4_configure_dp_tx, 2046 .configure_dp_phy = qmp_v4_configure_dp_phy, 2047 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 2048 2049 .regs = qmp_v6_usb3phy_regs_layout, 2050 .reset_list = msm8996_usb3phy_reset_l, 2051 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2052 .vreg_list = qmp_phy_vreg_l, 2053 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2054 }; 2055 2056 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 2057 { 2058 const struct qmp_phy_cfg *cfg = qmp->cfg; 2059 void __iomem *serdes = qmp->dp_serdes; 2060 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2061 2062 qmp_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 2063 2064 switch (dp_opts->link_rate) { 2065 case 1620: 2066 qmp_configure(serdes, cfg->serdes_tbl_rbr, 2067 cfg->serdes_tbl_rbr_num); 2068 break; 2069 case 2700: 2070 qmp_configure(serdes, cfg->serdes_tbl_hbr, 2071 cfg->serdes_tbl_hbr_num); 2072 break; 2073 case 5400: 2074 qmp_configure(serdes, cfg->serdes_tbl_hbr2, 2075 cfg->serdes_tbl_hbr2_num); 2076 break; 2077 case 8100: 2078 qmp_configure(serdes, cfg->serdes_tbl_hbr3, 2079 cfg->serdes_tbl_hbr3_num); 2080 break; 2081 default: 2082 /* Other link rates aren't supported */ 2083 return -EINVAL; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 2090 { 2091 const struct qmp_phy_cfg *cfg = qmp->cfg; 2092 2093 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2094 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2095 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2096 2097 /* Turn on BIAS current for PHY/PLL */ 2098 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 2099 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 2100 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2101 2102 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2103 2104 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2105 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 2106 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 2107 DP_PHY_PD_CTL_DP_CLAMP_EN, 2108 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2109 2110 writel(QSERDES_V3_COM_BIAS_EN | 2111 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 2112 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 2113 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 2114 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2115 2116 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2117 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2118 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2119 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2120 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2121 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2122 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2123 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2124 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2125 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2126 qmp->dp_aux_cfg = 0; 2127 2128 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2129 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2130 PHY_AUX_REQ_ERR_MASK, 2131 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 2132 } 2133 2134 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 2135 { 2136 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2137 const struct qmp_phy_cfg *cfg = qmp->cfg; 2138 unsigned int v_level = 0, p_level = 0; 2139 u8 voltage_swing_cfg, pre_emphasis_cfg; 2140 int i; 2141 2142 for (i = 0; i < dp_opts->lanes; i++) { 2143 v_level = max(v_level, dp_opts->voltage[i]); 2144 p_level = max(p_level, dp_opts->pre[i]); 2145 } 2146 2147 if (dp_opts->link_rate <= 2700) { 2148 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 2149 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 2150 } else { 2151 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 2152 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 2153 } 2154 2155 /* TODO: Move check to config check */ 2156 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2157 return -EINVAL; 2158 2159 /* Enable MUX to use Cursor values from these registers */ 2160 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2161 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2162 2163 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2164 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2165 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2166 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2167 2168 return 0; 2169 } 2170 2171 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2172 { 2173 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2174 u32 bias_en, drvr_en; 2175 2176 if (qmp_combo_configure_dp_swing(qmp) < 0) 2177 return; 2178 2179 if (dp_opts->lanes == 1) { 2180 bias_en = 0x3e; 2181 drvr_en = 0x13; 2182 } else { 2183 bias_en = 0x3f; 2184 drvr_en = 0x10; 2185 } 2186 2187 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2188 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2189 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2190 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2191 } 2192 2193 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2194 { 2195 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2196 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2197 u32 val; 2198 2199 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2200 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2201 2202 if (dp_opts->lanes == 4 || reverse) 2203 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2204 if (dp_opts->lanes == 4 || !reverse) 2205 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2206 2207 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2208 2209 if (reverse) 2210 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2211 else 2212 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2213 2214 return reverse; 2215 } 2216 2217 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2218 { 2219 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2220 u32 phy_vco_div; 2221 unsigned long pixel_freq; 2222 const struct qmp_phy_cfg *cfg = qmp->cfg; 2223 2224 switch (dp_opts->link_rate) { 2225 case 1620: 2226 phy_vco_div = 0x1; 2227 pixel_freq = 1620000000UL / 2; 2228 break; 2229 case 2700: 2230 phy_vco_div = 0x1; 2231 pixel_freq = 2700000000UL / 2; 2232 break; 2233 case 5400: 2234 phy_vco_div = 0x2; 2235 pixel_freq = 5400000000UL / 4; 2236 break; 2237 case 8100: 2238 phy_vco_div = 0x0; 2239 pixel_freq = 8100000000UL / 6; 2240 break; 2241 default: 2242 /* Other link rates aren't supported */ 2243 return -EINVAL; 2244 } 2245 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 2246 2247 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2248 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2249 2250 return 0; 2251 } 2252 2253 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2254 { 2255 const struct qmp_phy_cfg *cfg = qmp->cfg; 2256 u32 status; 2257 int ret; 2258 2259 qmp_combo_configure_dp_mode(qmp); 2260 2261 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2262 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2263 2264 ret = qmp_combo_configure_dp_clocks(qmp); 2265 if (ret) 2266 return ret; 2267 2268 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2269 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2270 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2271 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2272 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2273 2274 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2275 2276 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2277 status, 2278 ((status & BIT(0)) > 0), 2279 500, 2280 10000)) 2281 return -ETIMEDOUT; 2282 2283 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2284 2285 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2286 status, 2287 ((status & BIT(1)) > 0), 2288 500, 2289 10000)) 2290 return -ETIMEDOUT; 2291 2292 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2293 udelay(2000); 2294 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2295 2296 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2297 status, 2298 ((status & BIT(1)) > 0), 2299 500, 2300 10000); 2301 } 2302 2303 /* 2304 * We need to calibrate the aux setting here as many times 2305 * as the caller tries 2306 */ 2307 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2308 { 2309 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2310 u8 val; 2311 2312 qmp->dp_aux_cfg++; 2313 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2314 val = cfg1_settings[qmp->dp_aux_cfg]; 2315 2316 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2317 2318 return 0; 2319 } 2320 2321 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2322 { 2323 const struct qmp_phy_cfg *cfg = qmp->cfg; 2324 2325 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2326 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2327 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2328 2329 /* Turn on BIAS current for PHY/PLL */ 2330 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2331 2332 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2333 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2334 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2335 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2336 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2337 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2338 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2339 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2340 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2341 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2342 qmp->dp_aux_cfg = 0; 2343 2344 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2345 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2346 PHY_AUX_REQ_ERR_MASK, 2347 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2348 } 2349 2350 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2351 { 2352 const struct qmp_phy_cfg *cfg = qmp->cfg; 2353 2354 /* Program default values before writing proper values */ 2355 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2356 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2357 2358 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2359 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2360 2361 qmp_combo_configure_dp_swing(qmp); 2362 } 2363 2364 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2365 { 2366 const struct qmp_phy_cfg *cfg = qmp->cfg; 2367 u32 status; 2368 int ret; 2369 2370 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 2371 2372 qmp_combo_configure_dp_mode(qmp); 2373 2374 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2375 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2376 2377 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2378 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2379 2380 ret = qmp_combo_configure_dp_clocks(qmp); 2381 if (ret) 2382 return ret; 2383 2384 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2385 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2386 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2387 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2388 2389 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2390 2391 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2392 status, 2393 ((status & BIT(0)) > 0), 2394 500, 2395 10000)) 2396 return -ETIMEDOUT; 2397 2398 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2399 status, 2400 ((status & BIT(0)) > 0), 2401 500, 2402 10000)) 2403 return -ETIMEDOUT; 2404 2405 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2406 status, 2407 ((status & BIT(1)) > 0), 2408 500, 2409 10000)) 2410 return -ETIMEDOUT; 2411 2412 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2413 2414 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2415 status, 2416 ((status & BIT(0)) > 0), 2417 500, 2418 10000)) 2419 return -ETIMEDOUT; 2420 2421 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2422 status, 2423 ((status & BIT(1)) > 0), 2424 500, 2425 10000)) 2426 return -ETIMEDOUT; 2427 2428 return 0; 2429 } 2430 2431 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2432 { 2433 const struct qmp_phy_cfg *cfg = qmp->cfg; 2434 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2435 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2436 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2437 u32 status; 2438 int ret; 2439 2440 ret = qmp_v456_configure_dp_phy(qmp); 2441 if (ret < 0) 2442 return ret; 2443 2444 /* 2445 * At least for 7nm DP PHY this has to be done after enabling link 2446 * clock. 2447 */ 2448 2449 if (dp_opts->lanes == 1) { 2450 bias0_en = reverse ? 0x3e : 0x15; 2451 bias1_en = reverse ? 0x15 : 0x3e; 2452 drvr0_en = reverse ? 0x13 : 0x10; 2453 drvr1_en = reverse ? 0x10 : 0x13; 2454 } else if (dp_opts->lanes == 2) { 2455 bias0_en = reverse ? 0x3f : 0x15; 2456 bias1_en = reverse ? 0x15 : 0x3f; 2457 drvr0_en = 0x10; 2458 drvr1_en = 0x10; 2459 } else { 2460 bias0_en = 0x3f; 2461 bias1_en = 0x3f; 2462 drvr0_en = 0x10; 2463 drvr1_en = 0x10; 2464 } 2465 2466 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2467 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2468 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2469 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2470 2471 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2472 udelay(2000); 2473 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2474 2475 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2476 status, 2477 ((status & BIT(1)) > 0), 2478 500, 2479 10000)) 2480 return -ETIMEDOUT; 2481 2482 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2483 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2484 2485 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2486 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2487 2488 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2489 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2490 2491 return 0; 2492 } 2493 2494 /* 2495 * We need to calibrate the aux setting here as many times 2496 * as the caller tries 2497 */ 2498 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2499 { 2500 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2501 u8 val; 2502 2503 qmp->dp_aux_cfg++; 2504 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2505 val = cfg1_settings[qmp->dp_aux_cfg]; 2506 2507 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2508 2509 return 0; 2510 } 2511 2512 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2513 { 2514 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2515 struct qmp_combo *qmp = phy_get_drvdata(phy); 2516 const struct qmp_phy_cfg *cfg = qmp->cfg; 2517 2518 mutex_lock(&qmp->phy_mutex); 2519 2520 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2521 if (qmp->dp_opts.set_voltages) { 2522 cfg->configure_dp_tx(qmp); 2523 qmp->dp_opts.set_voltages = 0; 2524 } 2525 2526 mutex_unlock(&qmp->phy_mutex); 2527 2528 return 0; 2529 } 2530 2531 static int qmp_combo_dp_calibrate(struct phy *phy) 2532 { 2533 struct qmp_combo *qmp = phy_get_drvdata(phy); 2534 const struct qmp_phy_cfg *cfg = qmp->cfg; 2535 int ret = 0; 2536 2537 mutex_lock(&qmp->phy_mutex); 2538 2539 if (cfg->calibrate_dp_phy) 2540 ret = cfg->calibrate_dp_phy(qmp); 2541 2542 mutex_unlock(&qmp->phy_mutex); 2543 2544 return ret; 2545 } 2546 2547 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2548 { 2549 const struct qmp_phy_cfg *cfg = qmp->cfg; 2550 void __iomem *com = qmp->com; 2551 int ret; 2552 u32 val; 2553 2554 if (!force && qmp->init_count++) 2555 return 0; 2556 2557 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2558 if (ret) { 2559 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2560 goto err_decrement_count; 2561 } 2562 2563 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2564 if (ret) { 2565 dev_err(qmp->dev, "reset assert failed\n"); 2566 goto err_disable_regulators; 2567 } 2568 2569 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2570 if (ret) { 2571 dev_err(qmp->dev, "reset deassert failed\n"); 2572 goto err_disable_regulators; 2573 } 2574 2575 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2576 if (ret) 2577 goto err_assert_reset; 2578 2579 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2580 2581 /* override hardware control for reset of qmp phy */ 2582 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2583 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2584 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2585 2586 /* Use software based port select and switch on typec orientation */ 2587 val = SW_PORTSELECT_MUX; 2588 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2589 val |= SW_PORTSELECT_VAL; 2590 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2591 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2592 2593 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2594 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2595 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2596 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2597 2598 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2599 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2600 2601 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2602 SW_PWRDN); 2603 2604 return 0; 2605 2606 err_assert_reset: 2607 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2608 err_disable_regulators: 2609 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2610 err_decrement_count: 2611 qmp->init_count--; 2612 2613 return ret; 2614 } 2615 2616 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2617 { 2618 const struct qmp_phy_cfg *cfg = qmp->cfg; 2619 2620 if (!force && --qmp->init_count) 2621 return 0; 2622 2623 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2624 2625 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2626 2627 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2628 2629 return 0; 2630 } 2631 2632 static int qmp_combo_dp_init(struct phy *phy) 2633 { 2634 struct qmp_combo *qmp = phy_get_drvdata(phy); 2635 const struct qmp_phy_cfg *cfg = qmp->cfg; 2636 int ret; 2637 2638 mutex_lock(&qmp->phy_mutex); 2639 2640 ret = qmp_combo_com_init(qmp, false); 2641 if (ret) 2642 goto out_unlock; 2643 2644 cfg->dp_aux_init(qmp); 2645 2646 qmp->dp_init_count++; 2647 2648 out_unlock: 2649 mutex_unlock(&qmp->phy_mutex); 2650 return ret; 2651 } 2652 2653 static int qmp_combo_dp_exit(struct phy *phy) 2654 { 2655 struct qmp_combo *qmp = phy_get_drvdata(phy); 2656 2657 mutex_lock(&qmp->phy_mutex); 2658 2659 qmp_combo_com_exit(qmp, false); 2660 2661 qmp->dp_init_count--; 2662 2663 mutex_unlock(&qmp->phy_mutex); 2664 2665 return 0; 2666 } 2667 2668 static int qmp_combo_dp_power_on(struct phy *phy) 2669 { 2670 struct qmp_combo *qmp = phy_get_drvdata(phy); 2671 const struct qmp_phy_cfg *cfg = qmp->cfg; 2672 void __iomem *tx = qmp->dp_tx; 2673 void __iomem *tx2 = qmp->dp_tx2; 2674 2675 mutex_lock(&qmp->phy_mutex); 2676 2677 qmp_combo_dp_serdes_init(qmp); 2678 2679 qmp_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2680 qmp_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2681 2682 /* Configure special DP tx tunings */ 2683 cfg->configure_dp_tx(qmp); 2684 2685 /* Configure link rate, swing, etc. */ 2686 cfg->configure_dp_phy(qmp); 2687 2688 mutex_unlock(&qmp->phy_mutex); 2689 2690 return 0; 2691 } 2692 2693 static int qmp_combo_dp_power_off(struct phy *phy) 2694 { 2695 struct qmp_combo *qmp = phy_get_drvdata(phy); 2696 2697 mutex_lock(&qmp->phy_mutex); 2698 2699 /* Assert DP PHY power down */ 2700 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2701 2702 mutex_unlock(&qmp->phy_mutex); 2703 2704 return 0; 2705 } 2706 2707 static int qmp_combo_usb_power_on(struct phy *phy) 2708 { 2709 struct qmp_combo *qmp = phy_get_drvdata(phy); 2710 const struct qmp_phy_cfg *cfg = qmp->cfg; 2711 void __iomem *serdes = qmp->serdes; 2712 void __iomem *tx = qmp->tx; 2713 void __iomem *rx = qmp->rx; 2714 void __iomem *tx2 = qmp->tx2; 2715 void __iomem *rx2 = qmp->rx2; 2716 void __iomem *pcs = qmp->pcs; 2717 void __iomem *pcs_usb = qmp->pcs_usb; 2718 void __iomem *status; 2719 unsigned int val; 2720 int ret; 2721 2722 qmp_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2723 2724 ret = clk_prepare_enable(qmp->pipe_clk); 2725 if (ret) { 2726 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2727 return ret; 2728 } 2729 2730 /* Tx, Rx, and PCS configurations */ 2731 qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2732 qmp_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2733 2734 qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2735 qmp_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2736 2737 qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2738 2739 if (pcs_usb) 2740 qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 2741 2742 if (cfg->has_pwrdn_delay) 2743 usleep_range(10, 20); 2744 2745 /* Pull PHY out of reset state */ 2746 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2747 2748 /* start SerDes and Phy-Coding-Sublayer */ 2749 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2750 2751 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2752 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2753 PHY_INIT_COMPLETE_TIMEOUT); 2754 if (ret) { 2755 dev_err(qmp->dev, "phy initialization timed-out\n"); 2756 goto err_disable_pipe_clk; 2757 } 2758 2759 return 0; 2760 2761 err_disable_pipe_clk: 2762 clk_disable_unprepare(qmp->pipe_clk); 2763 2764 return ret; 2765 } 2766 2767 static int qmp_combo_usb_power_off(struct phy *phy) 2768 { 2769 struct qmp_combo *qmp = phy_get_drvdata(phy); 2770 const struct qmp_phy_cfg *cfg = qmp->cfg; 2771 2772 clk_disable_unprepare(qmp->pipe_clk); 2773 2774 /* PHY reset */ 2775 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2776 2777 /* stop SerDes and Phy-Coding-Sublayer */ 2778 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2779 SERDES_START | PCS_START); 2780 2781 /* Put PHY into POWER DOWN state: active low */ 2782 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2783 SW_PWRDN); 2784 2785 return 0; 2786 } 2787 2788 static int qmp_combo_usb_init(struct phy *phy) 2789 { 2790 struct qmp_combo *qmp = phy_get_drvdata(phy); 2791 int ret; 2792 2793 mutex_lock(&qmp->phy_mutex); 2794 ret = qmp_combo_com_init(qmp, false); 2795 if (ret) 2796 goto out_unlock; 2797 2798 ret = qmp_combo_usb_power_on(phy); 2799 if (ret) { 2800 qmp_combo_com_exit(qmp, false); 2801 goto out_unlock; 2802 } 2803 2804 qmp->usb_init_count++; 2805 2806 out_unlock: 2807 mutex_unlock(&qmp->phy_mutex); 2808 return ret; 2809 } 2810 2811 static int qmp_combo_usb_exit(struct phy *phy) 2812 { 2813 struct qmp_combo *qmp = phy_get_drvdata(phy); 2814 int ret; 2815 2816 mutex_lock(&qmp->phy_mutex); 2817 ret = qmp_combo_usb_power_off(phy); 2818 if (ret) 2819 goto out_unlock; 2820 2821 ret = qmp_combo_com_exit(qmp, false); 2822 if (ret) 2823 goto out_unlock; 2824 2825 qmp->usb_init_count--; 2826 2827 out_unlock: 2828 mutex_unlock(&qmp->phy_mutex); 2829 return ret; 2830 } 2831 2832 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2833 { 2834 struct qmp_combo *qmp = phy_get_drvdata(phy); 2835 2836 qmp->mode = mode; 2837 2838 return 0; 2839 } 2840 2841 static const struct phy_ops qmp_combo_usb_phy_ops = { 2842 .init = qmp_combo_usb_init, 2843 .exit = qmp_combo_usb_exit, 2844 .set_mode = qmp_combo_usb_set_mode, 2845 .owner = THIS_MODULE, 2846 }; 2847 2848 static const struct phy_ops qmp_combo_dp_phy_ops = { 2849 .init = qmp_combo_dp_init, 2850 .configure = qmp_combo_dp_configure, 2851 .power_on = qmp_combo_dp_power_on, 2852 .calibrate = qmp_combo_dp_calibrate, 2853 .power_off = qmp_combo_dp_power_off, 2854 .exit = qmp_combo_dp_exit, 2855 .owner = THIS_MODULE, 2856 }; 2857 2858 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2859 { 2860 const struct qmp_phy_cfg *cfg = qmp->cfg; 2861 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2862 void __iomem *pcs_misc = qmp->pcs_misc; 2863 u32 intr_mask; 2864 2865 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2866 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2867 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2868 else 2869 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2870 2871 /* Clear any pending interrupts status */ 2872 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2873 /* Writing 1 followed by 0 clears the interrupt */ 2874 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2875 2876 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2877 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2878 2879 /* Enable required PHY autonomous mode interrupts */ 2880 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2881 2882 /* Enable i/o clamp_n for autonomous mode */ 2883 if (pcs_misc) 2884 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2885 } 2886 2887 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2888 { 2889 const struct qmp_phy_cfg *cfg = qmp->cfg; 2890 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2891 void __iomem *pcs_misc = qmp->pcs_misc; 2892 2893 /* Disable i/o clamp_n on resume for normal mode */ 2894 if (pcs_misc) 2895 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2896 2897 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2898 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2899 2900 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2901 /* Writing 1 followed by 0 clears the interrupt */ 2902 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2903 } 2904 2905 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2906 { 2907 struct qmp_combo *qmp = dev_get_drvdata(dev); 2908 2909 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2910 2911 if (!qmp->init_count) { 2912 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2913 return 0; 2914 } 2915 2916 qmp_combo_enable_autonomous_mode(qmp); 2917 2918 clk_disable_unprepare(qmp->pipe_clk); 2919 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2920 2921 return 0; 2922 } 2923 2924 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2925 { 2926 struct qmp_combo *qmp = dev_get_drvdata(dev); 2927 int ret = 0; 2928 2929 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2930 2931 if (!qmp->init_count) { 2932 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2933 return 0; 2934 } 2935 2936 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2937 if (ret) 2938 return ret; 2939 2940 ret = clk_prepare_enable(qmp->pipe_clk); 2941 if (ret) { 2942 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2943 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2944 return ret; 2945 } 2946 2947 qmp_combo_disable_autonomous_mode(qmp); 2948 2949 return 0; 2950 } 2951 2952 static const struct dev_pm_ops qmp_combo_pm_ops = { 2953 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2954 qmp_combo_runtime_resume, NULL) 2955 }; 2956 2957 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2958 { 2959 const struct qmp_phy_cfg *cfg = qmp->cfg; 2960 struct device *dev = qmp->dev; 2961 int num = cfg->num_vregs; 2962 int ret, i; 2963 2964 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2965 if (!qmp->vregs) 2966 return -ENOMEM; 2967 2968 for (i = 0; i < num; i++) 2969 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2970 2971 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2972 if (ret) { 2973 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2974 return ret; 2975 } 2976 2977 for (i = 0; i < num; i++) { 2978 ret = regulator_set_load(qmp->vregs[i].consumer, 2979 cfg->vreg_list[i].enable_load); 2980 if (ret) { 2981 dev_err(dev, "failed to set load at %s\n", 2982 qmp->vregs[i].supply); 2983 return ret; 2984 } 2985 } 2986 2987 return 0; 2988 } 2989 2990 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2991 { 2992 const struct qmp_phy_cfg *cfg = qmp->cfg; 2993 struct device *dev = qmp->dev; 2994 int i; 2995 int ret; 2996 2997 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2998 sizeof(*qmp->resets), GFP_KERNEL); 2999 if (!qmp->resets) 3000 return -ENOMEM; 3001 3002 for (i = 0; i < cfg->num_resets; i++) 3003 qmp->resets[i].id = cfg->reset_list[i]; 3004 3005 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 3006 if (ret) 3007 return dev_err_probe(dev, ret, "failed to get resets\n"); 3008 3009 return 0; 3010 } 3011 3012 static int qmp_combo_clk_init(struct qmp_combo *qmp) 3013 { 3014 struct device *dev = qmp->dev; 3015 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 3016 int i; 3017 3018 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 3019 if (!qmp->clks) 3020 return -ENOMEM; 3021 3022 for (i = 0; i < num; i++) 3023 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 3024 3025 qmp->num_clks = num; 3026 3027 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 3028 } 3029 3030 static void phy_clk_release_provider(void *res) 3031 { 3032 of_clk_del_provider(res); 3033 } 3034 3035 /* 3036 * Register a fixed rate pipe clock. 3037 * 3038 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 3039 * controls it. The <s>_pipe_clk coming out of the GCC is requested 3040 * by the PHY driver for its operations. 3041 * We register the <s>_pipe_clksrc here. The gcc driver takes care 3042 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 3043 * Below picture shows this relationship. 3044 * 3045 * +---------------+ 3046 * | PHY block |<<---------------------------------------+ 3047 * | | | 3048 * | +-------+ | +-----+ | 3049 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3050 * clk | +-------+ | +-----+ 3051 * +---------------+ 3052 */ 3053 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 3054 { 3055 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3056 struct clk_init_data init = { }; 3057 char name[64]; 3058 3059 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 3060 init.name = name; 3061 init.ops = &clk_fixed_rate_ops; 3062 3063 /* controllers using QMP phys use 125MHz pipe clock interface */ 3064 fixed->fixed_rate = 125000000; 3065 fixed->hw.init = &init; 3066 3067 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3068 } 3069 3070 /* 3071 * Display Port PLL driver block diagram for branch clocks 3072 * 3073 * +------------------------------+ 3074 * | DP_VCO_CLK | 3075 * | | 3076 * | +-------------------+ | 3077 * | | (DP PLL/VCO) | | 3078 * | +---------+---------+ | 3079 * | v | 3080 * | +----------+-----------+ | 3081 * | | hsclk_divsel_clk_src | | 3082 * | +----------+-----------+ | 3083 * +------------------------------+ 3084 * | 3085 * +---------<---------v------------>----------+ 3086 * | | 3087 * +--------v----------------+ | 3088 * | dp_phy_pll_link_clk | | 3089 * | link_clk | | 3090 * +--------+----------------+ | 3091 * | | 3092 * | | 3093 * v v 3094 * Input to DISPCC block | 3095 * for link clk, crypto clk | 3096 * and interface clock | 3097 * | 3098 * | 3099 * +--------<------------+-----------------+---<---+ 3100 * | | | 3101 * +----v---------+ +--------v-----+ +--------v------+ 3102 * | vco_divided | | vco_divided | | vco_divided | 3103 * | _clk_src | | _clk_src | | _clk_src | 3104 * | | | | | | 3105 * |divsel_six | | divsel_two | | divsel_four | 3106 * +-------+------+ +-----+--------+ +--------+------+ 3107 * | | | 3108 * v---->----------v-------------<------v 3109 * | 3110 * +----------+-----------------+ 3111 * | dp_phy_pll_vco_div_clk | 3112 * +---------+------------------+ 3113 * | 3114 * v 3115 * Input to DISPCC block 3116 * for DP pixel clock 3117 * 3118 */ 3119 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3120 { 3121 switch (req->rate) { 3122 case 1620000000UL / 2: 3123 case 2700000000UL / 2: 3124 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3125 return 0; 3126 default: 3127 return -EINVAL; 3128 } 3129 } 3130 3131 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3132 { 3133 const struct qmp_combo *qmp; 3134 const struct phy_configure_opts_dp *dp_opts; 3135 3136 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 3137 dp_opts = &qmp->dp_opts; 3138 3139 switch (dp_opts->link_rate) { 3140 case 1620: 3141 return 1620000000UL / 2; 3142 case 2700: 3143 return 2700000000UL / 2; 3144 case 5400: 3145 return 5400000000UL / 4; 3146 case 8100: 3147 return 8100000000UL / 6; 3148 default: 3149 return 0; 3150 } 3151 } 3152 3153 static const struct clk_ops qmp_dp_pixel_clk_ops = { 3154 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3155 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3156 }; 3157 3158 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3159 { 3160 switch (req->rate) { 3161 case 162000000: 3162 case 270000000: 3163 case 540000000: 3164 case 810000000: 3165 return 0; 3166 default: 3167 return -EINVAL; 3168 } 3169 } 3170 3171 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3172 { 3173 const struct qmp_combo *qmp; 3174 const struct phy_configure_opts_dp *dp_opts; 3175 3176 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3177 dp_opts = &qmp->dp_opts; 3178 3179 switch (dp_opts->link_rate) { 3180 case 1620: 3181 case 2700: 3182 case 5400: 3183 case 8100: 3184 return dp_opts->link_rate * 100000; 3185 default: 3186 return 0; 3187 } 3188 } 3189 3190 static const struct clk_ops qmp_dp_link_clk_ops = { 3191 .determine_rate = qmp_dp_link_clk_determine_rate, 3192 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3193 }; 3194 3195 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3196 { 3197 struct qmp_combo *qmp = data; 3198 unsigned int idx = clkspec->args[0]; 3199 3200 if (idx >= 2) { 3201 pr_err("%s: invalid index %u\n", __func__, idx); 3202 return ERR_PTR(-EINVAL); 3203 } 3204 3205 if (idx == 0) 3206 return &qmp->dp_link_hw; 3207 3208 return &qmp->dp_pixel_hw; 3209 } 3210 3211 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3212 { 3213 struct clk_init_data init = { }; 3214 char name[64]; 3215 int ret; 3216 3217 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3218 init.ops = &qmp_dp_link_clk_ops; 3219 init.name = name; 3220 qmp->dp_link_hw.init = &init; 3221 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3222 if (ret) 3223 return ret; 3224 3225 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3226 init.ops = &qmp_dp_pixel_clk_ops; 3227 init.name = name; 3228 qmp->dp_pixel_hw.init = &init; 3229 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3230 if (ret) 3231 return ret; 3232 3233 return 0; 3234 } 3235 3236 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3237 { 3238 struct qmp_combo *qmp = data; 3239 3240 switch (clkspec->args[0]) { 3241 case QMP_USB43DP_USB3_PIPE_CLK: 3242 return &qmp->pipe_clk_fixed.hw; 3243 case QMP_USB43DP_DP_LINK_CLK: 3244 return &qmp->dp_link_hw; 3245 case QMP_USB43DP_DP_VCO_DIV_CLK: 3246 return &qmp->dp_pixel_hw; 3247 } 3248 3249 return ERR_PTR(-EINVAL); 3250 } 3251 3252 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3253 struct device_node *dp_np) 3254 { 3255 int ret; 3256 3257 ret = phy_pipe_clk_register(qmp, usb_np); 3258 if (ret) 3259 return ret; 3260 3261 ret = phy_dp_clks_register(qmp, dp_np); 3262 if (ret) 3263 return ret; 3264 3265 /* 3266 * Register a single provider for bindings without child nodes. 3267 */ 3268 if (usb_np == qmp->dev->of_node) 3269 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3270 3271 /* 3272 * Register multiple providers for legacy bindings with child nodes. 3273 */ 3274 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3275 &qmp->pipe_clk_fixed.hw); 3276 if (ret) 3277 return ret; 3278 3279 /* 3280 * Roll a devm action because the clock provider is the child node, but 3281 * the child node is not actually a device. 3282 */ 3283 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3284 if (ret) 3285 return ret; 3286 3287 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3288 if (ret) 3289 return ret; 3290 3291 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3292 } 3293 3294 #if IS_ENABLED(CONFIG_TYPEC) 3295 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3296 enum typec_orientation orientation) 3297 { 3298 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3299 const struct qmp_phy_cfg *cfg = qmp->cfg; 3300 3301 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3302 return 0; 3303 3304 mutex_lock(&qmp->phy_mutex); 3305 qmp->orientation = orientation; 3306 3307 if (qmp->init_count) { 3308 if (qmp->usb_init_count) 3309 qmp_combo_usb_power_off(qmp->usb_phy); 3310 qmp_combo_com_exit(qmp, true); 3311 3312 qmp_combo_com_init(qmp, true); 3313 if (qmp->usb_init_count) 3314 qmp_combo_usb_power_on(qmp->usb_phy); 3315 if (qmp->dp_init_count) 3316 cfg->dp_aux_init(qmp); 3317 } 3318 mutex_unlock(&qmp->phy_mutex); 3319 3320 return 0; 3321 } 3322 3323 static void qmp_combo_typec_unregister(void *data) 3324 { 3325 struct qmp_combo *qmp = data; 3326 3327 typec_switch_unregister(qmp->sw); 3328 } 3329 3330 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3331 { 3332 struct typec_switch_desc sw_desc = {}; 3333 struct device *dev = qmp->dev; 3334 3335 sw_desc.drvdata = qmp; 3336 sw_desc.fwnode = dev->fwnode; 3337 sw_desc.set = qmp_combo_typec_switch_set; 3338 qmp->sw = typec_switch_register(dev, &sw_desc); 3339 if (IS_ERR(qmp->sw)) { 3340 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3341 return PTR_ERR(qmp->sw); 3342 } 3343 3344 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3345 } 3346 #else 3347 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3348 { 3349 return 0; 3350 } 3351 #endif 3352 3353 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3354 { 3355 struct device *dev = qmp->dev; 3356 3357 /* 3358 * Get memory resources from the DP child node: 3359 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3360 * tx2 -> 3; rx2 -> 4 3361 * 3362 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3363 * implementation. 3364 */ 3365 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3366 if (IS_ERR(qmp->dp_tx)) 3367 return PTR_ERR(qmp->dp_tx); 3368 3369 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3370 if (IS_ERR(qmp->dp_dp_phy)) 3371 return PTR_ERR(qmp->dp_dp_phy); 3372 3373 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3374 if (IS_ERR(qmp->dp_tx2)) 3375 return PTR_ERR(qmp->dp_tx2); 3376 3377 return 0; 3378 } 3379 3380 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3381 { 3382 const struct qmp_phy_cfg *cfg = qmp->cfg; 3383 struct device *dev = qmp->dev; 3384 3385 /* 3386 * Get memory resources from the USB child node: 3387 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3388 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3389 */ 3390 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3391 if (IS_ERR(qmp->tx)) 3392 return PTR_ERR(qmp->tx); 3393 3394 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3395 if (IS_ERR(qmp->rx)) 3396 return PTR_ERR(qmp->rx); 3397 3398 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3399 if (IS_ERR(qmp->pcs)) 3400 return PTR_ERR(qmp->pcs); 3401 3402 if (cfg->pcs_usb_offset) 3403 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3404 3405 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3406 if (IS_ERR(qmp->tx2)) 3407 return PTR_ERR(qmp->tx2); 3408 3409 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3410 if (IS_ERR(qmp->rx2)) 3411 return PTR_ERR(qmp->rx2); 3412 3413 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3414 if (IS_ERR(qmp->pcs_misc)) { 3415 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3416 qmp->pcs_misc = NULL; 3417 } 3418 3419 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3420 if (IS_ERR(qmp->pipe_clk)) { 3421 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3422 "failed to get pipe clock\n"); 3423 } 3424 3425 return 0; 3426 } 3427 3428 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3429 struct device_node *dp_np) 3430 { 3431 struct platform_device *pdev = to_platform_device(qmp->dev); 3432 int ret; 3433 3434 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3435 if (IS_ERR(qmp->serdes)) 3436 return PTR_ERR(qmp->serdes); 3437 3438 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3439 if (IS_ERR(qmp->com)) 3440 return PTR_ERR(qmp->com); 3441 3442 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3443 if (IS_ERR(qmp->dp_serdes)) 3444 return PTR_ERR(qmp->dp_serdes); 3445 3446 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3447 if (ret) 3448 return ret; 3449 3450 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3451 if (ret) 3452 return ret; 3453 3454 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3455 if (ret < 0) 3456 return ret; 3457 3458 qmp->num_clks = ret; 3459 3460 return 0; 3461 } 3462 3463 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3464 { 3465 struct platform_device *pdev = to_platform_device(qmp->dev); 3466 const struct qmp_phy_cfg *cfg = qmp->cfg; 3467 const struct qmp_combo_offsets *offs = cfg->offsets; 3468 struct device *dev = qmp->dev; 3469 void __iomem *base; 3470 int ret; 3471 3472 if (!offs) 3473 return -EINVAL; 3474 3475 base = devm_platform_ioremap_resource(pdev, 0); 3476 if (IS_ERR(base)) 3477 return PTR_ERR(base); 3478 3479 qmp->com = base + offs->com; 3480 qmp->tx = base + offs->txa; 3481 qmp->rx = base + offs->rxa; 3482 qmp->tx2 = base + offs->txb; 3483 qmp->rx2 = base + offs->rxb; 3484 3485 qmp->serdes = base + offs->usb3_serdes; 3486 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3487 qmp->pcs = base + offs->usb3_pcs; 3488 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3489 3490 qmp->dp_serdes = base + offs->dp_serdes; 3491 if (offs->dp_txa) { 3492 qmp->dp_tx = base + offs->dp_txa; 3493 qmp->dp_tx2 = base + offs->dp_txb; 3494 } else { 3495 qmp->dp_tx = base + offs->txa; 3496 qmp->dp_tx2 = base + offs->txb; 3497 } 3498 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3499 3500 ret = qmp_combo_clk_init(qmp); 3501 if (ret) 3502 return ret; 3503 3504 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3505 if (IS_ERR(qmp->pipe_clk)) { 3506 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3507 "failed to get usb3_pipe clock\n"); 3508 } 3509 3510 return 0; 3511 } 3512 3513 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 3514 { 3515 struct qmp_combo *qmp = dev_get_drvdata(dev); 3516 3517 if (args->args_count == 0) 3518 return ERR_PTR(-EINVAL); 3519 3520 switch (args->args[0]) { 3521 case QMP_USB43DP_USB3_PHY: 3522 return qmp->usb_phy; 3523 case QMP_USB43DP_DP_PHY: 3524 return qmp->dp_phy; 3525 } 3526 3527 return ERR_PTR(-EINVAL); 3528 } 3529 3530 static int qmp_combo_probe(struct platform_device *pdev) 3531 { 3532 struct qmp_combo *qmp; 3533 struct device *dev = &pdev->dev; 3534 struct device_node *dp_np, *usb_np; 3535 struct phy_provider *phy_provider; 3536 int ret; 3537 3538 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3539 if (!qmp) 3540 return -ENOMEM; 3541 3542 qmp->dev = dev; 3543 3544 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3545 3546 qmp->cfg = of_device_get_match_data(dev); 3547 if (!qmp->cfg) 3548 return -EINVAL; 3549 3550 mutex_init(&qmp->phy_mutex); 3551 3552 ret = qmp_combo_reset_init(qmp); 3553 if (ret) 3554 return ret; 3555 3556 ret = qmp_combo_vreg_init(qmp); 3557 if (ret) 3558 return ret; 3559 3560 /* Check for legacy binding with child nodes. */ 3561 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3562 if (usb_np) { 3563 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3564 if (!dp_np) { 3565 of_node_put(usb_np); 3566 return -EINVAL; 3567 } 3568 3569 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3570 } else { 3571 usb_np = of_node_get(dev->of_node); 3572 dp_np = of_node_get(dev->of_node); 3573 3574 ret = qmp_combo_parse_dt(qmp); 3575 } 3576 if (ret) 3577 goto err_node_put; 3578 3579 ret = qmp_combo_typec_switch_register(qmp); 3580 if (ret) 3581 goto err_node_put; 3582 3583 ret = drm_aux_bridge_register(dev); 3584 if (ret) 3585 goto err_node_put; 3586 3587 pm_runtime_set_active(dev); 3588 ret = devm_pm_runtime_enable(dev); 3589 if (ret) 3590 goto err_node_put; 3591 /* 3592 * Prevent runtime pm from being ON by default. Users can enable 3593 * it using power/control in sysfs. 3594 */ 3595 pm_runtime_forbid(dev); 3596 3597 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3598 if (ret) 3599 goto err_node_put; 3600 3601 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3602 if (IS_ERR(qmp->usb_phy)) { 3603 ret = PTR_ERR(qmp->usb_phy); 3604 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3605 goto err_node_put; 3606 } 3607 3608 phy_set_drvdata(qmp->usb_phy, qmp); 3609 3610 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3611 if (IS_ERR(qmp->dp_phy)) { 3612 ret = PTR_ERR(qmp->dp_phy); 3613 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3614 goto err_node_put; 3615 } 3616 3617 phy_set_drvdata(qmp->dp_phy, qmp); 3618 3619 dev_set_drvdata(dev, qmp); 3620 3621 if (usb_np == dev->of_node) 3622 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3623 else 3624 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3625 3626 of_node_put(usb_np); 3627 of_node_put(dp_np); 3628 3629 return PTR_ERR_OR_ZERO(phy_provider); 3630 3631 err_node_put: 3632 of_node_put(usb_np); 3633 of_node_put(dp_np); 3634 return ret; 3635 } 3636 3637 static const struct of_device_id qmp_combo_of_match_table[] = { 3638 { 3639 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3640 .data = &sc7180_usb3dpphy_cfg, 3641 }, 3642 { 3643 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3644 .data = &sm8250_usb3dpphy_cfg, 3645 }, 3646 { 3647 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3648 .data = &sc8180x_usb3dpphy_cfg, 3649 }, 3650 { 3651 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3652 .data = &sc8280xp_usb43dpphy_cfg, 3653 }, 3654 { 3655 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3656 .data = &sdm845_usb3dpphy_cfg, 3657 }, 3658 { 3659 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3660 .data = &sm6350_usb3dpphy_cfg, 3661 }, 3662 { 3663 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3664 .data = &sc8180x_usb3dpphy_cfg, 3665 }, 3666 { 3667 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3668 .data = &sm8250_usb3dpphy_cfg, 3669 }, 3670 { 3671 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3672 .data = &sm8350_usb3dpphy_cfg, 3673 }, 3674 { 3675 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3676 .data = &sm8350_usb3dpphy_cfg, 3677 }, 3678 { 3679 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3680 .data = &sm8550_usb3dpphy_cfg, 3681 }, 3682 { 3683 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 3684 .data = &sm8650_usb3dpphy_cfg, 3685 }, 3686 { 3687 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 3688 .data = &x1e80100_usb3dpphy_cfg, 3689 }, 3690 { } 3691 }; 3692 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3693 3694 static struct platform_driver qmp_combo_driver = { 3695 .probe = qmp_combo_probe, 3696 .driver = { 3697 .name = "qcom-qmp-combo-phy", 3698 .pm = &qmp_combo_pm_ops, 3699 .of_match_table = qmp_combo_of_match_table, 3700 }, 3701 }; 3702 3703 module_platform_driver(qmp_combo_driver); 3704 3705 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3706 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3707 MODULE_LICENSE("GPL v2"); 3708