1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Ltd. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/phy/phy.h> 17 #include <linux/phy/phy-dp.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp-dp-phy.h" 26 #include "phy-qcom-qmp-qserdes-com-v4.h" 27 28 /* EDP_PHY registers */ 29 #define DP_PHY_CFG 0x0010 30 #define DP_PHY_CFG_1 0x0014 31 #define DP_PHY_PD_CTL 0x001c 32 #define DP_PHY_MODE 0x0020 33 34 #define DP_PHY_AUX_CFG0 0x0024 35 #define DP_PHY_AUX_CFG1 0x0028 36 #define DP_PHY_AUX_CFG2 0x002C 37 #define DP_PHY_AUX_CFG3 0x0030 38 #define DP_PHY_AUX_CFG4 0x0034 39 #define DP_PHY_AUX_CFG5 0x0038 40 #define DP_PHY_AUX_CFG6 0x003C 41 #define DP_PHY_AUX_CFG7 0x0040 42 #define DP_PHY_AUX_CFG8 0x0044 43 #define DP_PHY_AUX_CFG9 0x0048 44 45 #define DP_PHY_AUX_INTERRUPT_MASK 0x0058 46 47 #define DP_PHY_VCO_DIV 0x0074 48 #define DP_PHY_TX0_TX1_LANE_CTL 0x007c 49 #define DP_PHY_TX2_TX3_LANE_CTL 0x00a0 50 51 #define DP_PHY_STATUS 0x00e0 52 53 /* LANE_TXn registers */ 54 #define TXn_CLKBUF_ENABLE 0x0000 55 #define TXn_TX_EMP_POST1_LVL 0x0004 56 57 #define TXn_TX_DRV_LVL 0x0014 58 #define TXn_TX_DRV_LVL_OFFSET 0x0018 59 #define TXn_RESET_TSYNC_EN 0x001c 60 #define TXn_LDO_CONFIG 0x0084 61 #define TXn_TX_BAND 0x0028 62 63 #define TXn_RES_CODE_LANE_OFFSET_TX0 0x0044 64 #define TXn_RES_CODE_LANE_OFFSET_TX1 0x0048 65 66 #define TXn_TRANSCEIVER_BIAS_EN 0x0054 67 #define TXn_HIGHZ_DRVR_EN 0x0058 68 #define TXn_TX_POL_INV 0x005c 69 #define TXn_LANE_MODE_1 0x0064 70 71 #define TXn_TRAN_DRVR_EMP_EN 0x0078 72 73 struct qcom_edp_swing_pre_emph_cfg { 74 const u8 (*swing_hbr_rbr)[4][4]; 75 const u8 (*swing_hbr3_hbr2)[4][4]; 76 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 77 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 78 }; 79 80 struct qcom_edp_phy_cfg { 81 bool is_edp; 82 const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; 83 }; 84 85 struct qcom_edp { 86 struct device *dev; 87 const struct qcom_edp_phy_cfg *cfg; 88 89 struct phy *phy; 90 91 void __iomem *edp; 92 void __iomem *tx0; 93 void __iomem *tx1; 94 void __iomem *pll; 95 96 struct clk_hw dp_link_hw; 97 struct clk_hw dp_pixel_hw; 98 99 struct phy_configure_opts_dp dp_opts; 100 101 struct clk_bulk_data clks[2]; 102 struct regulator_bulk_data supplies[2]; 103 104 bool is_edp; 105 }; 106 107 static const u8 dp_swing_hbr_rbr[4][4] = { 108 { 0x08, 0x0f, 0x16, 0x1f }, 109 { 0x11, 0x1e, 0x1f, 0xff }, 110 { 0x16, 0x1f, 0xff, 0xff }, 111 { 0x1f, 0xff, 0xff, 0xff } 112 }; 113 114 static const u8 dp_pre_emp_hbr_rbr[4][4] = { 115 { 0x00, 0x0d, 0x14, 0x1a }, 116 { 0x00, 0x0e, 0x15, 0xff }, 117 { 0x00, 0x0e, 0xff, 0xff }, 118 { 0x03, 0xff, 0xff, 0xff } 119 }; 120 121 static const u8 dp_swing_hbr2_hbr3[4][4] = { 122 { 0x02, 0x12, 0x16, 0x1a }, 123 { 0x09, 0x19, 0x1f, 0xff }, 124 { 0x10, 0x1f, 0xff, 0xff }, 125 { 0x1f, 0xff, 0xff, 0xff } 126 }; 127 128 static const u8 dp_pre_emp_hbr2_hbr3[4][4] = { 129 { 0x00, 0x0c, 0x15, 0x1b }, 130 { 0x02, 0x0e, 0x16, 0xff }, 131 { 0x02, 0x11, 0xff, 0xff }, 132 { 0x04, 0xff, 0xff, 0xff } 133 }; 134 135 static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = { 136 .swing_hbr_rbr = &dp_swing_hbr_rbr, 137 .swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3, 138 .pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr, 139 .pre_emphasis_hbr3_hbr2 = &dp_pre_emp_hbr2_hbr3, 140 }; 141 142 static const u8 edp_swing_hbr_rbr[4][4] = { 143 { 0x07, 0x0f, 0x16, 0x1f }, 144 { 0x0d, 0x16, 0x1e, 0xff }, 145 { 0x11, 0x1b, 0xff, 0xff }, 146 { 0x16, 0xff, 0xff, 0xff } 147 }; 148 149 static const u8 edp_pre_emp_hbr_rbr[4][4] = { 150 { 0x05, 0x12, 0x17, 0x1d }, 151 { 0x05, 0x11, 0x18, 0xff }, 152 { 0x06, 0x11, 0xff, 0xff }, 153 { 0x00, 0xff, 0xff, 0xff } 154 }; 155 156 static const u8 edp_swing_hbr2_hbr3[4][4] = { 157 { 0x0b, 0x11, 0x17, 0x1c }, 158 { 0x10, 0x19, 0x1f, 0xff }, 159 { 0x19, 0x1f, 0xff, 0xff }, 160 { 0x1f, 0xff, 0xff, 0xff } 161 }; 162 163 static const u8 edp_pre_emp_hbr2_hbr3[4][4] = { 164 { 0x08, 0x11, 0x17, 0x1b }, 165 { 0x00, 0x0c, 0x13, 0xff }, 166 { 0x05, 0x10, 0xff, 0xff }, 167 { 0x00, 0xff, 0xff, 0xff } 168 }; 169 170 static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = { 171 .swing_hbr_rbr = &edp_swing_hbr_rbr, 172 .swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3, 173 .pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr, 174 .pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3, 175 }; 176 177 static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = { 178 }; 179 180 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = { 181 .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg, 182 }; 183 184 static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = { 185 .is_edp = true, 186 .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg, 187 }; 188 189 static int qcom_edp_phy_init(struct phy *phy) 190 { 191 struct qcom_edp *edp = phy_get_drvdata(phy); 192 int ret; 193 u8 cfg8; 194 195 ret = regulator_bulk_enable(ARRAY_SIZE(edp->supplies), edp->supplies); 196 if (ret) 197 return ret; 198 199 ret = clk_bulk_prepare_enable(ARRAY_SIZE(edp->clks), edp->clks); 200 if (ret) 201 goto out_disable_supplies; 202 203 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 204 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 205 edp->edp + DP_PHY_PD_CTL); 206 207 /* Turn on BIAS current for PHY/PLL */ 208 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 209 210 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); 211 msleep(20); 212 213 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 214 DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | 215 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 216 edp->edp + DP_PHY_PD_CTL); 217 218 /* 219 * TODO: Re-work the conditions around setting the cfg8 value 220 * when more information becomes available about why this is 221 * even needed. 222 */ 223 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) 224 cfg8 = 0xb7; 225 else 226 cfg8 = 0x37; 227 228 writel(0xfc, edp->edp + DP_PHY_MODE); 229 230 writel(0x00, edp->edp + DP_PHY_AUX_CFG0); 231 writel(0x13, edp->edp + DP_PHY_AUX_CFG1); 232 writel(0x24, edp->edp + DP_PHY_AUX_CFG2); 233 writel(0x00, edp->edp + DP_PHY_AUX_CFG3); 234 writel(0x0a, edp->edp + DP_PHY_AUX_CFG4); 235 writel(0x26, edp->edp + DP_PHY_AUX_CFG5); 236 writel(0x0a, edp->edp + DP_PHY_AUX_CFG6); 237 writel(0x03, edp->edp + DP_PHY_AUX_CFG7); 238 writel(cfg8, edp->edp + DP_PHY_AUX_CFG8); 239 writel(0x03, edp->edp + DP_PHY_AUX_CFG9); 240 241 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 242 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 243 PHY_AUX_REQ_ERR_MASK, edp->edp + DP_PHY_AUX_INTERRUPT_MASK); 244 245 msleep(20); 246 247 return 0; 248 249 out_disable_supplies: 250 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); 251 252 return ret; 253 } 254 255 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts) 256 { 257 const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg; 258 unsigned int v_level = 0; 259 unsigned int p_level = 0; 260 u8 ldo_config; 261 u8 swing; 262 u8 emph; 263 int i; 264 265 if (!cfg) 266 return 0; 267 268 if (edp->is_edp) 269 cfg = &edp_phy_swing_pre_emph_cfg; 270 271 for (i = 0; i < dp_opts->lanes; i++) { 272 v_level = max(v_level, dp_opts->voltage[i]); 273 p_level = max(p_level, dp_opts->pre[i]); 274 } 275 276 if (dp_opts->link_rate <= 2700) { 277 swing = (*cfg->swing_hbr_rbr)[v_level][p_level]; 278 emph = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 279 } else { 280 swing = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 281 emph = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 282 } 283 284 if (swing == 0xff || emph == 0xff) 285 return -EINVAL; 286 287 ldo_config = edp->is_edp ? 0x0 : 0x1; 288 289 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); 290 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); 291 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); 292 293 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); 294 writel(swing, edp->tx1 + TXn_TX_DRV_LVL); 295 writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); 296 297 return 0; 298 } 299 300 static int qcom_edp_phy_configure(struct phy *phy, union phy_configure_opts *opts) 301 { 302 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 303 struct qcom_edp *edp = phy_get_drvdata(phy); 304 int ret = 0; 305 306 memcpy(&edp->dp_opts, dp_opts, sizeof(*dp_opts)); 307 308 if (dp_opts->set_voltages) 309 ret = qcom_edp_set_voltages(edp, dp_opts); 310 311 return ret; 312 } 313 314 static int qcom_edp_configure_ssc(const struct qcom_edp *edp) 315 { 316 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; 317 u32 step1; 318 u32 step2; 319 320 switch (dp_opts->link_rate) { 321 case 1620: 322 case 2700: 323 case 8100: 324 step1 = 0x45; 325 step2 = 0x06; 326 break; 327 328 case 5400: 329 step1 = 0x5c; 330 step2 = 0x08; 331 break; 332 333 default: 334 /* Other link rates aren't supported */ 335 return -EINVAL; 336 } 337 338 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); 339 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); 340 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); 341 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); 342 writel(step1, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0); 343 writel(step2, edp->pll + QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0); 344 345 return 0; 346 } 347 348 static int qcom_edp_configure_pll(const struct qcom_edp *edp) 349 { 350 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; 351 u32 div_frac_start2_mode0; 352 u32 div_frac_start3_mode0; 353 u32 dec_start_mode0; 354 u32 lock_cmp1_mode0; 355 u32 lock_cmp2_mode0; 356 u32 hsclk_sel; 357 358 switch (dp_opts->link_rate) { 359 case 1620: 360 hsclk_sel = 0x5; 361 dec_start_mode0 = 0x69; 362 div_frac_start2_mode0 = 0x80; 363 div_frac_start3_mode0 = 0x07; 364 lock_cmp1_mode0 = 0x6f; 365 lock_cmp2_mode0 = 0x08; 366 break; 367 368 case 2700: 369 hsclk_sel = 0x3; 370 dec_start_mode0 = 0x69; 371 div_frac_start2_mode0 = 0x80; 372 div_frac_start3_mode0 = 0x07; 373 lock_cmp1_mode0 = 0x0f; 374 lock_cmp2_mode0 = 0x0e; 375 break; 376 377 case 5400: 378 hsclk_sel = 0x1; 379 dec_start_mode0 = 0x8c; 380 div_frac_start2_mode0 = 0x00; 381 div_frac_start3_mode0 = 0x0a; 382 lock_cmp1_mode0 = 0x1f; 383 lock_cmp2_mode0 = 0x1c; 384 break; 385 386 case 8100: 387 hsclk_sel = 0x0; 388 dec_start_mode0 = 0x69; 389 div_frac_start2_mode0 = 0x80; 390 div_frac_start3_mode0 = 0x07; 391 lock_cmp1_mode0 = 0x2f; 392 lock_cmp2_mode0 = 0x2a; 393 break; 394 395 default: 396 /* Other link rates aren't supported */ 397 return -EINVAL; 398 } 399 400 writel(0x01, edp->pll + QSERDES_V4_COM_SVS_MODE_CLK_SEL); 401 writel(0x0b, edp->pll + QSERDES_V4_COM_SYSCLK_EN_SEL); 402 writel(0x02, edp->pll + QSERDES_V4_COM_SYS_CLK_CTRL); 403 writel(0x0c, edp->pll + QSERDES_V4_COM_CLK_ENABLE1); 404 writel(0x06, edp->pll + QSERDES_V4_COM_SYSCLK_BUF_ENABLE); 405 writel(0x30, edp->pll + QSERDES_V4_COM_CLK_SELECT); 406 writel(hsclk_sel, edp->pll + QSERDES_V4_COM_HSCLK_SEL); 407 writel(0x0f, edp->pll + QSERDES_V4_COM_PLL_IVCO); 408 writel(0x08, edp->pll + QSERDES_V4_COM_LOCK_CMP_EN); 409 writel(0x36, edp->pll + QSERDES_V4_COM_PLL_CCTRL_MODE0); 410 writel(0x16, edp->pll + QSERDES_V4_COM_PLL_RCTRL_MODE0); 411 writel(0x06, edp->pll + QSERDES_V4_COM_CP_CTRL_MODE0); 412 writel(dec_start_mode0, edp->pll + QSERDES_V4_COM_DEC_START_MODE0); 413 writel(0x00, edp->pll + QSERDES_V4_COM_DIV_FRAC_START1_MODE0); 414 writel(div_frac_start2_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START2_MODE0); 415 writel(div_frac_start3_mode0, edp->pll + QSERDES_V4_COM_DIV_FRAC_START3_MODE0); 416 writel(0x02, edp->pll + QSERDES_V4_COM_CMN_CONFIG); 417 writel(0x3f, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0); 418 writel(0x00, edp->pll + QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0); 419 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_MAP); 420 writel(lock_cmp1_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP1_MODE0); 421 writel(lock_cmp2_mode0, edp->pll + QSERDES_V4_COM_LOCK_CMP2_MODE0); 422 423 writel(0x0a, edp->pll + QSERDES_V4_COM_BG_TIMER); 424 writel(0x14, edp->pll + QSERDES_V4_COM_CORECLK_DIV_MODE0); 425 writel(0x00, edp->pll + QSERDES_V4_COM_VCO_TUNE_CTRL); 426 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 427 writel(0x0f, edp->pll + QSERDES_V4_COM_CORE_CLK_EN); 428 writel(0xa0, edp->pll + QSERDES_V4_COM_VCO_TUNE1_MODE0); 429 writel(0x03, edp->pll + QSERDES_V4_COM_VCO_TUNE2_MODE0); 430 431 return 0; 432 } 433 434 static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel_freq) 435 { 436 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; 437 u32 vco_div; 438 439 switch (dp_opts->link_rate) { 440 case 1620: 441 vco_div = 0x1; 442 *pixel_freq = 1620000000UL / 2; 443 break; 444 445 case 2700: 446 vco_div = 0x1; 447 *pixel_freq = 2700000000UL / 2; 448 break; 449 450 case 5400: 451 vco_div = 0x2; 452 *pixel_freq = 5400000000UL / 4; 453 break; 454 455 case 8100: 456 vco_div = 0x0; 457 *pixel_freq = 8100000000UL / 6; 458 break; 459 460 default: 461 /* Other link rates aren't supported */ 462 return -EINVAL; 463 } 464 465 writel(vco_div, edp->edp + DP_PHY_VCO_DIV); 466 467 return 0; 468 } 469 470 static int qcom_edp_phy_power_on(struct phy *phy) 471 { 472 const struct qcom_edp *edp = phy_get_drvdata(phy); 473 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 474 unsigned long pixel_freq; 475 u8 ldo_config = 0x0; 476 int timeout; 477 int ret; 478 u32 val; 479 u8 cfg1; 480 481 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 482 DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | 483 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 484 edp->edp + DP_PHY_PD_CTL); 485 writel(0xfc, edp->edp + DP_PHY_MODE); 486 487 timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, 488 val, val & BIT(7), 5, 200); 489 if (timeout) 490 return timeout; 491 492 493 if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) 494 ldo_config = 0x1; 495 496 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); 497 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); 498 writel(0x00, edp->tx0 + TXn_LANE_MODE_1); 499 writel(0x00, edp->tx1 + TXn_LANE_MODE_1); 500 501 if (edp->dp_opts.ssc) { 502 ret = qcom_edp_configure_ssc(edp); 503 if (ret) 504 return ret; 505 } 506 507 ret = qcom_edp_configure_pll(edp); 508 if (ret) 509 return ret; 510 511 /* TX Lane configuration */ 512 writel(0x05, edp->edp + DP_PHY_TX0_TX1_LANE_CTL); 513 writel(0x05, edp->edp + DP_PHY_TX2_TX3_LANE_CTL); 514 515 /* TX-0 register configuration */ 516 writel(0x03, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); 517 writel(0x0f, edp->tx0 + TXn_CLKBUF_ENABLE); 518 writel(0x03, edp->tx0 + TXn_RESET_TSYNC_EN); 519 writel(0x01, edp->tx0 + TXn_TRAN_DRVR_EMP_EN); 520 writel(0x04, edp->tx0 + TXn_TX_BAND); 521 522 /* TX-1 register configuration */ 523 writel(0x03, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); 524 writel(0x0f, edp->tx1 + TXn_CLKBUF_ENABLE); 525 writel(0x03, edp->tx1 + TXn_RESET_TSYNC_EN); 526 writel(0x01, edp->tx1 + TXn_TRAN_DRVR_EMP_EN); 527 writel(0x04, edp->tx1 + TXn_TX_BAND); 528 529 ret = qcom_edp_set_vco_div(edp, &pixel_freq); 530 if (ret) 531 return ret; 532 533 writel(0x01, edp->edp + DP_PHY_CFG); 534 writel(0x05, edp->edp + DP_PHY_CFG); 535 writel(0x01, edp->edp + DP_PHY_CFG); 536 writel(0x09, edp->edp + DP_PHY_CFG); 537 538 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); 539 540 timeout = readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, 541 val, val & BIT(0), 500, 10000); 542 if (timeout) 543 return timeout; 544 545 writel(0x19, edp->edp + DP_PHY_CFG); 546 writel(0x1f, edp->tx0 + TXn_HIGHZ_DRVR_EN); 547 writel(0x04, edp->tx0 + TXn_HIGHZ_DRVR_EN); 548 writel(0x00, edp->tx0 + TXn_TX_POL_INV); 549 writel(0x1f, edp->tx1 + TXn_HIGHZ_DRVR_EN); 550 writel(0x04, edp->tx1 + TXn_HIGHZ_DRVR_EN); 551 writel(0x00, edp->tx1 + TXn_TX_POL_INV); 552 writel(0x10, edp->tx0 + TXn_TX_DRV_LVL_OFFSET); 553 writel(0x10, edp->tx1 + TXn_TX_DRV_LVL_OFFSET); 554 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX0); 555 writel(0x11, edp->tx0 + TXn_RES_CODE_LANE_OFFSET_TX1); 556 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX0); 557 writel(0x11, edp->tx1 + TXn_RES_CODE_LANE_OFFSET_TX1); 558 559 writel(0x10, edp->tx0 + TXn_TX_EMP_POST1_LVL); 560 writel(0x10, edp->tx1 + TXn_TX_EMP_POST1_LVL); 561 writel(0x1f, edp->tx0 + TXn_TX_DRV_LVL); 562 writel(0x1f, edp->tx1 + TXn_TX_DRV_LVL); 563 564 if (edp->dp_opts.lanes == 1) { 565 bias0_en = 0x01; 566 bias1_en = 0x00; 567 drvr0_en = 0x06; 568 drvr1_en = 0x07; 569 cfg1 = 0x1; 570 } else if (edp->dp_opts.lanes == 2) { 571 bias0_en = 0x03; 572 bias1_en = 0x00; 573 drvr0_en = 0x04; 574 drvr1_en = 0x07; 575 cfg1 = 0x3; 576 } else { 577 bias0_en = 0x03; 578 bias1_en = 0x03; 579 drvr0_en = 0x04; 580 drvr1_en = 0x04; 581 cfg1 = 0xf; 582 } 583 584 writel(drvr0_en, edp->tx0 + TXn_HIGHZ_DRVR_EN); 585 writel(bias0_en, edp->tx0 + TXn_TRANSCEIVER_BIAS_EN); 586 writel(drvr1_en, edp->tx1 + TXn_HIGHZ_DRVR_EN); 587 writel(bias1_en, edp->tx1 + TXn_TRANSCEIVER_BIAS_EN); 588 writel(cfg1, edp->edp + DP_PHY_CFG_1); 589 590 writel(0x18, edp->edp + DP_PHY_CFG); 591 usleep_range(100, 1000); 592 593 writel(0x19, edp->edp + DP_PHY_CFG); 594 595 ret = readl_poll_timeout(edp->edp + DP_PHY_STATUS, 596 val, val & BIT(1), 500, 10000); 597 if (ret) 598 return ret; 599 600 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); 601 clk_set_rate(edp->dp_pixel_hw.clk, pixel_freq); 602 603 return 0; 604 } 605 606 static int qcom_edp_phy_power_off(struct phy *phy) 607 { 608 const struct qcom_edp *edp = phy_get_drvdata(phy); 609 610 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); 611 612 return 0; 613 } 614 615 static int qcom_edp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) 616 { 617 struct qcom_edp *edp = phy_get_drvdata(phy); 618 619 if (mode != PHY_MODE_DP) 620 return -EINVAL; 621 622 edp->is_edp = submode == PHY_SUBMODE_EDP; 623 624 return 0; 625 } 626 627 static int qcom_edp_phy_exit(struct phy *phy) 628 { 629 struct qcom_edp *edp = phy_get_drvdata(phy); 630 631 clk_bulk_disable_unprepare(ARRAY_SIZE(edp->clks), edp->clks); 632 regulator_bulk_disable(ARRAY_SIZE(edp->supplies), edp->supplies); 633 634 return 0; 635 } 636 637 static const struct phy_ops qcom_edp_ops = { 638 .init = qcom_edp_phy_init, 639 .configure = qcom_edp_phy_configure, 640 .power_on = qcom_edp_phy_power_on, 641 .power_off = qcom_edp_phy_power_off, 642 .set_mode = qcom_edp_phy_set_mode, 643 .exit = qcom_edp_phy_exit, 644 .owner = THIS_MODULE, 645 }; 646 647 /* 648 * Embedded Display Port PLL driver block diagram for branch clocks 649 * 650 * +------------------------------+ 651 * | EDP_VCO_CLK | 652 * | | 653 * | +-------------------+ | 654 * | | (EDP PLL/VCO) | | 655 * | +---------+---------+ | 656 * | v | 657 * | +----------+-----------+ | 658 * | | hsclk_divsel_clk_src | | 659 * | +----------+-----------+ | 660 * +------------------------------+ 661 * | 662 * +---------<---------v------------>----------+ 663 * | | 664 * +--------v----------------+ | 665 * | edp_phy_pll_link_clk | | 666 * | link_clk | | 667 * +--------+----------------+ | 668 * | | 669 * | | 670 * v v 671 * Input to DISPCC block | 672 * for link clk, crypto clk | 673 * and interface clock | 674 * | 675 * | 676 * +--------<------------+-----------------+---<---+ 677 * | | | 678 * +----v---------+ +--------v-----+ +--------v------+ 679 * | vco_divided | | vco_divided | | vco_divided | 680 * | _clk_src | | _clk_src | | _clk_src | 681 * | | | | | | 682 * |divsel_six | | divsel_two | | divsel_four | 683 * +-------+------+ +-----+--------+ +--------+------+ 684 * | | | 685 * v---->----------v-------------<------v 686 * | 687 * +----------+-----------------+ 688 * | edp_phy_pll_vco_div_clk | 689 * +---------+------------------+ 690 * | 691 * v 692 * Input to DISPCC block 693 * for EDP pixel clock 694 * 695 */ 696 static int qcom_edp_dp_pixel_clk_determine_rate(struct clk_hw *hw, 697 struct clk_rate_request *req) 698 { 699 switch (req->rate) { 700 case 1620000000UL / 2: 701 case 2700000000UL / 2: 702 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 703 return 0; 704 705 default: 706 return -EINVAL; 707 } 708 } 709 710 static unsigned long 711 qcom_edp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 712 { 713 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_pixel_hw); 714 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; 715 716 switch (dp_opts->link_rate) { 717 case 1620: 718 return 1620000000UL / 2; 719 case 2700: 720 return 2700000000UL / 2; 721 case 5400: 722 return 5400000000UL / 4; 723 case 8100: 724 return 8100000000UL / 6; 725 default: 726 return 0; 727 } 728 } 729 730 static const struct clk_ops qcom_edp_dp_pixel_clk_ops = { 731 .determine_rate = qcom_edp_dp_pixel_clk_determine_rate, 732 .recalc_rate = qcom_edp_dp_pixel_clk_recalc_rate, 733 }; 734 735 static int qcom_edp_dp_link_clk_determine_rate(struct clk_hw *hw, 736 struct clk_rate_request *req) 737 { 738 switch (req->rate) { 739 case 162000000: 740 case 270000000: 741 case 540000000: 742 case 810000000: 743 return 0; 744 745 default: 746 return -EINVAL; 747 } 748 } 749 750 static unsigned long 751 qcom_edp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 752 { 753 const struct qcom_edp *edp = container_of(hw, struct qcom_edp, dp_link_hw); 754 const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts; 755 756 switch (dp_opts->link_rate) { 757 case 1620: 758 case 2700: 759 case 5400: 760 case 8100: 761 return dp_opts->link_rate * 100000; 762 763 default: 764 return 0; 765 } 766 } 767 768 static const struct clk_ops qcom_edp_dp_link_clk_ops = { 769 .determine_rate = qcom_edp_dp_link_clk_determine_rate, 770 .recalc_rate = qcom_edp_dp_link_clk_recalc_rate, 771 }; 772 773 static int qcom_edp_clks_register(struct qcom_edp *edp, struct device_node *np) 774 { 775 struct clk_hw_onecell_data *data; 776 struct clk_init_data init = { }; 777 char name[64]; 778 int ret; 779 780 data = devm_kzalloc(edp->dev, struct_size(data, hws, 2), GFP_KERNEL); 781 if (!data) 782 return -ENOMEM; 783 data->num = 2; 784 785 snprintf(name, sizeof(name), "%s::link_clk", dev_name(edp->dev)); 786 init.ops = &qcom_edp_dp_link_clk_ops; 787 init.name = name; 788 edp->dp_link_hw.init = &init; 789 ret = devm_clk_hw_register(edp->dev, &edp->dp_link_hw); 790 if (ret) 791 return ret; 792 793 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(edp->dev)); 794 init.ops = &qcom_edp_dp_pixel_clk_ops; 795 init.name = name; 796 edp->dp_pixel_hw.init = &init; 797 ret = devm_clk_hw_register(edp->dev, &edp->dp_pixel_hw); 798 if (ret) 799 return ret; 800 801 data->hws[0] = &edp->dp_link_hw; 802 data->hws[1] = &edp->dp_pixel_hw; 803 804 return devm_of_clk_add_hw_provider(edp->dev, of_clk_hw_onecell_get, data); 805 } 806 807 static int qcom_edp_phy_probe(struct platform_device *pdev) 808 { 809 struct phy_provider *phy_provider; 810 struct device *dev = &pdev->dev; 811 struct qcom_edp *edp; 812 int ret; 813 814 edp = devm_kzalloc(dev, sizeof(*edp), GFP_KERNEL); 815 if (!edp) 816 return -ENOMEM; 817 818 edp->dev = dev; 819 edp->cfg = of_device_get_match_data(&pdev->dev); 820 edp->is_edp = edp->cfg->is_edp; 821 822 edp->edp = devm_platform_ioremap_resource(pdev, 0); 823 if (IS_ERR(edp->edp)) 824 return PTR_ERR(edp->edp); 825 826 edp->tx0 = devm_platform_ioremap_resource(pdev, 1); 827 if (IS_ERR(edp->tx0)) 828 return PTR_ERR(edp->tx0); 829 830 edp->tx1 = devm_platform_ioremap_resource(pdev, 2); 831 if (IS_ERR(edp->tx1)) 832 return PTR_ERR(edp->tx1); 833 834 edp->pll = devm_platform_ioremap_resource(pdev, 3); 835 if (IS_ERR(edp->pll)) 836 return PTR_ERR(edp->pll); 837 838 edp->clks[0].id = "aux"; 839 edp->clks[1].id = "cfg_ahb"; 840 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(edp->clks), edp->clks); 841 if (ret) 842 return ret; 843 844 edp->supplies[0].supply = "vdda-phy"; 845 edp->supplies[1].supply = "vdda-pll"; 846 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(edp->supplies), edp->supplies); 847 if (ret) 848 return ret; 849 850 ret = regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ 851 if (ret) { 852 dev_err(dev, "failed to set load at %s\n", edp->supplies[0].supply); 853 return ret; 854 } 855 856 ret = regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ 857 if (ret) { 858 dev_err(dev, "failed to set load at %s\n", edp->supplies[1].supply); 859 return ret; 860 } 861 862 ret = qcom_edp_clks_register(edp, pdev->dev.of_node); 863 if (ret) 864 return ret; 865 866 edp->phy = devm_phy_create(dev, pdev->dev.of_node, &qcom_edp_ops); 867 if (IS_ERR(edp->phy)) { 868 dev_err(dev, "failed to register phy\n"); 869 return PTR_ERR(edp->phy); 870 } 871 872 phy_set_drvdata(edp->phy, edp); 873 874 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 875 return PTR_ERR_OR_ZERO(phy_provider); 876 } 877 878 static const struct of_device_id qcom_edp_phy_match_table[] = { 879 { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, }, 880 { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, }, 881 { .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, }, 882 { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, }, 883 { } 884 }; 885 MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table); 886 887 static struct platform_driver qcom_edp_phy_driver = { 888 .probe = qcom_edp_phy_probe, 889 .driver = { 890 .name = "qcom-edp-phy", 891 .of_match_table = qcom_edp_phy_match_table, 892 }, 893 }; 894 895 module_platform_driver(qcom_edp_phy_driver); 896 897 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@linaro.org>"); 898 MODULE_DESCRIPTION("Qualcomm eDP QMP PHY driver"); 899 MODULE_LICENSE("GPL v2"); 900