1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/auxiliary_bus.h> 4 #include <linux/bitfield.h> 5 #include <linux/bits.h> 6 #include <linux/delay.h> 7 #include <linux/device.h> 8 #include <linux/err.h> 9 #include <linux/errno.h> 10 #include <linux/gfp_types.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/mod_devicetable.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/phy.h> 18 #include <linux/phy/phy.h> 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 22 #define EQ5_PHY_COUNT 2 23 24 #define EQ5_PHY0_GP 0x128 25 #define EQ5_PHY1_GP 0x12c 26 #define EQ5_PHY0_SGMII 0x134 27 #define EQ5_PHY1_SGMII 0x138 28 29 #define EQ5_GP_TX_SWRST_DIS BIT(0) // Tx SW reset 30 #define EQ5_GP_TX_M_CLKE BIT(1) // Tx M clock enable 31 #define EQ5_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset 32 #define EQ5_GP_SYS_M_CLKE BIT(3) // Sys clock enable 33 #define EQ5_GP_SGMII_MODE BIT(4) // SGMII mode 34 #define EQ5_GP_RGMII_DRV GENMASK(8, 5) // RGMII drive strength 35 36 #define EQ5_SGMII_PWR_EN BIT(0) 37 #define EQ5_SGMII_RST_DIS BIT(1) 38 #define EQ5_SGMII_PLL_EN BIT(2) 39 #define EQ5_SGMII_SIG_DET_SW BIT(3) 40 #define EQ5_SGMII_PWR_STATE BIT(4) 41 #define EQ5_SGMII_PLL_ACK BIT(18) 42 #define EQ5_SGMII_PWR_STATE_ACK GENMASK(24, 20) 43 44 /* 45 * Instead of storing a phy_interface_t, we store this enum. 46 * 47 * We do not deal with RGMII timings in this generic PHY driver, 48 * it is all handled inside the net PHY. 49 */ 50 enum eq5_phy_submode { 51 EQ5_PHY_SUBMODE_SGMII, 52 EQ5_PHY_SUBMODE_RGMII, 53 }; 54 55 struct eq5_phy_inst { 56 struct device *dev; 57 struct phy *phy; 58 void __iomem *gp, *sgmii; 59 enum eq5_phy_submode submode; 60 bool sgmii_support; 61 }; 62 63 struct eq5_phy_private { 64 struct eq5_phy_inst phys[EQ5_PHY_COUNT]; 65 }; 66 67 static int eq5_phy_exit(struct phy *phy) 68 { 69 struct eq5_phy_inst *inst = phy_get_drvdata(phy); 70 71 writel(0, inst->gp); 72 writel(0, inst->sgmii); 73 udelay(5); /* settling time */ 74 return 0; 75 } 76 77 static int eq5_phy_init(struct phy *phy) 78 { 79 struct eq5_phy_inst *inst = phy_get_drvdata(phy); 80 u32 reg; 81 82 /* 83 * Hardware stops listening to our instructions once it is started. 84 * It must be reset to reconfigure it. 85 */ 86 eq5_phy_exit(phy); 87 88 reg = EQ5_GP_TX_SWRST_DIS | EQ5_GP_TX_M_CLKE | 89 EQ5_GP_SYS_SWRST_DIS | EQ5_GP_SYS_M_CLKE | 90 FIELD_PREP(EQ5_GP_RGMII_DRV, 0x9); 91 writel(reg, inst->gp); 92 93 return 0; 94 } 95 96 static int eq5_phy_power_on(struct phy *phy) 97 { 98 struct eq5_phy_inst *inst = phy_get_drvdata(phy); 99 u32 reg; 100 101 if (inst->submode == EQ5_PHY_SUBMODE_SGMII) { 102 writel(readl(inst->gp) | EQ5_GP_SGMII_MODE, inst->gp); 103 104 reg = EQ5_SGMII_PWR_EN | EQ5_SGMII_RST_DIS | EQ5_SGMII_PLL_EN; 105 writel(reg, inst->sgmii); 106 107 if (readl_poll_timeout(inst->sgmii, reg, 108 reg & EQ5_SGMII_PLL_ACK, 1, 100)) { 109 dev_err(inst->dev, "PLL timeout\n"); 110 return -ETIMEDOUT; 111 } 112 113 reg = readl(inst->sgmii); 114 reg |= EQ5_SGMII_PWR_STATE | EQ5_SGMII_SIG_DET_SW; 115 writel(reg, inst->sgmii); 116 } else { 117 writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp); 118 writel(0, inst->sgmii); 119 } 120 121 return 0; 122 } 123 124 static int eq5_phy_power_off(struct phy *phy) 125 { 126 struct eq5_phy_inst *inst = phy_get_drvdata(phy); 127 128 writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp); 129 writel(0, inst->sgmii); 130 131 return 0; 132 } 133 134 static int eq5_phy_validate(struct phy *phy, enum phy_mode mode, int submode, 135 union phy_configure_opts *opts) 136 { 137 struct eq5_phy_inst *inst = phy_get_drvdata(phy); 138 139 if (mode != PHY_MODE_ETHERNET) 140 return -EINVAL; 141 142 if (phy_interface_mode_is_rgmii(submode)) 143 return 0; 144 145 if (inst->sgmii_support && submode == PHY_INTERFACE_MODE_SGMII) 146 return 0; 147 148 return -EINVAL; 149 } 150 151 static int eq5_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) 152 { 153 struct eq5_phy_inst *inst = phy_get_drvdata(phy); 154 enum eq5_phy_submode target_submode; 155 int ret; 156 157 ret = eq5_phy_validate(phy, mode, submode, NULL); 158 if (ret) 159 return ret; 160 161 if (submode == PHY_INTERFACE_MODE_SGMII) 162 target_submode = EQ5_PHY_SUBMODE_SGMII; 163 else 164 target_submode = EQ5_PHY_SUBMODE_RGMII; 165 166 if (target_submode == inst->submode) 167 return 0; 168 169 inst->submode = target_submode; 170 171 if (phy->power_count) { 172 eq5_phy_init(phy); 173 return eq5_phy_power_on(phy); 174 } 175 176 return 0; 177 } 178 179 static const struct phy_ops eq5_phy_ops = { 180 .init = eq5_phy_init, 181 .exit = eq5_phy_exit, 182 .power_on = eq5_phy_power_on, 183 .power_off = eq5_phy_power_off, 184 .set_mode = eq5_phy_set_mode, 185 .validate = eq5_phy_validate, 186 }; 187 188 static struct phy *eq5_phy_xlate(struct device *dev, 189 const struct of_phandle_args *args) 190 { 191 struct eq5_phy_private *priv = dev_get_drvdata(dev); 192 193 if (args->args_count != 1 || args->args[0] >= EQ5_PHY_COUNT) 194 return ERR_PTR(-EINVAL); 195 196 return priv->phys[args->args[0]].phy; 197 } 198 199 static int eq5_phy_probe_phy(struct device *dev, struct eq5_phy_private *priv, 200 unsigned int index, void __iomem *base, 201 unsigned int gp, unsigned int sgmii, 202 bool sgmii_support) 203 { 204 struct eq5_phy_inst *inst = &priv->phys[index]; 205 struct phy *phy; 206 207 phy = devm_phy_create(dev, dev->of_node, &eq5_phy_ops); 208 if (IS_ERR(phy)) 209 return dev_err_probe(dev, PTR_ERR(phy), 210 "failed to create PHY %u\n", index); 211 212 inst->dev = dev; 213 inst->phy = phy; 214 inst->gp = base + gp; 215 inst->sgmii = base + sgmii; 216 inst->sgmii_support = sgmii_support; 217 phy_set_drvdata(phy, inst); 218 219 /* 220 * Init inst->submode based on probe hardware state, allowing 221 * consumers to power us on without first setting the mode. 222 */ 223 if (sgmii_support && (readl(inst->gp) & EQ5_GP_SGMII_MODE)) 224 inst->submode = EQ5_PHY_SUBMODE_SGMII; 225 else 226 inst->submode = EQ5_PHY_SUBMODE_RGMII; 227 228 return 0; 229 } 230 231 static int eq5_phy_probe(struct auxiliary_device *adev, 232 const struct auxiliary_device_id *id) 233 { 234 struct device *dev = &adev->dev; 235 struct phy_provider *provider; 236 struct eq5_phy_private *priv; 237 void __iomem *base; 238 int ret; 239 240 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 241 if (!priv) 242 return -ENOMEM; 243 244 dev_set_drvdata(dev, priv); 245 246 base = (void __iomem *)dev_get_platdata(dev); 247 248 ret = eq5_phy_probe_phy(dev, priv, 0, base, EQ5_PHY0_GP, 249 EQ5_PHY0_SGMII, true); 250 if (ret) 251 return ret; 252 253 ret = eq5_phy_probe_phy(dev, priv, 1, base, EQ5_PHY1_GP, 254 EQ5_PHY1_SGMII, false); 255 if (ret) 256 return ret; 257 258 provider = devm_of_phy_provider_register(dev, eq5_phy_xlate); 259 if (IS_ERR(provider)) 260 return dev_err_probe(dev, PTR_ERR(provider), 261 "registering provider failed\n"); 262 263 return 0; 264 } 265 266 static const struct auxiliary_device_id eq5_phy_id_table[] = { 267 { .name = "clk_eyeq.phy" }, 268 {} 269 }; 270 MODULE_DEVICE_TABLE(auxiliary, eq5_phy_id_table); 271 272 static struct auxiliary_driver eq5_phy_driver = { 273 .probe = eq5_phy_probe, 274 .id_table = eq5_phy_id_table, 275 }; 276 module_auxiliary_driver(eq5_phy_driver); 277 278 MODULE_DESCRIPTION("EyeQ5 Ethernet PHY driver"); 279 MODULE_AUTHOR("Théo Lebrun <theo.lebrun@bootlin.com>"); 280 MODULE_LICENSE("GPL"); 281