1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Microchip Sparx5 Switch SerDes driver 3 * 4 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 * and the datasheet is available here: 9 * https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf 10 */ 11 #include <linux/printk.h> 12 #include <linux/module.h> 13 #include <linux/device.h> 14 #include <linux/netdevice.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/phy.h> 20 #include <linux/phy/phy.h> 21 22 #include "sparx5_serdes.h" 23 24 #define SPX5_SERDES_10G_START 13 25 #define SPX5_SERDES_25G_START 25 26 #define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START 27 28 #define LAN969X_SERDES_10G_CNT 10 29 30 /* Optimal power settings from GUC */ 31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c 32 33 /* Register target sizes */ 34 const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = { 35 [TC_SD10G_LANE] = 12, 36 [TC_SD_CMU] = 14, 37 [TC_SD_CMU_CFG] = 14, 38 [TC_SD_LANE] = 25, 39 }; 40 41 const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = { 42 [TC_SD10G_LANE] = 10, 43 [TC_SD_CMU] = 6, 44 [TC_SD_CMU_CFG] = 6, 45 [TC_SD_LANE] = 10, 46 }; 47 48 /* Pointer to the register target size table */ 49 const unsigned int *tsize; 50 51 enum sparx5_sd25g28_mode_preset_type { 52 SPX5_SD25G28_MODE_PRESET_25000, 53 SPX5_SD25G28_MODE_PRESET_10000, 54 SPX5_SD25G28_MODE_PRESET_5000, 55 SPX5_SD25G28_MODE_PRESET_SD_2G5, 56 SPX5_SD25G28_MODE_PRESET_1000BASEX, 57 }; 58 59 enum sparx5_sd10g28_mode_preset_type { 60 SPX5_SD10G28_MODE_PRESET_10000, 61 SPX5_SD10G28_MODE_PRESET_SFI_5000_6G, 62 SPX5_SD10G28_MODE_PRESET_SFI_5000_10G, 63 SPX5_SD10G28_MODE_PRESET_QSGMII, 64 SPX5_SD10G28_MODE_PRESET_SD_2G5, 65 SPX5_SD10G28_MODE_PRESET_1000BASEX, 66 }; 67 68 struct sparx5_serdes_io_resource { 69 enum sparx5_serdes_target id; 70 phys_addr_t offset; 71 }; 72 73 struct sparx5_sd25g28_mode_preset { 74 u8 bitwidth; 75 u8 tx_pre_div; 76 u8 fifo_ck_div; 77 u8 pre_divsel; 78 u8 vco_div_mode; 79 u8 sel_div; 80 u8 ck_bitwidth; 81 u8 subrate; 82 u8 com_txcal_en; 83 u8 com_tx_reserve_msb; 84 u8 com_tx_reserve_lsb; 85 u8 cfg_itx_ipcml_base; 86 u8 tx_reserve_lsb; 87 u8 tx_reserve_msb; 88 u8 bw; 89 u8 rxterm; 90 u8 dfe_tap; 91 u8 dfe_enable; 92 bool txmargin; 93 u8 cfg_ctle_rstn; 94 u8 r_dfe_rstn; 95 u8 cfg_pi_bw_3_0; 96 u8 tx_tap_dly; 97 u8 tx_tap_adv; 98 }; 99 100 struct sparx5_sd25g28_media_preset { 101 u8 cfg_eq_c_force_3_0; 102 u8 cfg_vga_ctrl_byp_4_0; 103 u8 cfg_eq_r_force_3_0; 104 u8 cfg_en_adv; 105 u8 cfg_en_main; 106 u8 cfg_en_dly; 107 u8 cfg_tap_adv_3_0; 108 u8 cfg_tap_main; 109 u8 cfg_tap_dly_4_0; 110 u8 cfg_alos_thr_2_0; 111 }; 112 113 struct sparx5_sd25g28_args { 114 u8 if_width; /* UDL if-width: 10/16/20/32/64 */ 115 bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */ 116 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */ 117 bool no_pwrcycle:1; /* Omit initial power-cycle */ 118 bool txinvert:1; /* Enable inversion of output data */ 119 bool rxinvert:1; /* Enable inversion of input data */ 120 u16 txswing; /* Set output level */ 121 u8 rate; /* Rate of network interface */ 122 u8 pi_bw_gen1; 123 u8 duty_cycle; /* Set output level to half/full */ 124 bool mute:1; /* Mute Output Buffer */ 125 bool reg_rst:1; 126 u8 com_pll_reserve; 127 }; 128 129 struct sparx5_sd25g28_params { 130 u8 reg_rst; 131 u8 cfg_jc_byp; 132 u8 cfg_common_reserve_7_0; 133 u8 r_reg_manual; 134 u8 r_d_width_ctrl_from_hwt; 135 u8 r_d_width_ctrl_2_0; 136 u8 r_txfifo_ck_div_pmad_2_0; 137 u8 r_rxfifo_ck_div_pmad_2_0; 138 u8 cfg_pll_lol_set; 139 u8 cfg_vco_div_mode_1_0; 140 u8 cfg_pre_divsel_1_0; 141 u8 cfg_sel_div_3_0; 142 u8 cfg_vco_start_code_3_0; 143 u8 cfg_pma_tx_ck_bitwidth_2_0; 144 u8 cfg_tx_prediv_1_0; 145 u8 cfg_rxdiv_sel_2_0; 146 u8 cfg_tx_subrate_2_0; 147 u8 cfg_rx_subrate_2_0; 148 u8 r_multi_lane_mode; 149 u8 cfg_cdrck_en; 150 u8 cfg_dfeck_en; 151 u8 cfg_dfe_pd; 152 u8 cfg_dfedmx_pd; 153 u8 cfg_dfetap_en_5_1; 154 u8 cfg_dmux_pd; 155 u8 cfg_dmux_clk_pd; 156 u8 cfg_erramp_pd; 157 u8 cfg_pi_dfe_en; 158 u8 cfg_pi_en; 159 u8 cfg_pd_ctle; 160 u8 cfg_summer_en; 161 u8 cfg_pmad_ck_pd; 162 u8 cfg_pd_clk; 163 u8 cfg_pd_cml; 164 u8 cfg_pd_driver; 165 u8 cfg_rx_reg_pu; 166 u8 cfg_pd_rms_det; 167 u8 cfg_dcdr_pd; 168 u8 cfg_ecdr_pd; 169 u8 cfg_pd_sq; 170 u8 cfg_itx_ipdriver_base_2_0; 171 u8 cfg_tap_dly_4_0; 172 u8 cfg_tap_main; 173 u8 cfg_en_main; 174 u8 cfg_tap_adv_3_0; 175 u8 cfg_en_adv; 176 u8 cfg_en_dly; 177 u8 cfg_iscan_en; 178 u8 l1_pcs_en_fast_iscan; 179 u8 l0_cfg_bw_1_0; 180 u8 l0_cfg_txcal_en; 181 u8 cfg_en_dummy; 182 u8 cfg_pll_reserve_3_0; 183 u8 l0_cfg_tx_reserve_15_8; 184 u8 l0_cfg_tx_reserve_7_0; 185 u8 cfg_tx_reserve_15_8; 186 u8 cfg_tx_reserve_7_0; 187 u8 cfg_bw_1_0; 188 u8 cfg_txcal_man_en; 189 u8 cfg_phase_man_4_0; 190 u8 cfg_quad_man_1_0; 191 u8 cfg_txcal_shift_code_5_0; 192 u8 cfg_txcal_valid_sel_3_0; 193 u8 cfg_txcal_en; 194 u8 cfg_cdr_kf_2_0; 195 u8 cfg_cdr_m_7_0; 196 u8 cfg_pi_bw_3_0; 197 u8 cfg_pi_steps_1_0; 198 u8 cfg_dis_2ndorder; 199 u8 cfg_ctle_rstn; 200 u8 r_dfe_rstn; 201 u8 cfg_alos_thr_2_0; 202 u8 cfg_itx_ipcml_base_1_0; 203 u8 cfg_rx_reserve_7_0; 204 u8 cfg_rx_reserve_15_8; 205 u8 cfg_rxterm_2_0; 206 u8 cfg_fom_selm; 207 u8 cfg_rx_sp_ctle_1_0; 208 u8 cfg_isel_ctle_1_0; 209 u8 cfg_vga_ctrl_byp_4_0; 210 u8 cfg_vga_byp; 211 u8 cfg_agc_adpt_byp; 212 u8 cfg_eqr_byp; 213 u8 cfg_eqr_force_3_0; 214 u8 cfg_eqc_force_3_0; 215 u8 cfg_sum_setcm_en; 216 u8 cfg_init_pos_iscan_6_0; 217 u8 cfg_init_pos_ipi_6_0; 218 u8 cfg_dfedig_m_2_0; 219 u8 cfg_en_dfedig; 220 u8 cfg_pi_DFE_en; 221 u8 cfg_tx2rx_lp_en; 222 u8 cfg_txlb_en; 223 u8 cfg_rx2tx_lp_en; 224 u8 cfg_rxlb_en; 225 u8 r_tx_pol_inv; 226 u8 r_rx_pol_inv; 227 }; 228 229 struct sparx5_sd10g28_media_preset { 230 u8 cfg_en_adv; 231 u8 cfg_en_main; 232 u8 cfg_en_dly; 233 u8 cfg_tap_adv_3_0; 234 u8 cfg_tap_main; 235 u8 cfg_tap_dly_4_0; 236 u8 cfg_vga_ctrl_3_0; 237 u8 cfg_vga_cp_2_0; 238 u8 cfg_eq_res_3_0; 239 u8 cfg_eq_r_byp; 240 u8 cfg_eq_c_force_3_0; 241 u8 cfg_alos_thr_3_0; 242 }; 243 244 struct sparx5_sd10g28_mode_preset { 245 u8 bwidth; /* interface width: 10/16/20/32/64 */ 246 enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */ 247 u8 rate; /* Rate of network interface */ 248 u8 dfe_tap; 249 u8 dfe_enable; 250 u8 pi_bw_gen1; 251 u8 duty_cycle; /* Set output level to half/full */ 252 }; 253 254 struct sparx5_sd10g28_args { 255 bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */ 256 bool no_pwrcycle:1; /* Omit initial power-cycle */ 257 bool txinvert:1; /* Enable inversion of output data */ 258 bool rxinvert:1; /* Enable inversion of input data */ 259 bool txmargin:1; /* Set output level to half/full */ 260 u16 txswing; /* Set output level */ 261 bool mute:1; /* Mute Output Buffer */ 262 bool is_6g:1; 263 bool reg_rst:1; 264 }; 265 266 struct sparx5_sd10g28_params { 267 u8 cmu_sel; 268 u8 is_6g; 269 u8 skip_cmu_cfg; 270 u8 cfg_lane_reserve_7_0; 271 u8 cfg_ssc_rtl_clk_sel; 272 u8 cfg_lane_reserve_15_8; 273 u8 cfg_txrate_1_0; 274 u8 cfg_rxrate_1_0; 275 u8 r_d_width_ctrl_2_0; 276 u8 cfg_pma_tx_ck_bitwidth_2_0; 277 u8 cfg_rxdiv_sel_2_0; 278 u8 r_pcs2pma_phymode_4_0; 279 u8 cfg_lane_id_2_0; 280 u8 cfg_cdrck_en; 281 u8 cfg_dfeck_en; 282 u8 cfg_dfe_pd; 283 u8 cfg_dfetap_en_5_1; 284 u8 cfg_erramp_pd; 285 u8 cfg_pi_DFE_en; 286 u8 cfg_pi_en; 287 u8 cfg_pd_ctle; 288 u8 cfg_summer_en; 289 u8 cfg_pd_rx_cktree; 290 u8 cfg_pd_clk; 291 u8 cfg_pd_cml; 292 u8 cfg_pd_driver; 293 u8 cfg_rx_reg_pu; 294 u8 cfg_d_cdr_pd; 295 u8 cfg_pd_sq; 296 u8 cfg_rxdet_en; 297 u8 cfg_rxdet_str; 298 u8 r_multi_lane_mode; 299 u8 cfg_en_adv; 300 u8 cfg_en_main; 301 u8 cfg_en_dly; 302 u8 cfg_tap_adv_3_0; 303 u8 cfg_tap_main; 304 u8 cfg_tap_dly_4_0; 305 u8 cfg_vga_ctrl_3_0; 306 u8 cfg_vga_cp_2_0; 307 u8 cfg_eq_res_3_0; 308 u8 cfg_eq_r_byp; 309 u8 cfg_eq_c_force_3_0; 310 u8 cfg_en_dfedig; 311 u8 cfg_sum_setcm_en; 312 u8 cfg_en_preemph; 313 u8 cfg_itx_ippreemp_base_1_0; 314 u8 cfg_itx_ipdriver_base_2_0; 315 u8 cfg_ibias_tune_reserve_5_0; 316 u8 cfg_txswing_half; 317 u8 cfg_dis_2nd_order; 318 u8 cfg_rx_ssc_lh; 319 u8 cfg_pi_floop_steps_1_0; 320 u8 cfg_pi_ext_dac_23_16; 321 u8 cfg_pi_ext_dac_15_8; 322 u8 cfg_iscan_ext_dac_7_0; 323 u8 cfg_cdr_kf_gen1_2_0; 324 u8 cfg_cdr_kf_gen2_2_0; 325 u8 cfg_cdr_kf_gen3_2_0; 326 u8 cfg_cdr_kf_gen4_2_0; 327 u8 r_cdr_m_gen1_7_0; 328 u8 cfg_pi_bw_gen1_3_0; 329 u8 cfg_pi_bw_gen2; 330 u8 cfg_pi_bw_gen3; 331 u8 cfg_pi_bw_gen4; 332 u8 cfg_pi_ext_dac_7_0; 333 u8 cfg_pi_steps; 334 u8 cfg_mp_max_3_0; 335 u8 cfg_rstn_dfedig; 336 u8 cfg_alos_thr_3_0; 337 u8 cfg_predrv_slewrate_1_0; 338 u8 cfg_itx_ipcml_base_1_0; 339 u8 cfg_ip_pre_base_1_0; 340 u8 r_cdr_m_gen2_7_0; 341 u8 r_cdr_m_gen3_7_0; 342 u8 r_cdr_m_gen4_7_0; 343 u8 r_en_auto_cdr_rstn; 344 u8 cfg_oscal_afe; 345 u8 cfg_pd_osdac_afe; 346 u8 cfg_resetb_oscal_afe[2]; 347 u8 cfg_center_spreading; 348 u8 cfg_m_cnt_maxval_4_0; 349 u8 cfg_ncnt_maxval_7_0; 350 u8 cfg_ncnt_maxval_10_8; 351 u8 cfg_ssc_en; 352 u8 cfg_tx2rx_lp_en; 353 u8 cfg_txlb_en; 354 u8 cfg_rx2tx_lp_en; 355 u8 cfg_rxlb_en; 356 u8 r_tx_pol_inv; 357 u8 r_rx_pol_inv; 358 u8 fx_100; 359 }; 360 361 static struct sparx5_sd25g28_media_preset media_presets_25g[] = { 362 { /* ETH_MEDIA_DEFAULT */ 363 .cfg_en_adv = 0, 364 .cfg_en_main = 1, 365 .cfg_en_dly = 0, 366 .cfg_tap_adv_3_0 = 0, 367 .cfg_tap_main = 1, 368 .cfg_tap_dly_4_0 = 0, 369 .cfg_eq_c_force_3_0 = 0xf, 370 .cfg_vga_ctrl_byp_4_0 = 4, 371 .cfg_eq_r_force_3_0 = 12, 372 .cfg_alos_thr_2_0 = 7, 373 }, 374 { /* ETH_MEDIA_SR */ 375 .cfg_en_adv = 1, 376 .cfg_en_main = 1, 377 .cfg_en_dly = 1, 378 .cfg_tap_adv_3_0 = 0, 379 .cfg_tap_main = 1, 380 .cfg_tap_dly_4_0 = 0x10, 381 .cfg_eq_c_force_3_0 = 0xf, 382 .cfg_vga_ctrl_byp_4_0 = 8, 383 .cfg_eq_r_force_3_0 = 4, 384 .cfg_alos_thr_2_0 = 0, 385 }, 386 { /* ETH_MEDIA_DAC */ 387 .cfg_en_adv = 0, 388 .cfg_en_main = 1, 389 .cfg_en_dly = 0, 390 .cfg_tap_adv_3_0 = 0, 391 .cfg_tap_main = 1, 392 .cfg_tap_dly_4_0 = 0, 393 .cfg_eq_c_force_3_0 = 0xf, 394 .cfg_vga_ctrl_byp_4_0 = 8, 395 .cfg_eq_r_force_3_0 = 0xc, 396 .cfg_alos_thr_2_0 = 0, 397 }, 398 }; 399 400 static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = { 401 { /* SPX5_SD25G28_MODE_PRESET_25000 */ 402 .bitwidth = 40, 403 .tx_pre_div = 0, 404 .fifo_ck_div = 0, 405 .pre_divsel = 1, 406 .vco_div_mode = 0, 407 .sel_div = 15, 408 .ck_bitwidth = 3, 409 .subrate = 0, 410 .com_txcal_en = 0, 411 .com_tx_reserve_msb = (0x26 << 1), 412 .com_tx_reserve_lsb = 0xf0, 413 .cfg_itx_ipcml_base = 0, 414 .tx_reserve_msb = 0xcc, 415 .tx_reserve_lsb = 0xfe, 416 .bw = 3, 417 .rxterm = 0, 418 .dfe_enable = 1, 419 .dfe_tap = 0x1f, 420 .txmargin = 1, 421 .cfg_ctle_rstn = 1, 422 .r_dfe_rstn = 1, 423 .cfg_pi_bw_3_0 = 0, 424 .tx_tap_dly = 8, 425 .tx_tap_adv = 0xc, 426 }, 427 { /* SPX5_SD25G28_MODE_PRESET_10000 */ 428 .bitwidth = 64, 429 .tx_pre_div = 0, 430 .fifo_ck_div = 2, 431 .pre_divsel = 0, 432 .vco_div_mode = 1, 433 .sel_div = 9, 434 .ck_bitwidth = 0, 435 .subrate = 0, 436 .com_txcal_en = 1, 437 .com_tx_reserve_msb = (0x20 << 1), 438 .com_tx_reserve_lsb = 0x40, 439 .cfg_itx_ipcml_base = 0, 440 .tx_reserve_msb = 0x4c, 441 .tx_reserve_lsb = 0x44, 442 .bw = 3, 443 .cfg_pi_bw_3_0 = 0, 444 .rxterm = 3, 445 .dfe_enable = 1, 446 .dfe_tap = 0x1f, 447 .txmargin = 0, 448 .cfg_ctle_rstn = 1, 449 .r_dfe_rstn = 1, 450 .tx_tap_dly = 0, 451 .tx_tap_adv = 0, 452 }, 453 { /* SPX5_SD25G28_MODE_PRESET_5000 */ 454 .bitwidth = 64, 455 .tx_pre_div = 0, 456 .fifo_ck_div = 2, 457 .pre_divsel = 0, 458 .vco_div_mode = 2, 459 .sel_div = 9, 460 .ck_bitwidth = 0, 461 .subrate = 0, 462 .com_txcal_en = 1, 463 .com_tx_reserve_msb = (0x20 << 1), 464 .com_tx_reserve_lsb = 0, 465 .cfg_itx_ipcml_base = 0, 466 .tx_reserve_msb = 0xe, 467 .tx_reserve_lsb = 0x80, 468 .bw = 0, 469 .rxterm = 0, 470 .cfg_pi_bw_3_0 = 6, 471 .dfe_enable = 0, 472 .dfe_tap = 0, 473 .tx_tap_dly = 0, 474 .tx_tap_adv = 0, 475 }, 476 { /* SPX5_SD25G28_MODE_PRESET_SD_2G5 */ 477 .bitwidth = 10, 478 .tx_pre_div = 0, 479 .fifo_ck_div = 0, 480 .pre_divsel = 0, 481 .vco_div_mode = 1, 482 .sel_div = 6, 483 .ck_bitwidth = 3, 484 .subrate = 2, 485 .com_txcal_en = 1, 486 .com_tx_reserve_msb = (0x26 << 1), 487 .com_tx_reserve_lsb = (0xf << 4), 488 .cfg_itx_ipcml_base = 2, 489 .tx_reserve_msb = 0x8, 490 .tx_reserve_lsb = 0x8a, 491 .bw = 0, 492 .cfg_pi_bw_3_0 = 0, 493 .rxterm = (1 << 2), 494 .dfe_enable = 0, 495 .dfe_tap = 0, 496 .tx_tap_dly = 0, 497 .tx_tap_adv = 0, 498 }, 499 { /* SPX5_SD25G28_MODE_PRESET_1000BASEX */ 500 .bitwidth = 10, 501 .tx_pre_div = 0, 502 .fifo_ck_div = 1, 503 .pre_divsel = 0, 504 .vco_div_mode = 1, 505 .sel_div = 8, 506 .ck_bitwidth = 3, 507 .subrate = 3, 508 .com_txcal_en = 1, 509 .com_tx_reserve_msb = (0x26 << 1), 510 .com_tx_reserve_lsb = 0xf0, 511 .cfg_itx_ipcml_base = 0, 512 .tx_reserve_msb = 0x8, 513 .tx_reserve_lsb = 0xce, 514 .bw = 0, 515 .rxterm = 0, 516 .cfg_pi_bw_3_0 = 0, 517 .dfe_enable = 0, 518 .dfe_tap = 0, 519 .tx_tap_dly = 0, 520 .tx_tap_adv = 0, 521 }, 522 }; 523 524 static struct sparx5_sd10g28_media_preset media_presets_10g[] = { 525 { /* ETH_MEDIA_DEFAULT */ 526 .cfg_en_adv = 0, 527 .cfg_en_main = 1, 528 .cfg_en_dly = 0, 529 .cfg_tap_adv_3_0 = 0, 530 .cfg_tap_main = 1, 531 .cfg_tap_dly_4_0 = 0, 532 .cfg_vga_ctrl_3_0 = 5, 533 .cfg_vga_cp_2_0 = 0, 534 .cfg_eq_res_3_0 = 0xa, 535 .cfg_eq_r_byp = 1, 536 .cfg_eq_c_force_3_0 = 0x8, 537 .cfg_alos_thr_3_0 = 0x3, 538 }, 539 { /* ETH_MEDIA_SR */ 540 .cfg_en_adv = 1, 541 .cfg_en_main = 1, 542 .cfg_en_dly = 1, 543 .cfg_tap_adv_3_0 = 0, 544 .cfg_tap_main = 1, 545 .cfg_tap_dly_4_0 = 0xc, 546 .cfg_vga_ctrl_3_0 = 0xa, 547 .cfg_vga_cp_2_0 = 0x4, 548 .cfg_eq_res_3_0 = 0xa, 549 .cfg_eq_r_byp = 1, 550 .cfg_eq_c_force_3_0 = 0xF, 551 .cfg_alos_thr_3_0 = 0x3, 552 }, 553 { /* ETH_MEDIA_DAC */ 554 .cfg_en_adv = 1, 555 .cfg_en_main = 1, 556 .cfg_en_dly = 1, 557 .cfg_tap_adv_3_0 = 12, 558 .cfg_tap_main = 1, 559 .cfg_tap_dly_4_0 = 8, 560 .cfg_vga_ctrl_3_0 = 0xa, 561 .cfg_vga_cp_2_0 = 4, 562 .cfg_eq_res_3_0 = 0xa, 563 .cfg_eq_r_byp = 1, 564 .cfg_eq_c_force_3_0 = 0xf, 565 .cfg_alos_thr_3_0 = 0x0, 566 } 567 }; 568 569 static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = { 570 { /* SPX5_SD10G28_MODE_PRESET_10000 */ 571 .bwidth = 64, 572 .cmu_sel = SPX5_SD10G28_CMU_MAIN, 573 .rate = 0x0, 574 .dfe_enable = 1, 575 .dfe_tap = 0x1f, 576 .pi_bw_gen1 = 0x0, 577 .duty_cycle = 0x2, 578 }, 579 { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */ 580 .bwidth = 16, 581 .cmu_sel = SPX5_SD10G28_CMU_MAIN, 582 .rate = 0x1, 583 .dfe_enable = 0, 584 .dfe_tap = 0, 585 .pi_bw_gen1 = 0x5, 586 .duty_cycle = 0x0, 587 }, 588 { /* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */ 589 .bwidth = 64, 590 .cmu_sel = SPX5_SD10G28_CMU_MAIN, 591 .rate = 0x1, 592 .dfe_enable = 0, 593 .dfe_tap = 0, 594 .pi_bw_gen1 = 0x5, 595 .duty_cycle = 0x0, 596 }, 597 { /* SPX5_SD10G28_MODE_PRESET_QSGMII */ 598 .bwidth = 20, 599 .cmu_sel = SPX5_SD10G28_CMU_AUX1, 600 .rate = 0x1, 601 .dfe_enable = 0, 602 .dfe_tap = 0, 603 .pi_bw_gen1 = 0x5, 604 .duty_cycle = 0x0, 605 }, 606 { /* SPX5_SD10G28_MODE_PRESET_SD_2G5 */ 607 .bwidth = 10, 608 .cmu_sel = SPX5_SD10G28_CMU_AUX2, 609 .rate = 0x2, 610 .dfe_enable = 0, 611 .dfe_tap = 0, 612 .pi_bw_gen1 = 0x7, 613 .duty_cycle = 0x0, 614 }, 615 { /* SPX5_SD10G28_MODE_PRESET_1000BASEX */ 616 .bwidth = 10, 617 .cmu_sel = SPX5_SD10G28_CMU_AUX1, 618 .rate = 0x3, 619 .dfe_enable = 0, 620 .dfe_tap = 0, 621 .pi_bw_gen1 = 0x7, 622 .duty_cycle = 0x0, 623 }, 624 }; 625 626 /* map from SD25G28 interface width to configuration value */ 627 static u8 sd25g28_get_iw_setting(struct device *dev, const u8 interface_width) 628 { 629 switch (interface_width) { 630 case 10: return 0; 631 case 16: return 1; 632 case 32: return 3; 633 case 40: return 4; 634 case 64: return 5; 635 default: 636 dev_err(dev, "%s: Illegal value %d for interface width\n", 637 __func__, interface_width); 638 } 639 return 0; 640 } 641 642 /* map from SD10G28 interface width to configuration value */ 643 static u8 sd10g28_get_iw_setting(struct device *dev, const u8 interface_width) 644 { 645 switch (interface_width) { 646 case 10: return 0; 647 case 16: return 1; 648 case 20: return 2; 649 case 32: return 3; 650 case 40: return 4; 651 case 64: return 7; 652 default: 653 dev_err(dev, "%s: Illegal value %d for interface width\n", __func__, 654 interface_width); 655 return 0; 656 } 657 } 658 659 static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro, 660 struct sparx5_sd25g28_mode_preset *mode) 661 { 662 switch (macro->serdesmode) { 663 case SPX5_SD_MODE_SFI: 664 if (macro->speed == SPEED_25000) 665 *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000]; 666 else if (macro->speed == SPEED_10000) 667 *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_10000]; 668 else if (macro->speed == SPEED_5000) 669 *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_5000]; 670 break; 671 case SPX5_SD_MODE_2G5: 672 *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_SD_2G5]; 673 break; 674 case SPX5_SD_MODE_1000BASEX: 675 *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_1000BASEX]; 676 break; 677 case SPX5_SD_MODE_100FX: 678 /* Not supported */ 679 return -EINVAL; 680 default: 681 *mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000]; 682 break; 683 } 684 return 0; 685 } 686 687 static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro, 688 struct sparx5_sd10g28_mode_preset *mode, 689 struct sparx5_sd10g28_args *args) 690 { 691 switch (macro->serdesmode) { 692 case SPX5_SD_MODE_SFI: 693 if (macro->speed == SPEED_10000) { 694 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000]; 695 } else if (macro->speed == SPEED_5000) { 696 if (args->is_6g) 697 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_6G]; 698 else 699 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_10G]; 700 } else { 701 dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)", 702 __func__, macro->speed, macro->sidx, 703 macro->serdesmode); 704 return -EINVAL; 705 } 706 break; 707 case SPX5_SD_MODE_QSGMII: 708 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_QSGMII]; 709 break; 710 case SPX5_SD_MODE_2G5: 711 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SD_2G5]; 712 break; 713 case SPX5_SD_MODE_100FX: 714 case SPX5_SD_MODE_1000BASEX: 715 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_1000BASEX]; 716 break; 717 default: 718 *mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000]; 719 break; 720 } 721 return 0; 722 } 723 724 static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro, 725 struct sparx5_sd25g28_media_preset *media, 726 struct sparx5_sd25g28_mode_preset *mode, 727 struct sparx5_sd25g28_args *args, 728 struct sparx5_sd25g28_params *params) 729 { 730 u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth); 731 struct sparx5_sd25g28_params init = { 732 .r_d_width_ctrl_2_0 = iw, 733 .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, 734 .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div, 735 .cfg_vco_div_mode_1_0 = mode->vco_div_mode, 736 .cfg_pre_divsel_1_0 = mode->pre_divsel, 737 .cfg_sel_div_3_0 = mode->sel_div, 738 .cfg_vco_start_code_3_0 = 0, 739 .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth, 740 .cfg_tx_prediv_1_0 = mode->tx_pre_div, 741 .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth, 742 .cfg_tx_subrate_2_0 = mode->subrate, 743 .cfg_rx_subrate_2_0 = mode->subrate, 744 .r_multi_lane_mode = 0, 745 .cfg_cdrck_en = 1, 746 .cfg_dfeck_en = mode->dfe_enable, 747 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1, 748 .cfg_dfedmx_pd = 1, 749 .cfg_dfetap_en_5_1 = mode->dfe_tap, 750 .cfg_dmux_pd = 0, 751 .cfg_dmux_clk_pd = 1, 752 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1, 753 .cfg_pi_DFE_en = mode->dfe_enable, 754 .cfg_pi_en = 1, 755 .cfg_pd_ctle = 0, 756 .cfg_summer_en = 1, 757 .cfg_pmad_ck_pd = 0, 758 .cfg_pd_clk = 0, 759 .cfg_pd_cml = 0, 760 .cfg_pd_driver = 0, 761 .cfg_rx_reg_pu = 1, 762 .cfg_pd_rms_det = 1, 763 .cfg_dcdr_pd = 0, 764 .cfg_ecdr_pd = 1, 765 .cfg_pd_sq = 1, 766 .cfg_itx_ipdriver_base_2_0 = mode->txmargin, 767 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, 768 .cfg_tap_main = media->cfg_tap_main, 769 .cfg_en_main = media->cfg_en_main, 770 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, 771 .cfg_en_adv = media->cfg_en_adv, 772 .cfg_en_dly = media->cfg_en_dly, 773 .cfg_iscan_en = 0, 774 .l1_pcs_en_fast_iscan = 0, 775 .l0_cfg_bw_1_0 = 0, 776 .cfg_en_dummy = 0, 777 .cfg_pll_reserve_3_0 = args->com_pll_reserve, 778 .l0_cfg_txcal_en = mode->com_txcal_en, 779 .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb, 780 .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb, 781 .cfg_tx_reserve_15_8 = mode->tx_reserve_msb, 782 .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb, 783 .cfg_bw_1_0 = mode->bw, 784 .cfg_txcal_man_en = 1, 785 .cfg_phase_man_4_0 = 0, 786 .cfg_quad_man_1_0 = 0, 787 .cfg_txcal_shift_code_5_0 = 2, 788 .cfg_txcal_valid_sel_3_0 = 4, 789 .cfg_txcal_en = 0, 790 .cfg_cdr_kf_2_0 = 1, 791 .cfg_cdr_m_7_0 = 6, 792 .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0, 793 .cfg_pi_steps_1_0 = 0, 794 .cfg_dis_2ndorder = 1, 795 .cfg_ctle_rstn = mode->cfg_ctle_rstn, 796 .r_dfe_rstn = mode->r_dfe_rstn, 797 .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0, 798 .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base, 799 .cfg_rx_reserve_7_0 = 0xbf, 800 .cfg_rx_reserve_15_8 = 0x61, 801 .cfg_rxterm_2_0 = mode->rxterm, 802 .cfg_fom_selm = 0, 803 .cfg_rx_sp_ctle_1_0 = 0, 804 .cfg_isel_ctle_1_0 = 0, 805 .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0, 806 .cfg_vga_byp = 1, 807 .cfg_agc_adpt_byp = 1, 808 .cfg_eqr_byp = 1, 809 .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0, 810 .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0, 811 .cfg_sum_setcm_en = 1, 812 .cfg_pi_dfe_en = 1, 813 .cfg_init_pos_iscan_6_0 = 6, 814 .cfg_init_pos_ipi_6_0 = 9, 815 .cfg_dfedig_m_2_0 = 6, 816 .cfg_en_dfedig = mode->dfe_enable, 817 .r_d_width_ctrl_from_hwt = 0, 818 .r_reg_manual = 1, 819 .reg_rst = args->reg_rst, 820 .cfg_jc_byp = 1, 821 .cfg_common_reserve_7_0 = 1, 822 .cfg_pll_lol_set = 1, 823 .cfg_tx2rx_lp_en = 0, 824 .cfg_txlb_en = 0, 825 .cfg_rx2tx_lp_en = 0, 826 .cfg_rxlb_en = 0, 827 .r_tx_pol_inv = args->txinvert, 828 .r_rx_pol_inv = args->rxinvert, 829 }; 830 831 *params = init; 832 } 833 834 static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro, 835 struct sparx5_sd10g28_media_preset *media, 836 struct sparx5_sd10g28_mode_preset *mode, 837 struct sparx5_sd10g28_args *args, 838 struct sparx5_sd10g28_params *params) 839 { 840 u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth); 841 struct sparx5_sd10g28_params init = { 842 .skip_cmu_cfg = args->skip_cmu_cfg, 843 .is_6g = args->is_6g, 844 .cmu_sel = mode->cmu_sel, 845 .cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6, 846 .cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2), 847 .cfg_lane_reserve_15_8 = mode->duty_cycle, 848 .cfg_txrate_1_0 = mode->rate, 849 .cfg_rxrate_1_0 = mode->rate, 850 .fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX, 851 .r_d_width_ctrl_2_0 = iw, 852 .cfg_pma_tx_ck_bitwidth_2_0 = iw, 853 .cfg_rxdiv_sel_2_0 = iw, 854 .r_pcs2pma_phymode_4_0 = 0, 855 .cfg_lane_id_2_0 = 0, 856 .cfg_cdrck_en = 1, 857 .cfg_dfeck_en = mode->dfe_enable, 858 .cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1, 859 .cfg_dfetap_en_5_1 = mode->dfe_tap, 860 .cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1, 861 .cfg_pi_DFE_en = mode->dfe_enable, 862 .cfg_pi_en = 1, 863 .cfg_pd_ctle = 0, 864 .cfg_summer_en = 1, 865 .cfg_pd_rx_cktree = 0, 866 .cfg_pd_clk = 0, 867 .cfg_pd_cml = 0, 868 .cfg_pd_driver = 0, 869 .cfg_rx_reg_pu = 1, 870 .cfg_d_cdr_pd = 0, 871 .cfg_pd_sq = mode->dfe_enable, 872 .cfg_rxdet_en = 0, 873 .cfg_rxdet_str = 0, 874 .r_multi_lane_mode = 0, 875 .cfg_en_adv = media->cfg_en_adv, 876 .cfg_en_main = 1, 877 .cfg_en_dly = media->cfg_en_dly, 878 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0, 879 .cfg_tap_main = media->cfg_tap_main, 880 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0, 881 .cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0, 882 .cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0, 883 .cfg_eq_res_3_0 = media->cfg_eq_res_3_0, 884 .cfg_eq_r_byp = media->cfg_eq_r_byp, 885 .cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0, 886 .cfg_en_dfedig = mode->dfe_enable, 887 .cfg_sum_setcm_en = 1, 888 .cfg_en_preemph = 0, 889 .cfg_itx_ippreemp_base_1_0 = 0, 890 .cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6), 891 .cfg_ibias_tune_reserve_5_0 = (args->txswing & 63), 892 .cfg_txswing_half = (args->txmargin), 893 .cfg_dis_2nd_order = 0x1, 894 .cfg_rx_ssc_lh = 0x0, 895 .cfg_pi_floop_steps_1_0 = 0x0, 896 .cfg_pi_ext_dac_23_16 = (1 << 5), 897 .cfg_pi_ext_dac_15_8 = (0 << 6), 898 .cfg_iscan_ext_dac_7_0 = (1 << 7) + 9, 899 .cfg_cdr_kf_gen1_2_0 = 1, 900 .cfg_cdr_kf_gen2_2_0 = 1, 901 .cfg_cdr_kf_gen3_2_0 = 1, 902 .cfg_cdr_kf_gen4_2_0 = 1, 903 .r_cdr_m_gen1_7_0 = 4, 904 .cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1, 905 .cfg_pi_bw_gen2 = mode->pi_bw_gen1, 906 .cfg_pi_bw_gen3 = mode->pi_bw_gen1, 907 .cfg_pi_bw_gen4 = mode->pi_bw_gen1, 908 .cfg_pi_ext_dac_7_0 = 3, 909 .cfg_pi_steps = 0, 910 .cfg_mp_max_3_0 = 1, 911 .cfg_rstn_dfedig = mode->dfe_enable, 912 .cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0, 913 .cfg_predrv_slewrate_1_0 = 3, 914 .cfg_itx_ipcml_base_1_0 = 0, 915 .cfg_ip_pre_base_1_0 = 0, 916 .r_cdr_m_gen2_7_0 = 2, 917 .r_cdr_m_gen3_7_0 = 2, 918 .r_cdr_m_gen4_7_0 = 2, 919 .r_en_auto_cdr_rstn = 0, 920 .cfg_oscal_afe = 1, 921 .cfg_pd_osdac_afe = 0, 922 .cfg_resetb_oscal_afe[0] = 0, 923 .cfg_resetb_oscal_afe[1] = 1, 924 .cfg_center_spreading = 0, 925 .cfg_m_cnt_maxval_4_0 = 15, 926 .cfg_ncnt_maxval_7_0 = 32, 927 .cfg_ncnt_maxval_10_8 = 6, 928 .cfg_ssc_en = 1, 929 .cfg_tx2rx_lp_en = 0, 930 .cfg_txlb_en = 0, 931 .cfg_rx2tx_lp_en = 0, 932 .cfg_rxlb_en = 0, 933 .r_tx_pol_inv = args->txinvert, 934 .r_rx_pol_inv = args->rxinvert, 935 }; 936 937 *params = init; 938 } 939 940 static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv, 941 u32 cmu_idx, 942 void __iomem *cmu_tgt, 943 void __iomem *cmu_cfg_tgt, 944 u32 spd10g) 945 { 946 void __iomem **regs = priv->regs; 947 struct device *dev = priv->dev; 948 int value; 949 950 cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); 951 cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); 952 953 if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || 954 cmu_idx == 10 || cmu_idx == 13) { 955 spd10g = 0; 956 } 957 958 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1), 959 SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, 960 cmu_cfg_tgt, 961 SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); 962 963 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), 964 SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, 965 cmu_cfg_tgt, 966 SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); 967 968 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1), 969 SD_CMU_CFG_SD_CMU_CFG_CMU_RST, 970 cmu_cfg_tgt, 971 SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); 972 973 sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) | 974 SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) | 975 SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) | 976 SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) | 977 SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0), 978 SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT | 979 SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT | 980 SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT | 981 SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT | 982 SD_CMU_CMU_45_R_EN_RATECHG_CTRL, 983 cmu_tgt, 984 SD_CMU_CMU_45(cmu_idx)); 985 986 sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0), 987 SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, 988 cmu_tgt, 989 SD_CMU_CMU_47(cmu_idx)); 990 991 sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0), 992 SD_CMU_CMU_1B_CFG_RESERVE_7_0, 993 cmu_tgt, 994 SD_CMU_CMU_1B(cmu_idx)); 995 996 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1), 997 SD_CMU_CMU_0D_CFG_JC_BYP, 998 cmu_tgt, 999 SD_CMU_CMU_0D(cmu_idx)); 1000 1001 sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1), 1002 SD_CMU_CMU_1F_CFG_VTUNE_SEL, 1003 cmu_tgt, 1004 SD_CMU_CMU_1F(cmu_idx)); 1005 1006 sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3), 1007 SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, 1008 cmu_tgt, 1009 SD_CMU_CMU_00(cmu_idx)); 1010 1011 sdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3), 1012 SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, 1013 cmu_tgt, 1014 SD_CMU_CMU_05(cmu_idx)); 1015 1016 sdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1), 1017 SD_CMU_CMU_30_R_PLL_DLOL_EN, 1018 cmu_tgt, 1019 SD_CMU_CMU_30(cmu_idx)); 1020 1021 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g), 1022 SD_CMU_CMU_09_CFG_SW_10G, 1023 cmu_tgt, 1024 SD_CMU_CMU_09(cmu_idx)); 1025 1026 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0), 1027 SD_CMU_CFG_SD_CMU_CFG_CMU_RST, 1028 cmu_cfg_tgt, 1029 SD_CMU_CFG_SD_CMU_CFG(cmu_idx)); 1030 1031 msleep(20); 1032 1033 sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0), 1034 SD_CMU_CMU_44_R_PLL_RSTN, 1035 cmu_tgt, 1036 SD_CMU_CMU_44(cmu_idx)); 1037 1038 sdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1), 1039 SD_CMU_CMU_44_R_PLL_RSTN, 1040 cmu_tgt, 1041 SD_CMU_CMU_44(cmu_idx)); 1042 1043 msleep(20); 1044 1045 value = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx))); 1046 value = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value); 1047 1048 if (value) { 1049 dev_err(dev, "CMU PLL Loss of Lock: 0x%x\n", value); 1050 return -EINVAL; 1051 } 1052 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0), 1053 SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, 1054 cmu_tgt, 1055 SD_CMU_CMU_0D(cmu_idx)); 1056 return 0; 1057 } 1058 1059 static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx) 1060 { 1061 void __iomem *cmu_tgt, *cmu_cfg_tgt; 1062 u32 spd10g = 1; 1063 1064 if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 || 1065 cmu_idx == 10 || cmu_idx == 13) { 1066 spd10g = 0; 1067 } 1068 1069 cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx); 1070 cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx); 1071 1072 return sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g); 1073 } 1074 1075 /* Map of 6G/10G serdes mode and index to CMU index. */ 1076 static const int 1077 sparx5_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][SPX5_SERDES_6G10G_CNT] = { 1078 [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2, 1079 2, 2, 2, 5, 5, 1080 5, 5, 5, 5, 5, 1081 5, 8, 11, 11, 11, 1082 11, 11, 11, 11, 11 }, 1083 [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3, 1084 3, 3, 3, 3, 3, 1085 6, 6, 6, 6, 6, 1086 6, 6, 9, 9, 12, 1087 12, 12, 12, 12, 12 }, 1088 [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4, 1089 4, 4, 4, 4, 4, 1090 4, 4, 7, 7, 7, 1091 7, 7, 10, 10, 10, 1092 10, 13, 13, 13, 13 }, 1093 [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4, 1094 4, 4, 4, 4, 4, 1095 4, 4, 7, 7, 7, 1096 7, 7, 10, 10, 10, 1097 10, 13, 13, 13, 13 }, 1098 }; 1099 1100 /* Get the index of the CMU which provides the clock for the specified serdes 1101 * mode and index. 1102 */ 1103 static int sparx5_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index) 1104 { 1105 return sparx5_serdes_cmu_map[mode][sd_index]; 1106 } 1107 1108 /* Map of 6G/10G serdes mode and index to CMU index. */ 1109 static const int 1110 lan969x_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][LAN969X_SERDES_10G_CNT] = { 1111 [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2, 1112 2, 2, 2, 5, 5 }, 1113 [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3, 1114 3, 3, 3, 3, 3 }, 1115 [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4, 1116 4, 4, 4, 4, 4 }, 1117 [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4, 1118 4, 4, 4, 4, 4 }, 1119 }; 1120 1121 static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index) 1122 { 1123 return lan969x_serdes_cmu_map[mode][sd_index]; 1124 } 1125 1126 static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv) 1127 { 1128 void __iomem *cmu_inst, *cmu_cfg_inst; 1129 int i; 1130 1131 /* Power down each CMU */ 1132 for (i = 0; i < priv->data->consts.cmu_max; i++) { 1133 cmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i); 1134 cmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i); 1135 1136 sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0), 1137 SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, cmu_cfg_inst, 1138 SD_CMU_CFG_SD_CMU_CFG(0)); 1139 1140 sdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0), 1141 SD_CMU_CMU_05_CFG_REFCK_TERM_EN, cmu_inst, 1142 SD_CMU_CMU_05(0)); 1143 1144 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0), 1145 SD_CMU_CMU_09_CFG_EN_TX_CK_DN, cmu_inst, 1146 SD_CMU_CMU_09(0)); 1147 1148 sdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1), 1149 SD_CMU_CMU_06_CFG_VCO_PD, cmu_inst, 1150 SD_CMU_CMU_06(0)); 1151 1152 sdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0), 1153 SD_CMU_CMU_09_CFG_EN_TX_CK_UP, cmu_inst, 1154 SD_CMU_CMU_09(0)); 1155 1156 sdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1), 1157 SD_CMU_CMU_08_CFG_CK_TREE_PD, cmu_inst, 1158 SD_CMU_CMU_08(0)); 1159 1160 sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) | 1161 SD_CMU_CMU_0D_CFG_PD_DIV64_SET(1) | 1162 SD_CMU_CMU_0D_CFG_PD_DIV66_SET(1), 1163 SD_CMU_CMU_0D_CFG_REFCK_PD | 1164 SD_CMU_CMU_0D_CFG_PD_DIV64 | 1165 SD_CMU_CMU_0D_CFG_PD_DIV66, cmu_inst, 1166 SD_CMU_CMU_0D(0)); 1167 1168 sdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1), 1169 SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, cmu_inst, 1170 SD_CMU_CMU_06(0)); 1171 } 1172 } 1173 1174 static void sparx5_sd25g28_reset(void __iomem *regs[], 1175 struct sparx5_sd25g28_params *params, 1176 u32 sd_index) 1177 { 1178 if (params->reg_rst == 1) { 1179 sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1), 1180 SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, 1181 sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))); 1182 1183 usleep_range(1000, 2000); 1184 1185 sdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), 1186 SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, 1187 sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))); 1188 } 1189 } 1190 1191 static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro, 1192 struct sparx5_sd25g28_params *params) 1193 { 1194 struct sparx5_serdes_private *priv = macro->priv; 1195 void __iomem **regs = priv->regs; 1196 struct device *dev = priv->dev; 1197 u32 sd_index = macro->stpidx; 1198 u32 value; 1199 1200 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1), 1201 SD_LANE_25G_SD_LANE_CFG_MACRO_RST, 1202 priv, 1203 SD_LANE_25G_SD_LANE_CFG(sd_index)); 1204 1205 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF), 1206 SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, 1207 priv, 1208 SD25G_LANE_CMU_FF(sd_index)); 1209 1210 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET 1211 (params->r_d_width_ctrl_from_hwt) | 1212 SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual), 1213 SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT | 1214 SD25G_LANE_CMU_1A_R_REG_MANUAL, 1215 priv, 1216 SD25G_LANE_CMU_1A(sd_index)); 1217 1218 sdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET 1219 (params->cfg_common_reserve_7_0), 1220 SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, 1221 priv, 1222 SD25G_LANE_CMU_31(sd_index)); 1223 1224 sdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy), 1225 SD25G_LANE_CMU_09_CFG_EN_DUMMY, 1226 priv, 1227 SD25G_LANE_CMU_09(sd_index)); 1228 1229 sdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET 1230 (params->cfg_pll_reserve_3_0), 1231 SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, 1232 priv, 1233 SD25G_LANE_CMU_13(sd_index)); 1234 1235 sdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en), 1236 SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, 1237 priv, 1238 SD25G_LANE_CMU_40(sd_index)); 1239 1240 sdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET 1241 (params->l0_cfg_tx_reserve_15_8), 1242 SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, 1243 priv, 1244 SD25G_LANE_CMU_46(sd_index)); 1245 1246 sdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET 1247 (params->l0_cfg_tx_reserve_7_0), 1248 SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, 1249 priv, 1250 SD25G_LANE_CMU_45(sd_index)); 1251 1252 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0), 1253 SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, 1254 priv, 1255 SD25G_LANE_CMU_0B(sd_index)); 1256 1257 sdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1), 1258 SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, 1259 priv, 1260 SD25G_LANE_CMU_0B(sd_index)); 1261 1262 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0), 1263 SD25G_LANE_CMU_19_R_CK_RESETB, 1264 priv, 1265 SD25G_LANE_CMU_19(sd_index)); 1266 1267 sdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1), 1268 SD25G_LANE_CMU_19_R_CK_RESETB, 1269 priv, 1270 SD25G_LANE_CMU_19(sd_index)); 1271 1272 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0), 1273 SD25G_LANE_CMU_18_R_PLL_RSTN, 1274 priv, 1275 SD25G_LANE_CMU_18(sd_index)); 1276 1277 sdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1), 1278 SD25G_LANE_CMU_18_R_PLL_RSTN, 1279 priv, 1280 SD25G_LANE_CMU_18(sd_index)); 1281 1282 sdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0), 1283 SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, 1284 priv, 1285 SD25G_LANE_CMU_1A(sd_index)); 1286 1287 sdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET 1288 (params->r_txfifo_ck_div_pmad_2_0) | 1289 SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET 1290 (params->r_rxfifo_ck_div_pmad_2_0), 1291 SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 | 1292 SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, 1293 priv, 1294 SD25G_LANE_CMU_30(sd_index)); 1295 1296 sdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) | 1297 SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET 1298 (params->cfg_vco_div_mode_1_0), 1299 SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET | 1300 SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, 1301 priv, 1302 SD25G_LANE_CMU_0C(sd_index)); 1303 1304 sdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET 1305 (params->cfg_pre_divsel_1_0), 1306 SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, 1307 priv, 1308 SD25G_LANE_CMU_0D(sd_index)); 1309 1310 sdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0), 1311 SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, 1312 priv, 1313 SD25G_LANE_CMU_0E(sd_index)); 1314 1315 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00), 1316 SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, 1317 priv, 1318 SD25G_LANE_CMU_FF(sd_index)); 1319 1320 sdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET 1321 (params->cfg_pma_tx_ck_bitwidth_2_0), 1322 SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, 1323 priv, 1324 SD25G_LANE_LANE_0C(sd_index)); 1325 1326 sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET 1327 (params->cfg_tx_prediv_1_0), 1328 SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, 1329 priv, 1330 SD25G_LANE_LANE_01(sd_index)); 1331 1332 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET 1333 (params->cfg_rxdiv_sel_2_0), 1334 SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, 1335 priv, 1336 SD25G_LANE_LANE_18(sd_index)); 1337 1338 sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET 1339 (params->cfg_tx_subrate_2_0), 1340 SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, 1341 priv, 1342 SD25G_LANE_LANE_2C(sd_index)); 1343 1344 sdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET 1345 (params->cfg_rx_subrate_2_0), 1346 SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, 1347 priv, 1348 SD25G_LANE_LANE_28(sd_index)); 1349 1350 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), 1351 SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, 1352 priv, 1353 SD25G_LANE_LANE_18(sd_index)); 1354 1355 sdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET 1356 (params->cfg_dfetap_en_5_1), 1357 SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, 1358 priv, 1359 SD25G_LANE_LANE_0F(sd_index)); 1360 1361 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), 1362 SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, 1363 priv, 1364 SD25G_LANE_LANE_18(sd_index)); 1365 1366 sdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en), 1367 SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, 1368 priv, 1369 SD25G_LANE_LANE_1D(sd_index)); 1370 1371 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd), 1372 SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, 1373 priv, 1374 SD25G_LANE_LANE_19(sd_index)); 1375 1376 sdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET 1377 (params->cfg_itx_ipdriver_base_2_0), 1378 SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, 1379 priv, 1380 SD25G_LANE_LANE_01(sd_index)); 1381 1382 sdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0), 1383 SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, 1384 priv, 1385 SD25G_LANE_LANE_03(sd_index)); 1386 1387 sdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0), 1388 SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, 1389 priv, 1390 SD25G_LANE_LANE_06(sd_index)); 1391 1392 sdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) | 1393 SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly), 1394 SD25G_LANE_LANE_07_LN_CFG_EN_ADV | 1395 SD25G_LANE_LANE_07_LN_CFG_EN_DLY, 1396 priv, 1397 SD25G_LANE_LANE_07(sd_index)); 1398 1399 sdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET 1400 (params->cfg_tx_reserve_15_8), 1401 SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, 1402 priv, 1403 SD25G_LANE_LANE_43(sd_index)); 1404 1405 sdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET 1406 (params->cfg_tx_reserve_7_0), 1407 SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, 1408 priv, 1409 SD25G_LANE_LANE_42(sd_index)); 1410 1411 sdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0), 1412 SD25G_LANE_LANE_05_LN_CFG_BW_1_0, 1413 priv, 1414 SD25G_LANE_LANE_05(sd_index)); 1415 1416 sdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET 1417 (params->cfg_txcal_man_en), 1418 SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, 1419 priv, 1420 SD25G_LANE_LANE_0B(sd_index)); 1421 1422 sdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET 1423 (params->cfg_txcal_shift_code_5_0), 1424 SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, 1425 priv, 1426 SD25G_LANE_LANE_0A(sd_index)); 1427 1428 sdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET 1429 (params->cfg_txcal_valid_sel_3_0), 1430 SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, 1431 priv, 1432 SD25G_LANE_LANE_09(sd_index)); 1433 1434 sdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0), 1435 SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, 1436 priv, 1437 SD25G_LANE_LANE_1A(sd_index)); 1438 1439 sdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0), 1440 SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, 1441 priv, 1442 SD25G_LANE_LANE_1B(sd_index)); 1443 1444 sdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0), 1445 SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, 1446 priv, 1447 SD25G_LANE_LANE_2B(sd_index)); 1448 1449 sdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET 1450 (params->cfg_dis_2ndorder), 1451 SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, 1452 priv, 1453 SD25G_LANE_LANE_2C(sd_index)); 1454 1455 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn), 1456 SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, 1457 priv, 1458 SD25G_LANE_LANE_2E(sd_index)); 1459 1460 sdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET 1461 (params->cfg_itx_ipcml_base_1_0), 1462 SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, 1463 priv, 1464 SD25G_LANE_LANE_00(sd_index)); 1465 1466 sdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET 1467 (params->cfg_rx_reserve_7_0), 1468 SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, 1469 priv, 1470 SD25G_LANE_LANE_44(sd_index)); 1471 1472 sdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET 1473 (params->cfg_rx_reserve_15_8), 1474 SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, 1475 priv, 1476 SD25G_LANE_LANE_45(sd_index)); 1477 1478 sdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) | 1479 SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0), 1480 SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN | 1481 SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, 1482 priv, 1483 SD25G_LANE_LANE_0D(sd_index)); 1484 1485 sdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET 1486 (params->cfg_vga_ctrl_byp_4_0), 1487 SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, 1488 priv, 1489 SD25G_LANE_LANE_21(sd_index)); 1490 1491 sdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET 1492 (params->cfg_eqr_force_3_0), 1493 SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, 1494 priv, 1495 SD25G_LANE_LANE_22(sd_index)); 1496 1497 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET 1498 (params->cfg_eqc_force_3_0) | 1499 SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd), 1500 SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 | 1501 SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, 1502 priv, 1503 SD25G_LANE_LANE_1C(sd_index)); 1504 1505 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET 1506 (params->cfg_sum_setcm_en), 1507 SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, 1508 priv, 1509 SD25G_LANE_LANE_1E(sd_index)); 1510 1511 sdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET 1512 (params->cfg_init_pos_iscan_6_0), 1513 SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, 1514 priv, 1515 SD25G_LANE_LANE_25(sd_index)); 1516 1517 sdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET 1518 (params->cfg_init_pos_ipi_6_0), 1519 SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, 1520 priv, 1521 SD25G_LANE_LANE_26(sd_index)); 1522 1523 sdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd), 1524 SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, 1525 priv, 1526 SD25G_LANE_LANE_18(sd_index)); 1527 1528 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET 1529 (params->cfg_dfedig_m_2_0), 1530 SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, 1531 priv, 1532 SD25G_LANE_LANE_0E(sd_index)); 1533 1534 sdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig), 1535 SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, 1536 priv, 1537 SD25G_LANE_LANE_0E(sd_index)); 1538 1539 sdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) | 1540 SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv), 1541 SD25G_LANE_LANE_40_LN_R_TX_POL_INV | 1542 SD25G_LANE_LANE_40_LN_R_RX_POL_INV, 1543 priv, 1544 SD25G_LANE_LANE_40(sd_index)); 1545 1546 sdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) | 1547 SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en), 1548 SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN | 1549 SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, 1550 priv, 1551 SD25G_LANE_LANE_04(sd_index)); 1552 1553 sdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en), 1554 SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, 1555 priv, 1556 SD25G_LANE_LANE_1E(sd_index)); 1557 1558 sdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en), 1559 SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, 1560 priv, 1561 SD25G_LANE_LANE_19(sd_index)); 1562 1563 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0), 1564 SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, 1565 priv, 1566 SD25G_LANE_LANE_2E(sd_index)); 1567 1568 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1), 1569 SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, 1570 priv, 1571 SD25G_LANE_LANE_2E(sd_index)); 1572 1573 sdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0), 1574 SD_LANE_25G_SD_LANE_CFG_MACRO_RST, 1575 priv, 1576 SD_LANE_25G_SD_LANE_CFG(sd_index)); 1577 1578 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0), 1579 SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, 1580 priv, 1581 SD25G_LANE_LANE_1C(sd_index)); 1582 1583 usleep_range(1000, 2000); 1584 1585 sdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1), 1586 SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, 1587 priv, 1588 SD25G_LANE_LANE_1C(sd_index)); 1589 1590 usleep_range(10000, 20000); 1591 1592 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff), 1593 SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, 1594 priv, 1595 SD25G_LANE_CMU_FF(sd_index)); 1596 1597 value = readl(sdx5_addr(regs, SD25G_LANE_CMU_C0(sd_index))); 1598 value = SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(value); 1599 1600 if (value) { 1601 dev_err(dev, "25G PLL Loss of Lock: 0x%x\n", value); 1602 return -EINVAL; 1603 } 1604 1605 value = readl(sdx5_addr(regs, SD_LANE_25G_SD_LANE_STAT(sd_index))); 1606 value = SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(value); 1607 1608 if (value != 0x1) { 1609 dev_err(dev, "25G PMA Reset failed: 0x%x\n", value); 1610 return -EINVAL; 1611 } 1612 sdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1), 1613 SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, 1614 priv, 1615 SD25G_LANE_CMU_2A(sd_index)); 1616 1617 sdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0), 1618 SD_LANE_25G_SD_SER_RST_SER_RST, 1619 priv, 1620 SD_LANE_25G_SD_SER_RST(sd_index)); 1621 1622 sdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0), 1623 SD_LANE_25G_SD_DES_RST_DES_RST, 1624 priv, 1625 SD_LANE_25G_SD_DES_RST(sd_index)); 1626 1627 sdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0), 1628 SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, 1629 priv, 1630 SD25G_LANE_CMU_FF(sd_index)); 1631 1632 sdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET 1633 (params->cfg_alos_thr_2_0), 1634 SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, 1635 priv, 1636 SD25G_LANE_LANE_2D(sd_index)); 1637 1638 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0), 1639 SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, 1640 priv, 1641 SD25G_LANE_LANE_2E(sd_index)); 1642 1643 sdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0), 1644 SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, 1645 priv, 1646 SD25G_LANE_LANE_2E(sd_index)); 1647 1648 return 0; 1649 } 1650 1651 static void sparx5_sd10g28_reset(void __iomem *regs[], u32 lane_index) 1652 { 1653 /* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */ 1654 sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(1), 1655 SD_LANE_SD_LANE_CFG_EXT_CFG_RST, 1656 sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index))); 1657 1658 usleep_range(1000, 2000); 1659 1660 sdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), 1661 SD_LANE_SD_LANE_CFG_EXT_CFG_RST, 1662 sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index))); 1663 } 1664 1665 static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro, 1666 struct sparx5_sd10g28_params *params) 1667 { 1668 struct sparx5_serdes_private *priv = macro->priv; 1669 void __iomem **regs = priv->regs; 1670 struct device *dev = priv->dev; 1671 u32 lane_index = macro->sidx; 1672 u32 sd_index = macro->stpidx; 1673 void __iomem *sd_inst; 1674 u32 value, cmu_idx; 1675 int err; 1676 1677 /* Do not configure serdes if CMU is not to be configured too */ 1678 if (params->skip_cmu_cfg) 1679 return 0; 1680 1681 cmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx); 1682 err = sparx5_cmu_cfg(priv, cmu_idx); 1683 if (err) 1684 return err; 1685 1686 if (params->is_6g) 1687 sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index); 1688 else 1689 sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, sd_index); 1690 1691 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1), 1692 SD_LANE_SD_LANE_CFG_MACRO_RST, 1693 priv, 1694 SD_LANE_SD_LANE_CFG(lane_index)); 1695 1696 sdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) | 1697 SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) | 1698 SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) | 1699 SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) | 1700 SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0), 1701 SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT | 1702 SD10G_LANE_LANE_93_R_REG_MANUAL | 1703 SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT | 1704 SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT | 1705 SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, 1706 sd_inst, 1707 SD10G_LANE_LANE_93(sd_index)); 1708 1709 sdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) | 1710 SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) | 1711 SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) | 1712 SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1), 1713 SD10G_LANE_LANE_94_R_ISCAN_REG | 1714 SD10G_LANE_LANE_94_R_TXEQ_REG | 1715 SD10G_LANE_LANE_94_R_MISC_REG | 1716 SD10G_LANE_LANE_94_R_SWING_REG, 1717 sd_inst, 1718 SD10G_LANE_LANE_94(sd_index)); 1719 1720 sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1), 1721 SD10G_LANE_LANE_9E_R_RXEQ_REG, 1722 sd_inst, 1723 SD10G_LANE_LANE_9E(sd_index)); 1724 1725 sdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) | 1726 SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) | 1727 SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1), 1728 SD10G_LANE_LANE_A1_R_SSC_FROM_HWT | 1729 SD10G_LANE_LANE_A1_R_CDR_FROM_HWT | 1730 SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, 1731 sd_inst, 1732 SD10G_LANE_LANE_A1(sd_index)); 1733 1734 sdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) | 1735 SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel), 1736 SD_LANE_SD_LANE_CFG_RX_REF_SEL | 1737 SD_LANE_SD_LANE_CFG_TX_REF_SEL, 1738 priv, 1739 SD_LANE_SD_LANE_CFG(lane_index)); 1740 1741 sdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET 1742 (params->cfg_lane_reserve_7_0), 1743 SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, 1744 sd_inst, 1745 SD10G_LANE_LANE_40(sd_index)); 1746 1747 sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET 1748 (params->cfg_ssc_rtl_clk_sel), 1749 SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, 1750 sd_inst, 1751 SD10G_LANE_LANE_50(sd_index)); 1752 1753 sdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET 1754 (params->cfg_txrate_1_0) | 1755 SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET 1756 (params->cfg_rxrate_1_0), 1757 SD10G_LANE_LANE_35_CFG_TXRATE_1_0 | 1758 SD10G_LANE_LANE_35_CFG_RXRATE_1_0, 1759 sd_inst, 1760 SD10G_LANE_LANE_35(sd_index)); 1761 1762 sdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET 1763 (params->r_d_width_ctrl_2_0), 1764 SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, 1765 sd_inst, 1766 SD10G_LANE_LANE_94(sd_index)); 1767 1768 sdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET 1769 (params->cfg_pma_tx_ck_bitwidth_2_0), 1770 SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, 1771 sd_inst, 1772 SD10G_LANE_LANE_01(sd_index)); 1773 1774 sdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET 1775 (params->cfg_rxdiv_sel_2_0), 1776 SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, 1777 sd_inst, 1778 SD10G_LANE_LANE_30(sd_index)); 1779 1780 sdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET 1781 (params->r_pcs2pma_phymode_4_0), 1782 SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, 1783 sd_inst, 1784 SD10G_LANE_LANE_A2(sd_index)); 1785 1786 sdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en), 1787 SD10G_LANE_LANE_13_CFG_CDRCK_EN, 1788 sd_inst, 1789 SD10G_LANE_LANE_13(sd_index)); 1790 1791 sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET 1792 (params->cfg_dfeck_en) | 1793 SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) | 1794 SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET 1795 (params->cfg_erramp_pd), 1796 SD10G_LANE_LANE_23_CFG_DFECK_EN | 1797 SD10G_LANE_LANE_23_CFG_DFE_PD | 1798 SD10G_LANE_LANE_23_CFG_ERRAMP_PD, 1799 sd_inst, 1800 SD10G_LANE_LANE_23(sd_index)); 1801 1802 sdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET 1803 (params->cfg_dfetap_en_5_1), 1804 SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, 1805 sd_inst, 1806 SD10G_LANE_LANE_22(sd_index)); 1807 1808 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET 1809 (params->cfg_pi_DFE_en), 1810 SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, 1811 sd_inst, 1812 SD10G_LANE_LANE_1A(sd_index)); 1813 1814 sdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) | 1815 SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) | 1816 SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) | 1817 SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET 1818 (params->cfg_tap_adv_3_0), 1819 SD10G_LANE_LANE_02_CFG_EN_ADV | 1820 SD10G_LANE_LANE_02_CFG_EN_MAIN | 1821 SD10G_LANE_LANE_02_CFG_EN_DLY | 1822 SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, 1823 sd_inst, 1824 SD10G_LANE_LANE_02(sd_index)); 1825 1826 sdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main), 1827 SD10G_LANE_LANE_03_CFG_TAP_MAIN, 1828 sd_inst, 1829 SD10G_LANE_LANE_03(sd_index)); 1830 1831 sdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET 1832 (params->cfg_tap_dly_4_0), 1833 SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, 1834 sd_inst, 1835 SD10G_LANE_LANE_04(sd_index)); 1836 1837 sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET 1838 (params->cfg_vga_ctrl_3_0), 1839 SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, 1840 sd_inst, 1841 SD10G_LANE_LANE_2F(sd_index)); 1842 1843 sdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET 1844 (params->cfg_vga_cp_2_0), 1845 SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, 1846 sd_inst, 1847 SD10G_LANE_LANE_2F(sd_index)); 1848 1849 sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET 1850 (params->cfg_eq_res_3_0), 1851 SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, 1852 sd_inst, 1853 SD10G_LANE_LANE_0B(sd_index)); 1854 1855 sdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp), 1856 SD10G_LANE_LANE_0D_CFG_EQR_BYP, 1857 sd_inst, 1858 SD10G_LANE_LANE_0D(sd_index)); 1859 1860 sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET 1861 (params->cfg_eq_c_force_3_0) | 1862 SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET 1863 (params->cfg_sum_setcm_en), 1864 SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 | 1865 SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, 1866 sd_inst, 1867 SD10G_LANE_LANE_0E(sd_index)); 1868 1869 sdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET 1870 (params->cfg_en_dfedig), 1871 SD10G_LANE_LANE_23_CFG_EN_DFEDIG, 1872 sd_inst, 1873 SD10G_LANE_LANE_23(sd_index)); 1874 1875 sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET 1876 (params->cfg_en_preemph), 1877 SD10G_LANE_LANE_06_CFG_EN_PREEMPH, 1878 sd_inst, 1879 SD10G_LANE_LANE_06(sd_index)); 1880 1881 sdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET 1882 (params->cfg_itx_ippreemp_base_1_0) | 1883 SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET 1884 (params->cfg_itx_ipdriver_base_2_0), 1885 SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 | 1886 SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, 1887 sd_inst, 1888 SD10G_LANE_LANE_33(sd_index)); 1889 1890 sdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET 1891 (params->cfg_ibias_tune_reserve_5_0), 1892 SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, 1893 sd_inst, 1894 SD10G_LANE_LANE_52(sd_index)); 1895 1896 sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET 1897 (params->cfg_txswing_half), 1898 SD10G_LANE_LANE_37_CFG_TXSWING_HALF, 1899 sd_inst, 1900 SD10G_LANE_LANE_37(sd_index)); 1901 1902 sdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET 1903 (params->cfg_dis_2nd_order), 1904 SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, 1905 sd_inst, 1906 SD10G_LANE_LANE_3C(sd_index)); 1907 1908 sdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET 1909 (params->cfg_rx_ssc_lh), 1910 SD10G_LANE_LANE_39_CFG_RX_SSC_LH, 1911 sd_inst, 1912 SD10G_LANE_LANE_39(sd_index)); 1913 1914 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET 1915 (params->cfg_pi_floop_steps_1_0), 1916 SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, 1917 sd_inst, 1918 SD10G_LANE_LANE_1A(sd_index)); 1919 1920 sdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET 1921 (params->cfg_pi_ext_dac_23_16), 1922 SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, 1923 sd_inst, 1924 SD10G_LANE_LANE_16(sd_index)); 1925 1926 sdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET 1927 (params->cfg_pi_ext_dac_15_8), 1928 SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, 1929 sd_inst, 1930 SD10G_LANE_LANE_15(sd_index)); 1931 1932 sdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET 1933 (params->cfg_iscan_ext_dac_7_0), 1934 SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, 1935 sd_inst, 1936 SD10G_LANE_LANE_26(sd_index)); 1937 1938 sdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET 1939 (params->cfg_cdr_kf_gen1_2_0), 1940 SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, 1941 sd_inst, 1942 SD10G_LANE_LANE_42(sd_index)); 1943 1944 sdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET 1945 (params->r_cdr_m_gen1_7_0), 1946 SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, 1947 sd_inst, 1948 SD10G_LANE_LANE_0F(sd_index)); 1949 1950 sdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET 1951 (params->cfg_pi_bw_gen1_3_0), 1952 SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, 1953 sd_inst, 1954 SD10G_LANE_LANE_24(sd_index)); 1955 1956 sdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET 1957 (params->cfg_pi_ext_dac_7_0), 1958 SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, 1959 sd_inst, 1960 SD10G_LANE_LANE_14(sd_index)); 1961 1962 sdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps), 1963 SD10G_LANE_LANE_1A_CFG_PI_STEPS, 1964 sd_inst, 1965 SD10G_LANE_LANE_1A(sd_index)); 1966 1967 sdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET 1968 (params->cfg_mp_max_3_0), 1969 SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, 1970 sd_inst, 1971 SD10G_LANE_LANE_3A(sd_index)); 1972 1973 sdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET 1974 (params->cfg_rstn_dfedig), 1975 SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, 1976 sd_inst, 1977 SD10G_LANE_LANE_31(sd_index)); 1978 1979 sdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET 1980 (params->cfg_alos_thr_3_0), 1981 SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, 1982 sd_inst, 1983 SD10G_LANE_LANE_48(sd_index)); 1984 1985 sdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET 1986 (params->cfg_predrv_slewrate_1_0), 1987 SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, 1988 sd_inst, 1989 SD10G_LANE_LANE_36(sd_index)); 1990 1991 sdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET 1992 (params->cfg_itx_ipcml_base_1_0), 1993 SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, 1994 sd_inst, 1995 SD10G_LANE_LANE_32(sd_index)); 1996 1997 sdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET 1998 (params->cfg_ip_pre_base_1_0), 1999 SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, 2000 sd_inst, 2001 SD10G_LANE_LANE_37(sd_index)); 2002 2003 sdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET 2004 (params->cfg_lane_reserve_15_8), 2005 SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, 2006 sd_inst, 2007 SD10G_LANE_LANE_41(sd_index)); 2008 2009 sdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET 2010 (params->r_en_auto_cdr_rstn), 2011 SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, 2012 sd_inst, 2013 SD10G_LANE_LANE_9E(sd_index)); 2014 2015 sdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET 2016 (params->cfg_oscal_afe) | 2017 SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET 2018 (params->cfg_pd_osdac_afe), 2019 SD10G_LANE_LANE_0C_CFG_OSCAL_AFE | 2020 SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, 2021 sd_inst, 2022 SD10G_LANE_LANE_0C(sd_index)); 2023 2024 sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET 2025 (params->cfg_resetb_oscal_afe[0]), 2026 SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, 2027 sd_inst, 2028 SD10G_LANE_LANE_0B(sd_index)); 2029 2030 sdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET 2031 (params->cfg_resetb_oscal_afe[1]), 2032 SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, 2033 sd_inst, 2034 SD10G_LANE_LANE_0B(sd_index)); 2035 2036 sdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET 2037 (params->r_tx_pol_inv) | 2038 SD10G_LANE_LANE_83_R_RX_POL_INV_SET 2039 (params->r_rx_pol_inv), 2040 SD10G_LANE_LANE_83_R_TX_POL_INV | 2041 SD10G_LANE_LANE_83_R_RX_POL_INV, 2042 sd_inst, 2043 SD10G_LANE_LANE_83(sd_index)); 2044 2045 sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET 2046 (params->cfg_rx2tx_lp_en) | 2047 SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET 2048 (params->cfg_tx2rx_lp_en), 2049 SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN | 2050 SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, 2051 sd_inst, 2052 SD10G_LANE_LANE_06(sd_index)); 2053 2054 sdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) | 2055 SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en), 2056 SD10G_LANE_LANE_0E_CFG_RXLB_EN | 2057 SD10G_LANE_LANE_0E_CFG_TXLB_EN, 2058 sd_inst, 2059 SD10G_LANE_LANE_0E(sd_index)); 2060 2061 sdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0), 2062 SD_LANE_SD_LANE_CFG_MACRO_RST, 2063 priv, 2064 SD_LANE_SD_LANE_CFG(lane_index)); 2065 2066 sdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1), 2067 SD10G_LANE_LANE_50_CFG_SSC_RESETB, 2068 sd_inst, 2069 SD10G_LANE_LANE_50(sd_index)); 2070 2071 sdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1), 2072 SD10G_LANE_LANE_50_CFG_SSC_RESETB, 2073 priv, 2074 SD10G_LANE_LANE_50(sd_index)); 2075 2076 sdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100), 2077 SD_LANE_MISC_SD_125_RST_DIS, 2078 priv, 2079 SD_LANE_MISC(lane_index)); 2080 2081 sdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100), 2082 SD_LANE_MISC_RX_ENA, 2083 priv, 2084 SD_LANE_MISC(lane_index)); 2085 2086 sdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100), 2087 SD_LANE_MISC_MUX_ENA, 2088 priv, 2089 SD_LANE_MISC(lane_index)); 2090 2091 usleep_range(3000, 6000); 2092 2093 value = readl(sdx5_addr(regs, SD_LANE_SD_LANE_STAT(lane_index))); 2094 value = SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(value); 2095 if (value != 1) { 2096 dev_err(dev, "10G PMA Reset failed: 0x%x\n", value); 2097 return -EINVAL; 2098 } 2099 2100 sdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0), 2101 SD_LANE_SD_SER_RST_SER_RST, 2102 priv, 2103 SD_LANE_SD_SER_RST(lane_index)); 2104 2105 sdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0), 2106 SD_LANE_SD_DES_RST_DES_RST, 2107 priv, 2108 SD_LANE_SD_DES_RST(lane_index)); 2109 2110 return 0; 2111 } 2112 2113 static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset) 2114 { 2115 struct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media]; 2116 struct sparx5_sd25g28_mode_preset mode; 2117 struct sparx5_sd25g28_args args = { 2118 .rxinvert = 1, 2119 .txinvert = 0, 2120 .txswing = 240, 2121 .com_pll_reserve = 0xf, 2122 .reg_rst = reset, 2123 }; 2124 struct sparx5_sd25g28_params params; 2125 int err; 2126 2127 err = sparx5_sd10g25_get_mode_preset(macro, &mode); 2128 if (err) 2129 return err; 2130 sparx5_sd25g28_get_params(macro, &media, &mode, &args, ¶ms); 2131 sparx5_sd25g28_reset(macro->priv->regs, ¶ms, macro->stpidx); 2132 return sparx5_sd25g28_apply_params(macro, ¶ms); 2133 } 2134 2135 static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset) 2136 { 2137 struct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media]; 2138 struct sparx5_sd10g28_mode_preset mode; 2139 struct sparx5_sd10g28_params params; 2140 struct sparx5_sd10g28_args args = { 2141 .is_6g = (macro->serdestype == SPX5_SDT_6G), 2142 .txinvert = 0, 2143 .rxinvert = 1, 2144 .txswing = 240, 2145 .reg_rst = reset, 2146 .skip_cmu_cfg = reset, 2147 }; 2148 int err; 2149 2150 err = sparx5_sd10g28_get_mode_preset(macro, &mode, &args); 2151 if (err) 2152 return err; 2153 sparx5_sd10g28_get_params(macro, &media, &mode, &args, ¶ms); 2154 sparx5_sd10g28_reset(macro->priv->regs, macro->sidx); 2155 return sparx5_sd10g28_apply_params(macro, ¶ms); 2156 } 2157 2158 /* Power down serdes TX driver */ 2159 static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn) 2160 { 2161 struct sparx5_serdes_private *priv = macro->priv; 2162 void __iomem *sd_inst, *sd_lane_inst; 2163 2164 if (macro->serdestype == SPX5_SDT_6G) 2165 sd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, macro->stpidx); 2166 else if (macro->serdestype == SPX5_SDT_10G) 2167 sd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, macro->stpidx); 2168 else 2169 sd_inst = sdx5_inst_get(priv, TARGET_SD25G_LANE, macro->stpidx); 2170 2171 if (macro->serdestype == SPX5_SDT_25G) { 2172 sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE_25G, 2173 macro->stpidx); 2174 /* Take serdes out of reset */ 2175 sdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0), 2176 SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, sd_lane_inst, 2177 SD_LANE_25G_SD_LANE_CFG(0)); 2178 2179 /* Configure optimal settings for quiet mode */ 2180 sdx5_inst_rmw(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL), 2181 SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, 2182 sd_lane_inst, SD_LANE_25G_QUIET_MODE_6G(0)); 2183 2184 sdx5_inst_rmw(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(pwdn), 2185 SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, 2186 sd_inst, 2187 SD25G_LANE_LANE_04(0)); 2188 } else { 2189 /* 6G and 10G */ 2190 sd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE, macro->sidx); 2191 2192 /* Take serdes out of reset */ 2193 sdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0), 2194 SD_LANE_SD_LANE_CFG_EXT_CFG_RST, sd_lane_inst, 2195 SD_LANE_SD_LANE_CFG(0)); 2196 2197 /* Configure optimal settings for quiet mode */ 2198 sdx5_inst_rmw(SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL), 2199 SD_LANE_QUIET_MODE_6G_QUIET_MODE, sd_lane_inst, 2200 SD_LANE_QUIET_MODE_6G(0)); 2201 2202 sdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(pwdn), 2203 SD10G_LANE_LANE_06_CFG_PD_DRIVER, 2204 sd_inst, 2205 SD10G_LANE_LANE_06(0)); 2206 } 2207 return 0; 2208 } 2209 2210 static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro) 2211 { 2212 struct sparx5_serdes_private *priv = macro->priv; 2213 2214 /* Clock is auto-detected in 100Base-FX mode on lan969x */ 2215 if (priv->data->type == SPX5_TARGET_LAN969X) 2216 return 0; 2217 2218 if (macro->serdesmode == SPX5_SD_MODE_100FX) { 2219 u32 freq = priv->coreclock == 250000000 ? 2 : 2220 priv->coreclock == 500000000 ? 1 : 0; 2221 2222 sdx5_rmw(SD_LANE_MISC_CORE_CLK_FREQ_SET(freq), 2223 SD_LANE_MISC_CORE_CLK_FREQ, 2224 priv, 2225 SD_LANE_MISC(macro->sidx)); 2226 } 2227 return 0; 2228 } 2229 2230 static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed) 2231 { 2232 switch (portmode) { 2233 case PHY_INTERFACE_MODE_1000BASEX: 2234 case PHY_INTERFACE_MODE_2500BASEX: 2235 if (speed == SPEED_2500) 2236 return SPX5_SD_MODE_2G5; 2237 if (speed == SPEED_100) 2238 return SPX5_SD_MODE_100FX; 2239 return SPX5_SD_MODE_1000BASEX; 2240 case PHY_INTERFACE_MODE_SGMII: 2241 /* The same Serdes mode is used for both SGMII and 1000BaseX */ 2242 return SPX5_SD_MODE_1000BASEX; 2243 case PHY_INTERFACE_MODE_QSGMII: 2244 return SPX5_SD_MODE_QSGMII; 2245 case PHY_INTERFACE_MODE_10GBASER: 2246 return SPX5_SD_MODE_SFI; 2247 default: 2248 return -EINVAL; 2249 } 2250 } 2251 2252 static int sparx5_serdes_config(struct sparx5_serdes_macro *macro) 2253 { 2254 struct device *dev = macro->priv->dev; 2255 int serdesmode; 2256 int err; 2257 2258 serdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed); 2259 if (serdesmode < 0) { 2260 dev_err(dev, "SerDes %u, interface not supported: %s\n", 2261 macro->sidx, 2262 phy_modes(macro->portmode)); 2263 return serdesmode; 2264 } 2265 macro->serdesmode = serdesmode; 2266 2267 sparx5_serdes_clock_config(macro); 2268 2269 if (macro->serdestype == SPX5_SDT_25G) 2270 err = sparx5_sd25g28_config(macro, false); 2271 else 2272 err = sparx5_sd10g28_config(macro, false); 2273 if (err) { 2274 dev_err(dev, "SerDes %u, config error: %d\n", 2275 macro->sidx, err); 2276 } 2277 return err; 2278 } 2279 2280 static int sparx5_serdes_power_on(struct phy *phy) 2281 { 2282 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); 2283 2284 return sparx5_serdes_power_save(macro, false); 2285 } 2286 2287 static int sparx5_serdes_power_off(struct phy *phy) 2288 { 2289 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); 2290 2291 return sparx5_serdes_power_save(macro, true); 2292 } 2293 2294 static int sparx5_serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2295 { 2296 struct sparx5_serdes_macro *macro; 2297 2298 if (mode != PHY_MODE_ETHERNET) 2299 return -EINVAL; 2300 2301 switch (submode) { 2302 case PHY_INTERFACE_MODE_1000BASEX: 2303 case PHY_INTERFACE_MODE_2500BASEX: 2304 case PHY_INTERFACE_MODE_SGMII: 2305 case PHY_INTERFACE_MODE_QSGMII: 2306 case PHY_INTERFACE_MODE_10GBASER: 2307 macro = phy_get_drvdata(phy); 2308 macro->portmode = submode; 2309 sparx5_serdes_config(macro); 2310 return 0; 2311 default: 2312 return -EINVAL; 2313 } 2314 } 2315 2316 static int sparx5_serdes_set_media(struct phy *phy, enum phy_media media) 2317 { 2318 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); 2319 2320 if (media != macro->media) { 2321 macro->media = media; 2322 if (macro->serdesmode != SPX5_SD_MODE_NONE) 2323 sparx5_serdes_config(macro); 2324 } 2325 return 0; 2326 } 2327 2328 static int sparx5_serdes_set_speed(struct phy *phy, int speed) 2329 { 2330 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); 2331 2332 if (macro->priv->data->type == SPX5_TARGET_SPARX5) { 2333 if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) 2334 return -EINVAL; 2335 if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) 2336 return -EINVAL; 2337 } 2338 if (speed != macro->speed) { 2339 macro->speed = speed; 2340 if (macro->serdesmode != SPX5_SD_MODE_NONE) 2341 sparx5_serdes_config(macro); 2342 } 2343 return 0; 2344 } 2345 2346 static int sparx5_serdes_reset(struct phy *phy) 2347 { 2348 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); 2349 int err; 2350 2351 if (macro->serdestype == SPX5_SDT_25G) 2352 err = sparx5_sd25g28_config(macro, true); 2353 else 2354 err = sparx5_sd10g28_config(macro, true); 2355 if (err) { 2356 dev_err(&phy->dev, "SerDes %u, reset error: %d\n", 2357 macro->sidx, err); 2358 } 2359 return err; 2360 } 2361 2362 static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode, 2363 int submode, 2364 union phy_configure_opts *opts) 2365 { 2366 struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); 2367 2368 if (mode != PHY_MODE_ETHERNET) 2369 return -EINVAL; 2370 2371 if (macro->speed == 0) 2372 return -EINVAL; 2373 2374 if (macro->priv->data->type == SPX5_TARGET_SPARX5) { 2375 if (macro->sidx < SPX5_SERDES_10G_START && 2376 macro->speed > SPEED_5000) 2377 return -EINVAL; 2378 if (macro->sidx < SPX5_SERDES_25G_START && 2379 macro->speed > SPEED_10000) 2380 return -EINVAL; 2381 } 2382 switch (submode) { 2383 case PHY_INTERFACE_MODE_1000BASEX: 2384 if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ 2385 macro->speed != SPEED_1000) 2386 return -EINVAL; 2387 break; 2388 case PHY_INTERFACE_MODE_SGMII: 2389 case PHY_INTERFACE_MODE_2500BASEX: 2390 case PHY_INTERFACE_MODE_QSGMII: 2391 if (macro->speed >= SPEED_5000) 2392 return -EINVAL; 2393 break; 2394 case PHY_INTERFACE_MODE_10GBASER: 2395 if (macro->speed < SPEED_5000) 2396 return -EINVAL; 2397 break; 2398 default: 2399 return -EINVAL; 2400 } 2401 return 0; 2402 } 2403 2404 static const struct phy_ops sparx5_serdes_ops = { 2405 .power_on = sparx5_serdes_power_on, 2406 .power_off = sparx5_serdes_power_off, 2407 .set_mode = sparx5_serdes_set_mode, 2408 .set_media = sparx5_serdes_set_media, 2409 .set_speed = sparx5_serdes_set_speed, 2410 .reset = sparx5_serdes_reset, 2411 .validate = sparx5_serdes_validate, 2412 .owner = THIS_MODULE, 2413 }; 2414 2415 static void sparx5_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx) 2416 { 2417 if (sidx < SPX5_SERDES_10G_START) { 2418 macro->serdestype = SPX5_SDT_6G; 2419 macro->stpidx = macro->sidx; 2420 } else if (sidx < SPX5_SERDES_25G_START) { 2421 macro->serdestype = SPX5_SDT_10G; 2422 macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; 2423 } else { 2424 macro->serdestype = SPX5_SDT_25G; 2425 macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; 2426 } 2427 } 2428 2429 static void lan969x_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx) 2430 { 2431 macro->serdestype = SPX5_SDT_10G; 2432 macro->stpidx = macro->sidx; 2433 } 2434 2435 static int sparx5_phy_create(struct sparx5_serdes_private *priv, 2436 int idx, struct phy **phy) 2437 { 2438 struct sparx5_serdes_macro *macro; 2439 2440 *phy = devm_phy_create(priv->dev, NULL, &sparx5_serdes_ops); 2441 if (IS_ERR(*phy)) 2442 return PTR_ERR(*phy); 2443 2444 macro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL); 2445 if (!macro) 2446 return -ENOMEM; 2447 2448 macro->sidx = idx; 2449 macro->priv = priv; 2450 macro->speed = SPEED_UNKNOWN; 2451 2452 priv->data->ops.serdes_type_set(macro, idx); 2453 2454 phy_set_drvdata(*phy, macro); 2455 2456 /* Power off serdes by default */ 2457 sparx5_serdes_power_off(*phy); 2458 2459 return 0; 2460 } 2461 2462 static struct sparx5_serdes_io_resource sparx5_serdes_iomap[] = { 2463 { TARGET_SD_CMU, 0x0 }, /* 0x610808000: sd_cmu_0 */ 2464 { TARGET_SD_CMU + 1, 0x8000 }, /* 0x610810000: sd_cmu_1 */ 2465 { TARGET_SD_CMU + 2, 0x10000 }, /* 0x610818000: sd_cmu_2 */ 2466 { TARGET_SD_CMU + 3, 0x18000 }, /* 0x610820000: sd_cmu_3 */ 2467 { TARGET_SD_CMU + 4, 0x20000 }, /* 0x610828000: sd_cmu_4 */ 2468 { TARGET_SD_CMU + 5, 0x28000 }, /* 0x610830000: sd_cmu_5 */ 2469 { TARGET_SD_CMU + 6, 0x30000 }, /* 0x610838000: sd_cmu_6 */ 2470 { TARGET_SD_CMU + 7, 0x38000 }, /* 0x610840000: sd_cmu_7 */ 2471 { TARGET_SD_CMU + 8, 0x40000 }, /* 0x610848000: sd_cmu_8 */ 2472 { TARGET_SD_CMU_CFG, 0x48000 }, /* 0x610850000: sd_cmu_cfg_0 */ 2473 { TARGET_SD_CMU_CFG + 1, 0x50000 }, /* 0x610858000: sd_cmu_cfg_1 */ 2474 { TARGET_SD_CMU_CFG + 2, 0x58000 }, /* 0x610860000: sd_cmu_cfg_2 */ 2475 { TARGET_SD_CMU_CFG + 3, 0x60000 }, /* 0x610868000: sd_cmu_cfg_3 */ 2476 { TARGET_SD_CMU_CFG + 4, 0x68000 }, /* 0x610870000: sd_cmu_cfg_4 */ 2477 { TARGET_SD_CMU_CFG + 5, 0x70000 }, /* 0x610878000: sd_cmu_cfg_5 */ 2478 { TARGET_SD_CMU_CFG + 6, 0x78000 }, /* 0x610880000: sd_cmu_cfg_6 */ 2479 { TARGET_SD_CMU_CFG + 7, 0x80000 }, /* 0x610888000: sd_cmu_cfg_7 */ 2480 { TARGET_SD_CMU_CFG + 8, 0x88000 }, /* 0x610890000: sd_cmu_cfg_8 */ 2481 { TARGET_SD6G_LANE, 0x90000 }, /* 0x610898000: sd6g_lane_0 */ 2482 { TARGET_SD6G_LANE + 1, 0x98000 }, /* 0x6108a0000: sd6g_lane_1 */ 2483 { TARGET_SD6G_LANE + 2, 0xa0000 }, /* 0x6108a8000: sd6g_lane_2 */ 2484 { TARGET_SD6G_LANE + 3, 0xa8000 }, /* 0x6108b0000: sd6g_lane_3 */ 2485 { TARGET_SD6G_LANE + 4, 0xb0000 }, /* 0x6108b8000: sd6g_lane_4 */ 2486 { TARGET_SD6G_LANE + 5, 0xb8000 }, /* 0x6108c0000: sd6g_lane_5 */ 2487 { TARGET_SD6G_LANE + 6, 0xc0000 }, /* 0x6108c8000: sd6g_lane_6 */ 2488 { TARGET_SD6G_LANE + 7, 0xc8000 }, /* 0x6108d0000: sd6g_lane_7 */ 2489 { TARGET_SD6G_LANE + 8, 0xd0000 }, /* 0x6108d8000: sd6g_lane_8 */ 2490 { TARGET_SD6G_LANE + 9, 0xd8000 }, /* 0x6108e0000: sd6g_lane_9 */ 2491 { TARGET_SD6G_LANE + 10, 0xe0000 }, /* 0x6108e8000: sd6g_lane_10 */ 2492 { TARGET_SD6G_LANE + 11, 0xe8000 }, /* 0x6108f0000: sd6g_lane_11 */ 2493 { TARGET_SD6G_LANE + 12, 0xf0000 }, /* 0x6108f8000: sd6g_lane_12 */ 2494 { TARGET_SD10G_LANE, 0xf8000 }, /* 0x610900000: sd10g_lane_0 */ 2495 { TARGET_SD10G_LANE + 1, 0x100000 }, /* 0x610908000: sd10g_lane_1 */ 2496 { TARGET_SD10G_LANE + 2, 0x108000 }, /* 0x610910000: sd10g_lane_2 */ 2497 { TARGET_SD10G_LANE + 3, 0x110000 }, /* 0x610918000: sd10g_lane_3 */ 2498 { TARGET_SD_LANE, 0x1a0000 }, /* 0x6109a8000: sd_lane_0 */ 2499 { TARGET_SD_LANE + 1, 0x1a8000 }, /* 0x6109b0000: sd_lane_1 */ 2500 { TARGET_SD_LANE + 2, 0x1b0000 }, /* 0x6109b8000: sd_lane_2 */ 2501 { TARGET_SD_LANE + 3, 0x1b8000 }, /* 0x6109c0000: sd_lane_3 */ 2502 { TARGET_SD_LANE + 4, 0x1c0000 }, /* 0x6109c8000: sd_lane_4 */ 2503 { TARGET_SD_LANE + 5, 0x1c8000 }, /* 0x6109d0000: sd_lane_5 */ 2504 { TARGET_SD_LANE + 6, 0x1d0000 }, /* 0x6109d8000: sd_lane_6 */ 2505 { TARGET_SD_LANE + 7, 0x1d8000 }, /* 0x6109e0000: sd_lane_7 */ 2506 { TARGET_SD_LANE + 8, 0x1e0000 }, /* 0x6109e8000: sd_lane_8 */ 2507 { TARGET_SD_LANE + 9, 0x1e8000 }, /* 0x6109f0000: sd_lane_9 */ 2508 { TARGET_SD_LANE + 10, 0x1f0000 }, /* 0x6109f8000: sd_lane_10 */ 2509 { TARGET_SD_LANE + 11, 0x1f8000 }, /* 0x610a00000: sd_lane_11 */ 2510 { TARGET_SD_LANE + 12, 0x200000 }, /* 0x610a08000: sd_lane_12 */ 2511 { TARGET_SD_LANE + 13, 0x208000 }, /* 0x610a10000: sd_lane_13 */ 2512 { TARGET_SD_LANE + 14, 0x210000 }, /* 0x610a18000: sd_lane_14 */ 2513 { TARGET_SD_LANE + 15, 0x218000 }, /* 0x610a20000: sd_lane_15 */ 2514 { TARGET_SD_LANE + 16, 0x220000 }, /* 0x610a28000: sd_lane_16 */ 2515 { TARGET_SD_CMU + 9, 0x400000 }, /* 0x610c08000: sd_cmu_9 */ 2516 { TARGET_SD_CMU + 10, 0x408000 }, /* 0x610c10000: sd_cmu_10 */ 2517 { TARGET_SD_CMU + 11, 0x410000 }, /* 0x610c18000: sd_cmu_11 */ 2518 { TARGET_SD_CMU + 12, 0x418000 }, /* 0x610c20000: sd_cmu_12 */ 2519 { TARGET_SD_CMU + 13, 0x420000 }, /* 0x610c28000: sd_cmu_13 */ 2520 { TARGET_SD_CMU_CFG + 9, 0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */ 2521 { TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */ 2522 { TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */ 2523 { TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */ 2524 { TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */ 2525 { TARGET_SD10G_LANE + 4, 0x450000 }, /* 0x610c58000: sd10g_lane_4 */ 2526 { TARGET_SD10G_LANE + 5, 0x458000 }, /* 0x610c60000: sd10g_lane_5 */ 2527 { TARGET_SD10G_LANE + 6, 0x460000 }, /* 0x610c68000: sd10g_lane_6 */ 2528 { TARGET_SD10G_LANE + 7, 0x468000 }, /* 0x610c70000: sd10g_lane_7 */ 2529 { TARGET_SD10G_LANE + 8, 0x470000 }, /* 0x610c78000: sd10g_lane_8 */ 2530 { TARGET_SD10G_LANE + 9, 0x478000 }, /* 0x610c80000: sd10g_lane_9 */ 2531 { TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */ 2532 { TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */ 2533 { TARGET_SD25G_LANE, 0x490000 }, /* 0x610c98000: sd25g_lane_0 */ 2534 { TARGET_SD25G_LANE + 1, 0x498000 }, /* 0x610ca0000: sd25g_lane_1 */ 2535 { TARGET_SD25G_LANE + 2, 0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */ 2536 { TARGET_SD25G_LANE + 3, 0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */ 2537 { TARGET_SD25G_LANE + 4, 0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */ 2538 { TARGET_SD25G_LANE + 5, 0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */ 2539 { TARGET_SD25G_LANE + 6, 0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */ 2540 { TARGET_SD25G_LANE + 7, 0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */ 2541 { TARGET_SD_LANE + 17, 0x550000 }, /* 0x610d58000: sd_lane_17 */ 2542 { TARGET_SD_LANE + 18, 0x558000 }, /* 0x610d60000: sd_lane_18 */ 2543 { TARGET_SD_LANE + 19, 0x560000 }, /* 0x610d68000: sd_lane_19 */ 2544 { TARGET_SD_LANE + 20, 0x568000 }, /* 0x610d70000: sd_lane_20 */ 2545 { TARGET_SD_LANE + 21, 0x570000 }, /* 0x610d78000: sd_lane_21 */ 2546 { TARGET_SD_LANE + 22, 0x578000 }, /* 0x610d80000: sd_lane_22 */ 2547 { TARGET_SD_LANE + 23, 0x580000 }, /* 0x610d88000: sd_lane_23 */ 2548 { TARGET_SD_LANE + 24, 0x588000 }, /* 0x610d90000: sd_lane_24 */ 2549 { TARGET_SD_LANE_25G, 0x590000 }, /* 0x610d98000: sd_lane_25g_25 */ 2550 { TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */ 2551 { TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */ 2552 { TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */ 2553 { TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */ 2554 { TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */ 2555 { TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */ 2556 { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ 2557 }; 2558 2559 static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] = { 2560 { TARGET_SD_CMU, 0x0 }, /* 0xe3410000 */ 2561 { TARGET_SD_CMU + 1, 0x8000 }, /* 0xe3418000 */ 2562 { TARGET_SD_CMU + 2, 0x10000 }, /* 0xe3420000 */ 2563 { TARGET_SD_CMU + 3, 0x18000 }, /* 0xe3428000 */ 2564 { TARGET_SD_CMU + 4, 0x20000 }, /* 0xe3430000 */ 2565 { TARGET_SD_CMU + 5, 0x28000 }, /* 0xe3438000 */ 2566 { TARGET_SD_CMU_CFG, 0x30000 }, /* 0xe3440000 */ 2567 { TARGET_SD_CMU_CFG + 1, 0x38000 }, /* 0xe3448000 */ 2568 { TARGET_SD_CMU_CFG + 2, 0x40000 }, /* 0xe3450000 */ 2569 { TARGET_SD_CMU_CFG + 3, 0x48000 }, /* 0xe3458000 */ 2570 { TARGET_SD_CMU_CFG + 4, 0x50000 }, /* 0xe3460000 */ 2571 { TARGET_SD_CMU_CFG + 5, 0x58000 }, /* 0xe3468000 */ 2572 { TARGET_SD10G_LANE, 0x60000 }, /* 0xe3470000 */ 2573 { TARGET_SD10G_LANE + 1, 0x68000 }, /* 0xe3478000 */ 2574 { TARGET_SD10G_LANE + 2, 0x70000 }, /* 0xe3480000 */ 2575 { TARGET_SD10G_LANE + 3, 0x78000 }, /* 0xe3488000 */ 2576 { TARGET_SD10G_LANE + 4, 0x80000 }, /* 0xe3490000 */ 2577 { TARGET_SD10G_LANE + 5, 0x88000 }, /* 0xe3498000 */ 2578 { TARGET_SD10G_LANE + 6, 0x90000 }, /* 0xe34a0000 */ 2579 { TARGET_SD10G_LANE + 7, 0x98000 }, /* 0xe34a8000 */ 2580 { TARGET_SD10G_LANE + 8, 0xa0000 }, /* 0xe34b0000 */ 2581 { TARGET_SD10G_LANE + 9, 0xa8000 }, /* 0xe34b8000 */ 2582 { TARGET_SD_LANE, 0x100000 }, /* 0xe3510000 */ 2583 { TARGET_SD_LANE + 1, 0x108000 }, /* 0xe3518000 */ 2584 { TARGET_SD_LANE + 2, 0x110000 }, /* 0xe3520000 */ 2585 { TARGET_SD_LANE + 3, 0x118000 }, /* 0xe3528000 */ 2586 { TARGET_SD_LANE + 4, 0x120000 }, /* 0xe3530000 */ 2587 { TARGET_SD_LANE + 5, 0x128000 }, /* 0xe3538000 */ 2588 { TARGET_SD_LANE + 6, 0x130000 }, /* 0xe3540000 */ 2589 { TARGET_SD_LANE + 7, 0x138000 }, /* 0xe3548000 */ 2590 { TARGET_SD_LANE + 8, 0x140000 }, /* 0xe3550000 */ 2591 { TARGET_SD_LANE + 9, 0x148000 }, /* 0xe3558000 */ 2592 }; 2593 2594 static const struct sparx5_serdes_match_data sparx5_desc = { 2595 .type = SPX5_TARGET_SPARX5, 2596 .iomap = sparx5_serdes_iomap, 2597 .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), 2598 .tsize = sparx5_serdes_tsize, 2599 .consts = { 2600 .sd_max = 33, 2601 .cmu_max = 14, 2602 }, 2603 .ops = { 2604 .serdes_type_set = &sparx5_serdes_type_set, 2605 .serdes_cmu_get = &sparx5_serdes_cmu_get, 2606 }, 2607 }; 2608 2609 static const struct sparx5_serdes_match_data lan969x_desc = { 2610 .type = SPX5_TARGET_LAN969X, 2611 .iomap = lan969x_serdes_iomap, 2612 .iomap_size = ARRAY_SIZE(lan969x_serdes_iomap), 2613 .tsize = lan969x_serdes_tsize, 2614 .consts = { 2615 .sd_max = 10, 2616 .cmu_max = 6, 2617 }, 2618 .ops = { 2619 .serdes_type_set = &lan969x_serdes_type_set, 2620 .serdes_cmu_get = &lan969x_serdes_cmu_get, 2621 } 2622 }; 2623 2624 /* Client lookup function, uses serdes index */ 2625 static struct phy *sparx5_serdes_xlate(struct device *dev, 2626 const struct of_phandle_args *args) 2627 { 2628 struct sparx5_serdes_private *priv = dev_get_drvdata(dev); 2629 int idx; 2630 unsigned int sidx; 2631 2632 if (args->args_count != 1) 2633 return ERR_PTR(-EINVAL); 2634 2635 sidx = args->args[0]; 2636 2637 /* Check validity: ERR_PTR(-ENODEV) if not valid */ 2638 for (idx = 0; idx < priv->data->consts.sd_max; idx++) { 2639 struct sparx5_serdes_macro *macro = 2640 phy_get_drvdata(priv->phys[idx]); 2641 2642 if (sidx != macro->sidx) 2643 continue; 2644 2645 return priv->phys[idx]; 2646 } 2647 return ERR_PTR(-ENODEV); 2648 } 2649 2650 static int sparx5_serdes_probe(struct platform_device *pdev) 2651 { 2652 struct device_node *np = pdev->dev.of_node; 2653 struct sparx5_serdes_private *priv; 2654 struct phy_provider *provider; 2655 struct resource *iores; 2656 void __iomem *iomem; 2657 unsigned long clock; 2658 struct clk *clk; 2659 int idx; 2660 int err; 2661 2662 if (!np && !pdev->dev.platform_data) 2663 return -ENODEV; 2664 2665 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2666 if (!priv) 2667 return -ENOMEM; 2668 2669 platform_set_drvdata(pdev, priv); 2670 priv->dev = &pdev->dev; 2671 2672 priv->data = device_get_match_data(priv->dev); 2673 if (!priv->data) 2674 return -EINVAL; 2675 2676 tsize = priv->data->tsize; 2677 2678 /* Get coreclock */ 2679 clk = devm_clk_get(priv->dev, NULL); 2680 if (IS_ERR(clk)) { 2681 dev_err(priv->dev, "Failed to get coreclock\n"); 2682 return PTR_ERR(clk); 2683 } 2684 clock = clk_get_rate(clk); 2685 if (clock == 0) { 2686 dev_err(priv->dev, "Invalid coreclock %lu\n", clock); 2687 return -EINVAL; 2688 } 2689 priv->coreclock = clock; 2690 2691 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2692 if (!iores) { 2693 dev_err(priv->dev, "Invalid resource\n"); 2694 return -EINVAL; 2695 } 2696 iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); 2697 if (!iomem) { 2698 dev_err(priv->dev, "Unable to get serdes registers: %s\n", 2699 iores->name); 2700 return -ENOMEM; 2701 } 2702 for (idx = 0; idx < priv->data->iomap_size; idx++) { 2703 const struct sparx5_serdes_io_resource *iomap = 2704 &priv->data->iomap[idx]; 2705 2706 priv->regs[iomap->id] = iomem + iomap->offset; 2707 } 2708 for (idx = 0; idx < priv->data->consts.sd_max; idx++) { 2709 err = sparx5_phy_create(priv, idx, &priv->phys[idx]); 2710 if (err) 2711 return err; 2712 } 2713 2714 /* Power down all CMU's by default */ 2715 if (priv->data->type == SPX5_TARGET_SPARX5) 2716 sparx5_serdes_cmu_power_off(priv); 2717 2718 provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); 2719 2720 return PTR_ERR_OR_ZERO(provider); 2721 } 2722 2723 static const struct of_device_id sparx5_serdes_match[] = { 2724 { .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc }, 2725 { .compatible = "microchip,lan9691-serdes", .data = &lan969x_desc }, 2726 { } 2727 }; 2728 MODULE_DEVICE_TABLE(of, sparx5_serdes_match); 2729 2730 static struct platform_driver sparx5_serdes_driver = { 2731 .probe = sparx5_serdes_probe, 2732 .driver = { 2733 .name = "sparx5-serdes", 2734 .of_match_table = sparx5_serdes_match, 2735 }, 2736 }; 2737 2738 module_platform_driver(sparx5_serdes_driver); 2739 2740 MODULE_DESCRIPTION("Microchip Sparx5 switch serdes driver"); 2741 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 2742 MODULE_LICENSE("GPL v2"); 2743