xref: /linux/drivers/phy/mediatek/phy-mtk-mipi-dsi.h (revision 702648721db590b3425c31ade294000e18808345)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2019 MediaTek Inc.
4  * Author: Jitao Shi <jitao.shi@mediatek.com>
5  */
6 
7 #ifndef _MTK_MIPI_TX_H
8 #define _MTK_MIPI_TX_H
9 
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/nvmem-consumer.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/slab.h>
19 
20 struct mtk_mipitx_data {
21 	const u32 mppll_preserve;
22 	const struct clk_ops *mipi_tx_clk_ops;
23 	void (*mipi_tx_enable_signal)(struct phy *phy);
24 	void (*mipi_tx_disable_signal)(struct phy *phy);
25 };
26 
27 struct mtk_mipi_tx {
28 	struct device *dev;
29 	void __iomem *regs;
30 	u32 data_rate;
31 	u32 mipitx_drive;
32 	u32 rt_code[5];
33 	const struct mtk_mipitx_data *driver_data;
34 	struct clk_hw pll_hw;
35 	struct clk *pll;
36 };
37 
38 struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw);
39 int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
40 			     unsigned long parent_rate);
41 unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
42 					  unsigned long parent_rate);
43 
44 extern const struct mtk_mipitx_data mt2701_mipitx_data;
45 extern const struct mtk_mipitx_data mt8173_mipitx_data;
46 extern const struct mtk_mipitx_data mt8183_mipitx_data;
47 
48 #endif
49