1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Marvell 4 * 5 * Authors: 6 * Evan Wang <xswang@marvell.com> 7 * Miquèl Raynal <miquel.raynal@bootlin.com> 8 * Pali Rohár <pali@kernel.org> 9 * Marek Behún <kabel@kernel.org> 10 * 11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart. 12 * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org> 13 * and Marek Behún <kabel@kernel.org>. 14 */ 15 16 #include <linux/bitfield.h> 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/phy.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/spinlock.h> 26 27 #define PLL_SET_DELAY_US 600 28 #define COMPHY_PLL_SLEEP 1000 29 #define COMPHY_PLL_TIMEOUT 150000 30 31 /* Comphy lane2 indirect access register offset */ 32 #define COMPHY_LANE2_INDIR_ADDR 0x0 33 #define COMPHY_LANE2_INDIR_DATA 0x4 34 35 /* SATA and USB3 PHY offset compared to SATA PHY */ 36 #define COMPHY_LANE2_REGS_BASE 0x200 37 38 /* 39 * When accessing common PHY lane registers directly, we need to shift by 1, 40 * since the registers are 16-bit. 41 */ 42 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1) 43 44 /* COMPHY registers */ 45 #define COMPHY_POWER_PLL_CTRL 0x01 46 #define PU_IVREF_BIT BIT(15) 47 #define PU_PLL_BIT BIT(14) 48 #define PU_RX_BIT BIT(13) 49 #define PU_TX_BIT BIT(12) 50 #define PU_TX_INTP_BIT BIT(11) 51 #define PU_DFE_BIT BIT(10) 52 #define RESET_DTL_RX_BIT BIT(9) 53 #define PLL_LOCK_BIT BIT(8) 54 #define REF_FREF_SEL_MASK GENMASK(4, 0) 55 #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1) 56 #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) 57 #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4) 58 #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2) 59 #define REF_FREF_SEL_PCIE_USB3_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3) 60 #define COMPHY_MODE_MASK GENMASK(7, 5) 61 #define COMPHY_MODE_SATA FIELD_PREP(COMPHY_MODE_MASK, 0x0) 62 #define COMPHY_MODE_PCIE FIELD_PREP(COMPHY_MODE_MASK, 0x3) 63 #define COMPHY_MODE_SERDES FIELD_PREP(COMPHY_MODE_MASK, 0x4) 64 #define COMPHY_MODE_USB3 FIELD_PREP(COMPHY_MODE_MASK, 0x5) 65 66 #define COMPHY_KVCO_CAL_CTRL 0x02 67 #define USE_MAX_PLL_RATE_BIT BIT(12) 68 #define SPEED_PLL_MASK GENMASK(7, 2) 69 #define SPEED_PLL_VALUE_16 FIELD_PREP(SPEED_PLL_MASK, 0x10) 70 71 #define COMPHY_DIG_LOOPBACK_EN 0x23 72 #define SEL_DATA_WIDTH_MASK GENMASK(11, 10) 73 #define DATA_WIDTH_10BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0) 74 #define DATA_WIDTH_20BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1) 75 #define DATA_WIDTH_40BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2) 76 #define PLL_READY_TX_BIT BIT(4) 77 78 #define COMPHY_SYNC_PATTERN 0x24 79 #define TXD_INVERT_BIT BIT(10) 80 #define RXD_INVERT_BIT BIT(11) 81 82 #define COMPHY_SYNC_MASK_GEN 0x25 83 #define PHY_GEN_MAX_MASK GENMASK(11, 10) 84 #define PHY_GEN_MAX_USB3_5G FIELD_PREP(PHY_GEN_MAX_MASK, 0x1) 85 86 #define COMPHY_ISOLATION_CTRL 0x26 87 #define PHY_ISOLATE_MODE BIT(15) 88 89 #define COMPHY_GEN2_SET2 0x3e 90 #define GS2_TX_SSC_AMP_MASK GENMASK(15, 9) 91 #define GS2_TX_SSC_AMP_4128 FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20) 92 #define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7) 93 #define GS2_VREG_RXTX_MAS_ISET_60U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 94 0x0) 95 #define GS2_VREG_RXTX_MAS_ISET_80U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 96 0x1) 97 #define GS2_VREG_RXTX_MAS_ISET_100U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 98 0x2) 99 #define GS2_VREG_RXTX_MAS_ISET_120U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\ 100 0x3) 101 #define GS2_RSVD_6_0_MASK GENMASK(6, 0) 102 103 #define COMPHY_GEN3_SET2 0x3f 104 105 #define COMPHY_IDLE_SYNC_EN 0x48 106 #define IDLE_SYNC_EN BIT(12) 107 108 #define COMPHY_MISC_CTRL0 0x4F 109 #define CLK100M_125M_EN BIT(4) 110 #define TXDCLK_2X_SEL BIT(6) 111 #define CLK500M_EN BIT(7) 112 #define PHY_REF_CLK_SEL BIT(10) 113 114 #define COMPHY_SFT_RESET 0x52 115 #define SFT_RST BIT(9) 116 #define SFT_RST_NO_REG BIT(10) 117 118 #define COMPHY_MISC_CTRL1 0x73 119 #define SEL_BITS_PCIE_FORCE BIT(15) 120 121 #define COMPHY_GEN2_SET3 0x112 122 #define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0) 123 #define GS3_FFE_CAP_SEL_VALUE FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF) 124 125 /* PIPE registers */ 126 #define COMPHY_PIPE_LANE_CFG0 0x180 127 #define PRD_TXDEEMPH0_MASK BIT(0) 128 #define PRD_TXMARGIN_MASK GENMASK(3, 1) 129 #define PRD_TXSWING_MASK BIT(4) 130 #define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5) 131 132 #define COMPHY_PIPE_LANE_CFG1 0x181 133 #define PRD_TXDEEMPH1_MASK BIT(15) 134 #define USE_MAX_PLL_RATE_EN BIT(9) 135 #define TX_DET_RX_MODE BIT(6) 136 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3) 137 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2) 138 #define TX_ELEC_IDLE_MODE_EN BIT(0) 139 140 #define COMPHY_PIPE_LANE_STAT1 0x183 141 #define TXDCLK_PCLK_EN BIT(0) 142 143 #define COMPHY_PIPE_LANE_CFG4 0x188 144 #define SPREAD_SPECTRUM_CLK_EN BIT(7) 145 146 #define COMPHY_PIPE_RST_CLK_CTRL 0x1C1 147 #define PIPE_SOFT_RESET BIT(0) 148 #define PIPE_REG_RESET BIT(1) 149 #define MODE_CORE_CLK_FREQ_SEL BIT(9) 150 #define MODE_PIPE_WIDTH_32 BIT(3) 151 #define MODE_REFDIV_MASK GENMASK(5, 4) 152 #define MODE_REFDIV_BY_4 FIELD_PREP(MODE_REFDIV_MASK, 0x2) 153 154 #define COMPHY_PIPE_TEST_MODE_CTRL 0x1C2 155 #define MODE_MARGIN_OVERRIDE BIT(2) 156 157 #define COMPHY_PIPE_CLK_SRC_LO 0x1C3 158 #define MODE_CLK_SRC BIT(0) 159 #define BUNDLE_PERIOD_SEL BIT(1) 160 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2) 161 #define BUNDLE_SAMPLE_CTRL BIT(4) 162 #define PLL_READY_DLY_MASK GENMASK(7, 5) 163 #define CFG_SEL_20B BIT(15) 164 165 #define COMPHY_PIPE_PWR_MGM_TIM1 0x1D0 166 #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12) 167 #define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8) 168 #define CFG_PM_RXDEN_WAIT_1_UNIT FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1) 169 #define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0) 170 #define CFG_PM_RXDLOZ_WAIT_7_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7) 171 #define CFG_PM_RXDLOZ_WAIT_12_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC) 172 173 /* 174 * This register is not from PHY lane register space. It only exists in the 175 * indirect register space, before the actual PHY lane 2 registers. So the 176 * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE. 177 * It is used only for SATA PHY initialization. 178 */ 179 #define COMPHY_RESERVED_REG 0x0E 180 #define PHYCTRL_FRM_PIN_BIT BIT(13) 181 182 /* South Bridge PHY Configuration Registers */ 183 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) 184 185 /* 186 * lane0: USB3/GbE1 PHY Configuration 1 187 * lane1: PCIe/GbE0 PHY Configuration 1 188 * (used only by SGMII code) 189 */ 190 #define COMPHY_PHY_CFG1 0x0 191 #define PIN_PU_IVREF_BIT BIT(1) 192 #define PIN_RESET_CORE_BIT BIT(11) 193 #define PIN_RESET_COMPHY_BIT BIT(12) 194 #define PIN_PU_PLL_BIT BIT(16) 195 #define PIN_PU_RX_BIT BIT(17) 196 #define PIN_PU_TX_BIT BIT(18) 197 #define PIN_TX_IDLE_BIT BIT(19) 198 #define GEN_RX_SEL_MASK GENMASK(25, 22) 199 #define GEN_RX_SEL_VALUE(val) FIELD_PREP(GEN_RX_SEL_MASK, (val)) 200 #define GEN_TX_SEL_MASK GENMASK(29, 26) 201 #define GEN_TX_SEL_VALUE(val) FIELD_PREP(GEN_TX_SEL_MASK, (val)) 202 #define SERDES_SPEED_1_25_G 0x6 203 #define SERDES_SPEED_3_125_G 0x8 204 #define PHY_RX_INIT_BIT BIT(30) 205 206 /* 207 * lane0: USB3/GbE1 PHY Status 1 208 * lane1: PCIe/GbE0 PHY Status 1 209 * (used only by SGMII code) 210 */ 211 #define COMPHY_PHY_STAT1 0x18 212 #define PHY_RX_INIT_DONE_BIT BIT(0) 213 #define PHY_PLL_READY_RX_BIT BIT(2) 214 #define PHY_PLL_READY_TX_BIT BIT(3) 215 216 /* PHY Selector */ 217 #define COMPHY_SELECTOR_PHY_REG 0xFC 218 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */ 219 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0) 220 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */ 221 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4) 222 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */ 223 #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8) 224 225 struct mvebu_a3700_comphy_conf { 226 unsigned int lane; 227 enum phy_mode mode; 228 int submode; 229 }; 230 231 #define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode) \ 232 { \ 233 .lane = _lane, \ 234 .mode = _mode, \ 235 .submode = _smode, \ 236 } 237 238 #define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \ 239 MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA) 240 241 #define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \ 242 MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode) 243 244 static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = { 245 /* lane 0 */ 246 MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS), 247 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII), 248 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX), 249 MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX), 250 /* lane 1 */ 251 MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE), 252 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII), 253 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX), 254 MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX), 255 /* lane 2 */ 256 MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA), 257 MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS), 258 }; 259 260 struct mvebu_a3700_comphy_priv { 261 void __iomem *comphy_regs; 262 void __iomem *lane0_phy_regs; /* USB3 and GbE1 */ 263 void __iomem *lane1_phy_regs; /* PCIe and GbE0 */ 264 void __iomem *lane2_phy_indirect; /* SATA and USB3 */ 265 spinlock_t lock; /* for PHY selector access */ 266 bool xtal_is_40m; 267 }; 268 269 struct mvebu_a3700_comphy_lane { 270 struct mvebu_a3700_comphy_priv *priv; 271 struct device *dev; 272 unsigned int id; 273 enum phy_mode mode; 274 int submode; 275 bool invert_tx; 276 bool invert_rx; 277 }; 278 279 struct gbe_phy_init_data_fix { 280 u16 addr; 281 u16 value; 282 }; 283 284 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */ 285 static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = { 286 { 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 }, 287 { 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 }, 288 { 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 }, 289 { 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC }, 290 { 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 }, 291 { 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 }, 292 { 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 }, 293 { 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 }, 294 { 0x104, 0x0C10 } 295 }; 296 297 /* 40M1G25 mode init data */ 298 static u16 gbe_phy_init[512] = { 299 /* 0 1 2 3 4 5 6 7 */ 300 /*-----------------------------------------------------------*/ 301 /* 8 9 A B C D E F */ 302 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */ 303 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */ 304 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */ 305 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */ 306 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */ 307 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */ 308 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ 309 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */ 310 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */ 311 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */ 312 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */ 313 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */ 314 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */ 315 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */ 316 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */ 317 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */ 318 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */ 319 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */ 320 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */ 321 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */ 322 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */ 323 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */ 324 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */ 325 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */ 326 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */ 327 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */ 328 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */ 329 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */ 330 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */ 331 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */ 332 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */ 333 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */ 334 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */ 335 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */ 336 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */ 337 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */ 338 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */ 339 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */ 340 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */ 341 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */ 342 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */ 343 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */ 344 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */ 345 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */ 346 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */ 347 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */ 348 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */ 349 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */ 350 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */ 351 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */ 352 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */ 353 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */ 354 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */ 355 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */ 356 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */ 357 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */ 358 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */ 359 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */ 360 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */ 361 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */ 362 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */ 363 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */ 364 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */ 365 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */ 366 }; 367 368 static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask) 369 { 370 u32 val; 371 372 val = readl(addr); 373 val = (val & ~mask) | (data & mask); 374 writel(val, addr); 375 } 376 377 static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask) 378 { 379 u16 val; 380 381 val = readw(addr); 382 val = (val & ~mask) | (data & mask); 383 writew(val, addr); 384 } 385 386 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */ 387 static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv, 388 u32 offset, u16 data, u16 mask) 389 { 390 writel(offset, 391 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); 392 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, 393 data, mask); 394 } 395 396 static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane, 397 u16 reg, u16 data, u16 mask) 398 { 399 if (lane->id == 2) { 400 /* lane 2 PHY registers are accessed indirectly */ 401 comphy_set_indirect(lane->priv, 402 reg + COMPHY_LANE2_REGS_BASE, 403 data, mask); 404 } else { 405 void __iomem *base = lane->id == 1 ? 406 lane->priv->lane1_phy_regs : 407 lane->priv->lane0_phy_regs; 408 409 comphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg), 410 data, mask); 411 } 412 } 413 414 static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane, 415 u16 reg, u16 bits, 416 ulong sleep_us, ulong timeout_us) 417 { 418 int ret; 419 420 if (lane->id == 2) { 421 u32 data; 422 423 /* lane 2 PHY registers are accessed indirectly */ 424 writel(reg + COMPHY_LANE2_REGS_BASE, 425 lane->priv->lane2_phy_indirect + 426 COMPHY_LANE2_INDIR_ADDR); 427 428 ret = readl_poll_timeout(lane->priv->lane2_phy_indirect + 429 COMPHY_LANE2_INDIR_DATA, 430 data, (data & bits) == bits, 431 sleep_us, timeout_us); 432 } else { 433 void __iomem *base = lane->id == 1 ? 434 lane->priv->lane1_phy_regs : 435 lane->priv->lane0_phy_regs; 436 u16 data; 437 438 ret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg), 439 data, (data & bits) == bits, 440 sleep_us, timeout_us); 441 } 442 443 return ret; 444 } 445 446 static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane, 447 u8 reg, u32 data, u32 mask) 448 { 449 comphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg), 450 data, mask); 451 } 452 453 static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane, 454 u8 reg, u32 bits, 455 ulong sleep_us, ulong timeout_us) 456 { 457 u32 data; 458 459 return readl_poll_timeout(lane->priv->comphy_regs + 460 COMPHY_PHY_REG(lane->id, reg), 461 data, (data & bits) == bits, 462 sleep_us, timeout_us); 463 } 464 465 /* PHY selector configures with corresponding modes */ 466 static int 467 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane) 468 { 469 u32 old, new, clr = 0, set = 0; 470 unsigned long flags; 471 472 switch (lane->mode) { 473 case PHY_MODE_SATA: 474 /* SATA must be in Lane2 */ 475 if (lane->id == 2) 476 clr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 477 else 478 goto error; 479 break; 480 481 case PHY_MODE_ETHERNET: 482 if (lane->id == 0) 483 clr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 484 else if (lane->id == 1) 485 clr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 486 else 487 goto error; 488 break; 489 490 case PHY_MODE_USB_HOST_SS: 491 if (lane->id == 2) 492 set = COMPHY_SELECTOR_USB3_PHY_SEL_BIT; 493 else if (lane->id == 0) 494 set = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT; 495 else 496 goto error; 497 break; 498 499 case PHY_MODE_PCIE: 500 /* PCIE must be in Lane1 */ 501 if (lane->id == 1) 502 set = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT; 503 else 504 goto error; 505 break; 506 507 default: 508 goto error; 509 } 510 511 spin_lock_irqsave(&lane->priv->lock, flags); 512 513 old = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); 514 new = (old & ~clr) | set; 515 writel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG); 516 517 spin_unlock_irqrestore(&lane->priv->lock, flags); 518 519 dev_dbg(lane->dev, 520 "COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\n", 521 lane->id, lane->mode, old, new); 522 523 return 0; 524 error: 525 dev_err(lane->dev, "COMPHY[%d] mode[%d] is invalid\n", lane->id, 526 lane->mode); 527 return -EINVAL; 528 } 529 530 static int 531 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane) 532 { 533 u32 mask, data, ref_clk; 534 int ret; 535 536 /* Configure phy selector for SATA */ 537 ret = mvebu_a3700_comphy_set_phy_selector(lane); 538 if (ret) 539 return ret; 540 541 /* Clear phy isolation mode to make it work in normal mode */ 542 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, 543 0x0, PHY_ISOLATE_MODE); 544 545 /* 0. Check the Polarity invert bits */ 546 data = 0x0; 547 if (lane->invert_tx) 548 data |= TXD_INVERT_BIT; 549 if (lane->invert_rx) 550 data |= RXD_INVERT_BIT; 551 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 552 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 553 554 /* 1. Select 40-bit data width */ 555 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, 556 DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK); 557 558 /* 2. Select reference clock(25M) and PHY mode (SATA) */ 559 if (lane->priv->xtal_is_40m) 560 ref_clk = REF_FREF_SEL_SERDES_40MHZ; 561 else 562 ref_clk = REF_FREF_SEL_SERDES_25MHZ; 563 564 data = ref_clk | COMPHY_MODE_SATA; 565 mask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK; 566 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 567 568 /* 3. Use maximum PLL rate (no power save) */ 569 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, 570 USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT); 571 572 /* 4. Reset reserved bit */ 573 comphy_set_indirect(lane->priv, COMPHY_RESERVED_REG, 574 0x0, PHYCTRL_FRM_PIN_BIT); 575 576 /* 5. Set vendor-specific configuration (It is done in sata driver) */ 577 /* XXX: in U-Boot below sequence was executed in this place, in Linux 578 * not. Now it is done only in U-Boot before this comphy 579 * initialization - tests shows that it works ok, but in case of any 580 * future problem it is left for reference. 581 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff); 582 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6)); 583 */ 584 585 /* Wait for > 55 us to allow PLL be enabled */ 586 udelay(PLL_SET_DELAY_US); 587 588 /* Polling status */ 589 ret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN, 590 PLL_READY_TX_BIT, COMPHY_PLL_SLEEP, 591 COMPHY_PLL_TIMEOUT); 592 if (ret) 593 dev_err(lane->dev, "Failed to lock SATA PLL\n"); 594 595 return ret; 596 } 597 598 static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane, 599 bool is_1gbps) 600 { 601 int addr, fix_idx; 602 u16 val; 603 604 fix_idx = 0; 605 for (addr = 0; addr < 512; addr++) { 606 /* 607 * All PHY register values are defined in full for 3.125Gbps 608 * SERDES speed. The values required for 1.25 Gbps are almost 609 * the same and only few registers should be "fixed" in 610 * comparison to 3.125 Gbps values. These register values are 611 * stored in "gbe_phy_init_fix" array. 612 */ 613 if (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) { 614 /* Use new value */ 615 val = gbe_phy_init_fix[fix_idx].value; 616 if (fix_idx < ARRAY_SIZE(gbe_phy_init_fix)) 617 fix_idx++; 618 } else { 619 val = gbe_phy_init[addr]; 620 } 621 622 comphy_lane_reg_set(lane, addr, val, 0xFFFF); 623 } 624 } 625 626 static int 627 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane) 628 { 629 u32 mask, data, speed_sel; 630 int ret; 631 632 /* Set selector */ 633 ret = mvebu_a3700_comphy_set_phy_selector(lane); 634 if (ret) 635 return ret; 636 637 /* 638 * 1. Reset PHY by setting PHY input port PIN_RESET=1. 639 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep 640 * PHY TXP/TXN output to idle state during PHY initialization 641 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0. 642 */ 643 data = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT; 644 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | 645 PIN_PU_TX_BIT | PHY_RX_INIT_BIT; 646 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 647 648 /* 4. Release reset to the PHY by setting PIN_RESET=0. */ 649 data = 0x0; 650 mask = PIN_RESET_COMPHY_BIT; 651 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 652 653 /* 654 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY 655 * bit rate 656 */ 657 switch (lane->submode) { 658 case PHY_INTERFACE_MODE_SGMII: 659 case PHY_INTERFACE_MODE_1000BASEX: 660 /* SGMII 1G, SerDes speed 1.25G */ 661 speed_sel = SERDES_SPEED_1_25_G; 662 break; 663 case PHY_INTERFACE_MODE_2500BASEX: 664 /* 2500Base-X, SerDes speed 3.125G */ 665 speed_sel = SERDES_SPEED_3_125_G; 666 break; 667 default: 668 /* Other rates are not supported */ 669 dev_err(lane->dev, 670 "unsupported phy speed %d on comphy lane%d\n", 671 lane->submode, lane->id); 672 return -EINVAL; 673 } 674 data = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel); 675 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK; 676 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 677 678 /* 679 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then 680 * start SW programming. 681 */ 682 mdelay(10); 683 684 /* 7. Program COMPHY register PHY_MODE */ 685 data = COMPHY_MODE_SERDES; 686 mask = COMPHY_MODE_MASK; 687 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 688 689 /* 690 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK 691 * source 692 */ 693 data = 0x0; 694 mask = PHY_REF_CLK_SEL; 695 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); 696 697 /* 698 * 9. Set correct reference clock frequency in COMPHY register 699 * REF_FREF_SEL. 700 */ 701 if (lane->priv->xtal_is_40m) 702 data = REF_FREF_SEL_SERDES_50MHZ; 703 else 704 data = REF_FREF_SEL_SERDES_25MHZ; 705 706 mask = REF_FREF_SEL_MASK; 707 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 708 709 /* 710 * 10. Program COMPHY register PHY_GEN_MAX[1:0] 711 * This step is mentioned in the flow received from verification team. 712 * However the PHY_GEN_MAX value is only meaningful for other interfaces 713 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or 714 * PCIe speed 2.5/5 Gbps 715 */ 716 717 /* 718 * 11. Program COMPHY register SEL_BITS to set correct parallel data 719 * bus width 720 */ 721 data = DATA_WIDTH_10BIT; 722 mask = SEL_DATA_WIDTH_MASK; 723 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask); 724 725 /* 726 * 12. As long as DFE function needs to be enabled in any mode, 727 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F 728 * for real chip during COMPHY power on. 729 * The value of the DFE_UPDATE_EN already is 0x3F, because it is the 730 * default value after reset of the PHY. 731 */ 732 733 /* 734 * 13. Program COMPHY GEN registers. 735 * These registers should be programmed based on the lab testing result 736 * to achieve optimal performance. Please contact the CEA group to get 737 * the related GEN table during real chip bring-up. We only required to 738 * run though the entire registers programming flow defined by 739 * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock 740 * 25 MHz the default values stored in PHY registers are OK. 741 */ 742 dev_dbg(lane->dev, "Running C-DPI phy init %s mode\n", 743 lane->submode == PHY_INTERFACE_MODE_2500BASEX ? "2G5" : "1G"); 744 if (lane->priv->xtal_is_40m) 745 comphy_gbe_phy_init(lane, 746 lane->submode != PHY_INTERFACE_MODE_2500BASEX); 747 748 /* 749 * 14. Check the PHY Polarity invert bit 750 */ 751 data = 0x0; 752 if (lane->invert_tx) 753 data |= TXD_INVERT_BIT; 754 if (lane->invert_rx) 755 data |= RXD_INVERT_BIT; 756 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 757 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 758 759 /* 760 * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to 761 * start PHY power up sequence. All the PHY register programming should 762 * be done before PIN_PU_PLL=1. There should be no register programming 763 * for normal PHY operation from this point. 764 */ 765 data = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT; 766 mask = data; 767 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 768 769 /* 770 * 16. Wait for PHY power up sequence to finish by checking output ports 771 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1. 772 */ 773 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 774 PHY_PLL_READY_TX_BIT | 775 PHY_PLL_READY_RX_BIT, 776 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 777 if (ret) { 778 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", 779 lane->id); 780 return ret; 781 } 782 783 /* 784 * 17. Set COMPHY input port PIN_TX_IDLE=0 785 */ 786 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT); 787 788 /* 789 * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To 790 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the 791 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to 792 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please 793 * refer to RX initialization part for details. 794 */ 795 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 796 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT); 797 798 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 799 PHY_PLL_READY_TX_BIT | 800 PHY_PLL_READY_RX_BIT, 801 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 802 if (ret) { 803 dev_err(lane->dev, "Failed to lock PLL for SERDES PHY %d\n", 804 lane->id); 805 return ret; 806 } 807 808 ret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1, 809 PHY_RX_INIT_DONE_BIT, 810 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 811 if (ret) 812 dev_err(lane->dev, "Failed to init RX of SERDES PHY %d\n", 813 lane->id); 814 815 return ret; 816 } 817 818 static int 819 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane) 820 { 821 u32 mask, data, cfg, ref_clk; 822 int ret; 823 824 /* Set phy seclector */ 825 ret = mvebu_a3700_comphy_set_phy_selector(lane); 826 if (ret) 827 return ret; 828 829 /* COMPHY register reset (cleared automatically) */ 830 comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST); 831 832 /* 833 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The 834 * register belong to UTMI module, so it is set in UTMI phy driver. 835 */ 836 837 /* 838 * 1. Set PRD_TXDEEMPH (3.5db de-emph) 839 */ 840 data = PRD_TXDEEMPH0_MASK; 841 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK | 842 CFG_TX_ALIGN_POS_MASK; 843 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask); 844 845 /* 846 * 2. Set BIT0: enable transmitter in high impedance mode 847 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency 848 * Set BIT6: Tx detect Rx at HiZ mode 849 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db 850 * together with bit 0 of COMPHY_PIPE_LANE_CFG0 register 851 */ 852 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN; 853 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK | 854 TX_ELEC_IDLE_MODE_EN; 855 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask); 856 857 /* 858 * 3. Set Spread Spectrum Clock Enabled 859 */ 860 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4, 861 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN); 862 863 /* 864 * 4. Set Override Margining Controls From the MAC: 865 * Use margining signals from lane configuration 866 */ 867 comphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL, 868 MODE_MARGIN_OVERRIDE, 0xFFFF); 869 870 /* 871 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles 872 * set Mode Clock Source = PCLK is generated from REFCLK 873 */ 874 data = 0x0; 875 mask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK | 876 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK; 877 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask); 878 879 /* 880 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K 881 */ 882 comphy_lane_reg_set(lane, COMPHY_GEN2_SET2, 883 GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK); 884 885 /* 886 * 7. Unset G3 Spread Spectrum Clock Amplitude 887 * set G3 TX and RX Register Master Current Select 888 */ 889 data = GS2_VREG_RXTX_MAS_ISET_60U; 890 mask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK | 891 GS2_RSVD_6_0_MASK; 892 comphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask); 893 894 /* 895 * 8. Check crystal jumper setting and program the Power and PLL Control 896 * accordingly Change RX wait 897 */ 898 if (lane->priv->xtal_is_40m) { 899 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 900 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT; 901 } else { 902 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 903 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT; 904 } 905 906 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 907 PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk; 908 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 909 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK | 910 REF_FREF_SEL_MASK; 911 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 912 913 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg; 914 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 915 CFG_PM_RXDLOZ_WAIT_MASK; 916 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); 917 918 /* 919 * 9. Enable idle sync 920 */ 921 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, 922 IDLE_SYNC_EN, IDLE_SYNC_EN); 923 924 /* 925 * 10. Enable the output of 500M clock 926 */ 927 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN); 928 929 /* 930 * 11. Set 20-bit data width 931 */ 932 comphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, 933 DATA_WIDTH_20BIT, 0xFFFF); 934 935 /* 936 * 12. Override Speed_PLL value and use MAC PLL 937 */ 938 data = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT; 939 mask = 0xFFFF; 940 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask); 941 942 /* 943 * 13. Check the Polarity invert bit 944 */ 945 data = 0x0; 946 if (lane->invert_tx) 947 data |= TXD_INVERT_BIT; 948 if (lane->invert_rx) 949 data |= RXD_INVERT_BIT; 950 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 951 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 952 953 /* 954 * 14. Set max speed generation to USB3.0 5Gbps 955 */ 956 comphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN, 957 PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK); 958 959 /* 960 * 15. Set capacitor value for FFE gain peaking to 0xF 961 */ 962 comphy_lane_reg_set(lane, COMPHY_GEN2_SET3, 963 GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK); 964 965 /* 966 * 16. Release SW reset 967 */ 968 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4; 969 mask = 0xFFFF; 970 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 971 972 /* Wait for > 55 us to allow PCLK be enabled */ 973 udelay(PLL_SET_DELAY_US); 974 975 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, 976 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 977 if (ret) 978 dev_err(lane->dev, "Failed to lock USB3 PLL\n"); 979 980 return ret; 981 } 982 983 static int 984 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane) 985 { 986 u32 mask, data, ref_clk; 987 int ret; 988 989 /* Configure phy selector for PCIe */ 990 ret = mvebu_a3700_comphy_set_phy_selector(lane); 991 if (ret) 992 return ret; 993 994 /* 1. Enable max PLL. */ 995 comphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, 996 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN); 997 998 /* 2. Select 20 bit SERDES interface. */ 999 comphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, 1000 CFG_SEL_20B, CFG_SEL_20B); 1001 1002 /* 3. Force to use reg setting for PCIe mode */ 1003 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL1, 1004 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE); 1005 1006 /* 4. Change RX wait */ 1007 data = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT; 1008 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK | 1009 CFG_PM_RXDLOZ_WAIT_MASK; 1010 comphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask); 1011 1012 /* 5. Enable idle sync */ 1013 comphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN, 1014 IDLE_SYNC_EN, IDLE_SYNC_EN); 1015 1016 /* 6. Enable the output of 100M/125M/500M clock */ 1017 data = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN; 1018 mask = data; 1019 comphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask); 1020 1021 /* 1022 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in 1023 * PCI-E driver 1024 */ 1025 1026 /* 1027 * 8. Check crystal jumper setting and program the Power and PLL 1028 * Control accordingly 1029 */ 1030 1031 if (lane->priv->xtal_is_40m) 1032 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; 1033 else 1034 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; 1035 1036 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT | 1037 PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk; 1038 mask = 0xFFFF; 1039 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask); 1040 1041 /* 9. Override Speed_PLL value and use MAC PLL */ 1042 comphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, 1043 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, 1044 0xFFFF); 1045 1046 /* 10. Check the Polarity invert bit */ 1047 data = 0x0; 1048 if (lane->invert_tx) 1049 data |= TXD_INVERT_BIT; 1050 if (lane->invert_rx) 1051 data |= RXD_INVERT_BIT; 1052 mask = TXD_INVERT_BIT | RXD_INVERT_BIT; 1053 comphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask); 1054 1055 /* 11. Release SW reset */ 1056 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32; 1057 mask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK; 1058 comphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask); 1059 1060 /* Wait for > 55 us to allow PCLK be enabled */ 1061 udelay(PLL_SET_DELAY_US); 1062 1063 ret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN, 1064 COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT); 1065 if (ret) 1066 dev_err(lane->dev, "Failed to lock PCIE PLL\n"); 1067 1068 return ret; 1069 } 1070 1071 static void 1072 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane) 1073 { 1074 /* Set phy isolation mode */ 1075 comphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL, 1076 PHY_ISOLATE_MODE, PHY_ISOLATE_MODE); 1077 1078 /* Power off PLL, Tx, Rx */ 1079 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, 1080 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 1081 } 1082 1083 static void 1084 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane) 1085 { 1086 u32 mask, data; 1087 1088 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT | 1089 PHY_RX_INIT_BIT; 1090 mask = data; 1091 comphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask); 1092 } 1093 1094 static void 1095 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane) 1096 { 1097 /* Power off PLL, Tx, Rx */ 1098 comphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, 1099 0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT); 1100 } 1101 1102 static void mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane) 1103 { 1104 /* 1105 * The USB3 MAC sets the USB3 PHY to low state, so we do not 1106 * need to power off USB3 PHY again. 1107 */ 1108 } 1109 1110 static bool mvebu_a3700_comphy_check_mode(int lane, 1111 enum phy_mode mode, 1112 int submode) 1113 { 1114 int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes); 1115 1116 /* Unused PHY mux value is 0x0 */ 1117 if (mode == PHY_MODE_INVALID) 1118 return false; 1119 1120 for (i = 0; i < n; i++) { 1121 if (mvebu_a3700_comphy_modes[i].lane == lane && 1122 mvebu_a3700_comphy_modes[i].mode == mode && 1123 mvebu_a3700_comphy_modes[i].submode == submode) 1124 break; 1125 } 1126 1127 if (i == n) 1128 return false; 1129 1130 return true; 1131 } 1132 1133 static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode, 1134 int submode) 1135 { 1136 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1137 1138 if (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) { 1139 dev_err(lane->dev, "invalid COMPHY mode\n"); 1140 return -EINVAL; 1141 } 1142 1143 /* Mode cannot be changed while the PHY is powered on */ 1144 if (phy->power_count && 1145 (lane->mode != mode || lane->submode != submode)) 1146 return -EBUSY; 1147 1148 /* Just remember the mode, ->power_on() will do the real setup */ 1149 lane->mode = mode; 1150 lane->submode = submode; 1151 1152 return 0; 1153 } 1154 1155 static int mvebu_a3700_comphy_power_on(struct phy *phy) 1156 { 1157 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1158 1159 if (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode, 1160 lane->submode)) { 1161 dev_err(lane->dev, "invalid COMPHY mode\n"); 1162 return -EINVAL; 1163 } 1164 1165 switch (lane->mode) { 1166 case PHY_MODE_USB_HOST_SS: 1167 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); 1168 return mvebu_a3700_comphy_usb3_power_on(lane); 1169 case PHY_MODE_SATA: 1170 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); 1171 return mvebu_a3700_comphy_sata_power_on(lane); 1172 case PHY_MODE_ETHERNET: 1173 dev_dbg(lane->dev, "set lane %d to Ethernet mode\n", lane->id); 1174 return mvebu_a3700_comphy_ethernet_power_on(lane); 1175 case PHY_MODE_PCIE: 1176 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); 1177 return mvebu_a3700_comphy_pcie_power_on(lane); 1178 default: 1179 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); 1180 return -EOPNOTSUPP; 1181 } 1182 } 1183 1184 static int mvebu_a3700_comphy_power_off(struct phy *phy) 1185 { 1186 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); 1187 1188 switch (lane->id) { 1189 case 0: 1190 mvebu_a3700_comphy_usb3_power_off(lane); 1191 mvebu_a3700_comphy_ethernet_power_off(lane); 1192 return 0; 1193 case 1: 1194 mvebu_a3700_comphy_pcie_power_off(lane); 1195 mvebu_a3700_comphy_ethernet_power_off(lane); 1196 return 0; 1197 case 2: 1198 mvebu_a3700_comphy_usb3_power_off(lane); 1199 mvebu_a3700_comphy_sata_power_off(lane); 1200 return 0; 1201 default: 1202 dev_err(lane->dev, "invalid COMPHY mode\n"); 1203 return -EINVAL; 1204 } 1205 } 1206 1207 static const struct phy_ops mvebu_a3700_comphy_ops = { 1208 .power_on = mvebu_a3700_comphy_power_on, 1209 .power_off = mvebu_a3700_comphy_power_off, 1210 .set_mode = mvebu_a3700_comphy_set_mode, 1211 .owner = THIS_MODULE, 1212 }; 1213 1214 static struct phy *mvebu_a3700_comphy_xlate(struct device *dev, 1215 struct of_phandle_args *args) 1216 { 1217 struct mvebu_a3700_comphy_lane *lane; 1218 unsigned int port; 1219 struct phy *phy; 1220 1221 phy = of_phy_simple_xlate(dev, args); 1222 if (IS_ERR(phy)) 1223 return phy; 1224 1225 lane = phy_get_drvdata(phy); 1226 1227 port = args->args[0]; 1228 if (port != 0 && (port != 1 || lane->id != 0)) { 1229 dev_err(lane->dev, "invalid port number %u\n", port); 1230 return ERR_PTR(-EINVAL); 1231 } 1232 1233 lane->invert_tx = args->args[1] & BIT(0); 1234 lane->invert_rx = args->args[1] & BIT(1); 1235 1236 return phy; 1237 } 1238 1239 static int mvebu_a3700_comphy_probe(struct platform_device *pdev) 1240 { 1241 struct mvebu_a3700_comphy_priv *priv; 1242 struct phy_provider *provider; 1243 struct device_node *child; 1244 struct resource *res; 1245 struct clk *clk; 1246 int ret; 1247 1248 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1249 if (!priv) 1250 return -ENOMEM; 1251 1252 spin_lock_init(&priv->lock); 1253 1254 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "comphy"); 1255 priv->comphy_regs = devm_ioremap_resource(&pdev->dev, res); 1256 if (IS_ERR(priv->comphy_regs)) 1257 return PTR_ERR(priv->comphy_regs); 1258 1259 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1260 "lane1_pcie_gbe"); 1261 priv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res); 1262 if (IS_ERR(priv->lane1_phy_regs)) 1263 return PTR_ERR(priv->lane1_phy_regs); 1264 1265 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1266 "lane0_usb3_gbe"); 1267 priv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res); 1268 if (IS_ERR(priv->lane0_phy_regs)) 1269 return PTR_ERR(priv->lane0_phy_regs); 1270 1271 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1272 "lane2_sata_usb3"); 1273 priv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res); 1274 if (IS_ERR(priv->lane2_phy_indirect)) 1275 return PTR_ERR(priv->lane2_phy_indirect); 1276 1277 /* 1278 * Driver needs to know if reference xtal clock is 40MHz or 25MHz. 1279 * Old DT bindings do not have xtal clk present. So do not fail here 1280 * and expects that default 25MHz reference clock is used. 1281 */ 1282 clk = clk_get(&pdev->dev, "xtal"); 1283 if (IS_ERR(clk)) { 1284 if (PTR_ERR(clk) == -EPROBE_DEFER) 1285 return -EPROBE_DEFER; 1286 dev_warn(&pdev->dev, "missing 'xtal' clk (%ld)\n", 1287 PTR_ERR(clk)); 1288 } else { 1289 ret = clk_prepare_enable(clk); 1290 if (ret) { 1291 dev_warn(&pdev->dev, "enabling xtal clk failed (%d)\n", 1292 ret); 1293 } else { 1294 if (clk_get_rate(clk) == 40000000) 1295 priv->xtal_is_40m = true; 1296 clk_disable_unprepare(clk); 1297 } 1298 clk_put(clk); 1299 } 1300 1301 dev_set_drvdata(&pdev->dev, priv); 1302 1303 for_each_available_child_of_node(pdev->dev.of_node, child) { 1304 struct mvebu_a3700_comphy_lane *lane; 1305 struct phy *phy; 1306 int ret; 1307 u32 lane_id; 1308 1309 ret = of_property_read_u32(child, "reg", &lane_id); 1310 if (ret < 0) { 1311 dev_err(&pdev->dev, "missing 'reg' property (%d)\n", 1312 ret); 1313 continue; 1314 } 1315 1316 if (lane_id >= 3) { 1317 dev_err(&pdev->dev, "invalid 'reg' property\n"); 1318 continue; 1319 } 1320 1321 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); 1322 if (!lane) { 1323 of_node_put(child); 1324 return -ENOMEM; 1325 } 1326 1327 phy = devm_phy_create(&pdev->dev, child, 1328 &mvebu_a3700_comphy_ops); 1329 if (IS_ERR(phy)) { 1330 of_node_put(child); 1331 return PTR_ERR(phy); 1332 } 1333 1334 lane->priv = priv; 1335 lane->dev = &pdev->dev; 1336 lane->mode = PHY_MODE_INVALID; 1337 lane->submode = PHY_INTERFACE_MODE_NA; 1338 lane->id = lane_id; 1339 lane->invert_tx = false; 1340 lane->invert_rx = false; 1341 phy_set_drvdata(phy, lane); 1342 1343 /* 1344 * To avoid relying on the bootloader/firmware configuration, 1345 * power off all comphys. 1346 */ 1347 mvebu_a3700_comphy_power_off(phy); 1348 } 1349 1350 provider = devm_of_phy_provider_register(&pdev->dev, 1351 mvebu_a3700_comphy_xlate); 1352 1353 return PTR_ERR_OR_ZERO(provider); 1354 } 1355 1356 static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = { 1357 { .compatible = "marvell,comphy-a3700" }, 1358 { }, 1359 }; 1360 MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table); 1361 1362 static struct platform_driver mvebu_a3700_comphy_driver = { 1363 .probe = mvebu_a3700_comphy_probe, 1364 .driver = { 1365 .name = "mvebu-a3700-comphy", 1366 .of_match_table = mvebu_a3700_comphy_of_match_table, 1367 }, 1368 }; 1369 module_platform_driver(mvebu_a3700_comphy_driver); 1370 1371 MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>"); 1372 MODULE_AUTHOR("Pali Rohár <pali@kernel.org>"); 1373 MODULE_AUTHOR("Marek Behún <kabel@kernel.org>"); 1374 MODULE_DESCRIPTION("Common PHY driver for A3700"); 1375 MODULE_LICENSE("GPL v2"); 1376