1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2020 NXP 4 * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bits.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 17 #define PHY_REG(reg) (reg * 4) 18 19 #define REG01_PMS_P_MASK GENMASK(3, 0) 20 #define REG03_PMS_S_MASK GENMASK(7, 4) 21 #define REG12_CK_DIV_MASK GENMASK(5, 4) 22 23 #define REG13_TG_CODE_LOW_MASK GENMASK(7, 0) 24 25 #define REG14_TOL_MASK GENMASK(7, 4) 26 #define REG14_RP_CODE_MASK GENMASK(3, 1) 27 #define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0) 28 29 #define REG21_SEL_TX_CK_INV BIT(7) 30 #define REG21_PMS_S_MASK GENMASK(3, 0) 31 /* 32 * REG33 does not match the ref manual. According to Sandor Yu from NXP, 33 * "There is a doc issue on the i.MX8MP latest RM" 34 * REG33 is being used per guidance from Sandor 35 */ 36 #define REG33_MODE_SET_DONE BIT(7) 37 #define REG33_FIX_DA BIT(1) 38 39 #define REG34_PHY_READY BIT(7) 40 #define REG34_PLL_LOCK BIT(6) 41 #define REG34_PHY_CLK_READY BIT(5) 42 43 #ifndef MHZ 44 #define MHZ (1000UL * 1000UL) 45 #endif 46 47 #define PHY_PLL_DIV_REGS_NUM 7 48 49 struct phy_config { 50 u32 pixclk; 51 u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM]; 52 }; 53 54 /* 55 * The calculated_phy_pll_cfg only handles integer divider for PMS, 56 * meaning the last four entries will be fixed, but the first three will 57 * be calculated by the PMS calculator. 58 */ 59 static struct phy_config calculated_phy_pll_cfg = { 60 .pixclk = 0, 61 .pll_div_regs = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00 }, 62 }; 63 64 /* The lookup table contains values for which the fractional divder is used */ 65 static const struct phy_config phy_pll_cfg[] = { 66 { 67 .pixclk = 22250000, 68 .pll_div_regs = { 0xd1, 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 }, 69 }, { 70 .pixclk = 23750000, 71 .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 }, 72 }, { 73 .pixclk = 24024000, 74 .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, 75 }, { 76 .pixclk = 25175000, 77 .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, 78 }, { 79 .pixclk = 26750000, 80 .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 }, 81 }, { 82 .pixclk = 27027000, 83 .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, 84 }, { 85 .pixclk = 29500000, 86 .pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, 87 }, { 88 .pixclk = 30750000, 89 .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, 90 }, { 91 .pixclk = 30888000, 92 .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, 93 }, { 94 .pixclk = 33750000, 95 .pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, 96 }, { 97 .pixclk = 35000000, 98 .pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 }, 99 }, { 100 .pixclk = 36036000, 101 .pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 }, 102 }, { 103 .pixclk = 43243200, 104 .pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 }, 105 }, { 106 .pixclk = 44500000, 107 .pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, 108 }, { 109 .pixclk = 47000000, 110 .pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, 111 }, { 112 .pixclk = 47500000, 113 .pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, 114 }, { 115 .pixclk = 50349650, 116 .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, 117 }, { 118 .pixclk = 53250000, 119 .pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 }, 120 }, { 121 .pixclk = 53500000, 122 .pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 }, 123 }, { 124 .pixclk = 54054000, 125 .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, 126 }, { 127 .pixclk = 59000000, 128 .pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, 129 }, { 130 .pixclk = 59340659, 131 .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, 132 }, { 133 .pixclk = 61500000, 134 .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, 135 }, { 136 .pixclk = 63500000, 137 .pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, 138 }, { 139 .pixclk = 67500000, 140 .pll_div_regs = { 0xd1, 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 }, 141 }, { 142 .pixclk = 70000000, 143 .pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 }, 144 }, { 145 .pixclk = 72072000, 146 .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, 147 }, { 148 .pixclk = 74176000, 149 .pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, 150 }, { 151 .pixclk = 74250000, 152 .pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, 153 }, { 154 .pixclk = 78500000, 155 .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, 156 }, { 157 .pixclk = 82000000, 158 .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, 159 }, { 160 .pixclk = 82500000, 161 .pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, 162 }, { 163 .pixclk = 89000000, 164 .pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, 165 }, { 166 .pixclk = 90000000, 167 .pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, 168 }, { 169 .pixclk = 94000000, 170 .pll_div_regs = { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 }, 171 }, { 172 .pixclk = 95000000, 173 .pll_div_regs = { 0xd1, 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 }, 174 }, { 175 .pixclk = 98901099, 176 .pll_div_regs = { 0xd1, 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 }, 177 }, { 178 .pixclk = 99000000, 179 .pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, 180 }, { 181 .pixclk = 100699300, 182 .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, 183 }, { 184 .pixclk = 102500000, 185 .pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b }, 186 }, { 187 .pixclk = 104750000, 188 .pll_div_regs = { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 }, 189 }, { 190 .pixclk = 106500000, 191 .pll_div_regs = { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 }, 192 }, { 193 .pixclk = 107000000, 194 .pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 }, 195 }, { 196 .pixclk = 108108000, 197 .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, 198 }, { 199 .pixclk = 118000000, 200 .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, 201 }, { 202 .pixclk = 123000000, 203 .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, 204 }, { 205 .pixclk = 127000000, 206 .pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, 207 }, { 208 .pixclk = 135000000, 209 .pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, 210 }, { 211 .pixclk = 135580000, 212 .pll_div_regs = { 0xd1, 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b }, 213 }, { 214 .pixclk = 137520000, 215 .pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, 216 }, { 217 .pixclk = 138750000, 218 .pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, 219 }, { 220 .pixclk = 140000000, 221 .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, 222 }, { 223 .pixclk = 148352000, 224 .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, 225 }, { 226 .pixclk = 148500000, 227 .pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, 228 }, { 229 .pixclk = 154000000, 230 .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, 231 }, { 232 .pixclk = 157000000, 233 .pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, 234 }, { 235 .pixclk = 160000000, 236 .pll_div_regs = { 0xd1, 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 }, 237 }, { 238 .pixclk = 162000000, 239 .pll_div_regs = { 0xd1, 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 }, 240 }, { 241 .pixclk = 164000000, 242 .pll_div_regs = { 0xd1, 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b }, 243 }, { 244 .pixclk = 165000000, 245 .pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b }, 246 }, { 247 .pixclk = 185625000, 248 .pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 }, 249 }, { 250 .pixclk = 188000000, 251 .pll_div_regs = { 0xd1, 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 }, 252 }, { 253 .pixclk = 198000000, 254 .pll_div_regs = { 0xd1, 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 }, 255 }, { 256 .pixclk = 205000000, 257 .pll_div_regs = { 0xd1, 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b }, 258 }, { 259 .pixclk = 209500000, 260 .pll_div_regs = { 0xd1, 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 }, 261 }, { 262 .pixclk = 213000000, 263 .pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 }, 264 }, { 265 .pixclk = 216216000, 266 .pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 }, 267 }, { 268 .pixclk = 254000000, 269 .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, 270 }, { 271 .pixclk = 277500000, 272 .pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, 273 }, { 274 .pixclk = 297000000, 275 .pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, 276 }, 277 }; 278 279 struct reg_settings { 280 u8 reg; 281 u8 val; 282 }; 283 284 static const struct reg_settings common_phy_cfg[] = { 285 { PHY_REG(0), 0x00 }, 286 /* PHY_REG(1-7) pix clk specific */ 287 { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 }, 288 { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 }, 289 /* REG12 pixclk specific */ 290 /* REG13 pixclk specific */ 291 /* REG14 pixclk specific */ 292 { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c }, 293 { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 }, 294 { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 }, 295 /* REG21 pixclk specific */ 296 { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 }, 297 { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f }, 298 { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 }, 299 { PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 }, 300 { PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 }, 301 { PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 }, 302 { PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 }, 303 { PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 }, 304 { PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 }, 305 { PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 }, 306 { PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f }, 307 { PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 }, 308 { PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 } 309 }; 310 311 struct fsl_samsung_hdmi_phy { 312 struct device *dev; 313 void __iomem *regs; 314 struct clk *apbclk; 315 struct clk *refclk; 316 317 /* clk provider */ 318 struct clk_hw hw; 319 const struct phy_config *cur_cfg; 320 }; 321 322 static inline struct fsl_samsung_hdmi_phy * 323 to_fsl_samsung_hdmi_phy(struct clk_hw *hw) 324 { 325 return container_of(hw, struct fsl_samsung_hdmi_phy, hw); 326 } 327 328 static void 329 fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, 330 const struct phy_config *cfg) 331 { 332 u32 pclk = cfg->pixclk; 333 u32 fld_tg_code; 334 u32 pclk_khz; 335 u8 div = 1; 336 337 switch (cfg->pixclk) { 338 case 22250000 ... 47500000: 339 div = 1; 340 break; 341 case 50349650 ... 99000000: 342 div = 2; 343 break; 344 case 100699300 ... 198000000: 345 div = 4; 346 break; 347 case 205000000 ... 297000000: 348 div = 8; 349 break; 350 } 351 352 writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12)); 353 354 /* 355 * Calculation for the frequency lock detector target code (fld_tg_code) 356 * is based on reference manual register description of PHY_REG13 357 * (13.10.3.1.14.2): 358 * 1st) Calculate int_pllclk which is determinded by FLD_CK_DIV 359 * 2nd) Increase resolution to avoid rounding issues 360 * 3th) Do the div (256 / Freq. of int_pllclk) * 24 361 * 4th) Reduce the resolution and always round up since the NXP 362 * settings rounding up always too. TODO: Check if that is 363 * correct. 364 */ 365 pclk /= div; 366 pclk_khz = pclk / 1000; 367 fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24; 368 fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000); 369 370 /* FLD_TOL and FLD_RP_CODE taken from downstream driver */ 371 writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code), 372 phy->regs + PHY_REG(13)); 373 writeb(FIELD_PREP(REG14_TOL_MASK, 2) | 374 FIELD_PREP(REG14_RP_CODE_MASK, 2) | 375 FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), 376 phy->regs + PHY_REG(14)); 377 } 378 379 static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s) 380 { 381 unsigned long best_freq = 0; 382 u32 min_delta = 0xffffffff; 383 u8 _p, best_p; 384 u16 _m, best_m; 385 u8 _s, best_s; 386 387 /* 388 * Figure 13-78 of the reference manual states the PLL should be TMDS x 5 389 * while the TMDS_CLKO should be the PLL / 5. So to calculate the PLL, 390 * take the pix clock x 5, then return the value of the PLL / 5. 391 */ 392 fout *= 5; 393 394 /* The ref manual states the values of 'P' range from 1 to 11 */ 395 for (_p = 1; _p <= 11; ++_p) { 396 for (_s = 1; _s <= 16; ++_s) { 397 u64 tmp; 398 u32 delta; 399 400 /* s must be one or even */ 401 if (_s > 1 && (_s & 0x01) == 1) 402 _s++; 403 404 /* _s cannot be 14 per the TRM */ 405 if (_s == 14) 406 continue; 407 408 /* 409 * TODO: Ref Manual doesn't state the range of _m 410 * so this should be further refined if possible. 411 * This range was set based on the original values 412 * in the lookup table 413 */ 414 tmp = (u64)fout * (_p * _s); 415 do_div(tmp, 24 * MHZ); 416 _m = tmp; 417 if (_m < 0x30 || _m > 0x7b) 418 continue; 419 420 /* 421 * Rev 2 of the Ref Manual states the 422 * VCO can range between 750MHz and 423 * 3GHz. The VCO is assumed to be 424 * Fvco = (M * f_ref) / P, 425 * where f_ref is 24MHz. 426 */ 427 tmp = (u64)_m * 24 * MHZ; 428 do_div(tmp, _p); 429 if (tmp < 750 * MHZ || 430 tmp > 3000 * MHZ) 431 continue; 432 433 /* Final frequency after post-divider */ 434 do_div(tmp, _s); 435 436 delta = abs(fout - tmp); 437 if (delta < min_delta) { 438 best_p = _p; 439 best_s = _s; 440 best_m = _m; 441 min_delta = delta; 442 best_freq = tmp; 443 } 444 } 445 } 446 447 if (best_freq) { 448 *p = best_p; 449 *m = best_m; 450 *s = best_s; 451 } 452 453 return best_freq / 5; 454 } 455 456 static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, 457 const struct phy_config *cfg) 458 { 459 int i, ret; 460 u8 val; 461 462 /* HDMI PHY init */ 463 writeb(REG33_FIX_DA, phy->regs + PHY_REG(33)); 464 465 /* common PHY registers */ 466 for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++) 467 writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg); 468 469 /* set individual PLL registers PHY_REG1 ... PHY_REG7 */ 470 for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++) 471 writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4); 472 473 /* High nibble of PHY_REG3 and low nibble of PHY_REG21 both contain 'S' */ 474 writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, 475 cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); 476 477 fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); 478 479 writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); 480 481 ret = readb_poll_timeout(phy->regs + PHY_REG(34), val, 482 val & REG34_PLL_LOCK, 50, 20000); 483 if (ret) 484 dev_err(phy->dev, "PLL failed to lock\n"); 485 486 return ret; 487 } 488 489 static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, 490 unsigned long parent_rate) 491 { 492 struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); 493 494 if (!phy->cur_cfg) 495 return 74250000; 496 497 return phy->cur_cfg->pixclk; 498 } 499 500 /* Helper function to lookup the available fractional-divider rate */ 501 static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigned long rate) 502 { 503 int i; 504 505 /* Search the lookup table */ 506 for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--) 507 if (phy_pll_cfg[i].pixclk <= rate) 508 break; 509 510 return &phy_pll_cfg[i]; 511 } 512 513 static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, unsigned long rate, 514 u8 p, u16 m, u8 s) 515 { 516 cal_phy->pixclk = rate; 517 cal_phy->pll_div_regs[0] = FIELD_PREP(REG01_PMS_P_MASK, p); 518 cal_phy->pll_div_regs[1] = m; 519 cal_phy->pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1); 520 /* pll_div_regs 3-6 are fixed and pre-defined already */ 521 } 522 523 static u32 fsl_samsung_hdmi_phy_get_closest_rate(unsigned long rate, 524 u32 int_div_clk, u32 frac_div_clk) 525 { 526 /* Calculate the absolute value of the differences and return whichever is closest */ 527 if (abs((long)rate - (long)int_div_clk) < abs((long)(rate - (long)frac_div_clk))) 528 return int_div_clk; 529 530 return frac_div_clk; 531 } 532 533 static long phy_clk_round_rate(struct clk_hw *hw, 534 unsigned long rate, unsigned long *parent_rate) 535 { 536 const struct phy_config *fract_div_phy; 537 u32 int_div_clk; 538 u16 m; 539 u8 p, s; 540 541 /* If the clock is out of range return error instead of searching */ 542 if (rate > 297000000 || rate < 22250000) 543 return -EINVAL; 544 545 /* Search the fractional divider lookup table */ 546 fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate); 547 548 /* If the rate is an exact match, return that value */ 549 if (rate == fract_div_phy->pixclk) 550 return fract_div_phy->pixclk; 551 552 /* If the exact match isn't found, calculate the integer divider */ 553 int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); 554 555 /* If the int_div_clk rate is an exact match, return that value */ 556 if (int_div_clk == rate) 557 return int_div_clk; 558 559 /* If neither rate is an exact match, use the value from the LUT */ 560 return fract_div_phy->pixclk; 561 } 562 563 static int phy_use_fract_div(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *fract_div_phy) 564 { 565 phy->cur_cfg = fract_div_phy; 566 dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n", 567 phy->cur_cfg->pixclk); 568 return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); 569 } 570 571 static int phy_use_integer_div(struct fsl_samsung_hdmi_phy *phy, 572 const struct phy_config *int_div_clk) 573 { 574 phy->cur_cfg = &calculated_phy_pll_cfg; 575 dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n", 576 phy->cur_cfg->pixclk); 577 return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); 578 } 579 580 static int phy_clk_set_rate(struct clk_hw *hw, 581 unsigned long rate, unsigned long parent_rate) 582 { 583 struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw); 584 const struct phy_config *fract_div_phy; 585 u32 int_div_clk; 586 u16 m; 587 u8 p, s; 588 589 /* Search the fractional divider lookup table */ 590 fract_div_phy = fsl_samsung_hdmi_phy_lookup_rate(rate); 591 592 /* If the rate is an exact match, use that value */ 593 if (fract_div_phy->pixclk == rate) 594 return phy_use_fract_div(phy, fract_div_phy); 595 596 /* 597 * If the rate from the fractional divider is not exact, check the integer divider, 598 * and use it if that value is an exact match. 599 */ 600 int_div_clk = fsl_samsung_hdmi_phy_find_pms(rate, &p, &m, &s); 601 fsl_samsung_hdmi_calculate_phy(&calculated_phy_pll_cfg, int_div_clk, p, m, s); 602 if (int_div_clk == rate) 603 return phy_use_integer_div(phy, &calculated_phy_pll_cfg); 604 605 /* 606 * Compare the difference between the integer clock and the fractional clock against 607 * the desired clock and which whichever is closest. 608 */ 609 if (fsl_samsung_hdmi_phy_get_closest_rate(rate, int_div_clk, 610 fract_div_phy->pixclk) == fract_div_phy->pixclk) 611 return phy_use_fract_div(phy, fract_div_phy); 612 else 613 return phy_use_integer_div(phy, &calculated_phy_pll_cfg); 614 } 615 616 static const struct clk_ops phy_clk_ops = { 617 .recalc_rate = phy_clk_recalc_rate, 618 .round_rate = phy_clk_round_rate, 619 .set_rate = phy_clk_set_rate, 620 }; 621 622 static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) 623 { 624 struct device *dev = phy->dev; 625 struct device_node *np = dev->of_node; 626 struct clk_init_data init; 627 const char *parent_name; 628 struct clk *phyclk; 629 int ret; 630 631 parent_name = __clk_get_name(phy->refclk); 632 633 init.parent_names = &parent_name; 634 init.num_parents = 1; 635 init.flags = 0; 636 init.name = "hdmi_pclk"; 637 init.ops = &phy_clk_ops; 638 639 phy->hw.init = &init; 640 641 phyclk = devm_clk_register(dev, &phy->hw); 642 if (IS_ERR(phyclk)) 643 return dev_err_probe(dev, PTR_ERR(phyclk), 644 "failed to register clock\n"); 645 646 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); 647 if (ret) 648 return dev_err_probe(dev, ret, 649 "failed to register clock provider\n"); 650 651 return 0; 652 } 653 654 static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) 655 { 656 struct fsl_samsung_hdmi_phy *phy; 657 int ret; 658 659 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); 660 if (!phy) 661 return -ENOMEM; 662 663 platform_set_drvdata(pdev, phy); 664 phy->dev = &pdev->dev; 665 666 phy->regs = devm_platform_ioremap_resource(pdev, 0); 667 if (IS_ERR(phy->regs)) 668 return PTR_ERR(phy->regs); 669 670 phy->apbclk = devm_clk_get(phy->dev, "apb"); 671 if (IS_ERR(phy->apbclk)) 672 return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk), 673 "failed to get apb clk\n"); 674 675 phy->refclk = devm_clk_get(phy->dev, "ref"); 676 if (IS_ERR(phy->refclk)) 677 return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), 678 "failed to get ref clk\n"); 679 680 ret = clk_prepare_enable(phy->apbclk); 681 if (ret) { 682 dev_err(phy->dev, "failed to enable apbclk\n"); 683 return ret; 684 } 685 686 pm_runtime_get_noresume(phy->dev); 687 pm_runtime_set_active(phy->dev); 688 pm_runtime_enable(phy->dev); 689 690 ret = phy_clk_register(phy); 691 if (ret) { 692 dev_err(&pdev->dev, "register clk failed\n"); 693 goto register_clk_failed; 694 } 695 696 pm_runtime_put(phy->dev); 697 698 return 0; 699 700 register_clk_failed: 701 clk_disable_unprepare(phy->apbclk); 702 703 return ret; 704 } 705 706 static void fsl_samsung_hdmi_phy_remove(struct platform_device *pdev) 707 { 708 of_clk_del_provider(pdev->dev.of_node); 709 } 710 711 static int __maybe_unused fsl_samsung_hdmi_phy_suspend(struct device *dev) 712 { 713 struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); 714 715 clk_disable_unprepare(phy->apbclk); 716 717 return 0; 718 } 719 720 static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev) 721 { 722 struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev); 723 int ret = 0; 724 725 ret = clk_prepare_enable(phy->apbclk); 726 if (ret) { 727 dev_err(phy->dev, "failed to enable apbclk\n"); 728 return ret; 729 } 730 731 if (phy->cur_cfg) 732 ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); 733 734 return ret; 735 736 } 737 738 static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops, 739 fsl_samsung_hdmi_phy_suspend, 740 fsl_samsung_hdmi_phy_resume, NULL); 741 742 static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = { 743 { 744 .compatible = "fsl,imx8mp-hdmi-phy", 745 }, { 746 /* sentinel */ 747 } 748 }; 749 MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match); 750 751 static struct platform_driver fsl_samsung_hdmi_phy_driver = { 752 .probe = fsl_samsung_hdmi_phy_probe, 753 .remove = fsl_samsung_hdmi_phy_remove, 754 .driver = { 755 .name = "fsl-samsung-hdmi-phy", 756 .of_match_table = fsl_samsung_hdmi_phy_of_match, 757 .pm = pm_ptr(&fsl_samsung_hdmi_phy_pm_ops), 758 }, 759 }; 760 module_platform_driver(fsl_samsung_hdmi_phy_driver); 761 762 MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>"); 763 MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver"); 764 MODULE_LICENSE("GPL"); 765