1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cadence Torrent SD0801 PHY driver. 4 * 5 * Copyright 2018 Cadence Design Systems, Inc. 6 * 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-cadence.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/reset.h> 25 #include <linux/regmap.h> 26 27 #define REF_CLK_19_2MHZ 19200000 28 #define REF_CLK_25MHZ 25000000 29 #define REF_CLK_100MHZ 100000000 30 31 #define MAX_NUM_LANES 4 32 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ 33 34 #define NUM_SSC_MODE 3 35 #define NUM_REF_CLK 3 36 #define NUM_PHY_TYPE 6 37 38 #define POLL_TIMEOUT_US 5000 39 #define PLL_LOCK_TIMEOUT 100000 40 41 #define TORRENT_COMMON_CDB_OFFSET 0x0 42 43 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 44 ((0x4000 << (block_offset)) + \ 45 (((ln) << 9) << (reg_offset))) 46 47 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 48 ((0x8000 << (block_offset)) + \ 49 (((ln) << 9) << (reg_offset))) 50 51 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ 52 (0xC000 << (block_offset)) 53 54 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 55 ((0xD000 << (block_offset)) + \ 56 (((ln) << 8) << (reg_offset))) 57 58 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ 59 (0xE000 << (block_offset)) 60 61 #define TORRENT_DPTX_PHY_OFFSET 0x0 62 63 /* 64 * register offsets from DPTX PHY register block base (i.e MHDP 65 * register base + 0x30a00) 66 */ 67 #define PHY_AUX_CTRL 0x04 68 #define PHY_RESET 0x20 69 #define PMA_TX_ELEC_IDLE_MASK 0xF0U 70 #define PMA_TX_ELEC_IDLE_SHIFT 4 71 #define PHY_L00_RESET_N_MASK 0x01U 72 #define PHY_PMA_XCVR_PLLCLK_EN 0x24 73 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 74 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c 75 #define PHY_POWER_STATE_LN_0 0x0000 76 #define PHY_POWER_STATE_LN_1 0x0008 77 #define PHY_POWER_STATE_LN_2 0x0010 78 #define PHY_POWER_STATE_LN_3 0x0018 79 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU 80 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 81 #define PHY_PMA_CMN_READY 0x34 82 83 /* 84 * register offsets from SD0801 PHY register block base (i.e MHDP 85 * register base + 0x500000) 86 */ 87 #define CMN_SSM_BANDGAP_TMR 0x0021U 88 #define CMN_SSM_BIAS_TMR 0x0022U 89 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU 90 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU 91 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U 92 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U 93 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U 94 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U 95 #define CMN_CDIAG_REFCLK_OVRD 0x004CU 96 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U 97 #define CMN_BGCAL_INIT_TMR 0x0064U 98 #define CMN_BGCAL_ITER_TMR 0x0065U 99 #define CMN_IBCAL_INIT_TMR 0x0074U 100 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U 101 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U 102 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U 103 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U 104 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U 105 #define CMN_PLL0_INTDIV_M0 0x0090U 106 #define CMN_PLL0_FRACDIVL_M0 0x0091U 107 #define CMN_PLL0_FRACDIVH_M0 0x0092U 108 #define CMN_PLL0_HIGH_THR_M0 0x0093U 109 #define CMN_PLL0_DSM_DIAG_M0 0x0094U 110 #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U 111 #define CMN_PLL0_SS_CTRL1_M0 0x0098U 112 #define CMN_PLL0_SS_CTRL2_M0 0x0099U 113 #define CMN_PLL0_SS_CTRL3_M0 0x009AU 114 #define CMN_PLL0_SS_CTRL4_M0 0x009BU 115 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU 116 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU 117 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU 118 #define CMN_PLL0_INTDIV_M1 0x00A0U 119 #define CMN_PLL0_FRACDIVH_M1 0x00A2U 120 #define CMN_PLL0_HIGH_THR_M1 0x00A3U 121 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U 122 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U 123 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U 124 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU 125 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU 126 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U 127 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U 128 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U 129 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U 130 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U 131 #define CMN_PLL1_INTDIV_M0 0x00D0U 132 #define CMN_PLL1_FRACDIVL_M0 0x00D1U 133 #define CMN_PLL1_FRACDIVH_M0 0x00D2U 134 #define CMN_PLL1_HIGH_THR_M0 0x00D3U 135 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U 136 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U 137 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U 138 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U 139 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U 140 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU 141 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU 142 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU 143 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU 144 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU 145 #define CMN_TXPUCAL_TUNE 0x0103U 146 #define CMN_TXPUCAL_INIT_TMR 0x0104U 147 #define CMN_TXPUCAL_ITER_TMR 0x0105U 148 #define CMN_TXPDCAL_TUNE 0x010BU 149 #define CMN_TXPDCAL_INIT_TMR 0x010CU 150 #define CMN_TXPDCAL_ITER_TMR 0x010DU 151 #define CMN_RXCAL_INIT_TMR 0x0114U 152 #define CMN_RXCAL_ITER_TMR 0x0115U 153 #define CMN_SD_CAL_INIT_TMR 0x0124U 154 #define CMN_SD_CAL_ITER_TMR 0x0125U 155 #define CMN_SD_CAL_REFTIM_START 0x0126U 156 #define CMN_SD_CAL_PLLCNT_START 0x0128U 157 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U 158 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U 159 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U 160 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U 161 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U 162 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U 163 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U 164 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U 165 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U 166 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U 167 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U 168 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U 169 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U 170 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U 171 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U 172 #define CMN_DIAG_BIAS_OVRD1 0x01E1U 173 174 /* PMA TX Lane registers */ 175 #define TX_TXCC_CTRL 0x0040U 176 #define TX_TXCC_CPOST_MULT_00 0x004CU 177 #define TX_TXCC_CPOST_MULT_01 0x004DU 178 #define TX_TXCC_MGNFS_MULT_000 0x0050U 179 #define TX_TXCC_MGNFS_MULT_100 0x0054U 180 #define DRV_DIAG_TX_DRV 0x00C6U 181 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U 182 #define XCVR_DIAG_HSCLK_SEL 0x00E6U 183 #define XCVR_DIAG_HSCLK_DIV 0x00E7U 184 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U 185 #define XCVR_DIAG_BIDI_CTRL 0x00EAU 186 #define XCVR_DIAG_PSC_OVRD 0x00EBU 187 #define TX_PSC_A0 0x0100U 188 #define TX_PSC_A1 0x0101U 189 #define TX_PSC_A2 0x0102U 190 #define TX_PSC_A3 0x0103U 191 #define TX_RCVDET_ST_TMR 0x0123U 192 #define TX_DIAG_ACYA 0x01E7U 193 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U 194 195 /* PMA RX Lane registers */ 196 #define RX_PSC_A0 0x0000U 197 #define RX_PSC_A1 0x0001U 198 #define RX_PSC_A2 0x0002U 199 #define RX_PSC_A3 0x0003U 200 #define RX_PSC_CAL 0x0006U 201 #define RX_CDRLF_CNFG 0x0080U 202 #define RX_CDRLF_CNFG3 0x0082U 203 #define RX_SIGDET_HL_FILT_TMR 0x0090U 204 #define RX_REE_GCSM1_CTRL 0x0108U 205 #define RX_REE_GCSM1_EQENM_PH1 0x0109U 206 #define RX_REE_GCSM1_EQENM_PH2 0x010AU 207 #define RX_REE_GCSM2_CTRL 0x0110U 208 #define RX_REE_PERGCSM_CTRL 0x0118U 209 #define RX_REE_ATTEN_THR 0x0149U 210 #define RX_REE_TAP1_CLIP 0x0171U 211 #define RX_REE_TAP2TON_CLIP 0x0172U 212 #define RX_REE_SMGM_CTRL1 0x0177U 213 #define RX_REE_SMGM_CTRL2 0x0178U 214 #define RX_DIAG_DFE_CTRL 0x01E0U 215 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U 216 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U 217 #define RX_DIAG_NQST_CTRL 0x01E5U 218 #define RX_DIAG_SIGDET_TUNE 0x01E8U 219 #define RX_DIAG_PI_RATE 0x01F4U 220 #define RX_DIAG_PI_CAP 0x01F5U 221 #define RX_DIAG_ACYA 0x01FFU 222 223 /* PHY PCS common registers */ 224 #define PHY_PIPE_CMN_CTRL1 0x0000U 225 #define PHY_PLL_CFG 0x000EU 226 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U 227 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U 228 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U 229 230 /* PHY PCS lane registers */ 231 #define PHY_PCS_ISO_LINK_CTRL 0x000BU 232 233 /* PHY PMA common registers */ 234 #define PHY_PMA_CMN_CTRL1 0x0000U 235 #define PHY_PMA_CMN_CTRL2 0x0001U 236 #define PHY_PMA_PLL_RAW_CTRL 0x0003U 237 238 #define CDNS_TORRENT_OUTPUT_CLOCKS 3 239 240 static const char * const clk_names[] = { 241 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", 242 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der", 243 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec", 244 }; 245 246 static const struct reg_field phy_pll_cfg = 247 REG_FIELD(PHY_PLL_CFG, 0, 1); 248 249 static const struct reg_field phy_pma_cmn_ctrl_1 = 250 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0); 251 252 static const struct reg_field phy_pma_cmn_ctrl_2 = 253 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); 254 255 static const struct reg_field phy_pma_pll_raw_ctrl = 256 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); 257 258 static const struct reg_field phy_reset_ctrl = 259 REG_FIELD(PHY_RESET, 8, 8); 260 261 static const struct reg_field phy_pcs_iso_link_ctrl_1 = 262 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1); 263 264 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0); 265 266 static const struct reg_field cmn_cdiag_refclk_ovrd_4 = 267 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4); 268 269 #define REFCLK_OUT_NUM_CMN_CONFIG 4 270 271 enum cdns_torrent_refclk_out_cmn { 272 CMN_CDIAG_REFCLK_DRV0_CTRL_1, 273 CMN_CDIAG_REFCLK_DRV0_CTRL_4, 274 CMN_CDIAG_REFCLK_DRV0_CTRL_5, 275 CMN_CDIAG_REFCLK_DRV0_CTRL_6, 276 }; 277 278 static const struct reg_field refclk_out_cmn_cfg[] = { 279 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), 280 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), 281 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), 282 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), 283 }; 284 285 static const int refclk_driver_parent_index[] = { 286 CDNS_TORRENT_DERIVED_REFCLK, 287 CDNS_TORRENT_RECEIVED_REFCLK 288 }; 289 290 static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 }; 291 292 enum cdns_torrent_phy_type { 293 TYPE_NONE, 294 TYPE_DP, 295 TYPE_PCIE, 296 TYPE_SGMII, 297 TYPE_QSGMII, 298 TYPE_USB, 299 }; 300 301 enum cdns_torrent_ref_clk { 302 CLK_19_2_MHZ, 303 CLK_25_MHZ, 304 CLK_100_MHZ 305 }; 306 307 enum cdns_torrent_ssc_mode { 308 NO_SSC, 309 EXTERNAL_SSC, 310 INTERNAL_SSC 311 }; 312 313 struct cdns_torrent_inst { 314 struct phy *phy; 315 u32 mlane; 316 enum cdns_torrent_phy_type phy_type; 317 u32 num_lanes; 318 struct reset_control *lnk_rst; 319 enum cdns_torrent_ssc_mode ssc_mode; 320 }; 321 322 struct cdns_torrent_phy { 323 void __iomem *base; /* DPTX registers base */ 324 void __iomem *sd_base; /* SD0801 registers base */ 325 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ 326 struct reset_control *phy_rst; 327 struct reset_control *apb_rst; 328 struct device *dev; 329 struct clk *clk; 330 enum cdns_torrent_ref_clk ref_clk_rate; 331 struct cdns_torrent_inst phys[MAX_NUM_LANES]; 332 int nsubnodes; 333 const struct cdns_torrent_data *init_data; 334 struct regmap *regmap_common_cdb; 335 struct regmap *regmap_phy_pcs_common_cdb; 336 struct regmap *regmap_phy_pma_common_cdb; 337 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; 338 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; 339 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES]; 340 struct regmap *regmap_dptx_phy_reg; 341 struct regmap_field *phy_pll_cfg; 342 struct regmap_field *phy_pipe_cmn_ctrl1_0; 343 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 344 struct regmap_field *phy_pma_cmn_ctrl_1; 345 struct regmap_field *phy_pma_cmn_ctrl_2; 346 struct regmap_field *phy_pma_pll_raw_ctrl; 347 struct regmap_field *phy_reset_ctrl; 348 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES]; 349 struct clk_hw_onecell_data *clk_hw_data; 350 }; 351 352 enum phy_powerstate { 353 POWERSTATE_A0 = 0, 354 /* Powerstate A1 is unused */ 355 POWERSTATE_A2 = 2, 356 POWERSTATE_A3 = 3, 357 }; 358 359 struct cdns_torrent_refclk_driver { 360 struct clk_hw hw; 361 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG]; 362 struct clk_init_data clk_data; 363 }; 364 365 #define to_cdns_torrent_refclk_driver(_hw) \ 366 container_of(_hw, struct cdns_torrent_refclk_driver, hw) 367 368 struct cdns_torrent_derived_refclk { 369 struct clk_hw hw; 370 struct regmap_field *phy_pipe_cmn_ctrl1_0; 371 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 372 struct clk_init_data clk_data; 373 }; 374 375 #define to_cdns_torrent_derived_refclk(_hw) \ 376 container_of(_hw, struct cdns_torrent_derived_refclk, hw) 377 378 struct cdns_torrent_received_refclk { 379 struct clk_hw hw; 380 struct regmap_field *phy_pipe_cmn_ctrl1_0; 381 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 382 struct clk_init_data clk_data; 383 }; 384 385 #define to_cdns_torrent_received_refclk(_hw) \ 386 container_of(_hw, struct cdns_torrent_received_refclk, hw) 387 388 struct cdns_reg_pairs { 389 u32 val; 390 u32 off; 391 }; 392 393 struct cdns_torrent_vals { 394 struct cdns_reg_pairs *reg_pairs; 395 u32 num_regs; 396 }; 397 398 struct cdns_torrent_data { 399 u8 block_offset_shift; 400 u8 reg_offset_shift; 401 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 402 [NUM_SSC_MODE]; 403 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 404 [NUM_SSC_MODE]; 405 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 406 [NUM_SSC_MODE]; 407 struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE] 408 [NUM_PHY_TYPE][NUM_SSC_MODE]; 409 struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE] 410 [NUM_PHY_TYPE][NUM_SSC_MODE]; 411 struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE] 412 [NUM_PHY_TYPE][NUM_SSC_MODE]; 413 }; 414 415 struct cdns_regmap_cdb_context { 416 struct device *dev; 417 void __iomem *base; 418 u8 reg_offset_shift; 419 }; 420 421 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 422 { 423 struct cdns_regmap_cdb_context *ctx = context; 424 u32 offset = reg << ctx->reg_offset_shift; 425 426 writew(val, ctx->base + offset); 427 428 return 0; 429 } 430 431 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 432 { 433 struct cdns_regmap_cdb_context *ctx = context; 434 u32 offset = reg << ctx->reg_offset_shift; 435 436 *val = readw(ctx->base + offset); 437 return 0; 438 } 439 440 static int cdns_regmap_dptx_write(void *context, unsigned int reg, 441 unsigned int val) 442 { 443 struct cdns_regmap_cdb_context *ctx = context; 444 u32 offset = reg; 445 446 writel(val, ctx->base + offset); 447 448 return 0; 449 } 450 451 static int cdns_regmap_dptx_read(void *context, unsigned int reg, 452 unsigned int *val) 453 { 454 struct cdns_regmap_cdb_context *ctx = context; 455 u32 offset = reg; 456 457 *val = readl(ctx->base + offset); 458 return 0; 459 } 460 461 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ 462 { \ 463 .name = "torrent_tx_lane" n "_cdb", \ 464 .reg_stride = 1, \ 465 .fast_io = true, \ 466 .reg_write = cdns_regmap_write, \ 467 .reg_read = cdns_regmap_read, \ 468 } 469 470 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ 471 { \ 472 .name = "torrent_rx_lane" n "_cdb", \ 473 .reg_stride = 1, \ 474 .fast_io = true, \ 475 .reg_write = cdns_regmap_write, \ 476 .reg_read = cdns_regmap_read, \ 477 } 478 479 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { 480 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), 481 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), 482 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), 483 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), 484 }; 485 486 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { 487 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), 488 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), 489 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), 490 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), 491 }; 492 493 static const struct regmap_config cdns_torrent_common_cdb_config = { 494 .name = "torrent_common_cdb", 495 .reg_stride = 1, 496 .fast_io = true, 497 .reg_write = cdns_regmap_write, 498 .reg_read = cdns_regmap_read, 499 }; 500 501 #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 502 { \ 503 .name = "torrent_phy_pcs_lane" n "_cdb", \ 504 .reg_stride = 1, \ 505 .fast_io = true, \ 506 .reg_write = cdns_regmap_write, \ 507 .reg_read = cdns_regmap_read, \ 508 } 509 510 static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = { 511 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 512 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 513 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 514 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 515 }; 516 517 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { 518 .name = "torrent_phy_pcs_cmn_cdb", 519 .reg_stride = 1, 520 .fast_io = true, 521 .reg_write = cdns_regmap_write, 522 .reg_read = cdns_regmap_read, 523 }; 524 525 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { 526 .name = "torrent_phy_pma_cmn_cdb", 527 .reg_stride = 1, 528 .fast_io = true, 529 .reg_write = cdns_regmap_write, 530 .reg_read = cdns_regmap_read, 531 }; 532 533 static const struct regmap_config cdns_torrent_dptx_phy_config = { 534 .name = "torrent_dptx_phy", 535 .reg_stride = 1, 536 .fast_io = true, 537 .reg_write = cdns_regmap_dptx_write, 538 .reg_read = cdns_regmap_dptx_read, 539 }; 540 541 /* PHY mmr access functions */ 542 543 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) 544 { 545 regmap_write(regmap, offset, val); 546 } 547 548 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) 549 { 550 unsigned int val; 551 552 regmap_read(regmap, offset, &val); 553 return val; 554 } 555 556 /* DPTX mmr access functions */ 557 558 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) 559 { 560 regmap_write(regmap, offset, val); 561 } 562 563 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) 564 { 565 u32 val; 566 567 regmap_read(regmap, offset, &val); 568 return val; 569 } 570 571 /* 572 * Structure used to store values of PHY registers for voltage-related 573 * coefficients, for particular voltage swing and pre-emphasis level. Values 574 * are shared across all physical lanes. 575 */ 576 struct coefficients { 577 /* Value of DRV_DIAG_TX_DRV register to use */ 578 u16 diag_tx_drv; 579 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ 580 u16 mgnfs_mult; 581 /* Value of TX_TXCC_CPOST_MULT_00 register to use */ 582 u16 cpost_mult; 583 }; 584 585 /* 586 * Array consists of values of voltage-related registers for sd0801 PHY. A value 587 * of 0xFFFF is a placeholder for invalid combination, and will never be used. 588 */ 589 static const struct coefficients vltg_coeff[4][4] = { 590 /* voltage swing 0, pre-emphasis 0->3 */ 591 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, 592 .cpost_mult = 0x0000}, 593 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 594 .cpost_mult = 0x0014}, 595 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, 596 .cpost_mult = 0x0020}, 597 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 598 .cpost_mult = 0x002A} 599 }, 600 601 /* voltage swing 1, pre-emphasis 0->3 */ 602 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 603 .cpost_mult = 0x0000}, 604 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 605 .cpost_mult = 0x0012}, 606 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 607 .cpost_mult = 0x001F}, 608 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 609 .cpost_mult = 0xFFFF} 610 }, 611 612 /* voltage swing 2, pre-emphasis 0->3 */ 613 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 614 .cpost_mult = 0x0000}, 615 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 616 .cpost_mult = 0x0013}, 617 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 618 .cpost_mult = 0xFFFF}, 619 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 620 .cpost_mult = 0xFFFF} 621 }, 622 623 /* voltage swing 3, pre-emphasis 0->3 */ 624 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 625 .cpost_mult = 0x0000}, 626 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 627 .cpost_mult = 0xFFFF}, 628 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 629 .cpost_mult = 0xFFFF}, 630 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 631 .cpost_mult = 0xFFFF} 632 } 633 }; 634 635 static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type) 636 { 637 switch (phy_type) { 638 case TYPE_DP: 639 return "DisplayPort"; 640 case TYPE_PCIE: 641 return "PCIe"; 642 case TYPE_SGMII: 643 return "SGMII"; 644 case TYPE_QSGMII: 645 return "QSGMII"; 646 case TYPE_USB: 647 return "USB"; 648 default: 649 return "None"; 650 } 651 } 652 653 /* 654 * Set registers responsible for enabling and configuring SSC, with second and 655 * third register values provided by parameters. 656 */ 657 static 658 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, 659 u32 ctrl2_val, u32 ctrl3_val) 660 { 661 struct regmap *regmap = cdns_phy->regmap_common_cdb; 662 663 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 664 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 665 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); 666 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 667 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 668 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 669 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); 670 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 671 } 672 673 static 674 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, 675 u32 rate, bool ssc) 676 { 677 struct regmap *regmap = cdns_phy->regmap_common_cdb; 678 679 /* Assumes 19.2 MHz refclock */ 680 switch (rate) { 681 /* Setting VCO for 10.8GHz */ 682 case 2700: 683 case 5400: 684 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119); 685 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 686 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 687 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC); 688 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012); 689 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119); 690 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 691 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 692 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC); 693 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012); 694 if (ssc) 695 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A); 696 break; 697 /* Setting VCO for 9.72GHz */ 698 case 1620: 699 case 2430: 700 case 3240: 701 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA); 702 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 703 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 704 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152); 705 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 706 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA); 707 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 708 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 709 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152); 710 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 711 if (ssc) 712 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069); 713 break; 714 /* Setting VCO for 8.64GHz */ 715 case 2160: 716 case 4320: 717 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2); 718 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 719 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 720 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C); 721 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 722 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2); 723 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 724 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 725 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C); 726 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 727 if (ssc) 728 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069); 729 break; 730 /* Setting VCO for 8.1GHz */ 731 case 8100: 732 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5); 733 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000); 734 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 735 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A); 736 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 737 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5); 738 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000); 739 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 740 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A); 741 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 742 if (ssc) 743 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A); 744 break; 745 } 746 747 if (ssc) { 748 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); 749 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 750 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); 751 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 752 } else { 753 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); 754 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); 755 /* Set reset register values to disable SSC */ 756 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 757 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 758 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 759 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 760 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 761 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 762 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 763 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 764 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 765 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 766 } 767 768 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); 769 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); 770 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); 771 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); 772 } 773 774 /* 775 * Set registers responsible for enabling and configuring SSC, with second 776 * register value provided by a parameter. 777 */ 778 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, 779 u32 ctrl2_val) 780 { 781 struct regmap *regmap = cdns_phy->regmap_common_cdb; 782 783 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 784 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 785 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); 786 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 787 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 788 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 789 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); 790 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 791 } 792 793 static 794 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, 795 u32 rate, bool ssc) 796 { 797 struct regmap *regmap = cdns_phy->regmap_common_cdb; 798 799 /* Assumes 25 MHz refclock */ 800 switch (rate) { 801 /* Setting VCO for 10.8GHz */ 802 case 2700: 803 case 5400: 804 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); 805 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 806 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 807 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); 808 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); 809 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 810 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 811 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); 812 if (ssc) 813 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); 814 break; 815 /* Setting VCO for 9.72GHz */ 816 case 1620: 817 case 2430: 818 case 3240: 819 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); 820 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); 821 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 822 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); 823 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); 824 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); 825 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 826 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); 827 if (ssc) 828 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); 829 break; 830 /* Setting VCO for 8.64GHz */ 831 case 2160: 832 case 4320: 833 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); 834 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); 835 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 836 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); 837 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); 838 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); 839 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 840 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); 841 if (ssc) 842 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); 843 break; 844 /* Setting VCO for 8.1GHz */ 845 case 8100: 846 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); 847 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 848 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 849 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); 850 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); 851 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 852 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 853 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); 854 if (ssc) 855 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); 856 break; 857 } 858 859 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 860 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 861 862 if (ssc) { 863 cdns_torrent_phy_write(regmap, 864 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); 865 cdns_torrent_phy_write(regmap, 866 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 867 cdns_torrent_phy_write(regmap, 868 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); 869 cdns_torrent_phy_write(regmap, 870 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 871 } else { 872 cdns_torrent_phy_write(regmap, 873 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); 874 cdns_torrent_phy_write(regmap, 875 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); 876 /* Set reset register values to disable SSC */ 877 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 878 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 879 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 880 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 881 cdns_torrent_phy_write(regmap, 882 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 883 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 884 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 885 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 886 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 887 cdns_torrent_phy_write(regmap, 888 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 889 } 890 891 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); 892 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); 893 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); 894 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); 895 } 896 897 static 898 void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy, 899 u32 rate, bool ssc) 900 { 901 struct regmap *regmap = cdns_phy->regmap_common_cdb; 902 903 /* Assumes 100 MHz refclock */ 904 switch (rate) { 905 /* Setting VCO for 10.8GHz */ 906 case 2700: 907 case 5400: 908 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028); 909 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022); 910 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022); 911 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C); 912 break; 913 /* Setting VCO for 9.72GHz */ 914 case 1620: 915 case 2430: 916 case 3240: 917 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 918 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 919 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 920 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 921 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 922 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 923 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 925 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061); 926 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061); 927 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333); 928 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333); 929 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 930 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 931 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042); 932 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042); 933 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 934 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 935 break; 936 /* Setting VCO for 8.64GHz */ 937 case 2160: 938 case 4320: 939 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 940 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 941 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 942 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 943 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 944 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 945 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 946 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 947 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056); 948 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056); 949 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666); 950 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666); 951 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 952 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 953 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A); 954 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A); 955 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 956 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 957 break; 958 /* Setting VCO for 8.1GHz */ 959 case 8100: 960 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 961 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 962 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 963 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 964 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 965 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 966 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 967 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 968 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051); 969 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051); 970 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 971 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 972 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036); 973 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036); 974 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 975 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 976 break; 977 } 978 } 979 980 /* 981 * Enable or disable PLL for selected lanes. 982 */ 983 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, 984 struct phy_configure_opts_dp *dp, 985 bool enable) 986 { 987 u32 rd_val; 988 u32 ret; 989 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 990 991 /* 992 * Used to determine, which bits to check for or enable in 993 * PHY_PMA_XCVR_PLLCLK_EN register. 994 */ 995 u32 pll_bits; 996 /* Used to enable or disable lanes. */ 997 u32 pll_val; 998 999 /* Select values of registers and mask, depending on enabled lane 1000 * count. 1001 */ 1002 switch (dp->lanes) { 1003 /* lane 0 */ 1004 case (1): 1005 pll_bits = 0x00000001; 1006 break; 1007 /* lanes 0-1 */ 1008 case (2): 1009 pll_bits = 0x00000003; 1010 break; 1011 /* lanes 0-3, all */ 1012 default: 1013 pll_bits = 0x0000000F; 1014 break; 1015 } 1016 1017 if (enable) 1018 pll_val = pll_bits; 1019 else 1020 pll_val = 0x00000000; 1021 1022 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val); 1023 1024 /* Wait for acknowledgment from PHY. */ 1025 ret = regmap_read_poll_timeout(regmap, 1026 PHY_PMA_XCVR_PLLCLK_EN_ACK, 1027 rd_val, 1028 (rd_val & pll_bits) == pll_val, 1029 0, POLL_TIMEOUT_US); 1030 ndelay(100); 1031 return ret; 1032 } 1033 1034 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, 1035 u32 num_lanes, 1036 enum phy_powerstate powerstate) 1037 { 1038 /* Register value for power state for a single byte. */ 1039 u32 value_part; 1040 u32 value; 1041 u32 mask; 1042 u32 read_val; 1043 u32 ret; 1044 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1045 1046 switch (powerstate) { 1047 case (POWERSTATE_A0): 1048 value_part = 0x01U; 1049 break; 1050 case (POWERSTATE_A2): 1051 value_part = 0x04U; 1052 break; 1053 default: 1054 /* Powerstate A3 */ 1055 value_part = 0x08U; 1056 break; 1057 } 1058 1059 /* Select values of registers and mask, depending on enabled 1060 * lane count. 1061 */ 1062 switch (num_lanes) { 1063 /* lane 0 */ 1064 case (1): 1065 value = value_part; 1066 mask = 0x0000003FU; 1067 break; 1068 /* lanes 0-1 */ 1069 case (2): 1070 value = (value_part 1071 | (value_part << 8)); 1072 mask = 0x00003F3FU; 1073 break; 1074 /* lanes 0-3, all */ 1075 default: 1076 value = (value_part 1077 | (value_part << 8) 1078 | (value_part << 16) 1079 | (value_part << 24)); 1080 mask = 0x3F3F3F3FU; 1081 break; 1082 } 1083 1084 /* Set power state A<n>. */ 1085 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value); 1086 /* Wait, until PHY acknowledges power state completion. */ 1087 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK, 1088 read_val, (read_val & mask) == value, 0, 1089 POLL_TIMEOUT_US); 1090 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000); 1091 ndelay(100); 1092 1093 return ret; 1094 } 1095 1096 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) 1097 { 1098 unsigned int read_val; 1099 int ret; 1100 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1101 1102 /* 1103 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the 1104 * master lane 1105 */ 1106 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK, 1107 read_val, read_val & 1, 1108 0, POLL_TIMEOUT_US); 1109 if (ret == -ETIMEDOUT) { 1110 dev_err(cdns_phy->dev, 1111 "timeout waiting for link PLL clock enable ack\n"); 1112 return ret; 1113 } 1114 1115 ndelay(100); 1116 1117 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, 1118 POWERSTATE_A2); 1119 if (ret) 1120 return ret; 1121 1122 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, 1123 POWERSTATE_A0); 1124 1125 return ret; 1126 } 1127 1128 static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) 1129 { 1130 unsigned int reg; 1131 int ret; 1132 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1133 1134 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg, 1135 reg & 1, 0, POLL_TIMEOUT_US); 1136 if (ret == -ETIMEDOUT) { 1137 dev_err(cdns_phy->dev, 1138 "timeout waiting for PMA common ready\n"); 1139 return -ETIMEDOUT; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, 1146 u32 rate, u32 num_lanes) 1147 { 1148 unsigned int clk_sel_val = 0; 1149 unsigned int hsclk_div_val = 0; 1150 unsigned int i; 1151 1152 switch (rate) { 1153 case 1620: 1154 clk_sel_val = 0x0f01; 1155 hsclk_div_val = 2; 1156 break; 1157 case 2160: 1158 case 2430: 1159 case 2700: 1160 clk_sel_val = 0x0701; 1161 hsclk_div_val = 1; 1162 break; 1163 case 3240: 1164 clk_sel_val = 0x0b00; 1165 hsclk_div_val = 2; 1166 break; 1167 case 4320: 1168 case 5400: 1169 clk_sel_val = 0x0301; 1170 hsclk_div_val = 0; 1171 break; 1172 case 8100: 1173 clk_sel_val = 0x0200; 1174 hsclk_div_val = 0; 1175 break; 1176 } 1177 1178 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1179 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); 1180 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1181 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); 1182 1183 /* PMA lane configuration to deal with multi-link operation */ 1184 for (i = 0; i < num_lanes; i++) 1185 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i], 1186 XCVR_DIAG_HSCLK_DIV, hsclk_div_val); 1187 } 1188 1189 /* 1190 * Perform register operations related to setting link rate, once powerstate is 1191 * set and PLL disable request was processed. 1192 */ 1193 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, 1194 struct phy_configure_opts_dp *dp) 1195 { 1196 u32 read_val, ret; 1197 1198 /* Disable the cmn_pll0_en before re-programming the new data rate. */ 1199 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0); 1200 1201 /* 1202 * Wait for PLL ready de-assertion. 1203 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 1204 */ 1205 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1206 read_val, 1207 ((read_val >> 2) & 0x01) != 0, 1208 0, POLL_TIMEOUT_US); 1209 if (ret) 1210 return ret; 1211 ndelay(200); 1212 1213 /* DP Rate Change - VCO Output settings. */ 1214 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1215 /* PMA common configuration 19.2MHz */ 1216 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc); 1217 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1218 /* PMA common configuration 25MHz */ 1219 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc); 1220 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1221 /* PMA common configuration 100MHz */ 1222 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc); 1223 1224 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes); 1225 1226 /* Enable the cmn_pll0_en. */ 1227 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3); 1228 1229 /* 1230 * Wait for PLL ready assertion. 1231 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 1232 */ 1233 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1234 read_val, 1235 (read_val & 0x01) != 0, 1236 0, POLL_TIMEOUT_US); 1237 return ret; 1238 } 1239 1240 /* 1241 * Verify, that parameters to configure PHY with are correct. 1242 */ 1243 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, 1244 struct phy_configure_opts_dp *dp) 1245 { 1246 u8 i; 1247 1248 /* If changing link rate was required, verify it's supported. */ 1249 if (dp->set_rate) { 1250 switch (dp->link_rate) { 1251 case 1620: 1252 case 2160: 1253 case 2430: 1254 case 2700: 1255 case 3240: 1256 case 4320: 1257 case 5400: 1258 case 8100: 1259 /* valid bit rate */ 1260 break; 1261 default: 1262 return -EINVAL; 1263 } 1264 } 1265 1266 /* Verify lane count. */ 1267 switch (dp->lanes) { 1268 case 1: 1269 case 2: 1270 case 4: 1271 /* valid lane count. */ 1272 break; 1273 default: 1274 return -EINVAL; 1275 } 1276 1277 /* Check against actual number of PHY's lanes. */ 1278 if (dp->lanes > inst->num_lanes) 1279 return -EINVAL; 1280 1281 /* 1282 * If changing voltages is required, check swing and pre-emphasis 1283 * levels, per-lane. 1284 */ 1285 if (dp->set_voltages) { 1286 /* Lane count verified previously. */ 1287 for (i = 0; i < dp->lanes; i++) { 1288 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1289 return -EINVAL; 1290 1291 /* Sum of voltage swing and pre-emphasis levels cannot 1292 * exceed 3. 1293 */ 1294 if (dp->voltage[i] + dp->pre[i] > 3) 1295 return -EINVAL; 1296 } 1297 } 1298 1299 return 0; 1300 } 1301 1302 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ 1303 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, 1304 u32 num_lanes) 1305 { 1306 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1307 u32 pwr_state = cdns_torrent_dp_read(regmap, 1308 PHY_PMA_XCVR_POWER_STATE_REQ); 1309 u32 pll_clk_en = cdns_torrent_dp_read(regmap, 1310 PHY_PMA_XCVR_PLLCLK_EN); 1311 1312 /* Lane 0 is always enabled. */ 1313 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1314 PHY_POWER_STATE_LN_0); 1315 pll_clk_en &= ~0x01U; 1316 1317 if (num_lanes > 1) { 1318 /* lane 1 */ 1319 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1320 PHY_POWER_STATE_LN_1); 1321 pll_clk_en &= ~(0x01U << 1); 1322 } 1323 1324 if (num_lanes > 2) { 1325 /* lanes 2 and 3 */ 1326 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1327 PHY_POWER_STATE_LN_2); 1328 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1329 PHY_POWER_STATE_LN_3); 1330 pll_clk_en &= ~(0x01U << 2); 1331 pll_clk_en &= ~(0x01U << 3); 1332 } 1333 1334 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); 1335 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); 1336 } 1337 1338 /* Configure lane count as required. */ 1339 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, 1340 struct phy_configure_opts_dp *dp) 1341 { 1342 u32 value; 1343 u32 ret; 1344 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1345 u8 lane_mask = (1 << dp->lanes) - 1; 1346 1347 value = cdns_torrent_dp_read(regmap, PHY_RESET); 1348 /* clear pma_tx_elec_idle_ln_* bits. */ 1349 value &= ~PMA_TX_ELEC_IDLE_MASK; 1350 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ 1351 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & 1352 PMA_TX_ELEC_IDLE_MASK; 1353 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1354 1355 /* reset the link by asserting phy_l00_reset_n low */ 1356 cdns_torrent_dp_write(regmap, PHY_RESET, 1357 value & (~PHY_L00_RESET_N_MASK)); 1358 1359 /* 1360 * Assert lane reset on unused lanes and lane 0 so they remain in reset 1361 * and powered down when re-enabling the link 1362 */ 1363 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask); 1364 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1365 1366 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes); 1367 1368 /* release phy_l0*_reset_n based on used laneCount */ 1369 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask); 1370 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1371 1372 /* Wait, until PHY gets ready after releasing PHY reset signal. */ 1373 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1374 if (ret) 1375 return ret; 1376 1377 ndelay(100); 1378 1379 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1380 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); 1381 1382 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes); 1383 1384 return ret; 1385 } 1386 1387 /* Configure link rate as required. */ 1388 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, 1389 struct phy_configure_opts_dp *dp) 1390 { 1391 u32 ret; 1392 1393 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 1394 POWERSTATE_A3); 1395 if (ret) 1396 return ret; 1397 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false); 1398 if (ret) 1399 return ret; 1400 ndelay(200); 1401 1402 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp); 1403 if (ret) 1404 return ret; 1405 ndelay(200); 1406 1407 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true); 1408 if (ret) 1409 return ret; 1410 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 1411 POWERSTATE_A2); 1412 if (ret) 1413 return ret; 1414 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 1415 POWERSTATE_A0); 1416 if (ret) 1417 return ret; 1418 ndelay(900); 1419 1420 return ret; 1421 } 1422 1423 /* Configure voltage swing and pre-emphasis for all enabled lanes. */ 1424 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, 1425 struct phy_configure_opts_dp *dp) 1426 { 1427 u8 lane; 1428 u16 val; 1429 1430 for (lane = 0; lane < dp->lanes; lane++) { 1431 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], 1432 TX_DIAG_ACYA); 1433 /* 1434 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the 1435 * current state of the analog TX driver. 1436 */ 1437 val |= TX_DIAG_ACYA_HBDC_MASK; 1438 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1439 TX_DIAG_ACYA, val); 1440 1441 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1442 TX_TXCC_CTRL, 0x08A4); 1443 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; 1444 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1445 DRV_DIAG_TX_DRV, val); 1446 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; 1447 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1448 TX_TXCC_MGNFS_MULT_000, 1449 val); 1450 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; 1451 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1452 TX_TXCC_CPOST_MULT_00, 1453 val); 1454 1455 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], 1456 TX_DIAG_ACYA); 1457 /* 1458 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of 1459 * analog TX driver to reflect the new programmed one. 1460 */ 1461 val &= ~TX_DIAG_ACYA_HBDC_MASK; 1462 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1463 TX_DIAG_ACYA, val); 1464 } 1465 }; 1466 1467 static int cdns_torrent_dp_configure(struct phy *phy, 1468 union phy_configure_opts *opts) 1469 { 1470 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1471 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1472 int ret; 1473 1474 ret = cdns_torrent_dp_verify_config(inst, &opts->dp); 1475 if (ret) { 1476 dev_err(&phy->dev, "invalid params for phy configure\n"); 1477 return ret; 1478 } 1479 1480 if (opts->dp.set_lanes) { 1481 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp); 1482 if (ret) { 1483 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); 1484 return ret; 1485 } 1486 } 1487 1488 if (opts->dp.set_rate) { 1489 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp); 1490 if (ret) { 1491 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); 1492 return ret; 1493 } 1494 } 1495 1496 if (opts->dp.set_voltages) 1497 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp); 1498 1499 return ret; 1500 } 1501 1502 static int cdns_torrent_phy_on(struct phy *phy) 1503 { 1504 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1505 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1506 u32 read_val; 1507 int ret; 1508 1509 if (cdns_phy->nsubnodes == 1) { 1510 /* Take the PHY lane group out of reset */ 1511 reset_control_deassert(inst->lnk_rst); 1512 1513 /* Take the PHY out of reset */ 1514 ret = reset_control_deassert(cdns_phy->phy_rst); 1515 if (ret) 1516 return ret; 1517 } 1518 1519 /* 1520 * Wait for cmn_ready assertion 1521 * PHY_PMA_CMN_CTRL1[0] == 1 1522 */ 1523 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1, 1524 read_val, read_val, 1000, 1525 PLL_LOCK_TIMEOUT); 1526 if (ret) { 1527 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n"); 1528 return ret; 1529 } 1530 1531 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) { 1532 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane], 1533 read_val, !read_val, 1000, 1534 PLL_LOCK_TIMEOUT); 1535 if (ret == -ETIMEDOUT) { 1536 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n"); 1537 return ret; 1538 } 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int cdns_torrent_phy_off(struct phy *phy) 1545 { 1546 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1547 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1548 int ret; 1549 1550 if (cdns_phy->nsubnodes != 1) 1551 return 0; 1552 1553 ret = reset_control_assert(cdns_phy->phy_rst); 1554 if (ret) 1555 return ret; 1556 1557 return reset_control_assert(inst->lnk_rst); 1558 } 1559 1560 static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy, 1561 struct cdns_torrent_inst *inst) 1562 { 1563 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1564 unsigned char lane_bits; 1565 1566 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */ 1567 1568 /* 1569 * Set lines power state to A0 1570 * Set lines pll clk enable to 0 1571 */ 1572 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes); 1573 1574 /* 1575 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on 1576 * used lanes 1577 */ 1578 lane_bits = (1 << inst->num_lanes) - 1; 1579 cdns_torrent_dp_write(regmap, PHY_RESET, 1580 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits)); 1581 1582 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1583 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); 1584 1585 /* 1586 * PHY PMA registers configuration functions 1587 * Initialize PHY with max supported link rate, without SSC. 1588 */ 1589 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1590 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, 1591 cdns_phy->max_bit_rate, 1592 false); 1593 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1594 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, 1595 cdns_phy->max_bit_rate, 1596 false); 1597 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1598 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, 1599 cdns_phy->max_bit_rate, 1600 false); 1601 1602 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate, 1603 inst->num_lanes); 1604 1605 /* take out of reset */ 1606 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1); 1607 } 1608 1609 static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy, 1610 struct cdns_torrent_inst *inst, 1611 struct phy *phy) 1612 { 1613 int ret; 1614 1615 cdns_torrent_phy_on(phy); 1616 1617 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1618 if (ret) 1619 return ret; 1620 1621 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes); 1622 1623 return ret; 1624 } 1625 1626 static int cdns_torrent_dp_init(struct phy *phy) 1627 { 1628 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1629 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1630 1631 switch (cdns_phy->ref_clk_rate) { 1632 case CLK_19_2_MHZ: 1633 case CLK_25_MHZ: 1634 case CLK_100_MHZ: 1635 /* Valid Ref Clock Rate */ 1636 break; 1637 default: 1638 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 1639 return -EINVAL; 1640 } 1641 1642 cdns_torrent_dp_common_init(cdns_phy, inst); 1643 1644 return cdns_torrent_dp_start(cdns_phy, inst, phy); 1645 } 1646 1647 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) 1648 { 1649 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1650 1651 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1); 1652 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1); 1653 1654 return 0; 1655 } 1656 1657 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) 1658 { 1659 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1660 1661 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0); 1662 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0); 1663 } 1664 1665 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) 1666 { 1667 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1668 int val; 1669 1670 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val); 1671 1672 return !!val; 1673 } 1674 1675 static const struct clk_ops cdns_torrent_derived_refclk_ops = { 1676 .enable = cdns_torrent_derived_refclk_enable, 1677 .disable = cdns_torrent_derived_refclk_disable, 1678 .is_enabled = cdns_torrent_derived_refclk_is_enabled, 1679 }; 1680 1681 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) 1682 { 1683 struct cdns_torrent_derived_refclk *derived_refclk; 1684 struct device *dev = cdns_phy->dev; 1685 struct clk_init_data *init; 1686 const char *parent_name; 1687 char clk_name[100]; 1688 struct clk_hw *hw; 1689 struct clk *clk; 1690 int ret; 1691 1692 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 1693 if (!derived_refclk) 1694 return -ENOMEM; 1695 1696 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1697 clk_names[CDNS_TORRENT_DERIVED_REFCLK]); 1698 1699 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1700 if (IS_ERR(clk)) { 1701 dev_err(dev, "No parent clock for derived_refclk\n"); 1702 return PTR_ERR(clk); 1703 } 1704 1705 init = &derived_refclk->clk_data; 1706 1707 if (clk) { 1708 parent_name = __clk_get_name(clk); 1709 init->parent_names = &parent_name; 1710 init->num_parents = 1; 1711 } 1712 init->ops = &cdns_torrent_derived_refclk_ops; 1713 init->flags = 0; 1714 init->name = clk_name; 1715 1716 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; 1717 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; 1718 1719 derived_refclk->hw.init = init; 1720 1721 hw = &derived_refclk->hw; 1722 ret = devm_clk_hw_register(dev, hw); 1723 if (ret) 1724 return ret; 1725 1726 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw; 1727 1728 return 0; 1729 } 1730 1731 static int cdns_torrent_received_refclk_enable(struct clk_hw *hw) 1732 { 1733 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1734 1735 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1); 1736 1737 return 0; 1738 } 1739 1740 static void cdns_torrent_received_refclk_disable(struct clk_hw *hw) 1741 { 1742 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1743 1744 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0); 1745 } 1746 1747 static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw) 1748 { 1749 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1750 int val, cmn_val; 1751 1752 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val); 1753 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val); 1754 1755 return val && !cmn_val; 1756 } 1757 1758 static const struct clk_ops cdns_torrent_received_refclk_ops = { 1759 .enable = cdns_torrent_received_refclk_enable, 1760 .disable = cdns_torrent_received_refclk_disable, 1761 .is_enabled = cdns_torrent_received_refclk_is_enabled, 1762 }; 1763 1764 static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy) 1765 { 1766 struct cdns_torrent_received_refclk *received_refclk; 1767 struct device *dev = cdns_phy->dev; 1768 struct clk_init_data *init; 1769 const char *parent_name; 1770 char clk_name[100]; 1771 struct clk_hw *hw; 1772 struct clk *clk; 1773 int ret; 1774 1775 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL); 1776 if (!received_refclk) 1777 return -ENOMEM; 1778 1779 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1780 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]); 1781 1782 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1783 if (IS_ERR(clk)) { 1784 dev_err(dev, "No parent clock for received_refclk\n"); 1785 return PTR_ERR(clk); 1786 } 1787 1788 init = &received_refclk->clk_data; 1789 1790 if (clk) { 1791 parent_name = __clk_get_name(clk); 1792 init->parent_names = &parent_name; 1793 init->num_parents = 1; 1794 } 1795 init->ops = &cdns_torrent_received_refclk_ops; 1796 init->flags = 0; 1797 init->name = clk_name; 1798 1799 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; 1800 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; 1801 1802 received_refclk->hw.init = init; 1803 1804 hw = &received_refclk->hw; 1805 ret = devm_clk_hw_register(dev, hw); 1806 if (ret) 1807 return ret; 1808 1809 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw; 1810 1811 return 0; 1812 } 1813 1814 static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw) 1815 { 1816 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1817 1818 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); 1819 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); 1820 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); 1821 1822 return 0; 1823 } 1824 1825 static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw) 1826 { 1827 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1828 1829 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1); 1830 } 1831 1832 static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw) 1833 { 1834 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1835 int val; 1836 1837 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val); 1838 1839 return !val; 1840 } 1841 1842 static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw) 1843 { 1844 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1845 unsigned int val; 1846 1847 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val); 1848 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val); 1849 } 1850 1851 static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index) 1852 { 1853 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1854 unsigned int val; 1855 1856 val = cdns_torrent_refclk_driver_mux_table[index]; 1857 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val); 1858 } 1859 1860 static const struct clk_ops cdns_torrent_refclk_driver_ops = { 1861 .enable = cdns_torrent_refclk_driver_enable, 1862 .disable = cdns_torrent_refclk_driver_disable, 1863 .is_enabled = cdns_torrent_refclk_driver_is_enabled, 1864 .determine_rate = __clk_mux_determine_rate, 1865 .set_parent = cdns_torrent_refclk_driver_set_parent, 1866 .get_parent = cdns_torrent_refclk_driver_get_parent, 1867 }; 1868 1869 static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy) 1870 { 1871 struct cdns_torrent_refclk_driver *refclk_driver; 1872 struct device *dev = cdns_phy->dev; 1873 struct regmap_field *field; 1874 struct clk_init_data *init; 1875 const char **parent_names; 1876 unsigned int num_parents; 1877 struct regmap *regmap; 1878 char clk_name[100]; 1879 struct clk_hw *hw; 1880 int i, ret; 1881 1882 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL); 1883 if (!refclk_driver) 1884 return -ENOMEM; 1885 1886 num_parents = ARRAY_SIZE(refclk_driver_parent_index); 1887 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); 1888 if (!parent_names) 1889 return -ENOMEM; 1890 1891 for (i = 0; i < num_parents; i++) { 1892 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]]; 1893 if (IS_ERR_OR_NULL(hw)) { 1894 dev_err(dev, "No parent clock for refclk driver clock\n"); 1895 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT; 1896 } 1897 parent_names[i] = clk_hw_get_name(hw); 1898 } 1899 1900 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1901 clk_names[CDNS_TORRENT_REFCLK_DRIVER]); 1902 1903 init = &refclk_driver->clk_data; 1904 1905 init->ops = &cdns_torrent_refclk_driver_ops; 1906 init->flags = CLK_SET_RATE_NO_REPARENT; 1907 init->parent_names = parent_names; 1908 init->num_parents = num_parents; 1909 init->name = clk_name; 1910 1911 regmap = cdns_phy->regmap_common_cdb; 1912 1913 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) { 1914 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); 1915 if (IS_ERR(field)) { 1916 dev_err(dev, "Refclk driver CMN reg field init failed\n"); 1917 return PTR_ERR(field); 1918 } 1919 refclk_driver->cmn_fields[i] = field; 1920 } 1921 1922 /* Enable Derived reference clock as default */ 1923 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); 1924 1925 refclk_driver->hw.init = init; 1926 1927 hw = &refclk_driver->hw; 1928 ret = devm_clk_hw_register(dev, hw); 1929 if (ret) 1930 return ret; 1931 1932 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw; 1933 1934 return 0; 1935 } 1936 1937 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 1938 u32 block_offset, 1939 u8 reg_offset_shift, 1940 const struct regmap_config *config) 1941 { 1942 struct cdns_regmap_cdb_context *ctx; 1943 1944 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1945 if (!ctx) 1946 return ERR_PTR(-ENOMEM); 1947 1948 ctx->dev = dev; 1949 ctx->base = base + block_offset; 1950 ctx->reg_offset_shift = reg_offset_shift; 1951 1952 return devm_regmap_init(dev, NULL, ctx, config); 1953 } 1954 1955 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) 1956 { 1957 struct device *dev = cdns_phy->dev; 1958 struct regmap_field *field; 1959 struct regmap *regmap; 1960 1961 regmap = cdns_phy->regmap_dptx_phy_reg; 1962 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); 1963 if (IS_ERR(field)) { 1964 dev_err(dev, "PHY_RESET reg field init failed\n"); 1965 return PTR_ERR(field); 1966 } 1967 cdns_phy->phy_reset_ctrl = field; 1968 1969 return 0; 1970 } 1971 1972 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) 1973 { 1974 struct device *dev = cdns_phy->dev; 1975 struct regmap_field *field; 1976 struct regmap *regmap; 1977 int i; 1978 1979 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 1980 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); 1981 if (IS_ERR(field)) { 1982 dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); 1983 return PTR_ERR(field); 1984 } 1985 cdns_phy->phy_pll_cfg = field; 1986 1987 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 1988 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0); 1989 if (IS_ERR(field)) { 1990 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n"); 1991 return PTR_ERR(field); 1992 } 1993 cdns_phy->phy_pipe_cmn_ctrl1_0 = field; 1994 1995 regmap = cdns_phy->regmap_common_cdb; 1996 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4); 1997 if (IS_ERR(field)) { 1998 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n"); 1999 return PTR_ERR(field); 2000 } 2001 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field; 2002 2003 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2004 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1); 2005 if (IS_ERR(field)) { 2006 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n"); 2007 return PTR_ERR(field); 2008 } 2009 cdns_phy->phy_pma_cmn_ctrl_1 = field; 2010 2011 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2012 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); 2013 if (IS_ERR(field)) { 2014 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); 2015 return PTR_ERR(field); 2016 } 2017 cdns_phy->phy_pma_cmn_ctrl_2 = field; 2018 2019 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2020 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); 2021 if (IS_ERR(field)) { 2022 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); 2023 return PTR_ERR(field); 2024 } 2025 cdns_phy->phy_pma_pll_raw_ctrl = field; 2026 2027 for (i = 0; i < MAX_NUM_LANES; i++) { 2028 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i]; 2029 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1); 2030 if (IS_ERR(field)) { 2031 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i); 2032 return PTR_ERR(field); 2033 } 2034 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field; 2035 } 2036 2037 return 0; 2038 } 2039 2040 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) 2041 { 2042 void __iomem *base = cdns_phy->base; 2043 struct device *dev = cdns_phy->dev; 2044 struct regmap *regmap; 2045 u8 reg_offset_shift; 2046 u32 block_offset; 2047 2048 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 2049 2050 block_offset = TORRENT_DPTX_PHY_OFFSET; 2051 regmap = cdns_regmap_init(dev, base, block_offset, 2052 reg_offset_shift, 2053 &cdns_torrent_dptx_phy_config); 2054 if (IS_ERR(regmap)) { 2055 dev_err(dev, "Failed to init DPTX PHY regmap\n"); 2056 return PTR_ERR(regmap); 2057 } 2058 cdns_phy->regmap_dptx_phy_reg = regmap; 2059 2060 return 0; 2061 } 2062 2063 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) 2064 { 2065 void __iomem *sd_base = cdns_phy->sd_base; 2066 u8 block_offset_shift, reg_offset_shift; 2067 struct device *dev = cdns_phy->dev; 2068 struct regmap *regmap; 2069 u32 block_offset; 2070 int i; 2071 2072 block_offset_shift = cdns_phy->init_data->block_offset_shift; 2073 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 2074 2075 for (i = 0; i < MAX_NUM_LANES; i++) { 2076 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, 2077 reg_offset_shift); 2078 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2079 reg_offset_shift, 2080 &cdns_torrent_tx_lane_cdb_config[i]); 2081 if (IS_ERR(regmap)) { 2082 dev_err(dev, "Failed to init tx lane CDB regmap\n"); 2083 return PTR_ERR(regmap); 2084 } 2085 cdns_phy->regmap_tx_lane_cdb[i] = regmap; 2086 2087 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, 2088 reg_offset_shift); 2089 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2090 reg_offset_shift, 2091 &cdns_torrent_rx_lane_cdb_config[i]); 2092 if (IS_ERR(regmap)) { 2093 dev_err(dev, "Failed to init rx lane CDB regmap\n"); 2094 return PTR_ERR(regmap); 2095 } 2096 cdns_phy->regmap_rx_lane_cdb[i] = regmap; 2097 2098 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 2099 reg_offset_shift); 2100 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2101 reg_offset_shift, 2102 &cdns_torrent_phy_pcs_lane_cdb_config[i]); 2103 if (IS_ERR(regmap)) { 2104 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 2105 return PTR_ERR(regmap); 2106 } 2107 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap; 2108 } 2109 2110 block_offset = TORRENT_COMMON_CDB_OFFSET; 2111 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2112 reg_offset_shift, 2113 &cdns_torrent_common_cdb_config); 2114 if (IS_ERR(regmap)) { 2115 dev_err(dev, "Failed to init common CDB regmap\n"); 2116 return PTR_ERR(regmap); 2117 } 2118 cdns_phy->regmap_common_cdb = regmap; 2119 2120 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); 2121 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2122 reg_offset_shift, 2123 &cdns_torrent_phy_pcs_cmn_cdb_config); 2124 if (IS_ERR(regmap)) { 2125 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 2126 return PTR_ERR(regmap); 2127 } 2128 cdns_phy->regmap_phy_pcs_common_cdb = regmap; 2129 2130 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); 2131 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2132 reg_offset_shift, 2133 &cdns_torrent_phy_pma_cmn_cdb_config); 2134 if (IS_ERR(regmap)) { 2135 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 2136 return PTR_ERR(regmap); 2137 } 2138 cdns_phy->regmap_phy_pma_common_cdb = regmap; 2139 2140 return 0; 2141 } 2142 2143 static int cdns_torrent_phy_init(struct phy *phy) 2144 { 2145 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 2146 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2147 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2148 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2149 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2150 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 2151 enum cdns_torrent_phy_type phy_type = inst->phy_type; 2152 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; 2153 struct cdns_torrent_vals *pcs_cmn_vals; 2154 struct cdns_reg_pairs *reg_pairs; 2155 struct regmap *regmap; 2156 u32 num_regs; 2157 int i, j; 2158 2159 if (cdns_phy->nsubnodes > 1) 2160 return 0; 2161 2162 /** 2163 * Spread spectrum generation is not required or supported 2164 * for SGMII/QSGMII 2165 */ 2166 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII) 2167 ssc = NO_SSC; 2168 2169 /* PHY configuration specific registers for single link */ 2170 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc]; 2171 if (link_cmn_vals) { 2172 reg_pairs = link_cmn_vals->reg_pairs; 2173 num_regs = link_cmn_vals->num_regs; 2174 regmap = cdns_phy->regmap_common_cdb; 2175 2176 /** 2177 * First array value in link_cmn_vals must be of 2178 * PHY_PLL_CFG register 2179 */ 2180 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val); 2181 2182 for (i = 1; i < num_regs; i++) 2183 regmap_write(regmap, reg_pairs[i].off, 2184 reg_pairs[i].val); 2185 } 2186 2187 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc]; 2188 if (xcvr_diag_vals) { 2189 reg_pairs = xcvr_diag_vals->reg_pairs; 2190 num_regs = xcvr_diag_vals->num_regs; 2191 for (i = 0; i < inst->num_lanes; i++) { 2192 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 2193 for (j = 0; j < num_regs; j++) 2194 regmap_write(regmap, reg_pairs[j].off, 2195 reg_pairs[j].val); 2196 } 2197 } 2198 2199 /* PHY PCS common registers configurations */ 2200 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; 2201 if (pcs_cmn_vals) { 2202 reg_pairs = pcs_cmn_vals->reg_pairs; 2203 num_regs = pcs_cmn_vals->num_regs; 2204 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2205 for (i = 0; i < num_regs; i++) 2206 regmap_write(regmap, reg_pairs[i].off, 2207 reg_pairs[i].val); 2208 } 2209 2210 /* PMA common registers configurations */ 2211 cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc]; 2212 if (cmn_vals) { 2213 reg_pairs = cmn_vals->reg_pairs; 2214 num_regs = cmn_vals->num_regs; 2215 regmap = cdns_phy->regmap_common_cdb; 2216 for (i = 0; i < num_regs; i++) 2217 regmap_write(regmap, reg_pairs[i].off, 2218 reg_pairs[i].val); 2219 } 2220 2221 /* PMA TX lane registers configurations */ 2222 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc]; 2223 if (tx_ln_vals) { 2224 reg_pairs = tx_ln_vals->reg_pairs; 2225 num_regs = tx_ln_vals->num_regs; 2226 for (i = 0; i < inst->num_lanes; i++) { 2227 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 2228 for (j = 0; j < num_regs; j++) 2229 regmap_write(regmap, reg_pairs[j].off, 2230 reg_pairs[j].val); 2231 } 2232 } 2233 2234 /* PMA RX lane registers configurations */ 2235 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc]; 2236 if (rx_ln_vals) { 2237 reg_pairs = rx_ln_vals->reg_pairs; 2238 num_regs = rx_ln_vals->num_regs; 2239 for (i = 0; i < inst->num_lanes; i++) { 2240 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane]; 2241 for (j = 0; j < num_regs; j++) 2242 regmap_write(regmap, reg_pairs[j].off, 2243 reg_pairs[j].val); 2244 } 2245 } 2246 2247 if (phy_type == TYPE_DP) 2248 return cdns_torrent_dp_init(phy); 2249 2250 return 0; 2251 } 2252 2253 static const struct phy_ops cdns_torrent_phy_ops = { 2254 .init = cdns_torrent_phy_init, 2255 .configure = cdns_torrent_dp_configure, 2256 .power_on = cdns_torrent_phy_on, 2257 .power_off = cdns_torrent_phy_off, 2258 .owner = THIS_MODULE, 2259 }; 2260 2261 static int cdns_torrent_noop_phy_on(struct phy *phy) 2262 { 2263 /* Give 5ms to 10ms delay for the PIPE clock to be stable */ 2264 usleep_range(5000, 10000); 2265 2266 return 0; 2267 } 2268 2269 static const struct phy_ops noop_ops = { 2270 .power_on = cdns_torrent_noop_phy_on, 2271 .owner = THIS_MODULE, 2272 }; 2273 2274 static 2275 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) 2276 { 2277 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2278 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2279 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2280 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2281 enum cdns_torrent_phy_type phy_t1, phy_t2; 2282 struct cdns_torrent_vals *pcs_cmn_vals; 2283 int i, j, node, mlane, num_lanes, ret; 2284 struct cdns_reg_pairs *reg_pairs; 2285 enum cdns_torrent_ssc_mode ssc; 2286 struct regmap *regmap; 2287 u32 num_regs; 2288 2289 /* Maximum 2 links (subnodes) are supported */ 2290 if (cdns_phy->nsubnodes != 2) 2291 return -EINVAL; 2292 2293 phy_t1 = cdns_phy->phys[0].phy_type; 2294 phy_t2 = cdns_phy->phys[1].phy_type; 2295 2296 /** 2297 * First configure the PHY for first link with phy_t1. Get the array 2298 * values as [phy_t1][phy_t2][ssc]. 2299 */ 2300 for (node = 0; node < cdns_phy->nsubnodes; node++) { 2301 if (node == 1) { 2302 /** 2303 * If first link with phy_t1 is configured, then 2304 * configure the PHY for second link with phy_t2. 2305 * Get the array values as [phy_t2][phy_t1][ssc]. 2306 */ 2307 swap(phy_t1, phy_t2); 2308 } 2309 2310 mlane = cdns_phy->phys[node].mlane; 2311 ssc = cdns_phy->phys[node].ssc_mode; 2312 num_lanes = cdns_phy->phys[node].num_lanes; 2313 2314 /** 2315 * PHY configuration specific registers: 2316 * link_cmn_vals depend on combination of PHY types being 2317 * configured and are common for both PHY types, so array 2318 * values should be same for [phy_t1][phy_t2][ssc] and 2319 * [phy_t2][phy_t1][ssc]. 2320 * xcvr_diag_vals also depend on combination of PHY types 2321 * being configured, but these can be different for particular 2322 * PHY type and are per lane. 2323 */ 2324 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc]; 2325 if (link_cmn_vals) { 2326 reg_pairs = link_cmn_vals->reg_pairs; 2327 num_regs = link_cmn_vals->num_regs; 2328 regmap = cdns_phy->regmap_common_cdb; 2329 2330 /** 2331 * First array value in link_cmn_vals must be of 2332 * PHY_PLL_CFG register 2333 */ 2334 regmap_field_write(cdns_phy->phy_pll_cfg, 2335 reg_pairs[0].val); 2336 2337 for (i = 1; i < num_regs; i++) 2338 regmap_write(regmap, reg_pairs[i].off, 2339 reg_pairs[i].val); 2340 } 2341 2342 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc]; 2343 if (xcvr_diag_vals) { 2344 reg_pairs = xcvr_diag_vals->reg_pairs; 2345 num_regs = xcvr_diag_vals->num_regs; 2346 for (i = 0; i < num_lanes; i++) { 2347 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2348 for (j = 0; j < num_regs; j++) 2349 regmap_write(regmap, reg_pairs[j].off, 2350 reg_pairs[j].val); 2351 } 2352 } 2353 2354 /* PHY PCS common registers configurations */ 2355 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; 2356 if (pcs_cmn_vals) { 2357 reg_pairs = pcs_cmn_vals->reg_pairs; 2358 num_regs = pcs_cmn_vals->num_regs; 2359 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2360 for (i = 0; i < num_regs; i++) 2361 regmap_write(regmap, reg_pairs[i].off, 2362 reg_pairs[i].val); 2363 } 2364 2365 /* PMA common registers configurations */ 2366 cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc]; 2367 if (cmn_vals) { 2368 reg_pairs = cmn_vals->reg_pairs; 2369 num_regs = cmn_vals->num_regs; 2370 regmap = cdns_phy->regmap_common_cdb; 2371 for (i = 0; i < num_regs; i++) 2372 regmap_write(regmap, reg_pairs[i].off, 2373 reg_pairs[i].val); 2374 } 2375 2376 /* PMA TX lane registers configurations */ 2377 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc]; 2378 if (tx_ln_vals) { 2379 reg_pairs = tx_ln_vals->reg_pairs; 2380 num_regs = tx_ln_vals->num_regs; 2381 for (i = 0; i < num_lanes; i++) { 2382 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2383 for (j = 0; j < num_regs; j++) 2384 regmap_write(regmap, reg_pairs[j].off, 2385 reg_pairs[j].val); 2386 } 2387 } 2388 2389 /* PMA RX lane registers configurations */ 2390 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc]; 2391 if (rx_ln_vals) { 2392 reg_pairs = rx_ln_vals->reg_pairs; 2393 num_regs = rx_ln_vals->num_regs; 2394 for (i = 0; i < num_lanes; i++) { 2395 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane]; 2396 for (j = 0; j < num_regs; j++) 2397 regmap_write(regmap, reg_pairs[j].off, 2398 reg_pairs[j].val); 2399 } 2400 } 2401 2402 reset_control_deassert(cdns_phy->phys[node].lnk_rst); 2403 } 2404 2405 /* Take the PHY out of reset */ 2406 ret = reset_control_deassert(cdns_phy->phy_rst); 2407 if (ret) 2408 return ret; 2409 2410 return 0; 2411 } 2412 2413 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) 2414 { 2415 struct device *dev = cdns_phy->dev; 2416 2417 of_clk_del_provider(dev->of_node); 2418 } 2419 2420 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) 2421 { 2422 struct device *dev = cdns_phy->dev; 2423 struct device_node *node = dev->of_node; 2424 struct clk_hw_onecell_data *data; 2425 int ret; 2426 2427 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL); 2428 if (!data) 2429 return -ENOMEM; 2430 2431 data->num = CDNS_TORRENT_OUTPUT_CLOCKS; 2432 cdns_phy->clk_hw_data = data; 2433 2434 ret = cdns_torrent_derived_refclk_register(cdns_phy); 2435 if (ret) { 2436 dev_err(dev, "failed to register derived refclk\n"); 2437 return ret; 2438 } 2439 2440 ret = cdns_torrent_received_refclk_register(cdns_phy); 2441 if (ret) { 2442 dev_err(dev, "failed to register received refclk\n"); 2443 return ret; 2444 } 2445 2446 ret = cdns_torrent_refclk_driver_register(cdns_phy); 2447 if (ret) { 2448 dev_err(dev, "failed to register refclk driver\n"); 2449 return ret; 2450 } 2451 2452 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data); 2453 if (ret) { 2454 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 2455 return ret; 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy) 2462 { 2463 struct device *dev = cdns_phy->dev; 2464 2465 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); 2466 if (IS_ERR(cdns_phy->phy_rst)) { 2467 dev_err(dev, "%s: failed to get reset\n", 2468 dev->of_node->full_name); 2469 return PTR_ERR(cdns_phy->phy_rst); 2470 } 2471 2472 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb"); 2473 if (IS_ERR(cdns_phy->apb_rst)) { 2474 dev_err(dev, "%s: failed to get apb reset\n", 2475 dev->of_node->full_name); 2476 return PTR_ERR(cdns_phy->apb_rst); 2477 } 2478 2479 return 0; 2480 } 2481 2482 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) 2483 { 2484 struct device *dev = cdns_phy->dev; 2485 unsigned long ref_clk_rate; 2486 int ret; 2487 2488 cdns_phy->clk = devm_clk_get(dev, "refclk"); 2489 if (IS_ERR(cdns_phy->clk)) { 2490 dev_err(dev, "phy ref clock not found\n"); 2491 return PTR_ERR(cdns_phy->clk); 2492 } 2493 2494 ret = clk_prepare_enable(cdns_phy->clk); 2495 if (ret) { 2496 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); 2497 return ret; 2498 } 2499 2500 ref_clk_rate = clk_get_rate(cdns_phy->clk); 2501 if (!ref_clk_rate) { 2502 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); 2503 clk_disable_unprepare(cdns_phy->clk); 2504 return -EINVAL; 2505 } 2506 2507 switch (ref_clk_rate) { 2508 case REF_CLK_19_2MHZ: 2509 cdns_phy->ref_clk_rate = CLK_19_2_MHZ; 2510 break; 2511 case REF_CLK_25MHZ: 2512 cdns_phy->ref_clk_rate = CLK_25_MHZ; 2513 break; 2514 case REF_CLK_100MHZ: 2515 cdns_phy->ref_clk_rate = CLK_100_MHZ; 2516 break; 2517 default: 2518 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n"); 2519 clk_disable_unprepare(cdns_phy->clk); 2520 return -EINVAL; 2521 } 2522 2523 return 0; 2524 } 2525 2526 static int cdns_torrent_phy_probe(struct platform_device *pdev) 2527 { 2528 struct cdns_torrent_phy *cdns_phy; 2529 struct device *dev = &pdev->dev; 2530 struct phy_provider *phy_provider; 2531 const struct cdns_torrent_data *data; 2532 struct device_node *child; 2533 int ret, subnodes, node = 0, i; 2534 u32 total_num_lanes = 0; 2535 int already_configured; 2536 u8 init_dp_regmap = 0; 2537 u32 phy_type; 2538 2539 /* Get init data for this PHY */ 2540 data = of_device_get_match_data(dev); 2541 if (!data) 2542 return -EINVAL; 2543 2544 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); 2545 if (!cdns_phy) 2546 return -ENOMEM; 2547 2548 dev_set_drvdata(dev, cdns_phy); 2549 cdns_phy->dev = dev; 2550 cdns_phy->init_data = data; 2551 2552 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0); 2553 if (IS_ERR(cdns_phy->sd_base)) 2554 return PTR_ERR(cdns_phy->sd_base); 2555 2556 subnodes = of_get_available_child_count(dev->of_node); 2557 if (subnodes == 0) { 2558 dev_err(dev, "No available link subnodes found\n"); 2559 return -EINVAL; 2560 } 2561 2562 ret = cdns_torrent_regmap_init(cdns_phy); 2563 if (ret) 2564 return ret; 2565 2566 ret = cdns_torrent_regfield_init(cdns_phy); 2567 if (ret) 2568 return ret; 2569 2570 ret = cdns_torrent_clk_register(cdns_phy); 2571 if (ret) 2572 return ret; 2573 2574 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured); 2575 2576 if (!already_configured) { 2577 ret = cdns_torrent_reset(cdns_phy); 2578 if (ret) 2579 goto clk_cleanup; 2580 2581 ret = cdns_torrent_clk(cdns_phy); 2582 if (ret) 2583 goto clk_cleanup; 2584 2585 /* Enable APB */ 2586 reset_control_deassert(cdns_phy->apb_rst); 2587 } 2588 2589 for_each_available_child_of_node(dev->of_node, child) { 2590 struct phy *gphy; 2591 2592 /* PHY subnode name must be 'phy'. */ 2593 if (!(of_node_name_eq(child, "phy"))) 2594 continue; 2595 2596 cdns_phy->phys[node].lnk_rst = 2597 of_reset_control_array_get_exclusive(child); 2598 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { 2599 dev_err(dev, "%s: failed to get reset\n", 2600 child->full_name); 2601 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst); 2602 goto put_lnk_rst; 2603 } 2604 2605 if (of_property_read_u32(child, "reg", 2606 &cdns_phy->phys[node].mlane)) { 2607 dev_err(dev, "%s: No \"reg\"-property.\n", 2608 child->full_name); 2609 ret = -EINVAL; 2610 goto put_child; 2611 } 2612 2613 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) { 2614 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", 2615 child->full_name); 2616 ret = -EINVAL; 2617 goto put_child; 2618 } 2619 2620 switch (phy_type) { 2621 case PHY_TYPE_PCIE: 2622 cdns_phy->phys[node].phy_type = TYPE_PCIE; 2623 break; 2624 case PHY_TYPE_DP: 2625 cdns_phy->phys[node].phy_type = TYPE_DP; 2626 break; 2627 case PHY_TYPE_SGMII: 2628 cdns_phy->phys[node].phy_type = TYPE_SGMII; 2629 break; 2630 case PHY_TYPE_QSGMII: 2631 cdns_phy->phys[node].phy_type = TYPE_QSGMII; 2632 break; 2633 case PHY_TYPE_USB3: 2634 cdns_phy->phys[node].phy_type = TYPE_USB; 2635 break; 2636 default: 2637 dev_err(dev, "Unsupported protocol\n"); 2638 ret = -EINVAL; 2639 goto put_child; 2640 } 2641 2642 if (of_property_read_u32(child, "cdns,num-lanes", 2643 &cdns_phy->phys[node].num_lanes)) { 2644 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n", 2645 child->full_name); 2646 ret = -EINVAL; 2647 goto put_child; 2648 } 2649 2650 total_num_lanes += cdns_phy->phys[node].num_lanes; 2651 2652 /* Get SSC mode */ 2653 cdns_phy->phys[node].ssc_mode = NO_SSC; 2654 of_property_read_u32(child, "cdns,ssc-mode", 2655 &cdns_phy->phys[node].ssc_mode); 2656 2657 if (!already_configured) 2658 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); 2659 else 2660 gphy = devm_phy_create(dev, child, &noop_ops); 2661 if (IS_ERR(gphy)) { 2662 ret = PTR_ERR(gphy); 2663 goto put_child; 2664 } 2665 2666 if (cdns_phy->phys[node].phy_type == TYPE_DP) { 2667 switch (cdns_phy->phys[node].num_lanes) { 2668 case 1: 2669 case 2: 2670 case 4: 2671 /* valid number of lanes */ 2672 break; 2673 default: 2674 dev_err(dev, "unsupported number of lanes: %d\n", 2675 cdns_phy->phys[node].num_lanes); 2676 ret = -EINVAL; 2677 goto put_child; 2678 } 2679 2680 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; 2681 of_property_read_u32(child, "cdns,max-bit-rate", 2682 &cdns_phy->max_bit_rate); 2683 2684 switch (cdns_phy->max_bit_rate) { 2685 case 1620: 2686 case 2160: 2687 case 2430: 2688 case 2700: 2689 case 3240: 2690 case 4320: 2691 case 5400: 2692 case 8100: 2693 /* valid bit rate */ 2694 break; 2695 default: 2696 dev_err(dev, "unsupported max bit rate: %dMbps\n", 2697 cdns_phy->max_bit_rate); 2698 ret = -EINVAL; 2699 goto put_child; 2700 } 2701 2702 /* DPTX registers */ 2703 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1); 2704 if (IS_ERR(cdns_phy->base)) { 2705 ret = PTR_ERR(cdns_phy->base); 2706 goto put_child; 2707 } 2708 2709 if (!init_dp_regmap) { 2710 ret = cdns_torrent_dp_regmap_init(cdns_phy); 2711 if (ret) 2712 goto put_child; 2713 2714 ret = cdns_torrent_dp_regfield_init(cdns_phy); 2715 if (ret) 2716 goto put_child; 2717 2718 init_dp_regmap++; 2719 } 2720 2721 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n", 2722 cdns_phy->max_bit_rate / 1000, 2723 cdns_phy->max_bit_rate % 1000); 2724 2725 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes; 2726 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate; 2727 gphy->attrs.mode = PHY_MODE_DP; 2728 } 2729 2730 cdns_phy->phys[node].phy = gphy; 2731 phy_set_drvdata(gphy, &cdns_phy->phys[node]); 2732 2733 node++; 2734 } 2735 cdns_phy->nsubnodes = node; 2736 2737 if (total_num_lanes > MAX_NUM_LANES) { 2738 dev_err(dev, "Invalid lane configuration\n"); 2739 ret = -EINVAL; 2740 goto put_lnk_rst; 2741 } 2742 2743 if (cdns_phy->nsubnodes > 1 && !already_configured) { 2744 ret = cdns_torrent_phy_configure_multilink(cdns_phy); 2745 if (ret) 2746 goto put_lnk_rst; 2747 } 2748 2749 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2750 if (IS_ERR(phy_provider)) { 2751 ret = PTR_ERR(phy_provider); 2752 goto put_lnk_rst; 2753 } 2754 2755 if (cdns_phy->nsubnodes > 1) 2756 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)", 2757 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), 2758 cdns_phy->phys[0].num_lanes, 2759 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type), 2760 cdns_phy->phys[1].num_lanes); 2761 else 2762 dev_dbg(dev, "Single link: %s (%d lanes)", 2763 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), 2764 cdns_phy->phys[0].num_lanes); 2765 2766 return 0; 2767 2768 put_child: 2769 node++; 2770 put_lnk_rst: 2771 for (i = 0; i < node; i++) 2772 reset_control_put(cdns_phy->phys[i].lnk_rst); 2773 of_node_put(child); 2774 reset_control_assert(cdns_phy->apb_rst); 2775 clk_disable_unprepare(cdns_phy->clk); 2776 clk_cleanup: 2777 cdns_torrent_clk_cleanup(cdns_phy); 2778 return ret; 2779 } 2780 2781 static void cdns_torrent_phy_remove(struct platform_device *pdev) 2782 { 2783 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev); 2784 int i; 2785 2786 reset_control_assert(cdns_phy->phy_rst); 2787 reset_control_assert(cdns_phy->apb_rst); 2788 for (i = 0; i < cdns_phy->nsubnodes; i++) { 2789 reset_control_assert(cdns_phy->phys[i].lnk_rst); 2790 reset_control_put(cdns_phy->phys[i].lnk_rst); 2791 } 2792 2793 clk_disable_unprepare(cdns_phy->clk); 2794 cdns_torrent_clk_cleanup(cdns_phy); 2795 } 2796 2797 /* Single DisplayPort(DP) link configuration */ 2798 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { 2799 {0x0000, PHY_PLL_CFG}, 2800 }; 2801 2802 static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { 2803 {0x0000, XCVR_DIAG_HSCLK_SEL}, 2804 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 2805 }; 2806 2807 static struct cdns_torrent_vals sl_dp_link_cmn_vals = { 2808 .reg_pairs = sl_dp_link_cmn_regs, 2809 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs), 2810 }; 2811 2812 static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = { 2813 .reg_pairs = sl_dp_xcvr_diag_ln_regs, 2814 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs), 2815 }; 2816 2817 /* Single DP, 19.2 MHz Ref clk, no SSC */ 2818 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { 2819 {0x0014, CMN_SSM_BIAS_TMR}, 2820 {0x0027, CMN_PLLSM0_PLLPRE_TMR}, 2821 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR}, 2822 {0x0027, CMN_PLLSM1_PLLPRE_TMR}, 2823 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR}, 2824 {0x0060, CMN_BGCAL_INIT_TMR}, 2825 {0x0060, CMN_BGCAL_ITER_TMR}, 2826 {0x0014, CMN_IBCAL_INIT_TMR}, 2827 {0x0018, CMN_TXPUCAL_INIT_TMR}, 2828 {0x0005, CMN_TXPUCAL_ITER_TMR}, 2829 {0x0018, CMN_TXPDCAL_INIT_TMR}, 2830 {0x0005, CMN_TXPDCAL_ITER_TMR}, 2831 {0x0240, CMN_RXCAL_INIT_TMR}, 2832 {0x0005, CMN_RXCAL_ITER_TMR}, 2833 {0x0002, CMN_SD_CAL_INIT_TMR}, 2834 {0x0002, CMN_SD_CAL_ITER_TMR}, 2835 {0x000B, CMN_SD_CAL_REFTIM_START}, 2836 {0x0137, CMN_SD_CAL_PLLCNT_START}, 2837 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 2838 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 2839 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 2840 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 2841 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2842 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 2843 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 2844 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 2845 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR}, 2846 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 2847 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR}, 2848 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 2849 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START}, 2850 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2851 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START}, 2852 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 2853 }; 2854 2855 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { 2856 {0x0780, TX_RCVDET_ST_TMR}, 2857 {0x00FB, TX_PSC_A0}, 2858 {0x04AA, TX_PSC_A2}, 2859 {0x04AA, TX_PSC_A3}, 2860 {0x000F, XCVR_DIAG_BIDI_CTRL} 2861 }; 2862 2863 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { 2864 {0x0000, RX_PSC_A0}, 2865 {0x0000, RX_PSC_A2}, 2866 {0x0000, RX_PSC_A3}, 2867 {0x0000, RX_PSC_CAL}, 2868 {0x0000, RX_REE_GCSM1_CTRL}, 2869 {0x0000, RX_REE_GCSM2_CTRL}, 2870 {0x0000, RX_REE_PERGCSM_CTRL} 2871 }; 2872 2873 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = { 2874 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs, 2875 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs), 2876 }; 2877 2878 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = { 2879 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs, 2880 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs), 2881 }; 2882 2883 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = { 2884 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs, 2885 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs), 2886 }; 2887 2888 /* Single DP, 25 MHz Ref clk, no SSC */ 2889 static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { 2890 {0x0019, CMN_SSM_BIAS_TMR}, 2891 {0x0032, CMN_PLLSM0_PLLPRE_TMR}, 2892 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR}, 2893 {0x0032, CMN_PLLSM1_PLLPRE_TMR}, 2894 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR}, 2895 {0x007D, CMN_BGCAL_INIT_TMR}, 2896 {0x007D, CMN_BGCAL_ITER_TMR}, 2897 {0x0019, CMN_IBCAL_INIT_TMR}, 2898 {0x001E, CMN_TXPUCAL_INIT_TMR}, 2899 {0x0006, CMN_TXPUCAL_ITER_TMR}, 2900 {0x001E, CMN_TXPDCAL_INIT_TMR}, 2901 {0x0006, CMN_TXPDCAL_ITER_TMR}, 2902 {0x02EE, CMN_RXCAL_INIT_TMR}, 2903 {0x0006, CMN_RXCAL_ITER_TMR}, 2904 {0x0002, CMN_SD_CAL_INIT_TMR}, 2905 {0x0002, CMN_SD_CAL_ITER_TMR}, 2906 {0x000E, CMN_SD_CAL_REFTIM_START}, 2907 {0x012B, CMN_SD_CAL_PLLCNT_START}, 2908 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 2909 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 2910 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 2911 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 2912 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2913 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 2914 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 2915 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 2916 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR}, 2917 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 2918 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR}, 2919 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 2920 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START}, 2921 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2922 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START}, 2923 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 2924 }; 2925 2926 static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { 2927 {0x09C4, TX_RCVDET_ST_TMR}, 2928 {0x00FB, TX_PSC_A0}, 2929 {0x04AA, TX_PSC_A2}, 2930 {0x04AA, TX_PSC_A3}, 2931 {0x000F, XCVR_DIAG_BIDI_CTRL} 2932 }; 2933 2934 static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { 2935 {0x0000, RX_PSC_A0}, 2936 {0x0000, RX_PSC_A2}, 2937 {0x0000, RX_PSC_A3}, 2938 {0x0000, RX_PSC_CAL}, 2939 {0x0000, RX_REE_GCSM1_CTRL}, 2940 {0x0000, RX_REE_GCSM2_CTRL}, 2941 {0x0000, RX_REE_PERGCSM_CTRL} 2942 }; 2943 2944 static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = { 2945 .reg_pairs = sl_dp_25_no_ssc_cmn_regs, 2946 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs), 2947 }; 2948 2949 static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = { 2950 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs, 2951 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs), 2952 }; 2953 2954 static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = { 2955 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs, 2956 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs), 2957 }; 2958 2959 /* Single DP, 100 MHz Ref clk, no SSC */ 2960 static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { 2961 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2962 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 2963 }; 2964 2965 static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { 2966 {0x00FB, TX_PSC_A0}, 2967 {0x04AA, TX_PSC_A2}, 2968 {0x04AA, TX_PSC_A3}, 2969 {0x000F, XCVR_DIAG_BIDI_CTRL} 2970 }; 2971 2972 static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { 2973 {0x0000, RX_PSC_A0}, 2974 {0x0000, RX_PSC_A2}, 2975 {0x0000, RX_PSC_A3}, 2976 {0x0000, RX_PSC_CAL}, 2977 {0x0000, RX_REE_GCSM1_CTRL}, 2978 {0x0000, RX_REE_GCSM2_CTRL}, 2979 {0x0000, RX_REE_PERGCSM_CTRL} 2980 }; 2981 2982 static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = { 2983 .reg_pairs = sl_dp_100_no_ssc_cmn_regs, 2984 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs), 2985 }; 2986 2987 static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = { 2988 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs, 2989 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs), 2990 }; 2991 2992 static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = { 2993 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs, 2994 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs), 2995 }; 2996 2997 /* USB and SGMII/QSGMII link configuration */ 2998 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { 2999 {0x0002, PHY_PLL_CFG}, 3000 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3001 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3002 }; 3003 3004 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { 3005 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3006 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3007 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3008 }; 3009 3010 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { 3011 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3012 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3013 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 3014 }; 3015 3016 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = { 3017 .reg_pairs = usb_sgmii_link_cmn_regs, 3018 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs), 3019 }; 3020 3021 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = { 3022 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs, 3023 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs), 3024 }; 3025 3026 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = { 3027 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs, 3028 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs), 3029 }; 3030 3031 /* PCIe and USB Unique SSC link configuration */ 3032 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { 3033 {0x0003, PHY_PLL_CFG}, 3034 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3035 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3036 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0} 3037 }; 3038 3039 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { 3040 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3041 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3042 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3043 }; 3044 3045 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { 3046 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3047 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3048 {0x00C9, XCVR_DIAG_PLLDRC_CTRL} 3049 }; 3050 3051 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = { 3052 .reg_pairs = pcie_usb_link_cmn_regs, 3053 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs), 3054 }; 3055 3056 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = { 3057 .reg_pairs = pcie_usb_xcvr_diag_ln_regs, 3058 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs), 3059 }; 3060 3061 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = { 3062 .reg_pairs = usb_pcie_xcvr_diag_ln_regs, 3063 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs), 3064 }; 3065 3066 /* USB 100 MHz Ref clk, internal SSC */ 3067 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { 3068 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3069 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3070 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3071 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3072 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3073 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3074 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3075 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3076 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3077 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3078 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3079 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3080 {0x0064, CMN_PLL0_INTDIV_M0}, 3081 {0x0050, CMN_PLL0_INTDIV_M1}, 3082 {0x0064, CMN_PLL1_INTDIV_M0}, 3083 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3084 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3085 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3086 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3087 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3088 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3089 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3090 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3091 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3092 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3093 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3094 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3095 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3096 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3097 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3098 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3099 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3100 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3101 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3102 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3103 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3104 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3105 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3106 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3107 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3108 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3109 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3110 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3111 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3112 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3113 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3114 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3115 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 3116 {0x007F, CMN_TXPUCAL_TUNE}, 3117 {0x007F, CMN_TXPDCAL_TUNE} 3118 }; 3119 3120 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = { 3121 .reg_pairs = usb_100_int_ssc_cmn_regs, 3122 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs), 3123 }; 3124 3125 /* Single USB link configuration */ 3126 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { 3127 {0x0000, PHY_PLL_CFG}, 3128 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3129 }; 3130 3131 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { 3132 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3133 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3134 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3135 }; 3136 3137 static struct cdns_torrent_vals sl_usb_link_cmn_vals = { 3138 .reg_pairs = sl_usb_link_cmn_regs, 3139 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs), 3140 }; 3141 3142 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = { 3143 .reg_pairs = sl_usb_xcvr_diag_ln_regs, 3144 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs), 3145 }; 3146 3147 /* USB PHY PCS common configuration */ 3148 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { 3149 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, 3150 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, 3151 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} 3152 }; 3153 3154 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { 3155 .reg_pairs = usb_phy_pcs_cmn_regs, 3156 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs), 3157 }; 3158 3159 /* USB 100 MHz Ref clk, no SSC */ 3160 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { 3161 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3162 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3163 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3164 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3165 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3166 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3167 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 3168 }; 3169 3170 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = { 3171 .reg_pairs = sl_usb_100_no_ssc_cmn_regs, 3172 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), 3173 }; 3174 3175 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { 3176 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3177 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 3178 {0x007F, CMN_TXPUCAL_TUNE}, 3179 {0x007F, CMN_TXPDCAL_TUNE} 3180 }; 3181 3182 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { 3183 {0x02FF, TX_PSC_A0}, 3184 {0x06AF, TX_PSC_A1}, 3185 {0x06AE, TX_PSC_A2}, 3186 {0x06AE, TX_PSC_A3}, 3187 {0x2A82, TX_TXCC_CTRL}, 3188 {0x0014, TX_TXCC_CPOST_MULT_01}, 3189 {0x0003, XCVR_DIAG_PSC_OVRD} 3190 }; 3191 3192 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { 3193 {0x0D1D, RX_PSC_A0}, 3194 {0x0D1D, RX_PSC_A1}, 3195 {0x0D00, RX_PSC_A2}, 3196 {0x0500, RX_PSC_A3}, 3197 {0x0013, RX_SIGDET_HL_FILT_TMR}, 3198 {0x0000, RX_REE_GCSM1_CTRL}, 3199 {0x0C02, RX_REE_ATTEN_THR}, 3200 {0x0330, RX_REE_SMGM_CTRL1}, 3201 {0x0300, RX_REE_SMGM_CTRL2}, 3202 {0x0019, RX_REE_TAP1_CLIP}, 3203 {0x0019, RX_REE_TAP2TON_CLIP}, 3204 {0x1004, RX_DIAG_SIGDET_TUNE}, 3205 {0x00F9, RX_DIAG_NQST_CTRL}, 3206 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3207 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 3208 {0x0000, RX_DIAG_PI_CAP}, 3209 {0x0031, RX_DIAG_PI_RATE}, 3210 {0x0001, RX_DIAG_ACYA}, 3211 {0x018C, RX_CDRLF_CNFG}, 3212 {0x0003, RX_CDRLF_CNFG3} 3213 }; 3214 3215 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = { 3216 .reg_pairs = usb_100_no_ssc_cmn_regs, 3217 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs), 3218 }; 3219 3220 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = { 3221 .reg_pairs = usb_100_no_ssc_tx_ln_regs, 3222 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs), 3223 }; 3224 3225 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = { 3226 .reg_pairs = usb_100_no_ssc_rx_ln_regs, 3227 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs), 3228 }; 3229 3230 /* Single link USB, 100 MHz Ref clk, internal SSC */ 3231 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { 3232 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3233 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3234 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3235 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3236 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3237 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3238 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3239 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3240 {0x0064, CMN_PLL0_INTDIV_M0}, 3241 {0x0064, CMN_PLL1_INTDIV_M0}, 3242 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3243 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3244 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3245 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3246 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3247 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3248 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3249 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3250 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3251 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3252 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3253 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3254 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3255 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3256 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3257 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3258 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3259 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3260 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3261 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3262 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3263 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3264 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3265 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3266 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3267 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3268 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3269 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 3270 }; 3271 3272 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = { 3273 .reg_pairs = sl_usb_100_int_ssc_cmn_regs, 3274 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs), 3275 }; 3276 3277 /* PCIe and SGMII/QSGMII Unique SSC link configuration */ 3278 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { 3279 {0x0003, PHY_PLL_CFG}, 3280 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3281 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3282 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3283 }; 3284 3285 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { 3286 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3287 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3288 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3289 }; 3290 3291 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { 3292 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3293 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3294 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 3295 }; 3296 3297 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = { 3298 .reg_pairs = pcie_sgmii_link_cmn_regs, 3299 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs), 3300 }; 3301 3302 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = { 3303 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs, 3304 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs), 3305 }; 3306 3307 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { 3308 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs, 3309 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs), 3310 }; 3311 3312 /* SGMII 100 MHz Ref clk, no SSC */ 3313 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { 3314 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3315 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3316 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3317 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3318 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3319 }; 3320 3321 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = { 3322 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs, 3323 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), 3324 }; 3325 3326 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { 3327 {0x007F, CMN_TXPUCAL_TUNE}, 3328 {0x007F, CMN_TXPDCAL_TUNE} 3329 }; 3330 3331 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { 3332 {0x00F3, TX_PSC_A0}, 3333 {0x04A2, TX_PSC_A2}, 3334 {0x04A2, TX_PSC_A3}, 3335 {0x0000, TX_TXCC_CPOST_MULT_00}, 3336 {0x00B3, DRV_DIAG_TX_DRV} 3337 }; 3338 3339 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { 3340 {0x00F3, TX_PSC_A0}, 3341 {0x04A2, TX_PSC_A2}, 3342 {0x04A2, TX_PSC_A3}, 3343 {0x0000, TX_TXCC_CPOST_MULT_00}, 3344 {0x00B3, DRV_DIAG_TX_DRV}, 3345 {0x4000, XCVR_DIAG_RXCLK_CTRL}, 3346 }; 3347 3348 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { 3349 {0x091D, RX_PSC_A0}, 3350 {0x0900, RX_PSC_A2}, 3351 {0x0100, RX_PSC_A3}, 3352 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3353 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3354 {0x0000, RX_DIAG_DFE_CTRL}, 3355 {0x0019, RX_REE_TAP1_CLIP}, 3356 {0x0019, RX_REE_TAP2TON_CLIP}, 3357 {0x0098, RX_DIAG_NQST_CTRL}, 3358 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3359 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 3360 {0x0000, RX_DIAG_PI_CAP}, 3361 {0x0010, RX_DIAG_PI_RATE}, 3362 {0x0001, RX_DIAG_ACYA}, 3363 {0x018C, RX_CDRLF_CNFG}, 3364 }; 3365 3366 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = { 3367 .reg_pairs = sgmii_100_no_ssc_cmn_regs, 3368 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs), 3369 }; 3370 3371 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { 3372 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs, 3373 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), 3374 }; 3375 3376 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = { 3377 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs, 3378 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs), 3379 }; 3380 3381 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { 3382 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, 3383 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), 3384 }; 3385 3386 /* SGMII 100 MHz Ref clk, internal SSC */ 3387 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { 3388 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3389 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3390 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3391 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3392 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3393 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3394 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3395 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3396 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3397 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3398 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3399 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3400 {0x0064, CMN_PLL0_INTDIV_M0}, 3401 {0x0050, CMN_PLL0_INTDIV_M1}, 3402 {0x0064, CMN_PLL1_INTDIV_M0}, 3403 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3404 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3405 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3406 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3407 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3408 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3409 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3410 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3411 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3412 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3413 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3414 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3415 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3416 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3417 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3418 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3419 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3420 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3421 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3422 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3423 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3424 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3425 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3426 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3427 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3428 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3429 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3430 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3431 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3432 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3433 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3434 {0x007F, CMN_TXPUCAL_TUNE}, 3435 {0x007F, CMN_TXPDCAL_TUNE} 3436 }; 3437 3438 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { 3439 .reg_pairs = sgmii_100_int_ssc_cmn_regs, 3440 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs), 3441 }; 3442 3443 /* QSGMII 100 MHz Ref clk, no SSC */ 3444 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { 3445 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3446 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3447 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3448 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3449 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3450 }; 3451 3452 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = { 3453 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs, 3454 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), 3455 }; 3456 3457 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { 3458 {0x007F, CMN_TXPUCAL_TUNE}, 3459 {0x007F, CMN_TXPDCAL_TUNE} 3460 }; 3461 3462 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { 3463 {0x00F3, TX_PSC_A0}, 3464 {0x04A2, TX_PSC_A2}, 3465 {0x04A2, TX_PSC_A3}, 3466 {0x0000, TX_TXCC_CPOST_MULT_00}, 3467 {0x0011, TX_TXCC_MGNFS_MULT_100}, 3468 {0x0003, DRV_DIAG_TX_DRV} 3469 }; 3470 3471 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { 3472 {0x00F3, TX_PSC_A0}, 3473 {0x04A2, TX_PSC_A2}, 3474 {0x04A2, TX_PSC_A3}, 3475 {0x0000, TX_TXCC_CPOST_MULT_00}, 3476 {0x0011, TX_TXCC_MGNFS_MULT_100}, 3477 {0x0003, DRV_DIAG_TX_DRV}, 3478 {0x4000, XCVR_DIAG_RXCLK_CTRL}, 3479 }; 3480 3481 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { 3482 {0x091D, RX_PSC_A0}, 3483 {0x0900, RX_PSC_A2}, 3484 {0x0100, RX_PSC_A3}, 3485 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3486 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3487 {0x0000, RX_DIAG_DFE_CTRL}, 3488 {0x0019, RX_REE_TAP1_CLIP}, 3489 {0x0019, RX_REE_TAP2TON_CLIP}, 3490 {0x0098, RX_DIAG_NQST_CTRL}, 3491 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3492 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 3493 {0x0000, RX_DIAG_PI_CAP}, 3494 {0x0010, RX_DIAG_PI_RATE}, 3495 {0x0001, RX_DIAG_ACYA}, 3496 {0x018C, RX_CDRLF_CNFG}, 3497 }; 3498 3499 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = { 3500 .reg_pairs = qsgmii_100_no_ssc_cmn_regs, 3501 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs), 3502 }; 3503 3504 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { 3505 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs, 3506 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), 3507 }; 3508 3509 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = { 3510 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs, 3511 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs), 3512 }; 3513 3514 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { 3515 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, 3516 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), 3517 }; 3518 3519 /* QSGMII 100 MHz Ref clk, internal SSC */ 3520 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { 3521 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3522 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3523 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3524 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3525 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3526 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3527 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3528 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3529 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3530 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3531 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3532 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3533 {0x0064, CMN_PLL0_INTDIV_M0}, 3534 {0x0050, CMN_PLL0_INTDIV_M1}, 3535 {0x0064, CMN_PLL1_INTDIV_M0}, 3536 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3537 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3538 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3539 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3540 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3541 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3542 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3543 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3544 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3545 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3546 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3547 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3548 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3549 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3550 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3551 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3552 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3553 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3554 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3555 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3556 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3557 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3558 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3559 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3560 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3561 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3562 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3563 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3564 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3565 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3566 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3567 {0x007F, CMN_TXPUCAL_TUNE}, 3568 {0x007F, CMN_TXPDCAL_TUNE} 3569 }; 3570 3571 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { 3572 .reg_pairs = qsgmii_100_int_ssc_cmn_regs, 3573 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs), 3574 }; 3575 3576 /* Single SGMII/QSGMII link configuration */ 3577 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { 3578 {0x0000, PHY_PLL_CFG}, 3579 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} 3580 }; 3581 3582 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { 3583 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3584 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3585 {0x0013, XCVR_DIAG_PLLDRC_CTRL} 3586 }; 3587 3588 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = { 3589 .reg_pairs = sl_sgmii_link_cmn_regs, 3590 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs), 3591 }; 3592 3593 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = { 3594 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs, 3595 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs), 3596 }; 3597 3598 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */ 3599 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { 3600 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3601 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3602 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3603 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3604 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3605 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3606 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3607 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3608 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3609 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3610 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3611 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3612 {0x0064, CMN_PLL0_INTDIV_M0}, 3613 {0x0050, CMN_PLL0_INTDIV_M1}, 3614 {0x0064, CMN_PLL1_INTDIV_M0}, 3615 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3616 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3617 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3618 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3619 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3620 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3621 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3622 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3623 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3624 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3625 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3626 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3627 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3628 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3629 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3630 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3631 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3632 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3633 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3634 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3635 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3636 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3637 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3638 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3639 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3640 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3641 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3642 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3643 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3644 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3645 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 3646 }; 3647 3648 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = { 3649 .reg_pairs = pcie_100_int_ssc_cmn_regs, 3650 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs), 3651 }; 3652 3653 /* Single link PCIe, 100 MHz Ref clk, internal SSC */ 3654 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { 3655 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3656 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3657 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3658 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3659 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3660 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3661 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3662 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3663 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3664 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3665 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3666 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3667 {0x0064, CMN_PLL0_INTDIV_M0}, 3668 {0x0050, CMN_PLL0_INTDIV_M1}, 3669 {0x0050, CMN_PLL1_INTDIV_M0}, 3670 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3671 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3672 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3673 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3674 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3675 {0x0036, CMN_PLL1_HIGH_THR_M0}, 3676 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3677 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3678 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3679 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3680 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3681 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3682 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3683 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3684 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3685 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3686 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3687 {0x0058, CMN_PLL1_SS_CTRL3_M0}, 3688 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3689 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3690 {0x0012, CMN_PLL1_SS_CTRL4_M0}, 3691 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3692 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3693 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3694 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3695 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3696 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3697 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3698 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3699 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3700 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 3701 }; 3702 3703 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { 3704 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs, 3705 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs), 3706 }; 3707 3708 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ 3709 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { 3710 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3711 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3712 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} 3713 }; 3714 3715 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { 3716 {0x0019, RX_REE_TAP1_CLIP}, 3717 {0x0019, RX_REE_TAP2TON_CLIP}, 3718 {0x0001, RX_DIAG_ACYA} 3719 }; 3720 3721 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = { 3722 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs, 3723 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs), 3724 }; 3725 3726 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { 3727 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs, 3728 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs), 3729 }; 3730 3731 static const struct cdns_torrent_data cdns_map_torrent = { 3732 .block_offset_shift = 0x2, 3733 .reg_offset_shift = 0x2, 3734 .link_cmn_vals = { 3735 [TYPE_DP] = { 3736 [TYPE_NONE] = { 3737 [NO_SSC] = &sl_dp_link_cmn_vals, 3738 }, 3739 }, 3740 [TYPE_PCIE] = { 3741 [TYPE_NONE] = { 3742 [NO_SSC] = NULL, 3743 [EXTERNAL_SSC] = NULL, 3744 [INTERNAL_SSC] = NULL, 3745 }, 3746 [TYPE_SGMII] = { 3747 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3748 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3749 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3750 }, 3751 [TYPE_QSGMII] = { 3752 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3753 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3754 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3755 }, 3756 [TYPE_USB] = { 3757 [NO_SSC] = &pcie_usb_link_cmn_vals, 3758 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3759 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3760 }, 3761 }, 3762 [TYPE_SGMII] = { 3763 [TYPE_NONE] = { 3764 [NO_SSC] = &sl_sgmii_link_cmn_vals, 3765 }, 3766 [TYPE_PCIE] = { 3767 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3768 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3769 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3770 }, 3771 [TYPE_USB] = { 3772 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3773 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3774 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3775 }, 3776 }, 3777 [TYPE_QSGMII] = { 3778 [TYPE_NONE] = { 3779 [NO_SSC] = &sl_sgmii_link_cmn_vals, 3780 }, 3781 [TYPE_PCIE] = { 3782 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3783 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3784 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3785 }, 3786 [TYPE_USB] = { 3787 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3788 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3789 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3790 }, 3791 }, 3792 [TYPE_USB] = { 3793 [TYPE_NONE] = { 3794 [NO_SSC] = &sl_usb_link_cmn_vals, 3795 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, 3796 [INTERNAL_SSC] = &sl_usb_link_cmn_vals, 3797 }, 3798 [TYPE_PCIE] = { 3799 [NO_SSC] = &pcie_usb_link_cmn_vals, 3800 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3801 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3802 }, 3803 [TYPE_SGMII] = { 3804 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3805 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3806 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3807 }, 3808 [TYPE_QSGMII] = { 3809 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3810 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3811 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3812 }, 3813 }, 3814 }, 3815 .xcvr_diag_vals = { 3816 [TYPE_DP] = { 3817 [TYPE_NONE] = { 3818 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals, 3819 }, 3820 }, 3821 [TYPE_PCIE] = { 3822 [TYPE_NONE] = { 3823 [NO_SSC] = NULL, 3824 [EXTERNAL_SSC] = NULL, 3825 [INTERNAL_SSC] = NULL, 3826 }, 3827 [TYPE_SGMII] = { 3828 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3829 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3830 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3831 }, 3832 [TYPE_QSGMII] = { 3833 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3834 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3835 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3836 }, 3837 [TYPE_USB] = { 3838 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals, 3839 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 3840 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 3841 }, 3842 }, 3843 [TYPE_SGMII] = { 3844 [TYPE_NONE] = { 3845 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 3846 }, 3847 [TYPE_PCIE] = { 3848 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3849 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3850 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3851 }, 3852 [TYPE_USB] = { 3853 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3854 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3855 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3856 }, 3857 }, 3858 [TYPE_QSGMII] = { 3859 [TYPE_NONE] = { 3860 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 3861 }, 3862 [TYPE_PCIE] = { 3863 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3864 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3865 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3866 }, 3867 [TYPE_USB] = { 3868 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3869 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3870 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3871 }, 3872 }, 3873 [TYPE_USB] = { 3874 [TYPE_NONE] = { 3875 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, 3876 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 3877 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 3878 }, 3879 [TYPE_PCIE] = { 3880 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals, 3881 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 3882 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 3883 }, 3884 [TYPE_SGMII] = { 3885 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3886 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3887 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3888 }, 3889 [TYPE_QSGMII] = { 3890 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3891 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3892 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3893 }, 3894 }, 3895 }, 3896 .pcs_cmn_vals = { 3897 [TYPE_USB] = { 3898 [TYPE_NONE] = { 3899 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3900 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3901 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3902 }, 3903 [TYPE_PCIE] = { 3904 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3905 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3906 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3907 }, 3908 [TYPE_SGMII] = { 3909 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3910 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3911 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3912 }, 3913 [TYPE_QSGMII] = { 3914 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3915 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3916 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3917 }, 3918 }, 3919 }, 3920 .cmn_vals = { 3921 [CLK_19_2_MHZ] = { 3922 [TYPE_DP] = { 3923 [TYPE_NONE] = { 3924 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals, 3925 }, 3926 }, 3927 }, 3928 [CLK_25_MHZ] = { 3929 [TYPE_DP] = { 3930 [TYPE_NONE] = { 3931 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals, 3932 }, 3933 }, 3934 }, 3935 [CLK_100_MHZ] = { 3936 [TYPE_DP] = { 3937 [TYPE_NONE] = { 3938 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals, 3939 }, 3940 }, 3941 [TYPE_PCIE] = { 3942 [TYPE_NONE] = { 3943 [NO_SSC] = NULL, 3944 [EXTERNAL_SSC] = NULL, 3945 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, 3946 }, 3947 [TYPE_SGMII] = { 3948 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 3949 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 3950 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 3951 }, 3952 [TYPE_QSGMII] = { 3953 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 3954 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 3955 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 3956 }, 3957 [TYPE_USB] = { 3958 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 3959 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 3960 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 3961 }, 3962 }, 3963 [TYPE_SGMII] = { 3964 [TYPE_NONE] = { 3965 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, 3966 }, 3967 [TYPE_PCIE] = { 3968 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 3969 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 3970 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, 3971 }, 3972 [TYPE_USB] = { 3973 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 3974 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 3975 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 3976 }, 3977 }, 3978 [TYPE_QSGMII] = { 3979 [TYPE_NONE] = { 3980 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, 3981 }, 3982 [TYPE_PCIE] = { 3983 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3984 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3985 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, 3986 }, 3987 [TYPE_USB] = { 3988 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3989 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3990 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3991 }, 3992 }, 3993 [TYPE_USB] = { 3994 [TYPE_NONE] = { 3995 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3996 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3997 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 3998 }, 3999 [TYPE_PCIE] = { 4000 [NO_SSC] = &usb_100_no_ssc_cmn_vals, 4001 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, 4002 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, 4003 }, 4004 [TYPE_SGMII] = { 4005 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4006 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4007 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4008 }, 4009 [TYPE_QSGMII] = { 4010 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4011 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4012 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4013 }, 4014 }, 4015 }, 4016 }, 4017 .tx_ln_vals = { 4018 [CLK_19_2_MHZ] = { 4019 [TYPE_DP] = { 4020 [TYPE_NONE] = { 4021 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals, 4022 }, 4023 }, 4024 }, 4025 [CLK_25_MHZ] = { 4026 [TYPE_DP] = { 4027 [TYPE_NONE] = { 4028 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals, 4029 }, 4030 }, 4031 }, 4032 [CLK_100_MHZ] = { 4033 [TYPE_DP] = { 4034 [TYPE_NONE] = { 4035 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals, 4036 }, 4037 }, 4038 [TYPE_PCIE] = { 4039 [TYPE_NONE] = { 4040 [NO_SSC] = NULL, 4041 [EXTERNAL_SSC] = NULL, 4042 [INTERNAL_SSC] = NULL, 4043 }, 4044 [TYPE_SGMII] = { 4045 [NO_SSC] = NULL, 4046 [EXTERNAL_SSC] = NULL, 4047 [INTERNAL_SSC] = NULL, 4048 }, 4049 [TYPE_QSGMII] = { 4050 [NO_SSC] = NULL, 4051 [EXTERNAL_SSC] = NULL, 4052 [INTERNAL_SSC] = NULL, 4053 }, 4054 [TYPE_USB] = { 4055 [NO_SSC] = NULL, 4056 [EXTERNAL_SSC] = NULL, 4057 [INTERNAL_SSC] = NULL, 4058 }, 4059 }, 4060 [TYPE_SGMII] = { 4061 [TYPE_NONE] = { 4062 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4063 }, 4064 [TYPE_PCIE] = { 4065 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4066 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4067 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4068 }, 4069 [TYPE_USB] = { 4070 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4071 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4072 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 4073 }, 4074 }, 4075 [TYPE_QSGMII] = { 4076 [TYPE_NONE] = { 4077 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4078 }, 4079 [TYPE_PCIE] = { 4080 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4081 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4082 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4083 }, 4084 [TYPE_USB] = { 4085 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4086 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4087 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 4088 }, 4089 }, 4090 [TYPE_USB] = { 4091 [TYPE_NONE] = { 4092 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4093 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4094 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4095 }, 4096 [TYPE_PCIE] = { 4097 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4098 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4099 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4100 }, 4101 [TYPE_SGMII] = { 4102 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4103 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4104 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4105 }, 4106 [TYPE_QSGMII] = { 4107 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4108 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4109 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4110 }, 4111 }, 4112 }, 4113 }, 4114 .rx_ln_vals = { 4115 [CLK_19_2_MHZ] = { 4116 [TYPE_DP] = { 4117 [TYPE_NONE] = { 4118 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals, 4119 }, 4120 }, 4121 }, 4122 [CLK_25_MHZ] = { 4123 [TYPE_DP] = { 4124 [TYPE_NONE] = { 4125 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals, 4126 }, 4127 }, 4128 }, 4129 [CLK_100_MHZ] = { 4130 [TYPE_DP] = { 4131 [TYPE_NONE] = { 4132 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals, 4133 }, 4134 }, 4135 [TYPE_PCIE] = { 4136 [TYPE_NONE] = { 4137 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4138 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4139 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4140 }, 4141 [TYPE_SGMII] = { 4142 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4143 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4144 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4145 }, 4146 [TYPE_QSGMII] = { 4147 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4148 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4149 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4150 }, 4151 [TYPE_USB] = { 4152 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4153 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4154 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4155 }, 4156 }, 4157 [TYPE_SGMII] = { 4158 [TYPE_NONE] = { 4159 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4160 }, 4161 [TYPE_PCIE] = { 4162 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4163 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4164 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4165 }, 4166 [TYPE_USB] = { 4167 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4168 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4169 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4170 }, 4171 }, 4172 [TYPE_QSGMII] = { 4173 [TYPE_NONE] = { 4174 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4175 }, 4176 [TYPE_PCIE] = { 4177 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4178 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4179 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4180 }, 4181 [TYPE_USB] = { 4182 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4183 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4184 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4185 }, 4186 }, 4187 [TYPE_USB] = { 4188 [TYPE_NONE] = { 4189 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4190 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4191 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4192 }, 4193 [TYPE_PCIE] = { 4194 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4195 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4196 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4197 }, 4198 [TYPE_SGMII] = { 4199 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4200 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4201 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4202 }, 4203 [TYPE_QSGMII] = { 4204 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4205 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4206 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4207 }, 4208 }, 4209 }, 4210 }, 4211 }; 4212 4213 static const struct cdns_torrent_data ti_j721e_map_torrent = { 4214 .block_offset_shift = 0x0, 4215 .reg_offset_shift = 0x1, 4216 .link_cmn_vals = { 4217 [TYPE_DP] = { 4218 [TYPE_NONE] = { 4219 [NO_SSC] = &sl_dp_link_cmn_vals, 4220 }, 4221 }, 4222 [TYPE_PCIE] = { 4223 [TYPE_NONE] = { 4224 [NO_SSC] = NULL, 4225 [EXTERNAL_SSC] = NULL, 4226 [INTERNAL_SSC] = NULL, 4227 }, 4228 [TYPE_SGMII] = { 4229 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 4230 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4231 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4232 }, 4233 [TYPE_QSGMII] = { 4234 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 4235 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4236 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4237 }, 4238 [TYPE_USB] = { 4239 [NO_SSC] = &pcie_usb_link_cmn_vals, 4240 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 4241 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 4242 }, 4243 }, 4244 [TYPE_SGMII] = { 4245 [TYPE_NONE] = { 4246 [NO_SSC] = &sl_sgmii_link_cmn_vals, 4247 }, 4248 [TYPE_PCIE] = { 4249 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 4250 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4251 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4252 }, 4253 [TYPE_USB] = { 4254 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4255 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4256 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4257 }, 4258 }, 4259 [TYPE_QSGMII] = { 4260 [TYPE_NONE] = { 4261 [NO_SSC] = &sl_sgmii_link_cmn_vals, 4262 }, 4263 [TYPE_PCIE] = { 4264 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 4265 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4266 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4267 }, 4268 [TYPE_USB] = { 4269 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4270 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4271 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4272 }, 4273 }, 4274 [TYPE_USB] = { 4275 [TYPE_NONE] = { 4276 [NO_SSC] = &sl_usb_link_cmn_vals, 4277 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, 4278 [INTERNAL_SSC] = &sl_usb_link_cmn_vals, 4279 }, 4280 [TYPE_PCIE] = { 4281 [NO_SSC] = &pcie_usb_link_cmn_vals, 4282 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 4283 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 4284 }, 4285 [TYPE_SGMII] = { 4286 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4287 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4288 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4289 }, 4290 [TYPE_QSGMII] = { 4291 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4292 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4293 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4294 }, 4295 }, 4296 }, 4297 .xcvr_diag_vals = { 4298 [TYPE_DP] = { 4299 [TYPE_NONE] = { 4300 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals, 4301 }, 4302 }, 4303 [TYPE_PCIE] = { 4304 [TYPE_NONE] = { 4305 [NO_SSC] = NULL, 4306 [EXTERNAL_SSC] = NULL, 4307 [INTERNAL_SSC] = NULL, 4308 }, 4309 [TYPE_SGMII] = { 4310 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4311 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4312 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4313 }, 4314 [TYPE_QSGMII] = { 4315 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4316 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4317 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4318 }, 4319 [TYPE_USB] = { 4320 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals, 4321 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 4322 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 4323 }, 4324 }, 4325 [TYPE_SGMII] = { 4326 [TYPE_NONE] = { 4327 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 4328 }, 4329 [TYPE_PCIE] = { 4330 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4331 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4332 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4333 }, 4334 [TYPE_USB] = { 4335 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4336 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4337 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4338 }, 4339 }, 4340 [TYPE_QSGMII] = { 4341 [TYPE_NONE] = { 4342 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 4343 }, 4344 [TYPE_PCIE] = { 4345 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4346 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4347 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4348 }, 4349 [TYPE_USB] = { 4350 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4351 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4352 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4353 }, 4354 }, 4355 [TYPE_USB] = { 4356 [TYPE_NONE] = { 4357 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, 4358 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 4359 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 4360 }, 4361 [TYPE_PCIE] = { 4362 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals, 4363 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 4364 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 4365 }, 4366 [TYPE_SGMII] = { 4367 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4368 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4369 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4370 }, 4371 [TYPE_QSGMII] = { 4372 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4373 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4374 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4375 }, 4376 }, 4377 }, 4378 .pcs_cmn_vals = { 4379 [TYPE_USB] = { 4380 [TYPE_NONE] = { 4381 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4382 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4383 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4384 }, 4385 [TYPE_PCIE] = { 4386 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4387 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4388 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4389 }, 4390 [TYPE_SGMII] = { 4391 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4392 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4393 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4394 }, 4395 [TYPE_QSGMII] = { 4396 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4397 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4398 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4399 }, 4400 }, 4401 }, 4402 .cmn_vals = { 4403 [CLK_19_2_MHZ] = { 4404 [TYPE_DP] = { 4405 [TYPE_NONE] = { 4406 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals, 4407 }, 4408 }, 4409 }, 4410 [CLK_25_MHZ] = { 4411 [TYPE_DP] = { 4412 [TYPE_NONE] = { 4413 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals, 4414 }, 4415 }, 4416 }, 4417 [CLK_100_MHZ] = { 4418 [TYPE_DP] = { 4419 [TYPE_NONE] = { 4420 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals, 4421 }, 4422 }, 4423 [TYPE_PCIE] = { 4424 [TYPE_NONE] = { 4425 [NO_SSC] = NULL, 4426 [EXTERNAL_SSC] = NULL, 4427 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, 4428 }, 4429 [TYPE_SGMII] = { 4430 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 4431 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 4432 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 4433 }, 4434 [TYPE_QSGMII] = { 4435 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 4436 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 4437 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 4438 }, 4439 [TYPE_USB] = { 4440 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 4441 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 4442 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 4443 }, 4444 }, 4445 [TYPE_SGMII] = { 4446 [TYPE_NONE] = { 4447 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, 4448 }, 4449 [TYPE_PCIE] = { 4450 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 4451 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 4452 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, 4453 }, 4454 [TYPE_USB] = { 4455 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 4456 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 4457 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 4458 }, 4459 }, 4460 [TYPE_QSGMII] = { 4461 [TYPE_NONE] = { 4462 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, 4463 }, 4464 [TYPE_PCIE] = { 4465 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4466 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4467 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, 4468 }, 4469 [TYPE_USB] = { 4470 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4471 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4472 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4473 }, 4474 }, 4475 [TYPE_USB] = { 4476 [TYPE_NONE] = { 4477 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4478 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4479 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4480 }, 4481 [TYPE_PCIE] = { 4482 [NO_SSC] = &usb_100_no_ssc_cmn_vals, 4483 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, 4484 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, 4485 }, 4486 [TYPE_SGMII] = { 4487 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4488 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4489 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4490 }, 4491 [TYPE_QSGMII] = { 4492 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4493 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4494 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4495 }, 4496 }, 4497 }, 4498 }, 4499 .tx_ln_vals = { 4500 [CLK_19_2_MHZ] = { 4501 [TYPE_DP] = { 4502 [TYPE_NONE] = { 4503 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals, 4504 }, 4505 }, 4506 }, 4507 [CLK_25_MHZ] = { 4508 [TYPE_DP] = { 4509 [TYPE_NONE] = { 4510 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals, 4511 }, 4512 }, 4513 }, 4514 [CLK_100_MHZ] = { 4515 [TYPE_DP] = { 4516 [TYPE_NONE] = { 4517 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals, 4518 }, 4519 }, 4520 [TYPE_PCIE] = { 4521 [TYPE_NONE] = { 4522 [NO_SSC] = NULL, 4523 [EXTERNAL_SSC] = NULL, 4524 [INTERNAL_SSC] = NULL, 4525 }, 4526 [TYPE_SGMII] = { 4527 [NO_SSC] = NULL, 4528 [EXTERNAL_SSC] = NULL, 4529 [INTERNAL_SSC] = NULL, 4530 }, 4531 [TYPE_QSGMII] = { 4532 [NO_SSC] = NULL, 4533 [EXTERNAL_SSC] = NULL, 4534 [INTERNAL_SSC] = NULL, 4535 }, 4536 [TYPE_USB] = { 4537 [NO_SSC] = NULL, 4538 [EXTERNAL_SSC] = NULL, 4539 [INTERNAL_SSC] = NULL, 4540 }, 4541 }, 4542 [TYPE_SGMII] = { 4543 [TYPE_NONE] = { 4544 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4545 }, 4546 [TYPE_PCIE] = { 4547 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4548 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4549 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4550 }, 4551 [TYPE_USB] = { 4552 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4553 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4554 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4555 }, 4556 }, 4557 [TYPE_QSGMII] = { 4558 [TYPE_NONE] = { 4559 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4560 }, 4561 [TYPE_PCIE] = { 4562 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4563 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4564 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4565 }, 4566 [TYPE_USB] = { 4567 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4568 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4569 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4570 }, 4571 }, 4572 [TYPE_USB] = { 4573 [TYPE_NONE] = { 4574 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4575 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4576 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4577 }, 4578 [TYPE_PCIE] = { 4579 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4580 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4581 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4582 }, 4583 [TYPE_SGMII] = { 4584 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4585 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4586 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4587 }, 4588 [TYPE_QSGMII] = { 4589 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4590 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4591 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4592 }, 4593 }, 4594 }, 4595 }, 4596 .rx_ln_vals = { 4597 [CLK_19_2_MHZ] = { 4598 [TYPE_DP] = { 4599 [TYPE_NONE] = { 4600 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals, 4601 }, 4602 }, 4603 }, 4604 [CLK_25_MHZ] = { 4605 [TYPE_DP] = { 4606 [TYPE_NONE] = { 4607 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals, 4608 }, 4609 }, 4610 }, 4611 [CLK_100_MHZ] = { 4612 [TYPE_DP] = { 4613 [TYPE_NONE] = { 4614 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals, 4615 }, 4616 }, 4617 [TYPE_PCIE] = { 4618 [TYPE_NONE] = { 4619 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4620 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4621 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4622 }, 4623 [TYPE_SGMII] = { 4624 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4625 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4626 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4627 }, 4628 [TYPE_QSGMII] = { 4629 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4630 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4631 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4632 }, 4633 [TYPE_USB] = { 4634 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4635 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4636 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4637 }, 4638 }, 4639 [TYPE_SGMII] = { 4640 [TYPE_NONE] = { 4641 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4642 }, 4643 [TYPE_PCIE] = { 4644 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4645 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4646 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4647 }, 4648 [TYPE_USB] = { 4649 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4650 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4651 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4652 }, 4653 }, 4654 [TYPE_QSGMII] = { 4655 [TYPE_NONE] = { 4656 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4657 }, 4658 [TYPE_PCIE] = { 4659 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4660 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4661 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4662 }, 4663 [TYPE_USB] = { 4664 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4665 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4666 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4667 }, 4668 }, 4669 [TYPE_USB] = { 4670 [TYPE_NONE] = { 4671 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4672 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4673 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4674 }, 4675 [TYPE_PCIE] = { 4676 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4677 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4678 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4679 }, 4680 [TYPE_SGMII] = { 4681 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4682 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4683 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4684 }, 4685 [TYPE_QSGMII] = { 4686 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4687 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4688 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4689 }, 4690 }, 4691 }, 4692 }, 4693 }; 4694 4695 static const struct of_device_id cdns_torrent_phy_of_match[] = { 4696 { 4697 .compatible = "cdns,torrent-phy", 4698 .data = &cdns_map_torrent, 4699 }, 4700 { 4701 .compatible = "ti,j721e-serdes-10g", 4702 .data = &ti_j721e_map_torrent, 4703 }, 4704 {} 4705 }; 4706 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); 4707 4708 static struct platform_driver cdns_torrent_phy_driver = { 4709 .probe = cdns_torrent_phy_probe, 4710 .remove_new = cdns_torrent_phy_remove, 4711 .driver = { 4712 .name = "cdns-torrent-phy", 4713 .of_match_table = cdns_torrent_phy_of_match, 4714 } 4715 }; 4716 module_platform_driver(cdns_torrent_phy_driver); 4717 4718 MODULE_AUTHOR("Cadence Design Systems, Inc."); 4719 MODULE_DESCRIPTION("Cadence Torrent PHY driver"); 4720 MODULE_LICENSE("GPL v2"); 4721