1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cadence Torrent SD0801 PHY driver. 4 * 5 * Copyright 2018 Cadence Design Systems, Inc. 6 * 7 */ 8 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/phy/phy-cadence.h> 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/iopoll.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/reset.h> 25 #include <linux/regmap.h> 26 27 #define REF_CLK_19_2MHZ 19200000 28 #define REF_CLK_25MHZ 25000000 29 #define REF_CLK_100MHZ 100000000 30 31 #define MAX_NUM_LANES 4 32 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ 33 34 #define NUM_SSC_MODE 3 35 #define NUM_REF_CLK 3 36 #define NUM_PHY_TYPE 6 37 38 #define POLL_TIMEOUT_US 5000 39 #define PLL_LOCK_TIMEOUT 100000 40 41 #define TORRENT_COMMON_CDB_OFFSET 0x0 42 43 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 44 ((0x4000 << (block_offset)) + \ 45 (((ln) << 9) << (reg_offset))) 46 47 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 48 ((0x8000 << (block_offset)) + \ 49 (((ln) << 9) << (reg_offset))) 50 51 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ 52 (0xC000 << (block_offset)) 53 54 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 55 ((0xD000 << (block_offset)) + \ 56 (((ln) << 8) << (reg_offset))) 57 58 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ 59 (0xE000 << (block_offset)) 60 61 #define TORRENT_DPTX_PHY_OFFSET 0x0 62 63 /* 64 * register offsets from DPTX PHY register block base (i.e MHDP 65 * register base + 0x30a00) 66 */ 67 #define PHY_AUX_CTRL 0x04 68 #define PHY_RESET 0x20 69 #define PMA_TX_ELEC_IDLE_MASK 0xF0U 70 #define PMA_TX_ELEC_IDLE_SHIFT 4 71 #define PHY_L00_RESET_N_MASK 0x01U 72 #define PHY_PMA_XCVR_PLLCLK_EN 0x24 73 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 74 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c 75 #define PHY_POWER_STATE_LN_0 0x0000 76 #define PHY_POWER_STATE_LN_1 0x0008 77 #define PHY_POWER_STATE_LN_2 0x0010 78 #define PHY_POWER_STATE_LN_3 0x0018 79 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU 80 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 81 #define PHY_PMA_CMN_READY 0x34 82 83 /* 84 * register offsets from SD0801 PHY register block base (i.e MHDP 85 * register base + 0x500000) 86 */ 87 #define CMN_SSM_BANDGAP_TMR 0x0021U 88 #define CMN_SSM_BIAS_TMR 0x0022U 89 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU 90 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU 91 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U 92 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U 93 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U 94 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U 95 #define CMN_CDIAG_REFCLK_OVRD 0x004CU 96 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U 97 #define CMN_BGCAL_INIT_TMR 0x0064U 98 #define CMN_BGCAL_ITER_TMR 0x0065U 99 #define CMN_IBCAL_INIT_TMR 0x0074U 100 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U 101 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U 102 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U 103 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U 104 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U 105 #define CMN_PLL0_INTDIV_M0 0x0090U 106 #define CMN_PLL0_FRACDIVL_M0 0x0091U 107 #define CMN_PLL0_FRACDIVH_M0 0x0092U 108 #define CMN_PLL0_HIGH_THR_M0 0x0093U 109 #define CMN_PLL0_DSM_DIAG_M0 0x0094U 110 #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U 111 #define CMN_PLL0_SS_CTRL1_M0 0x0098U 112 #define CMN_PLL0_SS_CTRL2_M0 0x0099U 113 #define CMN_PLL0_SS_CTRL3_M0 0x009AU 114 #define CMN_PLL0_SS_CTRL4_M0 0x009BU 115 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU 116 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU 117 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU 118 #define CMN_PLL0_INTDIV_M1 0x00A0U 119 #define CMN_PLL0_FRACDIVH_M1 0x00A2U 120 #define CMN_PLL0_HIGH_THR_M1 0x00A3U 121 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U 122 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U 123 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U 124 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU 125 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU 126 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U 127 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U 128 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U 129 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U 130 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U 131 #define CMN_PLL1_INTDIV_M0 0x00D0U 132 #define CMN_PLL1_FRACDIVL_M0 0x00D1U 133 #define CMN_PLL1_FRACDIVH_M0 0x00D2U 134 #define CMN_PLL1_HIGH_THR_M0 0x00D3U 135 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U 136 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U 137 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U 138 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U 139 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U 140 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU 141 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU 142 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU 143 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU 144 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU 145 #define CMN_TXPUCAL_TUNE 0x0103U 146 #define CMN_TXPUCAL_INIT_TMR 0x0104U 147 #define CMN_TXPUCAL_ITER_TMR 0x0105U 148 #define CMN_TXPDCAL_TUNE 0x010BU 149 #define CMN_TXPDCAL_INIT_TMR 0x010CU 150 #define CMN_TXPDCAL_ITER_TMR 0x010DU 151 #define CMN_RXCAL_INIT_TMR 0x0114U 152 #define CMN_RXCAL_ITER_TMR 0x0115U 153 #define CMN_SD_CAL_INIT_TMR 0x0124U 154 #define CMN_SD_CAL_ITER_TMR 0x0125U 155 #define CMN_SD_CAL_REFTIM_START 0x0126U 156 #define CMN_SD_CAL_PLLCNT_START 0x0128U 157 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U 158 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U 159 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U 160 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U 161 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U 162 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U 163 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U 164 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U 165 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U 166 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U 167 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U 168 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U 169 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U 170 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U 171 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U 172 #define CMN_DIAG_BIAS_OVRD1 0x01E1U 173 174 /* PMA TX Lane registers */ 175 #define TX_TXCC_CTRL 0x0040U 176 #define TX_TXCC_CPOST_MULT_00 0x004CU 177 #define TX_TXCC_CPOST_MULT_01 0x004DU 178 #define TX_TXCC_MGNFS_MULT_000 0x0050U 179 #define TX_TXCC_MGNFS_MULT_100 0x0054U 180 #define DRV_DIAG_TX_DRV 0x00C6U 181 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U 182 #define XCVR_DIAG_HSCLK_SEL 0x00E6U 183 #define XCVR_DIAG_HSCLK_DIV 0x00E7U 184 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U 185 #define XCVR_DIAG_BIDI_CTRL 0x00EAU 186 #define XCVR_DIAG_PSC_OVRD 0x00EBU 187 #define TX_PSC_A0 0x0100U 188 #define TX_PSC_A1 0x0101U 189 #define TX_PSC_A2 0x0102U 190 #define TX_PSC_A3 0x0103U 191 #define TX_RCVDET_ST_TMR 0x0123U 192 #define TX_DIAG_ACYA 0x01E7U 193 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U 194 195 /* PMA RX Lane registers */ 196 #define RX_PSC_A0 0x0000U 197 #define RX_PSC_A1 0x0001U 198 #define RX_PSC_A2 0x0002U 199 #define RX_PSC_A3 0x0003U 200 #define RX_PSC_CAL 0x0006U 201 #define RX_CDRLF_CNFG 0x0080U 202 #define RX_CDRLF_CNFG3 0x0082U 203 #define RX_SIGDET_HL_FILT_TMR 0x0090U 204 #define RX_REE_GCSM1_CTRL 0x0108U 205 #define RX_REE_GCSM1_EQENM_PH1 0x0109U 206 #define RX_REE_GCSM1_EQENM_PH2 0x010AU 207 #define RX_REE_GCSM2_CTRL 0x0110U 208 #define RX_REE_PERGCSM_CTRL 0x0118U 209 #define RX_REE_ATTEN_THR 0x0149U 210 #define RX_REE_TAP1_CLIP 0x0171U 211 #define RX_REE_TAP2TON_CLIP 0x0172U 212 #define RX_REE_SMGM_CTRL1 0x0177U 213 #define RX_REE_SMGM_CTRL2 0x0178U 214 #define RX_DIAG_DFE_CTRL 0x01E0U 215 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U 216 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U 217 #define RX_DIAG_NQST_CTRL 0x01E5U 218 #define RX_DIAG_SIGDET_TUNE 0x01E8U 219 #define RX_DIAG_PI_RATE 0x01F4U 220 #define RX_DIAG_PI_CAP 0x01F5U 221 #define RX_DIAG_ACYA 0x01FFU 222 223 /* PHY PCS common registers */ 224 #define PHY_PIPE_CMN_CTRL1 0x0000U 225 #define PHY_PLL_CFG 0x000EU 226 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U 227 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U 228 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U 229 230 /* PHY PCS lane registers */ 231 #define PHY_PCS_ISO_LINK_CTRL 0x000BU 232 233 /* PHY PMA common registers */ 234 #define PHY_PMA_CMN_CTRL1 0x0000U 235 #define PHY_PMA_CMN_CTRL2 0x0001U 236 #define PHY_PMA_PLL_RAW_CTRL 0x0003U 237 238 static const char * const clk_names[] = { 239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", 240 }; 241 242 static const struct reg_field phy_pll_cfg = 243 REG_FIELD(PHY_PLL_CFG, 0, 1); 244 245 static const struct reg_field phy_pma_cmn_ctrl_1 = 246 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0); 247 248 static const struct reg_field phy_pma_cmn_ctrl_2 = 249 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); 250 251 static const struct reg_field phy_pma_pll_raw_ctrl = 252 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); 253 254 static const struct reg_field phy_reset_ctrl = 255 REG_FIELD(PHY_RESET, 8, 8); 256 257 static const struct reg_field phy_pcs_iso_link_ctrl_1 = 258 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1); 259 260 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0); 261 262 #define REFCLK_OUT_NUM_CMN_CONFIG 5 263 264 enum cdns_torrent_refclk_out_cmn { 265 CMN_CDIAG_REFCLK_OVRD_4, 266 CMN_CDIAG_REFCLK_DRV0_CTRL_1, 267 CMN_CDIAG_REFCLK_DRV0_CTRL_4, 268 CMN_CDIAG_REFCLK_DRV0_CTRL_5, 269 CMN_CDIAG_REFCLK_DRV0_CTRL_6, 270 }; 271 272 static const struct reg_field refclk_out_cmn_cfg[] = { 273 [CMN_CDIAG_REFCLK_OVRD_4] = REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4), 274 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), 275 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), 276 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), 277 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), 278 }; 279 280 enum cdns_torrent_phy_type { 281 TYPE_NONE, 282 TYPE_DP, 283 TYPE_PCIE, 284 TYPE_SGMII, 285 TYPE_QSGMII, 286 TYPE_USB, 287 }; 288 289 enum cdns_torrent_ref_clk { 290 CLK_19_2_MHZ, 291 CLK_25_MHZ, 292 CLK_100_MHZ 293 }; 294 295 enum cdns_torrent_ssc_mode { 296 NO_SSC, 297 EXTERNAL_SSC, 298 INTERNAL_SSC 299 }; 300 301 struct cdns_torrent_inst { 302 struct phy *phy; 303 u32 mlane; 304 enum cdns_torrent_phy_type phy_type; 305 u32 num_lanes; 306 struct reset_control *lnk_rst; 307 enum cdns_torrent_ssc_mode ssc_mode; 308 }; 309 310 struct cdns_torrent_phy { 311 void __iomem *base; /* DPTX registers base */ 312 void __iomem *sd_base; /* SD0801 registers base */ 313 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ 314 struct reset_control *phy_rst; 315 struct reset_control *apb_rst; 316 struct device *dev; 317 struct clk *clk; 318 enum cdns_torrent_ref_clk ref_clk_rate; 319 struct cdns_torrent_inst phys[MAX_NUM_LANES]; 320 int nsubnodes; 321 const struct cdns_torrent_data *init_data; 322 struct regmap *regmap; 323 struct regmap *regmap_common_cdb; 324 struct regmap *regmap_phy_pcs_common_cdb; 325 struct regmap *regmap_phy_pma_common_cdb; 326 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; 327 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; 328 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES]; 329 struct regmap *regmap_dptx_phy_reg; 330 struct regmap_field *phy_pll_cfg; 331 struct regmap_field *phy_pma_cmn_ctrl_1; 332 struct regmap_field *phy_pma_cmn_ctrl_2; 333 struct regmap_field *phy_pma_pll_raw_ctrl; 334 struct regmap_field *phy_reset_ctrl; 335 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES]; 336 struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1]; 337 struct clk_onecell_data clk_data; 338 }; 339 340 enum phy_powerstate { 341 POWERSTATE_A0 = 0, 342 /* Powerstate A1 is unused */ 343 POWERSTATE_A2 = 2, 344 POWERSTATE_A3 = 3, 345 }; 346 347 struct cdns_torrent_derived_refclk { 348 struct clk_hw hw; 349 struct regmap_field *phy_pipe_cmn_ctrl1_0; 350 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG]; 351 struct clk_init_data clk_data; 352 }; 353 354 #define to_cdns_torrent_derived_refclk(_hw) \ 355 container_of(_hw, struct cdns_torrent_derived_refclk, hw) 356 357 struct cdns_reg_pairs { 358 u32 val; 359 u32 off; 360 }; 361 362 struct cdns_torrent_vals { 363 struct cdns_reg_pairs *reg_pairs; 364 u32 num_regs; 365 }; 366 367 struct cdns_torrent_data { 368 u8 block_offset_shift; 369 u8 reg_offset_shift; 370 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 371 [NUM_SSC_MODE]; 372 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 373 [NUM_SSC_MODE]; 374 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 375 [NUM_SSC_MODE]; 376 struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE] 377 [NUM_PHY_TYPE][NUM_SSC_MODE]; 378 struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE] 379 [NUM_PHY_TYPE][NUM_SSC_MODE]; 380 struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE] 381 [NUM_PHY_TYPE][NUM_SSC_MODE]; 382 }; 383 384 struct cdns_regmap_cdb_context { 385 struct device *dev; 386 void __iomem *base; 387 u8 reg_offset_shift; 388 }; 389 390 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 391 { 392 struct cdns_regmap_cdb_context *ctx = context; 393 u32 offset = reg << ctx->reg_offset_shift; 394 395 writew(val, ctx->base + offset); 396 397 return 0; 398 } 399 400 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 401 { 402 struct cdns_regmap_cdb_context *ctx = context; 403 u32 offset = reg << ctx->reg_offset_shift; 404 405 *val = readw(ctx->base + offset); 406 return 0; 407 } 408 409 static int cdns_regmap_dptx_write(void *context, unsigned int reg, 410 unsigned int val) 411 { 412 struct cdns_regmap_cdb_context *ctx = context; 413 u32 offset = reg; 414 415 writel(val, ctx->base + offset); 416 417 return 0; 418 } 419 420 static int cdns_regmap_dptx_read(void *context, unsigned int reg, 421 unsigned int *val) 422 { 423 struct cdns_regmap_cdb_context *ctx = context; 424 u32 offset = reg; 425 426 *val = readl(ctx->base + offset); 427 return 0; 428 } 429 430 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ 431 { \ 432 .name = "torrent_tx_lane" n "_cdb", \ 433 .reg_stride = 1, \ 434 .fast_io = true, \ 435 .reg_write = cdns_regmap_write, \ 436 .reg_read = cdns_regmap_read, \ 437 } 438 439 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ 440 { \ 441 .name = "torrent_rx_lane" n "_cdb", \ 442 .reg_stride = 1, \ 443 .fast_io = true, \ 444 .reg_write = cdns_regmap_write, \ 445 .reg_read = cdns_regmap_read, \ 446 } 447 448 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { 449 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), 450 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), 451 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), 452 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), 453 }; 454 455 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { 456 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), 457 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), 458 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), 459 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), 460 }; 461 462 static const struct regmap_config cdns_torrent_common_cdb_config = { 463 .name = "torrent_common_cdb", 464 .reg_stride = 1, 465 .fast_io = true, 466 .reg_write = cdns_regmap_write, 467 .reg_read = cdns_regmap_read, 468 }; 469 470 #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 471 { \ 472 .name = "torrent_phy_pcs_lane" n "_cdb", \ 473 .reg_stride = 1, \ 474 .fast_io = true, \ 475 .reg_write = cdns_regmap_write, \ 476 .reg_read = cdns_regmap_read, \ 477 } 478 479 static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = { 480 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 481 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 482 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 483 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 484 }; 485 486 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { 487 .name = "torrent_phy_pcs_cmn_cdb", 488 .reg_stride = 1, 489 .fast_io = true, 490 .reg_write = cdns_regmap_write, 491 .reg_read = cdns_regmap_read, 492 }; 493 494 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { 495 .name = "torrent_phy_pma_cmn_cdb", 496 .reg_stride = 1, 497 .fast_io = true, 498 .reg_write = cdns_regmap_write, 499 .reg_read = cdns_regmap_read, 500 }; 501 502 static const struct regmap_config cdns_torrent_dptx_phy_config = { 503 .name = "torrent_dptx_phy", 504 .reg_stride = 1, 505 .fast_io = true, 506 .reg_write = cdns_regmap_dptx_write, 507 .reg_read = cdns_regmap_dptx_read, 508 }; 509 510 /* PHY mmr access functions */ 511 512 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) 513 { 514 regmap_write(regmap, offset, val); 515 } 516 517 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) 518 { 519 unsigned int val; 520 521 regmap_read(regmap, offset, &val); 522 return val; 523 } 524 525 /* DPTX mmr access functions */ 526 527 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) 528 { 529 regmap_write(regmap, offset, val); 530 } 531 532 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) 533 { 534 u32 val; 535 536 regmap_read(regmap, offset, &val); 537 return val; 538 } 539 540 /* 541 * Structure used to store values of PHY registers for voltage-related 542 * coefficients, for particular voltage swing and pre-emphasis level. Values 543 * are shared across all physical lanes. 544 */ 545 struct coefficients { 546 /* Value of DRV_DIAG_TX_DRV register to use */ 547 u16 diag_tx_drv; 548 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ 549 u16 mgnfs_mult; 550 /* Value of TX_TXCC_CPOST_MULT_00 register to use */ 551 u16 cpost_mult; 552 }; 553 554 /* 555 * Array consists of values of voltage-related registers for sd0801 PHY. A value 556 * of 0xFFFF is a placeholder for invalid combination, and will never be used. 557 */ 558 static const struct coefficients vltg_coeff[4][4] = { 559 /* voltage swing 0, pre-emphasis 0->3 */ 560 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, 561 .cpost_mult = 0x0000}, 562 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 563 .cpost_mult = 0x0014}, 564 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, 565 .cpost_mult = 0x0020}, 566 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 567 .cpost_mult = 0x002A} 568 }, 569 570 /* voltage swing 1, pre-emphasis 0->3 */ 571 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 572 .cpost_mult = 0x0000}, 573 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 574 .cpost_mult = 0x0012}, 575 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 576 .cpost_mult = 0x001F}, 577 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 578 .cpost_mult = 0xFFFF} 579 }, 580 581 /* voltage swing 2, pre-emphasis 0->3 */ 582 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 583 .cpost_mult = 0x0000}, 584 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 585 .cpost_mult = 0x0013}, 586 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 587 .cpost_mult = 0xFFFF}, 588 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 589 .cpost_mult = 0xFFFF} 590 }, 591 592 /* voltage swing 3, pre-emphasis 0->3 */ 593 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 594 .cpost_mult = 0x0000}, 595 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 596 .cpost_mult = 0xFFFF}, 597 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 598 .cpost_mult = 0xFFFF}, 599 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 600 .cpost_mult = 0xFFFF} 601 } 602 }; 603 604 static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type) 605 { 606 switch (phy_type) { 607 case TYPE_DP: 608 return "DisplayPort"; 609 case TYPE_PCIE: 610 return "PCIe"; 611 case TYPE_SGMII: 612 return "SGMII"; 613 case TYPE_QSGMII: 614 return "QSGMII"; 615 case TYPE_USB: 616 return "USB"; 617 default: 618 return "None"; 619 } 620 } 621 622 /* 623 * Set registers responsible for enabling and configuring SSC, with second and 624 * third register values provided by parameters. 625 */ 626 static 627 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, 628 u32 ctrl2_val, u32 ctrl3_val) 629 { 630 struct regmap *regmap = cdns_phy->regmap_common_cdb; 631 632 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 633 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 634 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); 635 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 636 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 637 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 638 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); 639 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 640 } 641 642 static 643 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, 644 u32 rate, bool ssc) 645 { 646 struct regmap *regmap = cdns_phy->regmap_common_cdb; 647 648 /* Assumes 19.2 MHz refclock */ 649 switch (rate) { 650 /* Setting VCO for 10.8GHz */ 651 case 2700: 652 case 5400: 653 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119); 654 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 655 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 656 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC); 657 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012); 658 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119); 659 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 660 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 661 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC); 662 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012); 663 if (ssc) 664 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A); 665 break; 666 /* Setting VCO for 9.72GHz */ 667 case 1620: 668 case 2430: 669 case 3240: 670 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA); 671 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 672 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 673 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152); 674 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 675 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA); 676 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 677 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 678 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152); 679 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 680 if (ssc) 681 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069); 682 break; 683 /* Setting VCO for 8.64GHz */ 684 case 2160: 685 case 4320: 686 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2); 687 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 688 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 689 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C); 690 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 691 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2); 692 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 693 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 694 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C); 695 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 696 if (ssc) 697 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069); 698 break; 699 /* Setting VCO for 8.1GHz */ 700 case 8100: 701 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5); 702 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000); 703 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 704 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A); 705 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 706 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5); 707 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000); 708 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 709 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A); 710 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 711 if (ssc) 712 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A); 713 break; 714 } 715 716 if (ssc) { 717 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); 718 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 719 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); 720 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 721 } else { 722 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); 723 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); 724 /* Set reset register values to disable SSC */ 725 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 726 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 727 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 728 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 729 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 730 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 731 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 732 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 733 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 734 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 735 } 736 737 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); 738 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); 739 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); 740 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); 741 } 742 743 /* 744 * Set registers responsible for enabling and configuring SSC, with second 745 * register value provided by a parameter. 746 */ 747 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, 748 u32 ctrl2_val) 749 { 750 struct regmap *regmap = cdns_phy->regmap_common_cdb; 751 752 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 753 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 754 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); 755 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 756 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 757 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 758 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); 759 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 760 } 761 762 static 763 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, 764 u32 rate, bool ssc) 765 { 766 struct regmap *regmap = cdns_phy->regmap_common_cdb; 767 768 /* Assumes 25 MHz refclock */ 769 switch (rate) { 770 /* Setting VCO for 10.8GHz */ 771 case 2700: 772 case 5400: 773 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); 774 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 775 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 776 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); 777 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); 778 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 779 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 780 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); 781 if (ssc) 782 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); 783 break; 784 /* Setting VCO for 9.72GHz */ 785 case 1620: 786 case 2430: 787 case 3240: 788 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); 789 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); 790 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 791 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); 792 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); 793 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); 794 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 795 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); 796 if (ssc) 797 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); 798 break; 799 /* Setting VCO for 8.64GHz */ 800 case 2160: 801 case 4320: 802 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); 803 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); 804 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 805 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); 806 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); 807 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); 808 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 809 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); 810 if (ssc) 811 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); 812 break; 813 /* Setting VCO for 8.1GHz */ 814 case 8100: 815 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); 816 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 817 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 818 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); 819 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); 820 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 821 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 822 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); 823 if (ssc) 824 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); 825 break; 826 } 827 828 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 829 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 830 831 if (ssc) { 832 cdns_torrent_phy_write(regmap, 833 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); 834 cdns_torrent_phy_write(regmap, 835 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 836 cdns_torrent_phy_write(regmap, 837 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); 838 cdns_torrent_phy_write(regmap, 839 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 840 } else { 841 cdns_torrent_phy_write(regmap, 842 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); 843 cdns_torrent_phy_write(regmap, 844 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); 845 /* Set reset register values to disable SSC */ 846 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 847 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 848 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 849 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 850 cdns_torrent_phy_write(regmap, 851 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 852 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 853 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 854 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 855 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 856 cdns_torrent_phy_write(regmap, 857 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 858 } 859 860 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); 861 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); 862 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); 863 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); 864 } 865 866 static 867 void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy, 868 u32 rate, bool ssc) 869 { 870 struct regmap *regmap = cdns_phy->regmap_common_cdb; 871 872 /* Assumes 100 MHz refclock */ 873 switch (rate) { 874 /* Setting VCO for 10.8GHz */ 875 case 2700: 876 case 5400: 877 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028); 878 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022); 879 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022); 880 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C); 881 break; 882 /* Setting VCO for 9.72GHz */ 883 case 1620: 884 case 2430: 885 case 3240: 886 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 887 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 888 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 889 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 890 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 891 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 892 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 893 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 894 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061); 895 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061); 896 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333); 897 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333); 898 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 899 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 900 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042); 901 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042); 902 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 903 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 904 break; 905 /* Setting VCO for 8.64GHz */ 906 case 2160: 907 case 4320: 908 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 909 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 910 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 911 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 912 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 913 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 914 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 915 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 916 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056); 917 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056); 918 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666); 919 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666); 920 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 921 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 922 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A); 923 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A); 924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 925 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 926 break; 927 /* Setting VCO for 8.1GHz */ 928 case 8100: 929 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 930 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 931 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 932 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 933 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 934 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 935 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 936 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 937 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051); 938 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051); 939 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 940 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 941 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036); 942 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036); 943 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 944 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 945 break; 946 } 947 } 948 949 /* 950 * Enable or disable PLL for selected lanes. 951 */ 952 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, 953 struct phy_configure_opts_dp *dp, 954 bool enable) 955 { 956 u32 rd_val; 957 u32 ret; 958 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 959 960 /* 961 * Used to determine, which bits to check for or enable in 962 * PHY_PMA_XCVR_PLLCLK_EN register. 963 */ 964 u32 pll_bits; 965 /* Used to enable or disable lanes. */ 966 u32 pll_val; 967 968 /* Select values of registers and mask, depending on enabled lane 969 * count. 970 */ 971 switch (dp->lanes) { 972 /* lane 0 */ 973 case (1): 974 pll_bits = 0x00000001; 975 break; 976 /* lanes 0-1 */ 977 case (2): 978 pll_bits = 0x00000003; 979 break; 980 /* lanes 0-3, all */ 981 default: 982 pll_bits = 0x0000000F; 983 break; 984 } 985 986 if (enable) 987 pll_val = pll_bits; 988 else 989 pll_val = 0x00000000; 990 991 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val); 992 993 /* Wait for acknowledgment from PHY. */ 994 ret = regmap_read_poll_timeout(regmap, 995 PHY_PMA_XCVR_PLLCLK_EN_ACK, 996 rd_val, 997 (rd_val & pll_bits) == pll_val, 998 0, POLL_TIMEOUT_US); 999 ndelay(100); 1000 return ret; 1001 } 1002 1003 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, 1004 u32 num_lanes, 1005 enum phy_powerstate powerstate) 1006 { 1007 /* Register value for power state for a single byte. */ 1008 u32 value_part; 1009 u32 value; 1010 u32 mask; 1011 u32 read_val; 1012 u32 ret; 1013 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1014 1015 switch (powerstate) { 1016 case (POWERSTATE_A0): 1017 value_part = 0x01U; 1018 break; 1019 case (POWERSTATE_A2): 1020 value_part = 0x04U; 1021 break; 1022 default: 1023 /* Powerstate A3 */ 1024 value_part = 0x08U; 1025 break; 1026 } 1027 1028 /* Select values of registers and mask, depending on enabled 1029 * lane count. 1030 */ 1031 switch (num_lanes) { 1032 /* lane 0 */ 1033 case (1): 1034 value = value_part; 1035 mask = 0x0000003FU; 1036 break; 1037 /* lanes 0-1 */ 1038 case (2): 1039 value = (value_part 1040 | (value_part << 8)); 1041 mask = 0x00003F3FU; 1042 break; 1043 /* lanes 0-3, all */ 1044 default: 1045 value = (value_part 1046 | (value_part << 8) 1047 | (value_part << 16) 1048 | (value_part << 24)); 1049 mask = 0x3F3F3F3FU; 1050 break; 1051 } 1052 1053 /* Set power state A<n>. */ 1054 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value); 1055 /* Wait, until PHY acknowledges power state completion. */ 1056 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK, 1057 read_val, (read_val & mask) == value, 0, 1058 POLL_TIMEOUT_US); 1059 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000); 1060 ndelay(100); 1061 1062 return ret; 1063 } 1064 1065 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) 1066 { 1067 unsigned int read_val; 1068 int ret; 1069 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1070 1071 /* 1072 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the 1073 * master lane 1074 */ 1075 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK, 1076 read_val, read_val & 1, 1077 0, POLL_TIMEOUT_US); 1078 if (ret == -ETIMEDOUT) { 1079 dev_err(cdns_phy->dev, 1080 "timeout waiting for link PLL clock enable ack\n"); 1081 return ret; 1082 } 1083 1084 ndelay(100); 1085 1086 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, 1087 POWERSTATE_A2); 1088 if (ret) 1089 return ret; 1090 1091 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, 1092 POWERSTATE_A0); 1093 1094 return ret; 1095 } 1096 1097 static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) 1098 { 1099 unsigned int reg; 1100 int ret; 1101 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1102 1103 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg, 1104 reg & 1, 0, POLL_TIMEOUT_US); 1105 if (ret == -ETIMEDOUT) { 1106 dev_err(cdns_phy->dev, 1107 "timeout waiting for PMA common ready\n"); 1108 return -ETIMEDOUT; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, 1115 u32 rate, u32 num_lanes) 1116 { 1117 unsigned int clk_sel_val = 0; 1118 unsigned int hsclk_div_val = 0; 1119 unsigned int i; 1120 1121 switch (rate) { 1122 case 1620: 1123 clk_sel_val = 0x0f01; 1124 hsclk_div_val = 2; 1125 break; 1126 case 2160: 1127 case 2430: 1128 case 2700: 1129 clk_sel_val = 0x0701; 1130 hsclk_div_val = 1; 1131 break; 1132 case 3240: 1133 clk_sel_val = 0x0b00; 1134 hsclk_div_val = 2; 1135 break; 1136 case 4320: 1137 case 5400: 1138 clk_sel_val = 0x0301; 1139 hsclk_div_val = 0; 1140 break; 1141 case 8100: 1142 clk_sel_val = 0x0200; 1143 hsclk_div_val = 0; 1144 break; 1145 } 1146 1147 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1148 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); 1149 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1150 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); 1151 1152 /* PMA lane configuration to deal with multi-link operation */ 1153 for (i = 0; i < num_lanes; i++) 1154 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i], 1155 XCVR_DIAG_HSCLK_DIV, hsclk_div_val); 1156 } 1157 1158 /* 1159 * Perform register operations related to setting link rate, once powerstate is 1160 * set and PLL disable request was processed. 1161 */ 1162 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, 1163 struct phy_configure_opts_dp *dp) 1164 { 1165 u32 read_val, ret; 1166 1167 /* Disable the cmn_pll0_en before re-programming the new data rate. */ 1168 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0); 1169 1170 /* 1171 * Wait for PLL ready de-assertion. 1172 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 1173 */ 1174 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1175 read_val, 1176 ((read_val >> 2) & 0x01) != 0, 1177 0, POLL_TIMEOUT_US); 1178 if (ret) 1179 return ret; 1180 ndelay(200); 1181 1182 /* DP Rate Change - VCO Output settings. */ 1183 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1184 /* PMA common configuration 19.2MHz */ 1185 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc); 1186 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1187 /* PMA common configuration 25MHz */ 1188 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc); 1189 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1190 /* PMA common configuration 100MHz */ 1191 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc); 1192 1193 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes); 1194 1195 /* Enable the cmn_pll0_en. */ 1196 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3); 1197 1198 /* 1199 * Wait for PLL ready assertion. 1200 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 1201 */ 1202 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1203 read_val, 1204 (read_val & 0x01) != 0, 1205 0, POLL_TIMEOUT_US); 1206 return ret; 1207 } 1208 1209 /* 1210 * Verify, that parameters to configure PHY with are correct. 1211 */ 1212 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, 1213 struct phy_configure_opts_dp *dp) 1214 { 1215 u8 i; 1216 1217 /* If changing link rate was required, verify it's supported. */ 1218 if (dp->set_rate) { 1219 switch (dp->link_rate) { 1220 case 1620: 1221 case 2160: 1222 case 2430: 1223 case 2700: 1224 case 3240: 1225 case 4320: 1226 case 5400: 1227 case 8100: 1228 /* valid bit rate */ 1229 break; 1230 default: 1231 return -EINVAL; 1232 } 1233 } 1234 1235 /* Verify lane count. */ 1236 switch (dp->lanes) { 1237 case 1: 1238 case 2: 1239 case 4: 1240 /* valid lane count. */ 1241 break; 1242 default: 1243 return -EINVAL; 1244 } 1245 1246 /* Check against actual number of PHY's lanes. */ 1247 if (dp->lanes > inst->num_lanes) 1248 return -EINVAL; 1249 1250 /* 1251 * If changing voltages is required, check swing and pre-emphasis 1252 * levels, per-lane. 1253 */ 1254 if (dp->set_voltages) { 1255 /* Lane count verified previously. */ 1256 for (i = 0; i < dp->lanes; i++) { 1257 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1258 return -EINVAL; 1259 1260 /* Sum of voltage swing and pre-emphasis levels cannot 1261 * exceed 3. 1262 */ 1263 if (dp->voltage[i] + dp->pre[i] > 3) 1264 return -EINVAL; 1265 } 1266 } 1267 1268 return 0; 1269 } 1270 1271 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ 1272 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, 1273 u32 num_lanes) 1274 { 1275 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1276 u32 pwr_state = cdns_torrent_dp_read(regmap, 1277 PHY_PMA_XCVR_POWER_STATE_REQ); 1278 u32 pll_clk_en = cdns_torrent_dp_read(regmap, 1279 PHY_PMA_XCVR_PLLCLK_EN); 1280 1281 /* Lane 0 is always enabled. */ 1282 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1283 PHY_POWER_STATE_LN_0); 1284 pll_clk_en &= ~0x01U; 1285 1286 if (num_lanes > 1) { 1287 /* lane 1 */ 1288 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1289 PHY_POWER_STATE_LN_1); 1290 pll_clk_en &= ~(0x01U << 1); 1291 } 1292 1293 if (num_lanes > 2) { 1294 /* lanes 2 and 3 */ 1295 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1296 PHY_POWER_STATE_LN_2); 1297 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK << 1298 PHY_POWER_STATE_LN_3); 1299 pll_clk_en &= ~(0x01U << 2); 1300 pll_clk_en &= ~(0x01U << 3); 1301 } 1302 1303 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); 1304 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); 1305 } 1306 1307 /* Configure lane count as required. */ 1308 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, 1309 struct phy_configure_opts_dp *dp) 1310 { 1311 u32 value; 1312 u32 ret; 1313 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1314 u8 lane_mask = (1 << dp->lanes) - 1; 1315 1316 value = cdns_torrent_dp_read(regmap, PHY_RESET); 1317 /* clear pma_tx_elec_idle_ln_* bits. */ 1318 value &= ~PMA_TX_ELEC_IDLE_MASK; 1319 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ 1320 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & 1321 PMA_TX_ELEC_IDLE_MASK; 1322 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1323 1324 /* reset the link by asserting phy_l00_reset_n low */ 1325 cdns_torrent_dp_write(regmap, PHY_RESET, 1326 value & (~PHY_L00_RESET_N_MASK)); 1327 1328 /* 1329 * Assert lane reset on unused lanes and lane 0 so they remain in reset 1330 * and powered down when re-enabling the link 1331 */ 1332 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask); 1333 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1334 1335 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes); 1336 1337 /* release phy_l0*_reset_n based on used laneCount */ 1338 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask); 1339 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1340 1341 /* Wait, until PHY gets ready after releasing PHY reset signal. */ 1342 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1343 if (ret) 1344 return ret; 1345 1346 ndelay(100); 1347 1348 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1349 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); 1350 1351 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes); 1352 1353 return ret; 1354 } 1355 1356 /* Configure link rate as required. */ 1357 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, 1358 struct phy_configure_opts_dp *dp) 1359 { 1360 u32 ret; 1361 1362 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 1363 POWERSTATE_A3); 1364 if (ret) 1365 return ret; 1366 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false); 1367 if (ret) 1368 return ret; 1369 ndelay(200); 1370 1371 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp); 1372 if (ret) 1373 return ret; 1374 ndelay(200); 1375 1376 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true); 1377 if (ret) 1378 return ret; 1379 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 1380 POWERSTATE_A2); 1381 if (ret) 1382 return ret; 1383 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes, 1384 POWERSTATE_A0); 1385 if (ret) 1386 return ret; 1387 ndelay(900); 1388 1389 return ret; 1390 } 1391 1392 /* Configure voltage swing and pre-emphasis for all enabled lanes. */ 1393 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, 1394 struct phy_configure_opts_dp *dp) 1395 { 1396 u8 lane; 1397 u16 val; 1398 1399 for (lane = 0; lane < dp->lanes; lane++) { 1400 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], 1401 TX_DIAG_ACYA); 1402 /* 1403 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the 1404 * current state of the analog TX driver. 1405 */ 1406 val |= TX_DIAG_ACYA_HBDC_MASK; 1407 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1408 TX_DIAG_ACYA, val); 1409 1410 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1411 TX_TXCC_CTRL, 0x08A4); 1412 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; 1413 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1414 DRV_DIAG_TX_DRV, val); 1415 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; 1416 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1417 TX_TXCC_MGNFS_MULT_000, 1418 val); 1419 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; 1420 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1421 TX_TXCC_CPOST_MULT_00, 1422 val); 1423 1424 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane], 1425 TX_DIAG_ACYA); 1426 /* 1427 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of 1428 * analog TX driver to reflect the new programmed one. 1429 */ 1430 val &= ~TX_DIAG_ACYA_HBDC_MASK; 1431 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane], 1432 TX_DIAG_ACYA, val); 1433 } 1434 }; 1435 1436 static int cdns_torrent_dp_configure(struct phy *phy, 1437 union phy_configure_opts *opts) 1438 { 1439 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1440 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1441 int ret; 1442 1443 ret = cdns_torrent_dp_verify_config(inst, &opts->dp); 1444 if (ret) { 1445 dev_err(&phy->dev, "invalid params for phy configure\n"); 1446 return ret; 1447 } 1448 1449 if (opts->dp.set_lanes) { 1450 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp); 1451 if (ret) { 1452 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); 1453 return ret; 1454 } 1455 } 1456 1457 if (opts->dp.set_rate) { 1458 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp); 1459 if (ret) { 1460 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); 1461 return ret; 1462 } 1463 } 1464 1465 if (opts->dp.set_voltages) 1466 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp); 1467 1468 return ret; 1469 } 1470 1471 static int cdns_torrent_phy_on(struct phy *phy) 1472 { 1473 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1474 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1475 u32 read_val; 1476 int ret; 1477 1478 if (cdns_phy->nsubnodes == 1) { 1479 /* Take the PHY lane group out of reset */ 1480 reset_control_deassert(inst->lnk_rst); 1481 1482 /* Take the PHY out of reset */ 1483 ret = reset_control_deassert(cdns_phy->phy_rst); 1484 if (ret) 1485 return ret; 1486 } 1487 1488 /* 1489 * Wait for cmn_ready assertion 1490 * PHY_PMA_CMN_CTRL1[0] == 1 1491 */ 1492 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1, 1493 read_val, read_val, 1000, 1494 PLL_LOCK_TIMEOUT); 1495 if (ret) { 1496 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n"); 1497 return ret; 1498 } 1499 1500 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) { 1501 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane], 1502 read_val, !read_val, 1000, 1503 PLL_LOCK_TIMEOUT); 1504 if (ret == -ETIMEDOUT) { 1505 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n"); 1506 return ret; 1507 } 1508 } 1509 1510 return 0; 1511 } 1512 1513 static int cdns_torrent_phy_off(struct phy *phy) 1514 { 1515 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1516 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1517 int ret; 1518 1519 if (cdns_phy->nsubnodes != 1) 1520 return 0; 1521 1522 ret = reset_control_assert(cdns_phy->phy_rst); 1523 if (ret) 1524 return ret; 1525 1526 return reset_control_assert(inst->lnk_rst); 1527 } 1528 1529 static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy, 1530 struct cdns_torrent_inst *inst) 1531 { 1532 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1533 unsigned char lane_bits; 1534 1535 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */ 1536 1537 /* 1538 * Set lines power state to A0 1539 * Set lines pll clk enable to 0 1540 */ 1541 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes); 1542 1543 /* 1544 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on 1545 * used lanes 1546 */ 1547 lane_bits = (1 << inst->num_lanes) - 1; 1548 cdns_torrent_dp_write(regmap, PHY_RESET, 1549 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits)); 1550 1551 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1552 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001); 1553 1554 /* 1555 * PHY PMA registers configuration functions 1556 * Initialize PHY with max supported link rate, without SSC. 1557 */ 1558 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1559 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, 1560 cdns_phy->max_bit_rate, 1561 false); 1562 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1563 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, 1564 cdns_phy->max_bit_rate, 1565 false); 1566 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1567 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, 1568 cdns_phy->max_bit_rate, 1569 false); 1570 1571 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate, 1572 inst->num_lanes); 1573 1574 /* take out of reset */ 1575 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1); 1576 } 1577 1578 static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy, 1579 struct cdns_torrent_inst *inst, 1580 struct phy *phy) 1581 { 1582 int ret; 1583 1584 cdns_torrent_phy_on(phy); 1585 1586 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1587 if (ret) 1588 return ret; 1589 1590 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes); 1591 1592 return ret; 1593 } 1594 1595 static int cdns_torrent_dp_init(struct phy *phy) 1596 { 1597 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1598 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1599 1600 switch (cdns_phy->ref_clk_rate) { 1601 case CLK_19_2_MHZ: 1602 case CLK_25_MHZ: 1603 case CLK_100_MHZ: 1604 /* Valid Ref Clock Rate */ 1605 break; 1606 default: 1607 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 1608 return -EINVAL; 1609 } 1610 1611 cdns_torrent_dp_common_init(cdns_phy, inst); 1612 1613 return cdns_torrent_dp_start(cdns_phy, inst, phy); 1614 } 1615 1616 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) 1617 { 1618 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1619 1620 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); 1621 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); 1622 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); 1623 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); 1624 regmap_field_write(derived_refclk->cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1); 1625 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1); 1626 1627 return 0; 1628 } 1629 1630 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) 1631 { 1632 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1633 1634 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0); 1635 } 1636 1637 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) 1638 { 1639 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1640 int val; 1641 1642 regmap_field_read(derived_refclk->phy_pipe_cmn_ctrl1_0, &val); 1643 1644 return !!val; 1645 } 1646 1647 static const struct clk_ops cdns_torrent_derived_refclk_ops = { 1648 .enable = cdns_torrent_derived_refclk_enable, 1649 .disable = cdns_torrent_derived_refclk_disable, 1650 .is_enabled = cdns_torrent_derived_refclk_is_enabled, 1651 }; 1652 1653 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) 1654 { 1655 struct cdns_torrent_derived_refclk *derived_refclk; 1656 struct device *dev = cdns_phy->dev; 1657 struct regmap_field *field; 1658 struct clk_init_data *init; 1659 const char *parent_name; 1660 struct regmap *regmap; 1661 char clk_name[100]; 1662 struct clk *clk; 1663 int i; 1664 1665 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 1666 if (!derived_refclk) 1667 return -ENOMEM; 1668 1669 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1670 clk_names[CDNS_TORRENT_REFCLK_DRIVER]); 1671 1672 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1673 if (IS_ERR(clk)) { 1674 dev_err(dev, "No parent clock for derived_refclk\n"); 1675 return PTR_ERR(clk); 1676 } 1677 1678 init = &derived_refclk->clk_data; 1679 1680 if (clk) { 1681 parent_name = __clk_get_name(clk); 1682 init->parent_names = &parent_name; 1683 init->num_parents = 1; 1684 } 1685 init->ops = &cdns_torrent_derived_refclk_ops; 1686 init->flags = 0; 1687 init->name = clk_name; 1688 1689 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 1690 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0); 1691 if (IS_ERR(field)) { 1692 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n"); 1693 return PTR_ERR(field); 1694 } 1695 derived_refclk->phy_pipe_cmn_ctrl1_0 = field; 1696 1697 regmap = cdns_phy->regmap_common_cdb; 1698 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) { 1699 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); 1700 if (IS_ERR(field)) { 1701 dev_err(dev, "CMN reg field init failed\n"); 1702 return PTR_ERR(field); 1703 } 1704 derived_refclk->cmn_fields[i] = field; 1705 } 1706 1707 derived_refclk->hw.init = init; 1708 1709 clk = devm_clk_register(dev, &derived_refclk->hw); 1710 if (IS_ERR(clk)) 1711 return PTR_ERR(clk); 1712 1713 cdns_phy->clks[CDNS_TORRENT_REFCLK_DRIVER] = clk; 1714 1715 return 0; 1716 } 1717 1718 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 1719 u32 block_offset, 1720 u8 reg_offset_shift, 1721 const struct regmap_config *config) 1722 { 1723 struct cdns_regmap_cdb_context *ctx; 1724 1725 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1726 if (!ctx) 1727 return ERR_PTR(-ENOMEM); 1728 1729 ctx->dev = dev; 1730 ctx->base = base + block_offset; 1731 ctx->reg_offset_shift = reg_offset_shift; 1732 1733 return devm_regmap_init(dev, NULL, ctx, config); 1734 } 1735 1736 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) 1737 { 1738 struct device *dev = cdns_phy->dev; 1739 struct regmap_field *field; 1740 struct regmap *regmap; 1741 1742 regmap = cdns_phy->regmap_dptx_phy_reg; 1743 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); 1744 if (IS_ERR(field)) { 1745 dev_err(dev, "PHY_RESET reg field init failed\n"); 1746 return PTR_ERR(field); 1747 } 1748 cdns_phy->phy_reset_ctrl = field; 1749 1750 return 0; 1751 } 1752 1753 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) 1754 { 1755 struct device *dev = cdns_phy->dev; 1756 struct regmap_field *field; 1757 struct regmap *regmap; 1758 int i; 1759 1760 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 1761 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); 1762 if (IS_ERR(field)) { 1763 dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); 1764 return PTR_ERR(field); 1765 } 1766 cdns_phy->phy_pll_cfg = field; 1767 1768 regmap = cdns_phy->regmap_phy_pma_common_cdb; 1769 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1); 1770 if (IS_ERR(field)) { 1771 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n"); 1772 return PTR_ERR(field); 1773 } 1774 cdns_phy->phy_pma_cmn_ctrl_1 = field; 1775 1776 regmap = cdns_phy->regmap_phy_pma_common_cdb; 1777 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); 1778 if (IS_ERR(field)) { 1779 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); 1780 return PTR_ERR(field); 1781 } 1782 cdns_phy->phy_pma_cmn_ctrl_2 = field; 1783 1784 regmap = cdns_phy->regmap_phy_pma_common_cdb; 1785 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); 1786 if (IS_ERR(field)) { 1787 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); 1788 return PTR_ERR(field); 1789 } 1790 cdns_phy->phy_pma_pll_raw_ctrl = field; 1791 1792 for (i = 0; i < MAX_NUM_LANES; i++) { 1793 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i]; 1794 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1); 1795 if (IS_ERR(field)) { 1796 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i); 1797 return PTR_ERR(field); 1798 } 1799 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field; 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) 1806 { 1807 void __iomem *base = cdns_phy->base; 1808 struct device *dev = cdns_phy->dev; 1809 struct regmap *regmap; 1810 u8 reg_offset_shift; 1811 u32 block_offset; 1812 1813 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 1814 1815 block_offset = TORRENT_DPTX_PHY_OFFSET; 1816 regmap = cdns_regmap_init(dev, base, block_offset, 1817 reg_offset_shift, 1818 &cdns_torrent_dptx_phy_config); 1819 if (IS_ERR(regmap)) { 1820 dev_err(dev, "Failed to init DPTX PHY regmap\n"); 1821 return PTR_ERR(regmap); 1822 } 1823 cdns_phy->regmap_dptx_phy_reg = regmap; 1824 1825 return 0; 1826 } 1827 1828 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) 1829 { 1830 void __iomem *sd_base = cdns_phy->sd_base; 1831 u8 block_offset_shift, reg_offset_shift; 1832 struct device *dev = cdns_phy->dev; 1833 struct regmap *regmap; 1834 u32 block_offset; 1835 int i; 1836 1837 block_offset_shift = cdns_phy->init_data->block_offset_shift; 1838 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 1839 1840 for (i = 0; i < MAX_NUM_LANES; i++) { 1841 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, 1842 reg_offset_shift); 1843 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1844 reg_offset_shift, 1845 &cdns_torrent_tx_lane_cdb_config[i]); 1846 if (IS_ERR(regmap)) { 1847 dev_err(dev, "Failed to init tx lane CDB regmap\n"); 1848 return PTR_ERR(regmap); 1849 } 1850 cdns_phy->regmap_tx_lane_cdb[i] = regmap; 1851 1852 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, 1853 reg_offset_shift); 1854 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1855 reg_offset_shift, 1856 &cdns_torrent_rx_lane_cdb_config[i]); 1857 if (IS_ERR(regmap)) { 1858 dev_err(dev, "Failed to init rx lane CDB regmap\n"); 1859 return PTR_ERR(regmap); 1860 } 1861 cdns_phy->regmap_rx_lane_cdb[i] = regmap; 1862 1863 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 1864 reg_offset_shift); 1865 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1866 reg_offset_shift, 1867 &cdns_torrent_phy_pcs_lane_cdb_config[i]); 1868 if (IS_ERR(regmap)) { 1869 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 1870 return PTR_ERR(regmap); 1871 } 1872 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap; 1873 } 1874 1875 block_offset = TORRENT_COMMON_CDB_OFFSET; 1876 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1877 reg_offset_shift, 1878 &cdns_torrent_common_cdb_config); 1879 if (IS_ERR(regmap)) { 1880 dev_err(dev, "Failed to init common CDB regmap\n"); 1881 return PTR_ERR(regmap); 1882 } 1883 cdns_phy->regmap_common_cdb = regmap; 1884 1885 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); 1886 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1887 reg_offset_shift, 1888 &cdns_torrent_phy_pcs_cmn_cdb_config); 1889 if (IS_ERR(regmap)) { 1890 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 1891 return PTR_ERR(regmap); 1892 } 1893 cdns_phy->regmap_phy_pcs_common_cdb = regmap; 1894 1895 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); 1896 regmap = cdns_regmap_init(dev, sd_base, block_offset, 1897 reg_offset_shift, 1898 &cdns_torrent_phy_pma_cmn_cdb_config); 1899 if (IS_ERR(regmap)) { 1900 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 1901 return PTR_ERR(regmap); 1902 } 1903 cdns_phy->regmap_phy_pma_common_cdb = regmap; 1904 1905 return 0; 1906 } 1907 1908 static int cdns_torrent_phy_init(struct phy *phy) 1909 { 1910 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1911 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 1912 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 1913 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 1914 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 1915 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1916 enum cdns_torrent_phy_type phy_type = inst->phy_type; 1917 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; 1918 struct cdns_torrent_vals *pcs_cmn_vals; 1919 struct cdns_reg_pairs *reg_pairs; 1920 struct regmap *regmap; 1921 u32 num_regs; 1922 int i, j; 1923 1924 if (cdns_phy->nsubnodes > 1) 1925 return 0; 1926 1927 /** 1928 * Spread spectrum generation is not required or supported 1929 * for SGMII/QSGMII 1930 */ 1931 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII) 1932 ssc = NO_SSC; 1933 1934 /* PHY configuration specific registers for single link */ 1935 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc]; 1936 if (link_cmn_vals) { 1937 reg_pairs = link_cmn_vals->reg_pairs; 1938 num_regs = link_cmn_vals->num_regs; 1939 regmap = cdns_phy->regmap_common_cdb; 1940 1941 /** 1942 * First array value in link_cmn_vals must be of 1943 * PHY_PLL_CFG register 1944 */ 1945 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val); 1946 1947 for (i = 1; i < num_regs; i++) 1948 regmap_write(regmap, reg_pairs[i].off, 1949 reg_pairs[i].val); 1950 } 1951 1952 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc]; 1953 if (xcvr_diag_vals) { 1954 reg_pairs = xcvr_diag_vals->reg_pairs; 1955 num_regs = xcvr_diag_vals->num_regs; 1956 for (i = 0; i < inst->num_lanes; i++) { 1957 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 1958 for (j = 0; j < num_regs; j++) 1959 regmap_write(regmap, reg_pairs[j].off, 1960 reg_pairs[j].val); 1961 } 1962 } 1963 1964 /* PHY PCS common registers configurations */ 1965 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; 1966 if (pcs_cmn_vals) { 1967 reg_pairs = pcs_cmn_vals->reg_pairs; 1968 num_regs = pcs_cmn_vals->num_regs; 1969 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 1970 for (i = 0; i < num_regs; i++) 1971 regmap_write(regmap, reg_pairs[i].off, 1972 reg_pairs[i].val); 1973 } 1974 1975 /* PMA common registers configurations */ 1976 cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc]; 1977 if (cmn_vals) { 1978 reg_pairs = cmn_vals->reg_pairs; 1979 num_regs = cmn_vals->num_regs; 1980 regmap = cdns_phy->regmap_common_cdb; 1981 for (i = 0; i < num_regs; i++) 1982 regmap_write(regmap, reg_pairs[i].off, 1983 reg_pairs[i].val); 1984 } 1985 1986 /* PMA TX lane registers configurations */ 1987 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc]; 1988 if (tx_ln_vals) { 1989 reg_pairs = tx_ln_vals->reg_pairs; 1990 num_regs = tx_ln_vals->num_regs; 1991 for (i = 0; i < inst->num_lanes; i++) { 1992 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 1993 for (j = 0; j < num_regs; j++) 1994 regmap_write(regmap, reg_pairs[j].off, 1995 reg_pairs[j].val); 1996 } 1997 } 1998 1999 /* PMA RX lane registers configurations */ 2000 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc]; 2001 if (rx_ln_vals) { 2002 reg_pairs = rx_ln_vals->reg_pairs; 2003 num_regs = rx_ln_vals->num_regs; 2004 for (i = 0; i < inst->num_lanes; i++) { 2005 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane]; 2006 for (j = 0; j < num_regs; j++) 2007 regmap_write(regmap, reg_pairs[j].off, 2008 reg_pairs[j].val); 2009 } 2010 } 2011 2012 if (phy_type == TYPE_DP) 2013 return cdns_torrent_dp_init(phy); 2014 2015 return 0; 2016 } 2017 2018 static const struct phy_ops cdns_torrent_phy_ops = { 2019 .init = cdns_torrent_phy_init, 2020 .configure = cdns_torrent_dp_configure, 2021 .power_on = cdns_torrent_phy_on, 2022 .power_off = cdns_torrent_phy_off, 2023 .owner = THIS_MODULE, 2024 }; 2025 2026 static int cdns_torrent_noop_phy_on(struct phy *phy) 2027 { 2028 /* Give 5ms to 10ms delay for the PIPE clock to be stable */ 2029 usleep_range(5000, 10000); 2030 2031 return 0; 2032 } 2033 2034 static const struct phy_ops noop_ops = { 2035 .power_on = cdns_torrent_noop_phy_on, 2036 .owner = THIS_MODULE, 2037 }; 2038 2039 static 2040 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) 2041 { 2042 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2043 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2044 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2045 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2046 enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type; 2047 struct cdns_torrent_vals *pcs_cmn_vals; 2048 int i, j, node, mlane, num_lanes, ret; 2049 struct cdns_reg_pairs *reg_pairs; 2050 enum cdns_torrent_ssc_mode ssc; 2051 struct regmap *regmap; 2052 u32 num_regs; 2053 2054 /* Maximum 2 links (subnodes) are supported */ 2055 if (cdns_phy->nsubnodes != 2) 2056 return -EINVAL; 2057 2058 phy_t1 = cdns_phy->phys[0].phy_type; 2059 phy_t2 = cdns_phy->phys[1].phy_type; 2060 2061 /** 2062 * First configure the PHY for first link with phy_t1. Get the array 2063 * values as [phy_t1][phy_t2][ssc]. 2064 */ 2065 for (node = 0; node < cdns_phy->nsubnodes; node++) { 2066 if (node == 1) { 2067 /** 2068 * If first link with phy_t1 is configured, then 2069 * configure the PHY for second link with phy_t2. 2070 * Get the array values as [phy_t2][phy_t1][ssc]. 2071 */ 2072 tmp_phy_type = phy_t1; 2073 phy_t1 = phy_t2; 2074 phy_t2 = tmp_phy_type; 2075 } 2076 2077 mlane = cdns_phy->phys[node].mlane; 2078 ssc = cdns_phy->phys[node].ssc_mode; 2079 num_lanes = cdns_phy->phys[node].num_lanes; 2080 2081 /** 2082 * PHY configuration specific registers: 2083 * link_cmn_vals depend on combination of PHY types being 2084 * configured and are common for both PHY types, so array 2085 * values should be same for [phy_t1][phy_t2][ssc] and 2086 * [phy_t2][phy_t1][ssc]. 2087 * xcvr_diag_vals also depend on combination of PHY types 2088 * being configured, but these can be different for particular 2089 * PHY type and are per lane. 2090 */ 2091 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc]; 2092 if (link_cmn_vals) { 2093 reg_pairs = link_cmn_vals->reg_pairs; 2094 num_regs = link_cmn_vals->num_regs; 2095 regmap = cdns_phy->regmap_common_cdb; 2096 2097 /** 2098 * First array value in link_cmn_vals must be of 2099 * PHY_PLL_CFG register 2100 */ 2101 regmap_field_write(cdns_phy->phy_pll_cfg, 2102 reg_pairs[0].val); 2103 2104 for (i = 1; i < num_regs; i++) 2105 regmap_write(regmap, reg_pairs[i].off, 2106 reg_pairs[i].val); 2107 } 2108 2109 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc]; 2110 if (xcvr_diag_vals) { 2111 reg_pairs = xcvr_diag_vals->reg_pairs; 2112 num_regs = xcvr_diag_vals->num_regs; 2113 for (i = 0; i < num_lanes; i++) { 2114 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2115 for (j = 0; j < num_regs; j++) 2116 regmap_write(regmap, reg_pairs[j].off, 2117 reg_pairs[j].val); 2118 } 2119 } 2120 2121 /* PHY PCS common registers configurations */ 2122 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; 2123 if (pcs_cmn_vals) { 2124 reg_pairs = pcs_cmn_vals->reg_pairs; 2125 num_regs = pcs_cmn_vals->num_regs; 2126 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2127 for (i = 0; i < num_regs; i++) 2128 regmap_write(regmap, reg_pairs[i].off, 2129 reg_pairs[i].val); 2130 } 2131 2132 /* PMA common registers configurations */ 2133 cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc]; 2134 if (cmn_vals) { 2135 reg_pairs = cmn_vals->reg_pairs; 2136 num_regs = cmn_vals->num_regs; 2137 regmap = cdns_phy->regmap_common_cdb; 2138 for (i = 0; i < num_regs; i++) 2139 regmap_write(regmap, reg_pairs[i].off, 2140 reg_pairs[i].val); 2141 } 2142 2143 /* PMA TX lane registers configurations */ 2144 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc]; 2145 if (tx_ln_vals) { 2146 reg_pairs = tx_ln_vals->reg_pairs; 2147 num_regs = tx_ln_vals->num_regs; 2148 for (i = 0; i < num_lanes; i++) { 2149 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2150 for (j = 0; j < num_regs; j++) 2151 regmap_write(regmap, reg_pairs[j].off, 2152 reg_pairs[j].val); 2153 } 2154 } 2155 2156 /* PMA RX lane registers configurations */ 2157 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc]; 2158 if (rx_ln_vals) { 2159 reg_pairs = rx_ln_vals->reg_pairs; 2160 num_regs = rx_ln_vals->num_regs; 2161 for (i = 0; i < num_lanes; i++) { 2162 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane]; 2163 for (j = 0; j < num_regs; j++) 2164 regmap_write(regmap, reg_pairs[j].off, 2165 reg_pairs[j].val); 2166 } 2167 } 2168 2169 reset_control_deassert(cdns_phy->phys[node].lnk_rst); 2170 } 2171 2172 /* Take the PHY out of reset */ 2173 ret = reset_control_deassert(cdns_phy->phy_rst); 2174 if (ret) 2175 return ret; 2176 2177 return 0; 2178 } 2179 2180 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) 2181 { 2182 struct device *dev = cdns_phy->dev; 2183 2184 of_clk_del_provider(dev->of_node); 2185 } 2186 2187 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) 2188 { 2189 struct device *dev = cdns_phy->dev; 2190 struct device_node *node = dev->of_node; 2191 int ret; 2192 2193 ret = cdns_torrent_derived_refclk_register(cdns_phy); 2194 if (ret) { 2195 dev_err(dev, "failed to register derived refclk\n"); 2196 return ret; 2197 } 2198 2199 cdns_phy->clk_data.clks = cdns_phy->clks; 2200 cdns_phy->clk_data.clk_num = CDNS_TORRENT_REFCLK_DRIVER + 1; 2201 2202 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &cdns_phy->clk_data); 2203 if (ret) { 2204 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 2205 return ret; 2206 } 2207 2208 return 0; 2209 } 2210 2211 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy) 2212 { 2213 struct device *dev = cdns_phy->dev; 2214 2215 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); 2216 if (IS_ERR(cdns_phy->phy_rst)) { 2217 dev_err(dev, "%s: failed to get reset\n", 2218 dev->of_node->full_name); 2219 return PTR_ERR(cdns_phy->phy_rst); 2220 } 2221 2222 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb"); 2223 if (IS_ERR(cdns_phy->apb_rst)) { 2224 dev_err(dev, "%s: failed to get apb reset\n", 2225 dev->of_node->full_name); 2226 return PTR_ERR(cdns_phy->apb_rst); 2227 } 2228 2229 return 0; 2230 } 2231 2232 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) 2233 { 2234 struct device *dev = cdns_phy->dev; 2235 unsigned long ref_clk_rate; 2236 int ret; 2237 2238 cdns_phy->clk = devm_clk_get(dev, "refclk"); 2239 if (IS_ERR(cdns_phy->clk)) { 2240 dev_err(dev, "phy ref clock not found\n"); 2241 return PTR_ERR(cdns_phy->clk); 2242 } 2243 2244 ret = clk_prepare_enable(cdns_phy->clk); 2245 if (ret) { 2246 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); 2247 return ret; 2248 } 2249 2250 ref_clk_rate = clk_get_rate(cdns_phy->clk); 2251 if (!ref_clk_rate) { 2252 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); 2253 clk_disable_unprepare(cdns_phy->clk); 2254 return -EINVAL; 2255 } 2256 2257 switch (ref_clk_rate) { 2258 case REF_CLK_19_2MHZ: 2259 cdns_phy->ref_clk_rate = CLK_19_2_MHZ; 2260 break; 2261 case REF_CLK_25MHZ: 2262 cdns_phy->ref_clk_rate = CLK_25_MHZ; 2263 break; 2264 case REF_CLK_100MHZ: 2265 cdns_phy->ref_clk_rate = CLK_100_MHZ; 2266 break; 2267 default: 2268 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n"); 2269 clk_disable_unprepare(cdns_phy->clk); 2270 return -EINVAL; 2271 } 2272 2273 return 0; 2274 } 2275 2276 static int cdns_torrent_phy_probe(struct platform_device *pdev) 2277 { 2278 struct cdns_torrent_phy *cdns_phy; 2279 struct device *dev = &pdev->dev; 2280 struct phy_provider *phy_provider; 2281 const struct cdns_torrent_data *data; 2282 struct device_node *child; 2283 int ret, subnodes, node = 0, i; 2284 u32 total_num_lanes = 0; 2285 int already_configured; 2286 u8 init_dp_regmap = 0; 2287 u32 phy_type; 2288 2289 /* Get init data for this PHY */ 2290 data = of_device_get_match_data(dev); 2291 if (!data) 2292 return -EINVAL; 2293 2294 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); 2295 if (!cdns_phy) 2296 return -ENOMEM; 2297 2298 dev_set_drvdata(dev, cdns_phy); 2299 cdns_phy->dev = dev; 2300 cdns_phy->init_data = data; 2301 2302 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0); 2303 if (IS_ERR(cdns_phy->sd_base)) 2304 return PTR_ERR(cdns_phy->sd_base); 2305 2306 subnodes = of_get_available_child_count(dev->of_node); 2307 if (subnodes == 0) { 2308 dev_err(dev, "No available link subnodes found\n"); 2309 return -EINVAL; 2310 } 2311 2312 ret = cdns_torrent_regmap_init(cdns_phy); 2313 if (ret) 2314 return ret; 2315 2316 ret = cdns_torrent_regfield_init(cdns_phy); 2317 if (ret) 2318 return ret; 2319 2320 ret = cdns_torrent_clk_register(cdns_phy); 2321 if (ret) 2322 return ret; 2323 2324 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured); 2325 2326 if (!already_configured) { 2327 ret = cdns_torrent_reset(cdns_phy); 2328 if (ret) 2329 goto clk_cleanup; 2330 2331 ret = cdns_torrent_clk(cdns_phy); 2332 if (ret) 2333 goto clk_cleanup; 2334 2335 /* Enable APB */ 2336 reset_control_deassert(cdns_phy->apb_rst); 2337 } 2338 2339 for_each_available_child_of_node(dev->of_node, child) { 2340 struct phy *gphy; 2341 2342 /* PHY subnode name must be 'phy'. */ 2343 if (!(of_node_name_eq(child, "phy"))) 2344 continue; 2345 2346 cdns_phy->phys[node].lnk_rst = 2347 of_reset_control_array_get_exclusive(child); 2348 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { 2349 dev_err(dev, "%s: failed to get reset\n", 2350 child->full_name); 2351 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst); 2352 goto put_lnk_rst; 2353 } 2354 2355 if (of_property_read_u32(child, "reg", 2356 &cdns_phy->phys[node].mlane)) { 2357 dev_err(dev, "%s: No \"reg\"-property.\n", 2358 child->full_name); 2359 ret = -EINVAL; 2360 goto put_child; 2361 } 2362 2363 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) { 2364 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", 2365 child->full_name); 2366 ret = -EINVAL; 2367 goto put_child; 2368 } 2369 2370 switch (phy_type) { 2371 case PHY_TYPE_PCIE: 2372 cdns_phy->phys[node].phy_type = TYPE_PCIE; 2373 break; 2374 case PHY_TYPE_DP: 2375 cdns_phy->phys[node].phy_type = TYPE_DP; 2376 break; 2377 case PHY_TYPE_SGMII: 2378 cdns_phy->phys[node].phy_type = TYPE_SGMII; 2379 break; 2380 case PHY_TYPE_QSGMII: 2381 cdns_phy->phys[node].phy_type = TYPE_QSGMII; 2382 break; 2383 case PHY_TYPE_USB3: 2384 cdns_phy->phys[node].phy_type = TYPE_USB; 2385 break; 2386 default: 2387 dev_err(dev, "Unsupported protocol\n"); 2388 ret = -EINVAL; 2389 goto put_child; 2390 } 2391 2392 if (of_property_read_u32(child, "cdns,num-lanes", 2393 &cdns_phy->phys[node].num_lanes)) { 2394 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n", 2395 child->full_name); 2396 ret = -EINVAL; 2397 goto put_child; 2398 } 2399 2400 total_num_lanes += cdns_phy->phys[node].num_lanes; 2401 2402 /* Get SSC mode */ 2403 cdns_phy->phys[node].ssc_mode = NO_SSC; 2404 of_property_read_u32(child, "cdns,ssc-mode", 2405 &cdns_phy->phys[node].ssc_mode); 2406 2407 if (!already_configured) 2408 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); 2409 else 2410 gphy = devm_phy_create(dev, child, &noop_ops); 2411 if (IS_ERR(gphy)) { 2412 ret = PTR_ERR(gphy); 2413 goto put_child; 2414 } 2415 2416 if (cdns_phy->phys[node].phy_type == TYPE_DP) { 2417 switch (cdns_phy->phys[node].num_lanes) { 2418 case 1: 2419 case 2: 2420 case 4: 2421 /* valid number of lanes */ 2422 break; 2423 default: 2424 dev_err(dev, "unsupported number of lanes: %d\n", 2425 cdns_phy->phys[node].num_lanes); 2426 ret = -EINVAL; 2427 goto put_child; 2428 } 2429 2430 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; 2431 of_property_read_u32(child, "cdns,max-bit-rate", 2432 &cdns_phy->max_bit_rate); 2433 2434 switch (cdns_phy->max_bit_rate) { 2435 case 1620: 2436 case 2160: 2437 case 2430: 2438 case 2700: 2439 case 3240: 2440 case 4320: 2441 case 5400: 2442 case 8100: 2443 /* valid bit rate */ 2444 break; 2445 default: 2446 dev_err(dev, "unsupported max bit rate: %dMbps\n", 2447 cdns_phy->max_bit_rate); 2448 ret = -EINVAL; 2449 goto put_child; 2450 } 2451 2452 /* DPTX registers */ 2453 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1); 2454 if (IS_ERR(cdns_phy->base)) { 2455 ret = PTR_ERR(cdns_phy->base); 2456 goto put_child; 2457 } 2458 2459 if (!init_dp_regmap) { 2460 ret = cdns_torrent_dp_regmap_init(cdns_phy); 2461 if (ret) 2462 goto put_child; 2463 2464 ret = cdns_torrent_dp_regfield_init(cdns_phy); 2465 if (ret) 2466 goto put_child; 2467 2468 init_dp_regmap++; 2469 } 2470 2471 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n", 2472 cdns_phy->max_bit_rate / 1000, 2473 cdns_phy->max_bit_rate % 1000); 2474 2475 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes; 2476 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate; 2477 gphy->attrs.mode = PHY_MODE_DP; 2478 } 2479 2480 cdns_phy->phys[node].phy = gphy; 2481 phy_set_drvdata(gphy, &cdns_phy->phys[node]); 2482 2483 node++; 2484 } 2485 cdns_phy->nsubnodes = node; 2486 2487 if (total_num_lanes > MAX_NUM_LANES) { 2488 dev_err(dev, "Invalid lane configuration\n"); 2489 ret = -EINVAL; 2490 goto put_lnk_rst; 2491 } 2492 2493 if (cdns_phy->nsubnodes > 1 && !already_configured) { 2494 ret = cdns_torrent_phy_configure_multilink(cdns_phy); 2495 if (ret) 2496 goto put_lnk_rst; 2497 } 2498 2499 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2500 if (IS_ERR(phy_provider)) { 2501 ret = PTR_ERR(phy_provider); 2502 goto put_lnk_rst; 2503 } 2504 2505 if (cdns_phy->nsubnodes > 1) 2506 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)", 2507 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), 2508 cdns_phy->phys[0].num_lanes, 2509 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type), 2510 cdns_phy->phys[1].num_lanes); 2511 else 2512 dev_dbg(dev, "Single link: %s (%d lanes)", 2513 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type), 2514 cdns_phy->phys[0].num_lanes); 2515 2516 return 0; 2517 2518 put_child: 2519 node++; 2520 put_lnk_rst: 2521 for (i = 0; i < node; i++) 2522 reset_control_put(cdns_phy->phys[i].lnk_rst); 2523 of_node_put(child); 2524 reset_control_assert(cdns_phy->apb_rst); 2525 clk_disable_unprepare(cdns_phy->clk); 2526 clk_cleanup: 2527 cdns_torrent_clk_cleanup(cdns_phy); 2528 return ret; 2529 } 2530 2531 static int cdns_torrent_phy_remove(struct platform_device *pdev) 2532 { 2533 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev); 2534 int i; 2535 2536 reset_control_assert(cdns_phy->phy_rst); 2537 reset_control_assert(cdns_phy->apb_rst); 2538 for (i = 0; i < cdns_phy->nsubnodes; i++) { 2539 reset_control_assert(cdns_phy->phys[i].lnk_rst); 2540 reset_control_put(cdns_phy->phys[i].lnk_rst); 2541 } 2542 2543 clk_disable_unprepare(cdns_phy->clk); 2544 cdns_torrent_clk_cleanup(cdns_phy); 2545 2546 return 0; 2547 } 2548 2549 /* Single DisplayPort(DP) link configuration */ 2550 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { 2551 {0x0000, PHY_PLL_CFG}, 2552 }; 2553 2554 static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { 2555 {0x0000, XCVR_DIAG_HSCLK_SEL}, 2556 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 2557 }; 2558 2559 static struct cdns_torrent_vals sl_dp_link_cmn_vals = { 2560 .reg_pairs = sl_dp_link_cmn_regs, 2561 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs), 2562 }; 2563 2564 static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = { 2565 .reg_pairs = sl_dp_xcvr_diag_ln_regs, 2566 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs), 2567 }; 2568 2569 /* Single DP, 19.2 MHz Ref clk, no SSC */ 2570 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { 2571 {0x0014, CMN_SSM_BIAS_TMR}, 2572 {0x0027, CMN_PLLSM0_PLLPRE_TMR}, 2573 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR}, 2574 {0x0027, CMN_PLLSM1_PLLPRE_TMR}, 2575 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR}, 2576 {0x0060, CMN_BGCAL_INIT_TMR}, 2577 {0x0060, CMN_BGCAL_ITER_TMR}, 2578 {0x0014, CMN_IBCAL_INIT_TMR}, 2579 {0x0018, CMN_TXPUCAL_INIT_TMR}, 2580 {0x0005, CMN_TXPUCAL_ITER_TMR}, 2581 {0x0018, CMN_TXPDCAL_INIT_TMR}, 2582 {0x0005, CMN_TXPDCAL_ITER_TMR}, 2583 {0x0240, CMN_RXCAL_INIT_TMR}, 2584 {0x0005, CMN_RXCAL_ITER_TMR}, 2585 {0x0002, CMN_SD_CAL_INIT_TMR}, 2586 {0x0002, CMN_SD_CAL_ITER_TMR}, 2587 {0x000B, CMN_SD_CAL_REFTIM_START}, 2588 {0x0137, CMN_SD_CAL_PLLCNT_START}, 2589 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 2590 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 2591 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 2592 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 2593 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2594 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 2595 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 2596 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 2597 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR}, 2598 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 2599 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR}, 2600 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 2601 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START}, 2602 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2603 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START}, 2604 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 2605 }; 2606 2607 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { 2608 {0x0780, TX_RCVDET_ST_TMR}, 2609 {0x00FB, TX_PSC_A0}, 2610 {0x04AA, TX_PSC_A2}, 2611 {0x04AA, TX_PSC_A3}, 2612 {0x000F, XCVR_DIAG_BIDI_CTRL} 2613 }; 2614 2615 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { 2616 {0x0000, RX_PSC_A0}, 2617 {0x0000, RX_PSC_A2}, 2618 {0x0000, RX_PSC_A3}, 2619 {0x0000, RX_PSC_CAL}, 2620 {0x0000, RX_REE_GCSM1_CTRL}, 2621 {0x0000, RX_REE_GCSM2_CTRL}, 2622 {0x0000, RX_REE_PERGCSM_CTRL} 2623 }; 2624 2625 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = { 2626 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs, 2627 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs), 2628 }; 2629 2630 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = { 2631 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs, 2632 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs), 2633 }; 2634 2635 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = { 2636 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs, 2637 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs), 2638 }; 2639 2640 /* Single DP, 25 MHz Ref clk, no SSC */ 2641 static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { 2642 {0x0019, CMN_SSM_BIAS_TMR}, 2643 {0x0032, CMN_PLLSM0_PLLPRE_TMR}, 2644 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR}, 2645 {0x0032, CMN_PLLSM1_PLLPRE_TMR}, 2646 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR}, 2647 {0x007D, CMN_BGCAL_INIT_TMR}, 2648 {0x007D, CMN_BGCAL_ITER_TMR}, 2649 {0x0019, CMN_IBCAL_INIT_TMR}, 2650 {0x001E, CMN_TXPUCAL_INIT_TMR}, 2651 {0x0006, CMN_TXPUCAL_ITER_TMR}, 2652 {0x001E, CMN_TXPDCAL_INIT_TMR}, 2653 {0x0006, CMN_TXPDCAL_ITER_TMR}, 2654 {0x02EE, CMN_RXCAL_INIT_TMR}, 2655 {0x0006, CMN_RXCAL_ITER_TMR}, 2656 {0x0002, CMN_SD_CAL_INIT_TMR}, 2657 {0x0002, CMN_SD_CAL_ITER_TMR}, 2658 {0x000E, CMN_SD_CAL_REFTIM_START}, 2659 {0x012B, CMN_SD_CAL_PLLCNT_START}, 2660 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 2661 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 2662 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 2663 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 2664 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2665 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 2666 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 2667 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 2668 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR}, 2669 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 2670 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR}, 2671 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 2672 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START}, 2673 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2674 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START}, 2675 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 2676 }; 2677 2678 static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { 2679 {0x09C4, TX_RCVDET_ST_TMR}, 2680 {0x00FB, TX_PSC_A0}, 2681 {0x04AA, TX_PSC_A2}, 2682 {0x04AA, TX_PSC_A3}, 2683 {0x000F, XCVR_DIAG_BIDI_CTRL} 2684 }; 2685 2686 static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { 2687 {0x0000, RX_PSC_A0}, 2688 {0x0000, RX_PSC_A2}, 2689 {0x0000, RX_PSC_A3}, 2690 {0x0000, RX_PSC_CAL}, 2691 {0x0000, RX_REE_GCSM1_CTRL}, 2692 {0x0000, RX_REE_GCSM2_CTRL}, 2693 {0x0000, RX_REE_PERGCSM_CTRL} 2694 }; 2695 2696 static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = { 2697 .reg_pairs = sl_dp_25_no_ssc_cmn_regs, 2698 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs), 2699 }; 2700 2701 static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = { 2702 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs, 2703 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs), 2704 }; 2705 2706 static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = { 2707 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs, 2708 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs), 2709 }; 2710 2711 /* Single DP, 100 MHz Ref clk, no SSC */ 2712 static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { 2713 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2714 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 2715 }; 2716 2717 static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { 2718 {0x00FB, TX_PSC_A0}, 2719 {0x04AA, TX_PSC_A2}, 2720 {0x04AA, TX_PSC_A3}, 2721 {0x000F, XCVR_DIAG_BIDI_CTRL} 2722 }; 2723 2724 static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { 2725 {0x0000, RX_PSC_A0}, 2726 {0x0000, RX_PSC_A2}, 2727 {0x0000, RX_PSC_A3}, 2728 {0x0000, RX_PSC_CAL}, 2729 {0x0000, RX_REE_GCSM1_CTRL}, 2730 {0x0000, RX_REE_GCSM2_CTRL}, 2731 {0x0000, RX_REE_PERGCSM_CTRL} 2732 }; 2733 2734 static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = { 2735 .reg_pairs = sl_dp_100_no_ssc_cmn_regs, 2736 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs), 2737 }; 2738 2739 static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = { 2740 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs, 2741 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs), 2742 }; 2743 2744 static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = { 2745 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs, 2746 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs), 2747 }; 2748 2749 /* USB and SGMII/QSGMII link configuration */ 2750 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { 2751 {0x0002, PHY_PLL_CFG}, 2752 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}, 2753 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 2754 }; 2755 2756 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { 2757 {0x0000, XCVR_DIAG_HSCLK_SEL}, 2758 {0x0001, XCVR_DIAG_HSCLK_DIV}, 2759 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 2760 }; 2761 2762 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { 2763 {0x0011, XCVR_DIAG_HSCLK_SEL}, 2764 {0x0003, XCVR_DIAG_HSCLK_DIV}, 2765 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 2766 }; 2767 2768 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = { 2769 .reg_pairs = usb_sgmii_link_cmn_regs, 2770 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs), 2771 }; 2772 2773 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = { 2774 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs, 2775 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs), 2776 }; 2777 2778 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = { 2779 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs, 2780 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs), 2781 }; 2782 2783 /* PCIe and USB Unique SSC link configuration */ 2784 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { 2785 {0x0003, PHY_PLL_CFG}, 2786 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 2787 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 2788 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0} 2789 }; 2790 2791 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { 2792 {0x0000, XCVR_DIAG_HSCLK_SEL}, 2793 {0x0001, XCVR_DIAG_HSCLK_DIV}, 2794 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 2795 }; 2796 2797 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { 2798 {0x0011, XCVR_DIAG_HSCLK_SEL}, 2799 {0x0001, XCVR_DIAG_HSCLK_DIV}, 2800 {0x00C9, XCVR_DIAG_PLLDRC_CTRL} 2801 }; 2802 2803 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = { 2804 .reg_pairs = pcie_usb_link_cmn_regs, 2805 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs), 2806 }; 2807 2808 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = { 2809 .reg_pairs = pcie_usb_xcvr_diag_ln_regs, 2810 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs), 2811 }; 2812 2813 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = { 2814 .reg_pairs = usb_pcie_xcvr_diag_ln_regs, 2815 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs), 2816 }; 2817 2818 /* USB 100 MHz Ref clk, internal SSC */ 2819 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { 2820 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 2821 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 2822 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 2823 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 2824 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 2825 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2826 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 2827 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 2828 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 2829 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 2830 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 2831 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 2832 {0x0064, CMN_PLL0_INTDIV_M0}, 2833 {0x0050, CMN_PLL0_INTDIV_M1}, 2834 {0x0064, CMN_PLL1_INTDIV_M0}, 2835 {0x0002, CMN_PLL0_FRACDIVH_M0}, 2836 {0x0002, CMN_PLL0_FRACDIVH_M1}, 2837 {0x0002, CMN_PLL1_FRACDIVH_M0}, 2838 {0x0044, CMN_PLL0_HIGH_THR_M0}, 2839 {0x0036, CMN_PLL0_HIGH_THR_M1}, 2840 {0x0044, CMN_PLL1_HIGH_THR_M0}, 2841 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 2842 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 2843 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 2844 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 2845 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 2846 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 2847 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 2848 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 2849 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 2850 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 2851 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 2852 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 2853 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 2854 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 2855 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 2856 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 2857 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 2858 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 2859 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 2860 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 2861 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 2862 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 2863 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 2864 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 2865 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 2866 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 2867 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 2868 {0x007F, CMN_TXPUCAL_TUNE}, 2869 {0x007F, CMN_TXPDCAL_TUNE} 2870 }; 2871 2872 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = { 2873 .reg_pairs = usb_100_int_ssc_cmn_regs, 2874 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs), 2875 }; 2876 2877 /* Single USB link configuration */ 2878 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { 2879 {0x0000, PHY_PLL_CFG}, 2880 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 2881 }; 2882 2883 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { 2884 {0x0000, XCVR_DIAG_HSCLK_SEL}, 2885 {0x0001, XCVR_DIAG_HSCLK_DIV}, 2886 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 2887 }; 2888 2889 static struct cdns_torrent_vals sl_usb_link_cmn_vals = { 2890 .reg_pairs = sl_usb_link_cmn_regs, 2891 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs), 2892 }; 2893 2894 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = { 2895 .reg_pairs = sl_usb_xcvr_diag_ln_regs, 2896 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs), 2897 }; 2898 2899 /* USB PHY PCS common configuration */ 2900 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { 2901 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, 2902 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, 2903 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} 2904 }; 2905 2906 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { 2907 .reg_pairs = usb_phy_pcs_cmn_regs, 2908 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs), 2909 }; 2910 2911 /* USB 100 MHz Ref clk, no SSC */ 2912 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { 2913 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2914 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 2915 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 2916 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 2917 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 2918 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 2919 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 2920 }; 2921 2922 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = { 2923 .reg_pairs = sl_usb_100_no_ssc_cmn_regs, 2924 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), 2925 }; 2926 2927 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { 2928 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 2929 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 2930 {0x007F, CMN_TXPUCAL_TUNE}, 2931 {0x007F, CMN_TXPDCAL_TUNE} 2932 }; 2933 2934 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { 2935 {0x02FF, TX_PSC_A0}, 2936 {0x06AF, TX_PSC_A1}, 2937 {0x06AE, TX_PSC_A2}, 2938 {0x06AE, TX_PSC_A3}, 2939 {0x2A82, TX_TXCC_CTRL}, 2940 {0x0014, TX_TXCC_CPOST_MULT_01}, 2941 {0x0003, XCVR_DIAG_PSC_OVRD} 2942 }; 2943 2944 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { 2945 {0x0D1D, RX_PSC_A0}, 2946 {0x0D1D, RX_PSC_A1}, 2947 {0x0D00, RX_PSC_A2}, 2948 {0x0500, RX_PSC_A3}, 2949 {0x0013, RX_SIGDET_HL_FILT_TMR}, 2950 {0x0000, RX_REE_GCSM1_CTRL}, 2951 {0x0C02, RX_REE_ATTEN_THR}, 2952 {0x0330, RX_REE_SMGM_CTRL1}, 2953 {0x0300, RX_REE_SMGM_CTRL2}, 2954 {0x0019, RX_REE_TAP1_CLIP}, 2955 {0x0019, RX_REE_TAP2TON_CLIP}, 2956 {0x1004, RX_DIAG_SIGDET_TUNE}, 2957 {0x00F9, RX_DIAG_NQST_CTRL}, 2958 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 2959 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 2960 {0x0000, RX_DIAG_PI_CAP}, 2961 {0x0031, RX_DIAG_PI_RATE}, 2962 {0x0001, RX_DIAG_ACYA}, 2963 {0x018C, RX_CDRLF_CNFG}, 2964 {0x0003, RX_CDRLF_CNFG3} 2965 }; 2966 2967 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = { 2968 .reg_pairs = usb_100_no_ssc_cmn_regs, 2969 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs), 2970 }; 2971 2972 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = { 2973 .reg_pairs = usb_100_no_ssc_tx_ln_regs, 2974 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs), 2975 }; 2976 2977 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = { 2978 .reg_pairs = usb_100_no_ssc_rx_ln_regs, 2979 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs), 2980 }; 2981 2982 /* Single link USB, 100 MHz Ref clk, internal SSC */ 2983 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { 2984 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 2985 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 2986 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 2987 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 2988 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 2989 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 2990 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 2991 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 2992 {0x0064, CMN_PLL0_INTDIV_M0}, 2993 {0x0064, CMN_PLL1_INTDIV_M0}, 2994 {0x0002, CMN_PLL0_FRACDIVH_M0}, 2995 {0x0002, CMN_PLL1_FRACDIVH_M0}, 2996 {0x0044, CMN_PLL0_HIGH_THR_M0}, 2997 {0x0044, CMN_PLL1_HIGH_THR_M0}, 2998 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 2999 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3000 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3001 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3002 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3003 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3004 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3005 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3006 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3007 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3008 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3009 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3010 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3011 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3012 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3013 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3014 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3015 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3016 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3017 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3018 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3019 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3020 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3021 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 3022 }; 3023 3024 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = { 3025 .reg_pairs = sl_usb_100_int_ssc_cmn_regs, 3026 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs), 3027 }; 3028 3029 /* PCIe and SGMII/QSGMII Unique SSC link configuration */ 3030 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { 3031 {0x0003, PHY_PLL_CFG}, 3032 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3033 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3034 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3035 }; 3036 3037 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { 3038 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3039 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3040 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3041 }; 3042 3043 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { 3044 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3045 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3046 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 3047 }; 3048 3049 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = { 3050 .reg_pairs = pcie_sgmii_link_cmn_regs, 3051 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs), 3052 }; 3053 3054 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = { 3055 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs, 3056 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs), 3057 }; 3058 3059 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { 3060 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs, 3061 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs), 3062 }; 3063 3064 /* SGMII 100 MHz Ref clk, no SSC */ 3065 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { 3066 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3067 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3068 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3069 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3070 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3071 }; 3072 3073 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = { 3074 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs, 3075 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), 3076 }; 3077 3078 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { 3079 {0x007F, CMN_TXPUCAL_TUNE}, 3080 {0x007F, CMN_TXPDCAL_TUNE} 3081 }; 3082 3083 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { 3084 {0x00F3, TX_PSC_A0}, 3085 {0x04A2, TX_PSC_A2}, 3086 {0x04A2, TX_PSC_A3}, 3087 {0x0000, TX_TXCC_CPOST_MULT_00}, 3088 {0x00B3, DRV_DIAG_TX_DRV} 3089 }; 3090 3091 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { 3092 {0x00F3, TX_PSC_A0}, 3093 {0x04A2, TX_PSC_A2}, 3094 {0x04A2, TX_PSC_A3}, 3095 {0x0000, TX_TXCC_CPOST_MULT_00}, 3096 {0x00B3, DRV_DIAG_TX_DRV}, 3097 {0x4000, XCVR_DIAG_RXCLK_CTRL}, 3098 }; 3099 3100 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { 3101 {0x091D, RX_PSC_A0}, 3102 {0x0900, RX_PSC_A2}, 3103 {0x0100, RX_PSC_A3}, 3104 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3105 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3106 {0x0000, RX_DIAG_DFE_CTRL}, 3107 {0x0019, RX_REE_TAP1_CLIP}, 3108 {0x0019, RX_REE_TAP2TON_CLIP}, 3109 {0x0098, RX_DIAG_NQST_CTRL}, 3110 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3111 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 3112 {0x0000, RX_DIAG_PI_CAP}, 3113 {0x0010, RX_DIAG_PI_RATE}, 3114 {0x0001, RX_DIAG_ACYA}, 3115 {0x018C, RX_CDRLF_CNFG}, 3116 }; 3117 3118 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = { 3119 .reg_pairs = sgmii_100_no_ssc_cmn_regs, 3120 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs), 3121 }; 3122 3123 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { 3124 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs, 3125 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), 3126 }; 3127 3128 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = { 3129 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs, 3130 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs), 3131 }; 3132 3133 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { 3134 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, 3135 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), 3136 }; 3137 3138 /* SGMII 100 MHz Ref clk, internal SSC */ 3139 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { 3140 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3141 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3142 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3143 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3144 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3145 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3146 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3147 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3148 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3149 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3150 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3151 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3152 {0x0064, CMN_PLL0_INTDIV_M0}, 3153 {0x0050, CMN_PLL0_INTDIV_M1}, 3154 {0x0064, CMN_PLL1_INTDIV_M0}, 3155 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3156 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3157 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3158 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3159 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3160 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3161 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3162 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3163 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3164 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3165 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3166 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3167 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3168 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3169 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3170 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3171 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3172 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3173 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3174 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3175 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3176 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3177 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3178 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3179 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3180 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3181 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3182 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3183 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3184 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3185 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3186 {0x007F, CMN_TXPUCAL_TUNE}, 3187 {0x007F, CMN_TXPDCAL_TUNE} 3188 }; 3189 3190 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { 3191 .reg_pairs = sgmii_100_int_ssc_cmn_regs, 3192 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs), 3193 }; 3194 3195 /* QSGMII 100 MHz Ref clk, no SSC */ 3196 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { 3197 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3198 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3199 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3200 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3201 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3202 }; 3203 3204 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = { 3205 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs, 3206 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), 3207 }; 3208 3209 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { 3210 {0x007F, CMN_TXPUCAL_TUNE}, 3211 {0x007F, CMN_TXPDCAL_TUNE} 3212 }; 3213 3214 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { 3215 {0x00F3, TX_PSC_A0}, 3216 {0x04A2, TX_PSC_A2}, 3217 {0x04A2, TX_PSC_A3}, 3218 {0x0000, TX_TXCC_CPOST_MULT_00}, 3219 {0x0011, TX_TXCC_MGNFS_MULT_100}, 3220 {0x0003, DRV_DIAG_TX_DRV} 3221 }; 3222 3223 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { 3224 {0x00F3, TX_PSC_A0}, 3225 {0x04A2, TX_PSC_A2}, 3226 {0x04A2, TX_PSC_A3}, 3227 {0x0000, TX_TXCC_CPOST_MULT_00}, 3228 {0x0011, TX_TXCC_MGNFS_MULT_100}, 3229 {0x0003, DRV_DIAG_TX_DRV}, 3230 {0x4000, XCVR_DIAG_RXCLK_CTRL}, 3231 }; 3232 3233 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { 3234 {0x091D, RX_PSC_A0}, 3235 {0x0900, RX_PSC_A2}, 3236 {0x0100, RX_PSC_A3}, 3237 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3238 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3239 {0x0000, RX_DIAG_DFE_CTRL}, 3240 {0x0019, RX_REE_TAP1_CLIP}, 3241 {0x0019, RX_REE_TAP2TON_CLIP}, 3242 {0x0098, RX_DIAG_NQST_CTRL}, 3243 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 3244 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 3245 {0x0000, RX_DIAG_PI_CAP}, 3246 {0x0010, RX_DIAG_PI_RATE}, 3247 {0x0001, RX_DIAG_ACYA}, 3248 {0x018C, RX_CDRLF_CNFG}, 3249 }; 3250 3251 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = { 3252 .reg_pairs = qsgmii_100_no_ssc_cmn_regs, 3253 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs), 3254 }; 3255 3256 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { 3257 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs, 3258 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), 3259 }; 3260 3261 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = { 3262 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs, 3263 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs), 3264 }; 3265 3266 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { 3267 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, 3268 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), 3269 }; 3270 3271 /* QSGMII 100 MHz Ref clk, internal SSC */ 3272 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { 3273 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3274 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3275 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3276 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3277 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3278 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3279 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3280 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3281 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3282 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3283 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3284 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3285 {0x0064, CMN_PLL0_INTDIV_M0}, 3286 {0x0050, CMN_PLL0_INTDIV_M1}, 3287 {0x0064, CMN_PLL1_INTDIV_M0}, 3288 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3289 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3290 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3291 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3292 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3293 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3294 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3295 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3296 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3297 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3298 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3299 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3300 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3301 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3302 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3303 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3304 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3305 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3306 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3307 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3308 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3309 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3310 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3311 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3312 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3313 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3314 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3315 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3316 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3317 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3318 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 3319 {0x007F, CMN_TXPUCAL_TUNE}, 3320 {0x007F, CMN_TXPDCAL_TUNE} 3321 }; 3322 3323 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { 3324 .reg_pairs = qsgmii_100_int_ssc_cmn_regs, 3325 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs), 3326 }; 3327 3328 /* Single SGMII/QSGMII link configuration */ 3329 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { 3330 {0x0000, PHY_PLL_CFG}, 3331 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} 3332 }; 3333 3334 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { 3335 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3336 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3337 {0x0013, XCVR_DIAG_PLLDRC_CTRL} 3338 }; 3339 3340 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = { 3341 .reg_pairs = sl_sgmii_link_cmn_regs, 3342 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs), 3343 }; 3344 3345 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = { 3346 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs, 3347 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs), 3348 }; 3349 3350 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */ 3351 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { 3352 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3353 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3354 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3355 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3356 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3357 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3358 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3359 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3360 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3361 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3362 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3363 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3364 {0x0064, CMN_PLL0_INTDIV_M0}, 3365 {0x0050, CMN_PLL0_INTDIV_M1}, 3366 {0x0064, CMN_PLL1_INTDIV_M0}, 3367 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3368 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3369 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3370 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3371 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3372 {0x0044, CMN_PLL1_HIGH_THR_M0}, 3373 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3374 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3375 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3376 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3377 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3378 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3379 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3380 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3381 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3382 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3383 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3384 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 3385 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3386 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3387 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 3388 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3389 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3390 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3391 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3392 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3393 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3394 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3395 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3396 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3397 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 3398 }; 3399 3400 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = { 3401 .reg_pairs = pcie_100_int_ssc_cmn_regs, 3402 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs), 3403 }; 3404 3405 /* Single link PCIe, 100 MHz Ref clk, internal SSC */ 3406 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { 3407 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3408 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3409 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3410 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3411 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 3412 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3413 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3414 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 3415 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3416 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3417 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 3418 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3419 {0x0064, CMN_PLL0_INTDIV_M0}, 3420 {0x0050, CMN_PLL0_INTDIV_M1}, 3421 {0x0050, CMN_PLL1_INTDIV_M0}, 3422 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3423 {0x0002, CMN_PLL0_FRACDIVH_M1}, 3424 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3425 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3426 {0x0036, CMN_PLL0_HIGH_THR_M1}, 3427 {0x0036, CMN_PLL1_HIGH_THR_M0}, 3428 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3429 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 3430 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3431 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3432 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 3433 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3434 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3435 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 3436 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3437 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3438 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 3439 {0x0058, CMN_PLL1_SS_CTRL3_M0}, 3440 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3441 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 3442 {0x0012, CMN_PLL1_SS_CTRL4_M0}, 3443 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3444 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3445 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3446 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3447 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3448 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3449 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3450 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3451 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3452 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 3453 }; 3454 3455 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { 3456 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs, 3457 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs), 3458 }; 3459 3460 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ 3461 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { 3462 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3463 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3464 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} 3465 }; 3466 3467 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { 3468 {0x0019, RX_REE_TAP1_CLIP}, 3469 {0x0019, RX_REE_TAP2TON_CLIP}, 3470 {0x0001, RX_DIAG_ACYA} 3471 }; 3472 3473 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = { 3474 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs, 3475 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs), 3476 }; 3477 3478 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { 3479 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs, 3480 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs), 3481 }; 3482 3483 static const struct cdns_torrent_data cdns_map_torrent = { 3484 .block_offset_shift = 0x2, 3485 .reg_offset_shift = 0x2, 3486 .link_cmn_vals = { 3487 [TYPE_DP] = { 3488 [TYPE_NONE] = { 3489 [NO_SSC] = &sl_dp_link_cmn_vals, 3490 }, 3491 }, 3492 [TYPE_PCIE] = { 3493 [TYPE_NONE] = { 3494 [NO_SSC] = NULL, 3495 [EXTERNAL_SSC] = NULL, 3496 [INTERNAL_SSC] = NULL, 3497 }, 3498 [TYPE_SGMII] = { 3499 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3500 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3501 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3502 }, 3503 [TYPE_QSGMII] = { 3504 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3505 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3506 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3507 }, 3508 [TYPE_USB] = { 3509 [NO_SSC] = &pcie_usb_link_cmn_vals, 3510 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3511 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3512 }, 3513 }, 3514 [TYPE_SGMII] = { 3515 [TYPE_NONE] = { 3516 [NO_SSC] = &sl_sgmii_link_cmn_vals, 3517 }, 3518 [TYPE_PCIE] = { 3519 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3520 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3521 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3522 }, 3523 [TYPE_USB] = { 3524 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3525 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3526 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3527 }, 3528 }, 3529 [TYPE_QSGMII] = { 3530 [TYPE_NONE] = { 3531 [NO_SSC] = &sl_sgmii_link_cmn_vals, 3532 }, 3533 [TYPE_PCIE] = { 3534 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3535 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3536 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3537 }, 3538 [TYPE_USB] = { 3539 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3540 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3541 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3542 }, 3543 }, 3544 [TYPE_USB] = { 3545 [TYPE_NONE] = { 3546 [NO_SSC] = &sl_usb_link_cmn_vals, 3547 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, 3548 [INTERNAL_SSC] = &sl_usb_link_cmn_vals, 3549 }, 3550 [TYPE_PCIE] = { 3551 [NO_SSC] = &pcie_usb_link_cmn_vals, 3552 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3553 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3554 }, 3555 [TYPE_SGMII] = { 3556 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3557 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3558 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3559 }, 3560 [TYPE_QSGMII] = { 3561 [NO_SSC] = &usb_sgmii_link_cmn_vals, 3562 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3563 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 3564 }, 3565 }, 3566 }, 3567 .xcvr_diag_vals = { 3568 [TYPE_DP] = { 3569 [TYPE_NONE] = { 3570 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals, 3571 }, 3572 }, 3573 [TYPE_PCIE] = { 3574 [TYPE_NONE] = { 3575 [NO_SSC] = NULL, 3576 [EXTERNAL_SSC] = NULL, 3577 [INTERNAL_SSC] = NULL, 3578 }, 3579 [TYPE_SGMII] = { 3580 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3581 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3582 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3583 }, 3584 [TYPE_QSGMII] = { 3585 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3586 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3587 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 3588 }, 3589 [TYPE_USB] = { 3590 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals, 3591 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 3592 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 3593 }, 3594 }, 3595 [TYPE_SGMII] = { 3596 [TYPE_NONE] = { 3597 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 3598 }, 3599 [TYPE_PCIE] = { 3600 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3601 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3602 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3603 }, 3604 [TYPE_USB] = { 3605 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3606 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3607 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3608 }, 3609 }, 3610 [TYPE_QSGMII] = { 3611 [TYPE_NONE] = { 3612 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 3613 }, 3614 [TYPE_PCIE] = { 3615 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3616 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3617 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 3618 }, 3619 [TYPE_USB] = { 3620 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3621 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3622 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 3623 }, 3624 }, 3625 [TYPE_USB] = { 3626 [TYPE_NONE] = { 3627 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, 3628 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 3629 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 3630 }, 3631 [TYPE_PCIE] = { 3632 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals, 3633 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 3634 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 3635 }, 3636 [TYPE_SGMII] = { 3637 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3638 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3639 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3640 }, 3641 [TYPE_QSGMII] = { 3642 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3643 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3644 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 3645 }, 3646 }, 3647 }, 3648 .pcs_cmn_vals = { 3649 [TYPE_USB] = { 3650 [TYPE_NONE] = { 3651 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3652 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3653 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3654 }, 3655 [TYPE_PCIE] = { 3656 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3657 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3658 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3659 }, 3660 [TYPE_SGMII] = { 3661 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3662 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3663 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3664 }, 3665 [TYPE_QSGMII] = { 3666 [NO_SSC] = &usb_phy_pcs_cmn_vals, 3667 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3668 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 3669 }, 3670 }, 3671 }, 3672 .cmn_vals = { 3673 [CLK_19_2_MHZ] = { 3674 [TYPE_DP] = { 3675 [TYPE_NONE] = { 3676 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals, 3677 }, 3678 }, 3679 }, 3680 [CLK_25_MHZ] = { 3681 [TYPE_DP] = { 3682 [TYPE_NONE] = { 3683 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals, 3684 }, 3685 }, 3686 }, 3687 [CLK_100_MHZ] = { 3688 [TYPE_DP] = { 3689 [TYPE_NONE] = { 3690 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals, 3691 }, 3692 }, 3693 [TYPE_PCIE] = { 3694 [TYPE_NONE] = { 3695 [NO_SSC] = NULL, 3696 [EXTERNAL_SSC] = NULL, 3697 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, 3698 }, 3699 [TYPE_SGMII] = { 3700 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 3701 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 3702 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 3703 }, 3704 [TYPE_QSGMII] = { 3705 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 3706 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 3707 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 3708 }, 3709 [TYPE_USB] = { 3710 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 3711 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 3712 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 3713 }, 3714 }, 3715 [TYPE_SGMII] = { 3716 [TYPE_NONE] = { 3717 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, 3718 }, 3719 [TYPE_PCIE] = { 3720 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 3721 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 3722 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, 3723 }, 3724 [TYPE_USB] = { 3725 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 3726 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 3727 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 3728 }, 3729 }, 3730 [TYPE_QSGMII] = { 3731 [TYPE_NONE] = { 3732 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, 3733 }, 3734 [TYPE_PCIE] = { 3735 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3736 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3737 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, 3738 }, 3739 [TYPE_USB] = { 3740 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3741 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3742 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 3743 }, 3744 }, 3745 [TYPE_USB] = { 3746 [TYPE_NONE] = { 3747 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3748 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3749 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 3750 }, 3751 [TYPE_PCIE] = { 3752 [NO_SSC] = &usb_100_no_ssc_cmn_vals, 3753 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, 3754 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, 3755 }, 3756 [TYPE_SGMII] = { 3757 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3758 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3759 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 3760 }, 3761 [TYPE_QSGMII] = { 3762 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3763 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 3764 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 3765 }, 3766 }, 3767 }, 3768 }, 3769 .tx_ln_vals = { 3770 [CLK_19_2_MHZ] = { 3771 [TYPE_DP] = { 3772 [TYPE_NONE] = { 3773 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals, 3774 }, 3775 }, 3776 }, 3777 [CLK_25_MHZ] = { 3778 [TYPE_DP] = { 3779 [TYPE_NONE] = { 3780 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals, 3781 }, 3782 }, 3783 }, 3784 [CLK_100_MHZ] = { 3785 [TYPE_DP] = { 3786 [TYPE_NONE] = { 3787 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals, 3788 }, 3789 }, 3790 [TYPE_PCIE] = { 3791 [TYPE_NONE] = { 3792 [NO_SSC] = NULL, 3793 [EXTERNAL_SSC] = NULL, 3794 [INTERNAL_SSC] = NULL, 3795 }, 3796 [TYPE_SGMII] = { 3797 [NO_SSC] = NULL, 3798 [EXTERNAL_SSC] = NULL, 3799 [INTERNAL_SSC] = NULL, 3800 }, 3801 [TYPE_QSGMII] = { 3802 [NO_SSC] = NULL, 3803 [EXTERNAL_SSC] = NULL, 3804 [INTERNAL_SSC] = NULL, 3805 }, 3806 [TYPE_USB] = { 3807 [NO_SSC] = NULL, 3808 [EXTERNAL_SSC] = NULL, 3809 [INTERNAL_SSC] = NULL, 3810 }, 3811 }, 3812 [TYPE_SGMII] = { 3813 [TYPE_NONE] = { 3814 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3815 }, 3816 [TYPE_PCIE] = { 3817 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3818 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3819 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3820 }, 3821 [TYPE_USB] = { 3822 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3823 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3824 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals, 3825 }, 3826 }, 3827 [TYPE_QSGMII] = { 3828 [TYPE_NONE] = { 3829 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3830 }, 3831 [TYPE_PCIE] = { 3832 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3833 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3834 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3835 }, 3836 [TYPE_USB] = { 3837 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3838 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3839 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals, 3840 }, 3841 }, 3842 [TYPE_USB] = { 3843 [TYPE_NONE] = { 3844 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 3845 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3846 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3847 }, 3848 [TYPE_PCIE] = { 3849 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 3850 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3851 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3852 }, 3853 [TYPE_SGMII] = { 3854 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 3855 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3856 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3857 }, 3858 [TYPE_QSGMII] = { 3859 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 3860 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3861 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 3862 }, 3863 }, 3864 }, 3865 }, 3866 .rx_ln_vals = { 3867 [CLK_19_2_MHZ] = { 3868 [TYPE_DP] = { 3869 [TYPE_NONE] = { 3870 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals, 3871 }, 3872 }, 3873 }, 3874 [CLK_25_MHZ] = { 3875 [TYPE_DP] = { 3876 [TYPE_NONE] = { 3877 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals, 3878 }, 3879 }, 3880 }, 3881 [CLK_100_MHZ] = { 3882 [TYPE_DP] = { 3883 [TYPE_NONE] = { 3884 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals, 3885 }, 3886 }, 3887 [TYPE_PCIE] = { 3888 [TYPE_NONE] = { 3889 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3890 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3891 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3892 }, 3893 [TYPE_SGMII] = { 3894 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3895 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3896 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3897 }, 3898 [TYPE_QSGMII] = { 3899 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3900 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3901 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3902 }, 3903 [TYPE_USB] = { 3904 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3905 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3906 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 3907 }, 3908 }, 3909 [TYPE_SGMII] = { 3910 [TYPE_NONE] = { 3911 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3912 }, 3913 [TYPE_PCIE] = { 3914 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3915 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3916 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3917 }, 3918 [TYPE_USB] = { 3919 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3920 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3921 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 3922 }, 3923 }, 3924 [TYPE_QSGMII] = { 3925 [TYPE_NONE] = { 3926 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3927 }, 3928 [TYPE_PCIE] = { 3929 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3930 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3931 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3932 }, 3933 [TYPE_USB] = { 3934 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3935 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3936 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 3937 }, 3938 }, 3939 [TYPE_USB] = { 3940 [TYPE_NONE] = { 3941 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 3942 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3943 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3944 }, 3945 [TYPE_PCIE] = { 3946 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 3947 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3948 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3949 }, 3950 [TYPE_SGMII] = { 3951 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 3952 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3953 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3954 }, 3955 [TYPE_QSGMII] = { 3956 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 3957 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3958 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 3959 }, 3960 }, 3961 }, 3962 }, 3963 }; 3964 3965 static const struct cdns_torrent_data ti_j721e_map_torrent = { 3966 .block_offset_shift = 0x0, 3967 .reg_offset_shift = 0x1, 3968 .link_cmn_vals = { 3969 [TYPE_DP] = { 3970 [TYPE_NONE] = { 3971 [NO_SSC] = &sl_dp_link_cmn_vals, 3972 }, 3973 }, 3974 [TYPE_PCIE] = { 3975 [TYPE_NONE] = { 3976 [NO_SSC] = NULL, 3977 [EXTERNAL_SSC] = NULL, 3978 [INTERNAL_SSC] = NULL, 3979 }, 3980 [TYPE_SGMII] = { 3981 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3982 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3983 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3984 }, 3985 [TYPE_QSGMII] = { 3986 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 3987 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3988 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 3989 }, 3990 [TYPE_USB] = { 3991 [NO_SSC] = &pcie_usb_link_cmn_vals, 3992 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3993 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 3994 }, 3995 }, 3996 [TYPE_SGMII] = { 3997 [TYPE_NONE] = { 3998 [NO_SSC] = &sl_sgmii_link_cmn_vals, 3999 }, 4000 [TYPE_PCIE] = { 4001 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 4002 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4003 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4004 }, 4005 [TYPE_USB] = { 4006 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4007 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4008 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4009 }, 4010 }, 4011 [TYPE_QSGMII] = { 4012 [TYPE_NONE] = { 4013 [NO_SSC] = &sl_sgmii_link_cmn_vals, 4014 }, 4015 [TYPE_PCIE] = { 4016 [NO_SSC] = &pcie_sgmii_link_cmn_vals, 4017 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4018 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals, 4019 }, 4020 [TYPE_USB] = { 4021 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4022 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4023 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4024 }, 4025 }, 4026 [TYPE_USB] = { 4027 [TYPE_NONE] = { 4028 [NO_SSC] = &sl_usb_link_cmn_vals, 4029 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals, 4030 [INTERNAL_SSC] = &sl_usb_link_cmn_vals, 4031 }, 4032 [TYPE_PCIE] = { 4033 [NO_SSC] = &pcie_usb_link_cmn_vals, 4034 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals, 4035 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals, 4036 }, 4037 [TYPE_SGMII] = { 4038 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4039 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4040 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4041 }, 4042 [TYPE_QSGMII] = { 4043 [NO_SSC] = &usb_sgmii_link_cmn_vals, 4044 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4045 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals, 4046 }, 4047 }, 4048 }, 4049 .xcvr_diag_vals = { 4050 [TYPE_DP] = { 4051 [TYPE_NONE] = { 4052 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals, 4053 }, 4054 }, 4055 [TYPE_PCIE] = { 4056 [TYPE_NONE] = { 4057 [NO_SSC] = NULL, 4058 [EXTERNAL_SSC] = NULL, 4059 [INTERNAL_SSC] = NULL, 4060 }, 4061 [TYPE_SGMII] = { 4062 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4063 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4064 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4065 }, 4066 [TYPE_QSGMII] = { 4067 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4068 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4069 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals, 4070 }, 4071 [TYPE_USB] = { 4072 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals, 4073 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 4074 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals, 4075 }, 4076 }, 4077 [TYPE_SGMII] = { 4078 [TYPE_NONE] = { 4079 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 4080 }, 4081 [TYPE_PCIE] = { 4082 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4083 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4084 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4085 }, 4086 [TYPE_USB] = { 4087 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4088 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4089 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4090 }, 4091 }, 4092 [TYPE_QSGMII] = { 4093 [TYPE_NONE] = { 4094 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals, 4095 }, 4096 [TYPE_PCIE] = { 4097 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4098 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4099 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals, 4100 }, 4101 [TYPE_USB] = { 4102 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4103 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4104 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals, 4105 }, 4106 }, 4107 [TYPE_USB] = { 4108 [TYPE_NONE] = { 4109 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals, 4110 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 4111 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals, 4112 }, 4113 [TYPE_PCIE] = { 4114 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals, 4115 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 4116 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals, 4117 }, 4118 [TYPE_SGMII] = { 4119 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4120 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4121 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4122 }, 4123 [TYPE_QSGMII] = { 4124 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4125 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4126 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals, 4127 }, 4128 }, 4129 }, 4130 .pcs_cmn_vals = { 4131 [TYPE_USB] = { 4132 [TYPE_NONE] = { 4133 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4134 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4135 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4136 }, 4137 [TYPE_PCIE] = { 4138 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4139 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4140 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4141 }, 4142 [TYPE_SGMII] = { 4143 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4144 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4145 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4146 }, 4147 [TYPE_QSGMII] = { 4148 [NO_SSC] = &usb_phy_pcs_cmn_vals, 4149 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4150 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals, 4151 }, 4152 }, 4153 }, 4154 .cmn_vals = { 4155 [CLK_19_2_MHZ] = { 4156 [TYPE_DP] = { 4157 [TYPE_NONE] = { 4158 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals, 4159 }, 4160 }, 4161 }, 4162 [CLK_25_MHZ] = { 4163 [TYPE_DP] = { 4164 [TYPE_NONE] = { 4165 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals, 4166 }, 4167 }, 4168 }, 4169 [CLK_100_MHZ] = { 4170 [TYPE_DP] = { 4171 [TYPE_NONE] = { 4172 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals, 4173 }, 4174 }, 4175 [TYPE_PCIE] = { 4176 [TYPE_NONE] = { 4177 [NO_SSC] = NULL, 4178 [EXTERNAL_SSC] = NULL, 4179 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals, 4180 }, 4181 [TYPE_SGMII] = { 4182 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 4183 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 4184 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 4185 }, 4186 [TYPE_QSGMII] = { 4187 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 4188 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 4189 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 4190 }, 4191 [TYPE_USB] = { 4192 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 4193 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals, 4194 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 4195 }, 4196 }, 4197 [TYPE_SGMII] = { 4198 [TYPE_NONE] = { 4199 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals, 4200 }, 4201 [TYPE_PCIE] = { 4202 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 4203 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 4204 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals, 4205 }, 4206 [TYPE_USB] = { 4207 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals, 4208 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 4209 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals, 4210 }, 4211 }, 4212 [TYPE_QSGMII] = { 4213 [TYPE_NONE] = { 4214 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals, 4215 }, 4216 [TYPE_PCIE] = { 4217 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4218 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4219 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals, 4220 }, 4221 [TYPE_USB] = { 4222 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4223 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4224 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals, 4225 }, 4226 }, 4227 [TYPE_USB] = { 4228 [TYPE_NONE] = { 4229 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4230 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4231 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4232 }, 4233 [TYPE_PCIE] = { 4234 [NO_SSC] = &usb_100_no_ssc_cmn_vals, 4235 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals, 4236 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals, 4237 }, 4238 [TYPE_SGMII] = { 4239 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4240 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4241 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4242 }, 4243 [TYPE_QSGMII] = { 4244 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4245 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals, 4246 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals, 4247 }, 4248 }, 4249 }, 4250 }, 4251 .tx_ln_vals = { 4252 [CLK_19_2_MHZ] = { 4253 [TYPE_DP] = { 4254 [TYPE_NONE] = { 4255 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals, 4256 }, 4257 }, 4258 }, 4259 [CLK_25_MHZ] = { 4260 [TYPE_DP] = { 4261 [TYPE_NONE] = { 4262 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals, 4263 }, 4264 }, 4265 }, 4266 [CLK_100_MHZ] = { 4267 [TYPE_DP] = { 4268 [TYPE_NONE] = { 4269 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals, 4270 }, 4271 }, 4272 [TYPE_PCIE] = { 4273 [TYPE_NONE] = { 4274 [NO_SSC] = NULL, 4275 [EXTERNAL_SSC] = NULL, 4276 [INTERNAL_SSC] = NULL, 4277 }, 4278 [TYPE_SGMII] = { 4279 [NO_SSC] = NULL, 4280 [EXTERNAL_SSC] = NULL, 4281 [INTERNAL_SSC] = NULL, 4282 }, 4283 [TYPE_QSGMII] = { 4284 [NO_SSC] = NULL, 4285 [EXTERNAL_SSC] = NULL, 4286 [INTERNAL_SSC] = NULL, 4287 }, 4288 [TYPE_USB] = { 4289 [NO_SSC] = NULL, 4290 [EXTERNAL_SSC] = NULL, 4291 [INTERNAL_SSC] = NULL, 4292 }, 4293 }, 4294 [TYPE_SGMII] = { 4295 [TYPE_NONE] = { 4296 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4297 }, 4298 [TYPE_PCIE] = { 4299 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4300 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4301 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4302 }, 4303 [TYPE_USB] = { 4304 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4305 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4306 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals, 4307 }, 4308 }, 4309 [TYPE_QSGMII] = { 4310 [TYPE_NONE] = { 4311 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4312 }, 4313 [TYPE_PCIE] = { 4314 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4315 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4316 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4317 }, 4318 [TYPE_USB] = { 4319 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4320 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4321 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals, 4322 }, 4323 }, 4324 [TYPE_USB] = { 4325 [TYPE_NONE] = { 4326 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4327 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4328 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4329 }, 4330 [TYPE_PCIE] = { 4331 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4332 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4333 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4334 }, 4335 [TYPE_SGMII] = { 4336 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4337 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4338 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4339 }, 4340 [TYPE_QSGMII] = { 4341 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals, 4342 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4343 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals, 4344 }, 4345 }, 4346 }, 4347 }, 4348 .rx_ln_vals = { 4349 [CLK_19_2_MHZ] = { 4350 [TYPE_DP] = { 4351 [TYPE_NONE] = { 4352 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals, 4353 }, 4354 }, 4355 }, 4356 [CLK_25_MHZ] = { 4357 [TYPE_DP] = { 4358 [TYPE_NONE] = { 4359 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals, 4360 }, 4361 }, 4362 }, 4363 [CLK_100_MHZ] = { 4364 [TYPE_DP] = { 4365 [TYPE_NONE] = { 4366 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals, 4367 }, 4368 }, 4369 [TYPE_PCIE] = { 4370 [TYPE_NONE] = { 4371 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4372 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4373 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4374 }, 4375 [TYPE_SGMII] = { 4376 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4377 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4378 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4379 }, 4380 [TYPE_QSGMII] = { 4381 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4382 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4383 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4384 }, 4385 [TYPE_USB] = { 4386 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4387 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4388 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals, 4389 }, 4390 }, 4391 [TYPE_SGMII] = { 4392 [TYPE_NONE] = { 4393 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4394 }, 4395 [TYPE_PCIE] = { 4396 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4397 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4398 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4399 }, 4400 [TYPE_USB] = { 4401 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4402 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4403 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals, 4404 }, 4405 }, 4406 [TYPE_QSGMII] = { 4407 [TYPE_NONE] = { 4408 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4409 }, 4410 [TYPE_PCIE] = { 4411 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4412 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4413 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4414 }, 4415 [TYPE_USB] = { 4416 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4417 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4418 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals, 4419 }, 4420 }, 4421 [TYPE_USB] = { 4422 [TYPE_NONE] = { 4423 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4424 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4425 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4426 }, 4427 [TYPE_PCIE] = { 4428 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4429 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4430 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4431 }, 4432 [TYPE_SGMII] = { 4433 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4434 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4435 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4436 }, 4437 [TYPE_QSGMII] = { 4438 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals, 4439 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4440 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals, 4441 }, 4442 }, 4443 }, 4444 }, 4445 }; 4446 4447 static const struct of_device_id cdns_torrent_phy_of_match[] = { 4448 { 4449 .compatible = "cdns,torrent-phy", 4450 .data = &cdns_map_torrent, 4451 }, 4452 { 4453 .compatible = "ti,j721e-serdes-10g", 4454 .data = &ti_j721e_map_torrent, 4455 }, 4456 {} 4457 }; 4458 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); 4459 4460 static struct platform_driver cdns_torrent_phy_driver = { 4461 .probe = cdns_torrent_phy_probe, 4462 .remove = cdns_torrent_phy_remove, 4463 .driver = { 4464 .name = "cdns-torrent-phy", 4465 .of_match_table = cdns_torrent_phy_of_match, 4466 } 4467 }; 4468 module_platform_driver(cdns_torrent_phy_driver); 4469 4470 MODULE_AUTHOR("Cadence Design Systems, Inc."); 4471 MODULE_DESCRIPTION("Cadence Torrent PHY driver"); 4472 MODULE_LICENSE("GPL v2"); 4473