1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <dt-bindings/phy/phy.h> 24 #include <dt-bindings/phy/phy-cadence.h> 25 26 #define NUM_SSC_MODE 3 27 #define NUM_PHY_TYPE 4 28 29 /* PHY register offsets */ 30 #define SIERRA_COMMON_CDB_OFFSET 0x0 31 #define SIERRA_MACRO_ID_REG 0x0 32 #define SIERRA_CMN_PLLLC_GEN_PREG 0x42 33 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 34 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 35 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 36 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 37 #define SIERRA_CMN_PLLLC_CLK1_PREG 0x4D 38 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 39 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 40 #define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51 41 #define SIERRA_CMN_PLLLC_SS_PREG 0x52 42 #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53 43 #define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54 44 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 45 #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63 46 #define SIERRA_CMN_REFRCV_PREG 0x98 47 #define SIERRA_CMN_REFRCV1_PREG 0xB8 48 #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 49 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA 50 #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 51 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 52 53 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 54 ((0x4000 << (block_offset)) + \ 55 (((ln) << 9) << (reg_offset))) 56 57 #define SIERRA_DET_STANDEC_A_PREG 0x000 58 #define SIERRA_DET_STANDEC_B_PREG 0x001 59 #define SIERRA_DET_STANDEC_C_PREG 0x002 60 #define SIERRA_DET_STANDEC_D_PREG 0x003 61 #define SIERRA_DET_STANDEC_E_PREG 0x004 62 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 63 #define SIERRA_PSM_A0IN_TMR_PREG 0x009 64 #define SIERRA_PSM_A3IN_TMR_PREG 0x00C 65 #define SIERRA_PSM_DIAG_PREG 0x015 66 #define SIERRA_PSC_LN_A3_PREG 0x023 67 #define SIERRA_PSC_LN_A4_PREG 0x024 68 #define SIERRA_PSC_LN_IDLE_PREG 0x026 69 #define SIERRA_PSC_TX_A0_PREG 0x028 70 #define SIERRA_PSC_TX_A1_PREG 0x029 71 #define SIERRA_PSC_TX_A2_PREG 0x02A 72 #define SIERRA_PSC_TX_A3_PREG 0x02B 73 #define SIERRA_PSC_RX_A0_PREG 0x030 74 #define SIERRA_PSC_RX_A1_PREG 0x031 75 #define SIERRA_PSC_RX_A2_PREG 0x032 76 #define SIERRA_PSC_RX_A3_PREG 0x033 77 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 78 #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B 79 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 80 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 81 #define SIERRA_PLLCTRL_STATUS_PREG 0x044 82 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 83 #define SIERRA_DFE_BIASTRIM_PREG 0x04C 84 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 85 #define SIERRA_DRVCTRL_BOOST_PREG 0x06F 86 #define SIERRA_TX_RCVDET_OVRD_PREG 0x072 87 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 88 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 89 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 90 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 91 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 92 #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C 93 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 94 #define SIERRA_RX_CTLE_CAL_PREG 0x08F 95 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 96 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 97 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 98 #define SIERRA_CREQ_SPARE_PREG 0x096 99 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 100 #define SIERRA_CTLELUT_CTRL_PREG 0x098 101 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 102 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 103 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 104 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 105 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 106 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 107 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 108 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 109 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 110 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 111 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 112 #define SIERRA_DEQ_GLUT0 0x0E8 113 #define SIERRA_DEQ_GLUT1 0x0E9 114 #define SIERRA_DEQ_GLUT2 0x0EA 115 #define SIERRA_DEQ_GLUT3 0x0EB 116 #define SIERRA_DEQ_GLUT4 0x0EC 117 #define SIERRA_DEQ_GLUT5 0x0ED 118 #define SIERRA_DEQ_GLUT6 0x0EE 119 #define SIERRA_DEQ_GLUT7 0x0EF 120 #define SIERRA_DEQ_GLUT8 0x0F0 121 #define SIERRA_DEQ_GLUT9 0x0F1 122 #define SIERRA_DEQ_GLUT10 0x0F2 123 #define SIERRA_DEQ_GLUT11 0x0F3 124 #define SIERRA_DEQ_GLUT12 0x0F4 125 #define SIERRA_DEQ_GLUT13 0x0F5 126 #define SIERRA_DEQ_GLUT14 0x0F6 127 #define SIERRA_DEQ_GLUT15 0x0F7 128 #define SIERRA_DEQ_GLUT16 0x0F8 129 #define SIERRA_DEQ_ALUT0 0x108 130 #define SIERRA_DEQ_ALUT1 0x109 131 #define SIERRA_DEQ_ALUT2 0x10A 132 #define SIERRA_DEQ_ALUT3 0x10B 133 #define SIERRA_DEQ_ALUT4 0x10C 134 #define SIERRA_DEQ_ALUT5 0x10D 135 #define SIERRA_DEQ_ALUT6 0x10E 136 #define SIERRA_DEQ_ALUT7 0x10F 137 #define SIERRA_DEQ_ALUT8 0x110 138 #define SIERRA_DEQ_ALUT9 0x111 139 #define SIERRA_DEQ_ALUT10 0x112 140 #define SIERRA_DEQ_ALUT11 0x113 141 #define SIERRA_DEQ_ALUT12 0x114 142 #define SIERRA_DEQ_ALUT13 0x115 143 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 144 #define SIERRA_DEQ_DFETAP0 0x129 145 #define SIERRA_DEQ_DFETAP1 0x12B 146 #define SIERRA_DEQ_DFETAP2 0x12D 147 #define SIERRA_DEQ_DFETAP3 0x12F 148 #define SIERRA_DEQ_DFETAP4 0x131 149 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 150 #define SIERRA_DEQ_PRECUR_PREG 0x138 151 #define SIERRA_DEQ_POSTCUR_PREG 0x140 152 #define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142 153 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 154 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 155 #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 156 #define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158 157 #define SIERRA_DEQ_PICTRL_PREG 0x161 158 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 159 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 160 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 161 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 162 #define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E 163 #define SIERRA_CPI_TRIM_PREG 0x17F 164 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 165 #define SIERRA_EPI_CTRL_PREG 0x187 166 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 167 #define SIERRA_LFPSFILT_NS_PREG 0x18A 168 #define SIERRA_LFPSFILT_RD_PREG 0x18B 169 #define SIERRA_LFPSFILT_MP_PREG 0x18C 170 #define SIERRA_SIGDET_SUPPORT_PREG 0x190 171 #define SIERRA_SDFILT_H2L_A_PREG 0x191 172 #define SIERRA_SDFILT_L2H_PREG 0x193 173 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 174 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 175 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 176 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 177 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 178 179 /* PHY PCS common registers */ 180 #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) \ 181 (0xc000 << (block_offset)) 182 #define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 183 #define SIERRA_PHY_PLL_CFG 0xe 184 185 /* PHY PCS lane registers */ 186 #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 187 ((0xD000 << (block_offset)) + \ 188 (((ln) << 8) << (reg_offset))) 189 190 #define SIERRA_PHY_ISO_LINK_CTRL 0xB 191 192 /* PHY PMA common registers */ 193 #define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset) \ 194 (0xE000 << (block_offset)) 195 #define SIERRA_PHY_PMA_CMN_CTRL 0x000 196 197 /* PHY PMA lane registers */ 198 #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 199 ((0xF000 << (block_offset)) + \ 200 (((ln) << 8) << (reg_offset))) 201 202 #define SIERRA_PHY_PMA_XCVR_CTRL 0x000 203 204 #define SIERRA_MACRO_ID 0x00007364 205 #define SIERRA_MAX_LANES 16 206 #define PLL_LOCK_TIME 100000 207 208 #define CDNS_SIERRA_OUTPUT_CLOCKS 3 209 #define CDNS_SIERRA_INPUT_CLOCKS 5 210 enum cdns_sierra_clock_input { 211 PHY_CLK, 212 CMN_REFCLK_DIG_DIV, 213 CMN_REFCLK1_DIG_DIV, 214 PLL0_REFCLK, 215 PLL1_REFCLK, 216 }; 217 218 #define SIERRA_NUM_CMN_PLLC 2 219 #define SIERRA_NUM_CMN_PLLC_PARENTS 2 220 221 static const struct reg_field macro_id_type = 222 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 223 static const struct reg_field phy_pll_cfg_1 = 224 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 225 static const struct reg_field pma_cmn_ready = 226 REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0); 227 static const struct reg_field pllctrl_lock = 228 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 229 static const struct reg_field phy_iso_link_ctrl_1 = 230 REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); 231 static const struct reg_field cmn_plllc_clk1outdiv_preg = 232 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6); 233 static const struct reg_field cmn_plllc_clk1_en_preg = 234 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12); 235 236 static const char * const clk_names[] = { 237 [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", 238 [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", 239 [CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der", 240 }; 241 242 enum cdns_sierra_cmn_plllc { 243 CMN_PLLLC, 244 CMN_PLLLC1, 245 }; 246 247 struct cdns_sierra_pll_mux_reg_fields { 248 struct reg_field pfdclk_sel_preg; 249 struct reg_field plllc1en_field; 250 struct reg_field termen_field; 251 }; 252 253 static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { 254 [CMN_PLLLC] = { 255 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), 256 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), 257 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), 258 }, 259 [CMN_PLLLC1] = { 260 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), 261 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), 262 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), 263 }, 264 }; 265 266 struct cdns_sierra_pll_mux { 267 struct clk_hw hw; 268 struct regmap_field *pfdclk_sel_preg; 269 struct regmap_field *plllc1en_field; 270 struct regmap_field *termen_field; 271 struct clk_init_data clk_data; 272 }; 273 274 #define to_cdns_sierra_pll_mux(_hw) \ 275 container_of(_hw, struct cdns_sierra_pll_mux, hw) 276 277 static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 278 [CMN_PLLLC] = { PLL0_REFCLK, PLL1_REFCLK }, 279 [CMN_PLLLC1] = { PLL1_REFCLK, PLL0_REFCLK }, 280 }; 281 282 static u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 283 [CMN_PLLLC] = { 0, 1 }, 284 [CMN_PLLLC1] = { 1, 0 }, 285 }; 286 287 struct cdns_sierra_derived_refclk { 288 struct clk_hw hw; 289 struct regmap_field *cmn_plllc_clk1outdiv_preg; 290 struct regmap_field *cmn_plllc_clk1_en_preg; 291 struct clk_init_data clk_data; 292 }; 293 294 #define to_cdns_sierra_derived_refclk(_hw) \ 295 container_of(_hw, struct cdns_sierra_derived_refclk, hw) 296 297 enum cdns_sierra_phy_type { 298 TYPE_NONE, 299 TYPE_PCIE, 300 TYPE_USB, 301 TYPE_QSGMII 302 }; 303 304 enum cdns_sierra_ssc_mode { 305 NO_SSC, 306 EXTERNAL_SSC, 307 INTERNAL_SSC 308 }; 309 310 struct cdns_sierra_inst { 311 struct phy *phy; 312 enum cdns_sierra_phy_type phy_type; 313 u32 num_lanes; 314 u32 mlane; 315 struct reset_control *lnk_rst; 316 enum cdns_sierra_ssc_mode ssc_mode; 317 }; 318 319 struct cdns_reg_pairs { 320 u16 val; 321 u32 off; 322 }; 323 324 struct cdns_sierra_vals { 325 const struct cdns_reg_pairs *reg_pairs; 326 u32 num_regs; 327 }; 328 329 struct cdns_sierra_data { 330 u32 id_value; 331 u8 block_offset_shift; 332 u8 reg_offset_shift; 333 struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 334 [NUM_SSC_MODE]; 335 struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 336 [NUM_SSC_MODE]; 337 struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 338 [NUM_SSC_MODE]; 339 struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 340 [NUM_SSC_MODE]; 341 }; 342 343 struct cdns_regmap_cdb_context { 344 struct device *dev; 345 void __iomem *base; 346 u8 reg_offset_shift; 347 }; 348 349 struct cdns_sierra_phy { 350 struct device *dev; 351 struct regmap *regmap; 352 const struct cdns_sierra_data *init_data; 353 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 354 struct reset_control *phy_rst; 355 struct reset_control *apb_rst; 356 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 357 struct regmap *regmap_phy_pcs_common_cdb; 358 struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES]; 359 struct regmap *regmap_phy_pma_common_cdb; 360 struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES]; 361 struct regmap *regmap_common_cdb; 362 struct regmap_field *macro_id_type; 363 struct regmap_field *phy_pll_cfg_1; 364 struct regmap_field *pma_cmn_ready; 365 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 366 struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES]; 367 struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; 368 struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; 369 struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; 370 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; 371 int nsubnodes; 372 u32 num_lanes; 373 bool autoconf; 374 int already_configured; 375 struct clk_onecell_data clk_data; 376 struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS]; 377 }; 378 379 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 380 { 381 struct cdns_regmap_cdb_context *ctx = context; 382 u32 offset = reg << ctx->reg_offset_shift; 383 384 writew(val, ctx->base + offset); 385 386 return 0; 387 } 388 389 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 390 { 391 struct cdns_regmap_cdb_context *ctx = context; 392 u32 offset = reg << ctx->reg_offset_shift; 393 394 *val = readw(ctx->base + offset); 395 return 0; 396 } 397 398 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 399 { \ 400 .name = "sierra_lane" n "_cdb", \ 401 .reg_stride = 1, \ 402 .fast_io = true, \ 403 .reg_write = cdns_regmap_write, \ 404 .reg_read = cdns_regmap_read, \ 405 } 406 407 static const struct regmap_config cdns_sierra_lane_cdb_config[] = { 408 SIERRA_LANE_CDB_REGMAP_CONF("0"), 409 SIERRA_LANE_CDB_REGMAP_CONF("1"), 410 SIERRA_LANE_CDB_REGMAP_CONF("2"), 411 SIERRA_LANE_CDB_REGMAP_CONF("3"), 412 SIERRA_LANE_CDB_REGMAP_CONF("4"), 413 SIERRA_LANE_CDB_REGMAP_CONF("5"), 414 SIERRA_LANE_CDB_REGMAP_CONF("6"), 415 SIERRA_LANE_CDB_REGMAP_CONF("7"), 416 SIERRA_LANE_CDB_REGMAP_CONF("8"), 417 SIERRA_LANE_CDB_REGMAP_CONF("9"), 418 SIERRA_LANE_CDB_REGMAP_CONF("10"), 419 SIERRA_LANE_CDB_REGMAP_CONF("11"), 420 SIERRA_LANE_CDB_REGMAP_CONF("12"), 421 SIERRA_LANE_CDB_REGMAP_CONF("13"), 422 SIERRA_LANE_CDB_REGMAP_CONF("14"), 423 SIERRA_LANE_CDB_REGMAP_CONF("15"), 424 }; 425 426 static const struct regmap_config cdns_sierra_common_cdb_config = { 427 .name = "sierra_common_cdb", 428 .reg_stride = 1, 429 .fast_io = true, 430 .reg_write = cdns_regmap_write, 431 .reg_read = cdns_regmap_read, 432 }; 433 434 static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = { 435 .name = "sierra_phy_pcs_cmn_cdb", 436 .reg_stride = 1, 437 .fast_io = true, 438 .reg_write = cdns_regmap_write, 439 .reg_read = cdns_regmap_read, 440 }; 441 442 #define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 443 { \ 444 .name = "sierra_phy_pcs_lane" n "_cdb", \ 445 .reg_stride = 1, \ 446 .fast_io = true, \ 447 .reg_write = cdns_regmap_write, \ 448 .reg_read = cdns_regmap_read, \ 449 } 450 451 static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = { 452 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 453 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 454 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 455 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 456 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"), 457 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"), 458 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"), 459 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"), 460 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"), 461 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"), 462 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"), 463 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"), 464 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"), 465 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"), 466 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"), 467 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"), 468 }; 469 470 static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = { 471 .name = "sierra_phy_pma_cmn_cdb", 472 .reg_stride = 1, 473 .fast_io = true, 474 .reg_write = cdns_regmap_write, 475 .reg_read = cdns_regmap_read, 476 }; 477 478 #define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \ 479 { \ 480 .name = "sierra_phy_pma_lane" n "_cdb", \ 481 .reg_stride = 1, \ 482 .fast_io = true, \ 483 .reg_write = cdns_regmap_write, \ 484 .reg_read = cdns_regmap_read, \ 485 } 486 487 static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = { 488 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"), 489 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"), 490 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"), 491 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"), 492 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"), 493 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"), 494 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"), 495 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"), 496 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"), 497 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"), 498 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"), 499 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"), 500 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"), 501 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"), 502 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"), 503 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"), 504 }; 505 506 static int cdns_sierra_phy_init(struct phy *gphy) 507 { 508 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 509 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 510 const struct cdns_sierra_data *init_data = phy->init_data; 511 struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 512 enum cdns_sierra_phy_type phy_type = ins->phy_type; 513 enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; 514 struct cdns_sierra_vals *phy_pma_ln_vals; 515 const struct cdns_reg_pairs *reg_pairs; 516 struct cdns_sierra_vals *pcs_cmn_vals; 517 struct regmap *regmap; 518 u32 num_regs; 519 int i, j; 520 521 /* Initialise the PHY registers, unless auto configured */ 522 if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1) 523 return 0; 524 525 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 526 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 527 528 /* PHY PCS common registers configurations */ 529 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; 530 if (pcs_cmn_vals) { 531 reg_pairs = pcs_cmn_vals->reg_pairs; 532 num_regs = pcs_cmn_vals->num_regs; 533 regmap = phy->regmap_phy_pcs_common_cdb; 534 for (i = 0; i < num_regs; i++) 535 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 536 } 537 538 /* PHY PMA lane registers configurations */ 539 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; 540 if (phy_pma_ln_vals) { 541 reg_pairs = phy_pma_ln_vals->reg_pairs; 542 num_regs = phy_pma_ln_vals->num_regs; 543 for (i = 0; i < ins->num_lanes; i++) { 544 regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane]; 545 for (j = 0; j < num_regs; j++) 546 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 547 } 548 } 549 550 /* PMA common registers configurations */ 551 pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; 552 if (pma_cmn_vals) { 553 reg_pairs = pma_cmn_vals->reg_pairs; 554 num_regs = pma_cmn_vals->num_regs; 555 regmap = phy->regmap_common_cdb; 556 for (i = 0; i < num_regs; i++) 557 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 558 } 559 560 /* PMA lane registers configurations */ 561 pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; 562 if (pma_ln_vals) { 563 reg_pairs = pma_ln_vals->reg_pairs; 564 num_regs = pma_ln_vals->num_regs; 565 for (i = 0; i < ins->num_lanes; i++) { 566 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 567 for (j = 0; j < num_regs; j++) 568 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 569 } 570 } 571 572 return 0; 573 } 574 575 static int cdns_sierra_phy_on(struct phy *gphy) 576 { 577 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 578 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 579 struct device *dev = sp->dev; 580 u32 val; 581 int ret; 582 583 if (sp->nsubnodes == 1) { 584 /* Take the PHY out of reset */ 585 ret = reset_control_deassert(sp->phy_rst); 586 if (ret) { 587 dev_err(dev, "Failed to take the PHY out of reset\n"); 588 return ret; 589 } 590 } 591 592 /* Take the PHY lane group out of reset */ 593 ret = reset_control_deassert(ins->lnk_rst); 594 if (ret) { 595 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 596 return ret; 597 } 598 599 if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) { 600 ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane], 601 val, !val, 1000, PLL_LOCK_TIME); 602 if (ret) { 603 dev_err(dev, "Timeout waiting for PHY status ready\n"); 604 return ret; 605 } 606 } 607 608 /* 609 * Wait for cmn_ready assertion 610 * PHY_PMA_CMN_CTRL[0] == 1 611 */ 612 ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val, 613 1000, PLL_LOCK_TIME); 614 if (ret) { 615 dev_err(dev, "Timeout waiting for CMN ready\n"); 616 return ret; 617 } 618 619 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 620 val, val, 1000, PLL_LOCK_TIME); 621 if (ret < 0) 622 dev_err(dev, "PLL lock of lane failed\n"); 623 624 return ret; 625 } 626 627 static int cdns_sierra_phy_off(struct phy *gphy) 628 { 629 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 630 631 return reset_control_assert(ins->lnk_rst); 632 } 633 634 static int cdns_sierra_phy_reset(struct phy *gphy) 635 { 636 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 637 638 reset_control_assert(sp->phy_rst); 639 reset_control_deassert(sp->phy_rst); 640 return 0; 641 }; 642 643 static const struct phy_ops ops = { 644 .init = cdns_sierra_phy_init, 645 .power_on = cdns_sierra_phy_on, 646 .power_off = cdns_sierra_phy_off, 647 .reset = cdns_sierra_phy_reset, 648 .owner = THIS_MODULE, 649 }; 650 651 static int cdns_sierra_noop_phy_on(struct phy *gphy) 652 { 653 usleep_range(5000, 10000); 654 655 return 0; 656 } 657 658 static const struct phy_ops noop_ops = { 659 .power_on = cdns_sierra_noop_phy_on, 660 .owner = THIS_MODULE, 661 }; 662 663 static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) 664 { 665 struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); 666 struct regmap_field *plllc1en_field = mux->plllc1en_field; 667 struct regmap_field *termen_field = mux->termen_field; 668 struct regmap_field *field = mux->pfdclk_sel_preg; 669 unsigned int val; 670 int index; 671 672 regmap_field_read(field, &val); 673 674 if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) { 675 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val); 676 if (index == 1) { 677 regmap_field_write(plllc1en_field, 1); 678 regmap_field_write(termen_field, 1); 679 } 680 } else { 681 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val); 682 } 683 684 return index; 685 } 686 687 static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) 688 { 689 struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); 690 struct regmap_field *plllc1en_field = mux->plllc1en_field; 691 struct regmap_field *termen_field = mux->termen_field; 692 struct regmap_field *field = mux->pfdclk_sel_preg; 693 int val, ret; 694 695 ret = regmap_field_write(plllc1en_field, 0); 696 ret |= regmap_field_write(termen_field, 0); 697 if (index == 1) { 698 ret |= regmap_field_write(plllc1en_field, 1); 699 ret |= regmap_field_write(termen_field, 1); 700 } 701 702 if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) 703 val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index]; 704 else 705 val = cdns_sierra_pll_mux_table[CMN_PLLLC][index]; 706 707 ret |= regmap_field_write(field, val); 708 709 return ret; 710 } 711 712 static const struct clk_ops cdns_sierra_pll_mux_ops = { 713 .set_parent = cdns_sierra_pll_mux_set_parent, 714 .get_parent = cdns_sierra_pll_mux_get_parent, 715 }; 716 717 static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, 718 struct regmap_field *pfdclk1_sel_field, 719 struct regmap_field *plllc1en_field, 720 struct regmap_field *termen_field, 721 int clk_index) 722 { 723 struct cdns_sierra_pll_mux *mux; 724 struct device *dev = sp->dev; 725 struct clk_init_data *init; 726 const char **parent_names; 727 unsigned int num_parents; 728 char clk_name[100]; 729 struct clk *clk; 730 int i; 731 732 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 733 if (!mux) 734 return -ENOMEM; 735 736 num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; 737 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); 738 if (!parent_names) 739 return -ENOMEM; 740 741 for (i = 0; i < num_parents; i++) { 742 clk = sp->input_clks[pll_mux_parent_index[clk_index][i]]; 743 if (IS_ERR_OR_NULL(clk)) { 744 dev_err(dev, "No parent clock for PLL mux clocks\n"); 745 return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT; 746 } 747 parent_names[i] = __clk_get_name(clk); 748 } 749 750 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]); 751 752 init = &mux->clk_data; 753 754 init->ops = &cdns_sierra_pll_mux_ops; 755 init->flags = CLK_SET_RATE_NO_REPARENT; 756 init->parent_names = parent_names; 757 init->num_parents = num_parents; 758 init->name = clk_name; 759 760 mux->pfdclk_sel_preg = pfdclk1_sel_field; 761 mux->plllc1en_field = plllc1en_field; 762 mux->termen_field = termen_field; 763 mux->hw.init = init; 764 765 clk = devm_clk_register(dev, &mux->hw); 766 if (IS_ERR(clk)) 767 return PTR_ERR(clk); 768 769 sp->output_clks[clk_index] = clk; 770 771 return 0; 772 } 773 774 static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) 775 { 776 struct regmap_field *pfdclk1_sel_field; 777 struct regmap_field *plllc1en_field; 778 struct regmap_field *termen_field; 779 struct device *dev = sp->dev; 780 int ret = 0, i, clk_index; 781 782 clk_index = CDNS_SIERRA_PLL_CMNLC; 783 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { 784 pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; 785 plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; 786 termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; 787 788 ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field, 789 termen_field, clk_index); 790 if (ret) { 791 dev_err(dev, "Fail to register cmn plllc mux\n"); 792 return ret; 793 } 794 } 795 796 return 0; 797 } 798 799 static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw) 800 { 801 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 802 803 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1); 804 805 /* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */ 806 regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E); 807 808 return 0; 809 } 810 811 static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw) 812 { 813 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 814 815 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0); 816 } 817 818 static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw) 819 { 820 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 821 int val; 822 823 regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val); 824 825 return !!val; 826 } 827 828 static const struct clk_ops cdns_sierra_derived_refclk_ops = { 829 .enable = cdns_sierra_derived_refclk_enable, 830 .disable = cdns_sierra_derived_refclk_disable, 831 .is_enabled = cdns_sierra_derived_refclk_is_enabled, 832 }; 833 834 static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp) 835 { 836 struct cdns_sierra_derived_refclk *derived_refclk; 837 struct device *dev = sp->dev; 838 struct regmap_field *field; 839 struct clk_init_data *init; 840 struct regmap *regmap; 841 char clk_name[100]; 842 struct clk *clk; 843 844 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 845 if (!derived_refclk) 846 return -ENOMEM; 847 848 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 849 clk_names[CDNS_SIERRA_DERIVED_REFCLK]); 850 851 init = &derived_refclk->clk_data; 852 853 init->ops = &cdns_sierra_derived_refclk_ops; 854 init->flags = 0; 855 init->name = clk_name; 856 857 regmap = sp->regmap_common_cdb; 858 859 field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg); 860 if (IS_ERR(field)) { 861 dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n"); 862 return PTR_ERR(field); 863 } 864 derived_refclk->cmn_plllc_clk1outdiv_preg = field; 865 866 field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg); 867 if (IS_ERR(field)) { 868 dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n"); 869 return PTR_ERR(field); 870 } 871 derived_refclk->cmn_plllc_clk1_en_preg = field; 872 873 derived_refclk->hw.init = init; 874 875 clk = devm_clk_register(dev, &derived_refclk->hw); 876 if (IS_ERR(clk)) 877 return PTR_ERR(clk); 878 879 sp->output_clks[CDNS_SIERRA_DERIVED_REFCLK] = clk; 880 881 return 0; 882 } 883 884 static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) 885 { 886 struct device *dev = sp->dev; 887 struct device_node *node = dev->of_node; 888 889 of_clk_del_provider(node); 890 } 891 892 static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) 893 { 894 struct device *dev = sp->dev; 895 struct device_node *node = dev->of_node; 896 int ret; 897 898 ret = cdns_sierra_phy_register_pll_mux(sp); 899 if (ret) { 900 dev_err(dev, "Failed to pll mux clocks\n"); 901 return ret; 902 } 903 904 ret = cdns_sierra_derived_refclk_register(sp); 905 if (ret) { 906 dev_err(dev, "Failed to register derived refclk\n"); 907 return ret; 908 } 909 910 sp->clk_data.clks = sp->output_clks; 911 sp->clk_data.clk_num = CDNS_SIERRA_OUTPUT_CLOCKS; 912 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &sp->clk_data); 913 if (ret) 914 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 915 916 return ret; 917 } 918 919 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 920 struct device_node *child) 921 { 922 u32 phy_type; 923 924 if (of_property_read_u32(child, "reg", &inst->mlane)) 925 return -EINVAL; 926 927 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 928 return -EINVAL; 929 930 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) 931 return -EINVAL; 932 933 switch (phy_type) { 934 case PHY_TYPE_PCIE: 935 inst->phy_type = TYPE_PCIE; 936 break; 937 case PHY_TYPE_USB3: 938 inst->phy_type = TYPE_USB; 939 break; 940 case PHY_TYPE_QSGMII: 941 inst->phy_type = TYPE_QSGMII; 942 break; 943 default: 944 return -EINVAL; 945 } 946 947 inst->ssc_mode = EXTERNAL_SSC; 948 of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode); 949 950 return 0; 951 } 952 953 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 954 u32 block_offset, u8 reg_offset_shift, 955 const struct regmap_config *config) 956 { 957 struct cdns_regmap_cdb_context *ctx; 958 959 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 960 if (!ctx) 961 return ERR_PTR(-ENOMEM); 962 963 ctx->dev = dev; 964 ctx->base = base + block_offset; 965 ctx->reg_offset_shift = reg_offset_shift; 966 967 return devm_regmap_init(dev, NULL, ctx, config); 968 } 969 970 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 971 { 972 struct device *dev = sp->dev; 973 struct regmap_field *field; 974 struct reg_field reg_field; 975 struct regmap *regmap; 976 int i; 977 978 regmap = sp->regmap_common_cdb; 979 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 980 if (IS_ERR(field)) { 981 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 982 return PTR_ERR(field); 983 } 984 sp->macro_id_type = field; 985 986 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { 987 reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; 988 field = devm_regmap_field_alloc(dev, regmap, reg_field); 989 if (IS_ERR(field)) { 990 dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); 991 return PTR_ERR(field); 992 } 993 sp->cmn_plllc_pfdclk1_sel_preg[i] = field; 994 995 reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; 996 field = devm_regmap_field_alloc(dev, regmap, reg_field); 997 if (IS_ERR(field)) { 998 dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); 999 return PTR_ERR(field); 1000 } 1001 sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; 1002 1003 reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; 1004 field = devm_regmap_field_alloc(dev, regmap, reg_field); 1005 if (IS_ERR(field)) { 1006 dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); 1007 return PTR_ERR(field); 1008 } 1009 sp->cmn_refrcv_refclk_termen_preg[i] = field; 1010 } 1011 1012 regmap = sp->regmap_phy_pcs_common_cdb; 1013 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 1014 if (IS_ERR(field)) { 1015 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 1016 return PTR_ERR(field); 1017 } 1018 sp->phy_pll_cfg_1 = field; 1019 1020 regmap = sp->regmap_phy_pma_common_cdb; 1021 field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready); 1022 if (IS_ERR(field)) { 1023 dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n"); 1024 return PTR_ERR(field); 1025 } 1026 sp->pma_cmn_ready = field; 1027 1028 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1029 regmap = sp->regmap_lane_cdb[i]; 1030 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 1031 if (IS_ERR(field)) { 1032 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 1033 return PTR_ERR(field); 1034 } 1035 sp->pllctrl_lock[i] = field; 1036 } 1037 1038 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1039 regmap = sp->regmap_phy_pcs_lane_cdb[i]; 1040 field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1); 1041 if (IS_ERR(field)) { 1042 dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i); 1043 return PTR_ERR(field); 1044 } 1045 sp->phy_iso_link_ctrl_1[i] = field; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 1052 void __iomem *base, u8 block_offset_shift, 1053 u8 reg_offset_shift) 1054 { 1055 struct device *dev = sp->dev; 1056 struct regmap *regmap; 1057 u32 block_offset; 1058 int i; 1059 1060 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1061 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 1062 reg_offset_shift); 1063 regmap = cdns_regmap_init(dev, base, block_offset, 1064 reg_offset_shift, 1065 &cdns_sierra_lane_cdb_config[i]); 1066 if (IS_ERR(regmap)) { 1067 dev_err(dev, "Failed to init lane CDB regmap\n"); 1068 return PTR_ERR(regmap); 1069 } 1070 sp->regmap_lane_cdb[i] = regmap; 1071 } 1072 1073 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 1074 reg_offset_shift, 1075 &cdns_sierra_common_cdb_config); 1076 if (IS_ERR(regmap)) { 1077 dev_err(dev, "Failed to init common CDB regmap\n"); 1078 return PTR_ERR(regmap); 1079 } 1080 sp->regmap_common_cdb = regmap; 1081 1082 block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift); 1083 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 1084 &cdns_sierra_phy_pcs_cmn_cdb_config); 1085 if (IS_ERR(regmap)) { 1086 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 1087 return PTR_ERR(regmap); 1088 } 1089 sp->regmap_phy_pcs_common_cdb = regmap; 1090 1091 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1092 block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 1093 reg_offset_shift); 1094 regmap = cdns_regmap_init(dev, base, block_offset, 1095 reg_offset_shift, 1096 &cdns_sierra_phy_pcs_lane_cdb_config[i]); 1097 if (IS_ERR(regmap)) { 1098 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 1099 return PTR_ERR(regmap); 1100 } 1101 sp->regmap_phy_pcs_lane_cdb[i] = regmap; 1102 } 1103 1104 block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift); 1105 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 1106 &cdns_sierra_phy_pma_cmn_cdb_config); 1107 if (IS_ERR(regmap)) { 1108 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 1109 return PTR_ERR(regmap); 1110 } 1111 sp->regmap_phy_pma_common_cdb = regmap; 1112 1113 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1114 block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift, 1115 reg_offset_shift); 1116 regmap = cdns_regmap_init(dev, base, block_offset, 1117 reg_offset_shift, 1118 &cdns_sierra_phy_pma_lane_cdb_config[i]); 1119 if (IS_ERR(regmap)) { 1120 dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n"); 1121 return PTR_ERR(regmap); 1122 } 1123 sp->regmap_phy_pma_lane_cdb[i] = regmap; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 1130 struct device *dev) 1131 { 1132 struct clk *clk; 1133 int ret; 1134 1135 clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); 1136 if (IS_ERR(clk)) { 1137 dev_err(dev, "cmn_refclk_dig_div clock not found\n"); 1138 ret = PTR_ERR(clk); 1139 return ret; 1140 } 1141 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; 1142 1143 clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); 1144 if (IS_ERR(clk)) { 1145 dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); 1146 ret = PTR_ERR(clk); 1147 return ret; 1148 } 1149 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; 1150 1151 clk = devm_clk_get_optional(dev, "pll0_refclk"); 1152 if (IS_ERR(clk)) { 1153 dev_err(dev, "pll0_refclk clock not found\n"); 1154 ret = PTR_ERR(clk); 1155 return ret; 1156 } 1157 sp->input_clks[PLL0_REFCLK] = clk; 1158 1159 clk = devm_clk_get_optional(dev, "pll1_refclk"); 1160 if (IS_ERR(clk)) { 1161 dev_err(dev, "pll1_refclk clock not found\n"); 1162 ret = PTR_ERR(clk); 1163 return ret; 1164 } 1165 sp->input_clks[PLL1_REFCLK] = clk; 1166 1167 return 0; 1168 } 1169 1170 static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) 1171 { 1172 struct device *dev = sp->dev; 1173 struct clk *clk; 1174 int ret; 1175 1176 clk = devm_clk_get_optional(dev, "phy_clk"); 1177 if (IS_ERR(clk)) { 1178 dev_err(dev, "failed to get clock phy_clk\n"); 1179 return PTR_ERR(clk); 1180 } 1181 sp->input_clks[PHY_CLK] = clk; 1182 1183 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); 1184 if (ret) 1185 return ret; 1186 1187 return 0; 1188 } 1189 1190 static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) 1191 { 1192 int ret; 1193 1194 ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); 1195 if (ret) 1196 return ret; 1197 1198 ret = clk_prepare_enable(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); 1199 if (ret) 1200 goto err_pll_cmnlc1; 1201 1202 return 0; 1203 1204 err_pll_cmnlc1: 1205 clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); 1206 1207 return ret; 1208 } 1209 1210 static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) 1211 { 1212 clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC1]); 1213 clk_disable_unprepare(sp->output_clks[CDNS_SIERRA_PLL_CMNLC]); 1214 if (!sp->already_configured) 1215 clk_disable_unprepare(sp->input_clks[PHY_CLK]); 1216 } 1217 1218 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, 1219 struct device *dev) 1220 { 1221 struct reset_control *rst; 1222 1223 rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); 1224 if (IS_ERR(rst)) { 1225 dev_err(dev, "failed to get reset\n"); 1226 return PTR_ERR(rst); 1227 } 1228 sp->phy_rst = rst; 1229 1230 rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); 1231 if (IS_ERR(rst)) { 1232 dev_err(dev, "failed to get apb reset\n"); 1233 return PTR_ERR(rst); 1234 } 1235 sp->apb_rst = rst; 1236 1237 return 0; 1238 } 1239 1240 static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) 1241 { 1242 const struct cdns_sierra_data *init_data = sp->init_data; 1243 struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 1244 enum cdns_sierra_phy_type phy_t1, phy_t2; 1245 struct cdns_sierra_vals *phy_pma_ln_vals; 1246 const struct cdns_reg_pairs *reg_pairs; 1247 struct cdns_sierra_vals *pcs_cmn_vals; 1248 int i, j, node, mlane, num_lanes, ret; 1249 enum cdns_sierra_ssc_mode ssc; 1250 struct regmap *regmap; 1251 u32 num_regs; 1252 1253 /* Maximum 2 links (subnodes) are supported */ 1254 if (sp->nsubnodes != 2) 1255 return -EINVAL; 1256 1257 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 1258 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 1259 1260 /* PHY configured to use both PLL LC and LC1 */ 1261 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 1262 1263 phy_t1 = sp->phys[0].phy_type; 1264 phy_t2 = sp->phys[1].phy_type; 1265 1266 /* 1267 * PHY configuration for multi-link operation is done in two steps. 1268 * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. 1269 * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe 1270 * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. 1271 * 1272 * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII 1273 * So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. 1274 * This will configure PHY registers associated for PCIe (i.e. first protocol) 1275 * involving PLLLC registers and registers for first 2 lanes of PHY. 1276 * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now, 1277 * phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as 1278 * [TYPE_QSGMII][TYPE_PCIE][ssc]. 1279 * This will configure PHY registers associated for QSGMII (i.e. second protocol) 1280 * involving PLLLC1 registers and registers for other 2 lanes of PHY. 1281 * 1282 * This completes the PHY configuration for multilink operation. This approach enables 1283 * dividing the large number of PHY register configurations into protocol specific 1284 * smaller groups. 1285 */ 1286 for (node = 0; node < sp->nsubnodes; node++) { 1287 if (node == 1) { 1288 /* 1289 * If first link with phy_t1 is configured, then configure the PHY for 1290 * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc]. 1291 */ 1292 swap(phy_t1, phy_t2); 1293 } 1294 1295 mlane = sp->phys[node].mlane; 1296 ssc = sp->phys[node].ssc_mode; 1297 num_lanes = sp->phys[node].num_lanes; 1298 1299 /* PHY PCS common registers configurations */ 1300 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; 1301 if (pcs_cmn_vals) { 1302 reg_pairs = pcs_cmn_vals->reg_pairs; 1303 num_regs = pcs_cmn_vals->num_regs; 1304 regmap = sp->regmap_phy_pcs_common_cdb; 1305 for (i = 0; i < num_regs; i++) 1306 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 1307 } 1308 1309 /* PHY PMA lane registers configurations */ 1310 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; 1311 if (phy_pma_ln_vals) { 1312 reg_pairs = phy_pma_ln_vals->reg_pairs; 1313 num_regs = phy_pma_ln_vals->num_regs; 1314 for (i = 0; i < num_lanes; i++) { 1315 regmap = sp->regmap_phy_pma_lane_cdb[i + mlane]; 1316 for (j = 0; j < num_regs; j++) 1317 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 1318 } 1319 } 1320 1321 /* PMA common registers configurations */ 1322 pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; 1323 if (pma_cmn_vals) { 1324 reg_pairs = pma_cmn_vals->reg_pairs; 1325 num_regs = pma_cmn_vals->num_regs; 1326 regmap = sp->regmap_common_cdb; 1327 for (i = 0; i < num_regs; i++) 1328 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 1329 } 1330 1331 /* PMA lane registers configurations */ 1332 pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc]; 1333 if (pma_ln_vals) { 1334 reg_pairs = pma_ln_vals->reg_pairs; 1335 num_regs = pma_ln_vals->num_regs; 1336 for (i = 0; i < num_lanes; i++) { 1337 regmap = sp->regmap_lane_cdb[i + mlane]; 1338 for (j = 0; j < num_regs; j++) 1339 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 1340 } 1341 } 1342 1343 if (phy_t1 == TYPE_QSGMII) 1344 reset_control_deassert(sp->phys[node].lnk_rst); 1345 } 1346 1347 /* Take the PHY out of reset */ 1348 ret = reset_control_deassert(sp->phy_rst); 1349 if (ret) 1350 return ret; 1351 1352 return 0; 1353 } 1354 1355 static int cdns_sierra_phy_probe(struct platform_device *pdev) 1356 { 1357 struct cdns_sierra_phy *sp; 1358 struct phy_provider *phy_provider; 1359 struct device *dev = &pdev->dev; 1360 const struct cdns_sierra_data *data; 1361 unsigned int id_value; 1362 int ret, node = 0; 1363 void __iomem *base; 1364 struct device_node *dn = dev->of_node, *child; 1365 1366 if (of_get_child_count(dn) == 0) 1367 return -ENODEV; 1368 1369 /* Get init data for this PHY */ 1370 data = of_device_get_match_data(dev); 1371 if (!data) 1372 return -EINVAL; 1373 1374 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 1375 if (!sp) 1376 return -ENOMEM; 1377 dev_set_drvdata(dev, sp); 1378 sp->dev = dev; 1379 sp->init_data = data; 1380 1381 base = devm_platform_ioremap_resource(pdev, 0); 1382 if (IS_ERR(base)) { 1383 dev_err(dev, "missing \"reg\"\n"); 1384 return PTR_ERR(base); 1385 } 1386 1387 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 1388 data->reg_offset_shift); 1389 if (ret) 1390 return ret; 1391 1392 ret = cdns_regfield_init(sp); 1393 if (ret) 1394 return ret; 1395 1396 platform_set_drvdata(pdev, sp); 1397 1398 ret = cdns_sierra_phy_get_clocks(sp, dev); 1399 if (ret) 1400 return ret; 1401 1402 ret = cdns_sierra_clk_register(sp); 1403 if (ret) 1404 return ret; 1405 1406 ret = cdns_sierra_phy_enable_clocks(sp); 1407 if (ret) 1408 goto unregister_clk; 1409 1410 regmap_field_read(sp->pma_cmn_ready, &sp->already_configured); 1411 1412 if (!sp->already_configured) { 1413 ret = cdns_sierra_phy_clk(sp); 1414 if (ret) 1415 goto clk_disable; 1416 1417 ret = cdns_sierra_phy_get_resets(sp, dev); 1418 if (ret) 1419 goto clk_disable; 1420 1421 /* Enable APB */ 1422 reset_control_deassert(sp->apb_rst); 1423 } 1424 1425 /* Check that PHY is present */ 1426 regmap_field_read(sp->macro_id_type, &id_value); 1427 if (sp->init_data->id_value != id_value) { 1428 ret = -EINVAL; 1429 goto ctrl_assert; 1430 } 1431 1432 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 1433 1434 for_each_available_child_of_node(dn, child) { 1435 struct phy *gphy; 1436 1437 if (!(of_node_name_eq(child, "phy") || 1438 of_node_name_eq(child, "link"))) 1439 continue; 1440 1441 sp->phys[node].lnk_rst = 1442 of_reset_control_array_get_exclusive(child); 1443 1444 if (IS_ERR(sp->phys[node].lnk_rst)) { 1445 dev_err(dev, "failed to get reset %s\n", 1446 child->full_name); 1447 ret = PTR_ERR(sp->phys[node].lnk_rst); 1448 of_node_put(child); 1449 goto put_control; 1450 } 1451 1452 if (!sp->autoconf) { 1453 ret = cdns_sierra_get_optional(&sp->phys[node], child); 1454 if (ret) { 1455 dev_err(dev, "missing property in node %s\n", 1456 child->name); 1457 of_node_put(child); 1458 reset_control_put(sp->phys[node].lnk_rst); 1459 goto put_control; 1460 } 1461 } 1462 1463 sp->num_lanes += sp->phys[node].num_lanes; 1464 1465 if (!sp->already_configured) 1466 gphy = devm_phy_create(dev, child, &ops); 1467 else 1468 gphy = devm_phy_create(dev, child, &noop_ops); 1469 if (IS_ERR(gphy)) { 1470 ret = PTR_ERR(gphy); 1471 of_node_put(child); 1472 reset_control_put(sp->phys[node].lnk_rst); 1473 goto put_control; 1474 } 1475 sp->phys[node].phy = gphy; 1476 phy_set_drvdata(gphy, &sp->phys[node]); 1477 1478 node++; 1479 } 1480 sp->nsubnodes = node; 1481 1482 if (sp->num_lanes > SIERRA_MAX_LANES) { 1483 ret = -EINVAL; 1484 dev_err(dev, "Invalid lane configuration\n"); 1485 goto put_control; 1486 } 1487 1488 /* If more than one subnode, configure the PHY as multilink */ 1489 if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) { 1490 ret = cdns_sierra_phy_configure_multilink(sp); 1491 if (ret) 1492 goto put_control; 1493 } 1494 1495 pm_runtime_enable(dev); 1496 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1497 if (IS_ERR(phy_provider)) { 1498 ret = PTR_ERR(phy_provider); 1499 goto put_control; 1500 } 1501 1502 return 0; 1503 1504 put_control: 1505 while (--node >= 0) 1506 reset_control_put(sp->phys[node].lnk_rst); 1507 ctrl_assert: 1508 if (!sp->already_configured) 1509 reset_control_assert(sp->apb_rst); 1510 clk_disable: 1511 cdns_sierra_phy_disable_clocks(sp); 1512 unregister_clk: 1513 cdns_sierra_clk_unregister(sp); 1514 return ret; 1515 } 1516 1517 static int cdns_sierra_phy_remove(struct platform_device *pdev) 1518 { 1519 struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); 1520 int i; 1521 1522 reset_control_assert(phy->phy_rst); 1523 reset_control_assert(phy->apb_rst); 1524 pm_runtime_disable(&pdev->dev); 1525 1526 cdns_sierra_phy_disable_clocks(phy); 1527 /* 1528 * The device level resets will be put automatically. 1529 * Need to put the subnode resets here though. 1530 */ 1531 for (i = 0; i < phy->nsubnodes; i++) { 1532 reset_control_assert(phy->phys[i].lnk_rst); 1533 reset_control_put(phy->phys[i].lnk_rst); 1534 } 1535 1536 cdns_sierra_clk_unregister(phy); 1537 1538 return 0; 1539 } 1540 1541 /* QSGMII PHY PMA lane configuration */ 1542 static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = { 1543 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} 1544 }; 1545 1546 static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = { 1547 .reg_pairs = qsgmii_phy_pma_ln_regs, 1548 .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs), 1549 }; 1550 1551 /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ 1552 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = { 1553 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1554 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1555 {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1556 }; 1557 1558 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = { 1559 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1560 {0x0252, SIERRA_DET_STANDEC_E_PREG}, 1561 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1562 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 1563 {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG}, 1564 {0x0001, SIERRA_PLLCTRL_GEN_A_PREG}, 1565 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1566 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1567 {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1568 {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1569 {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1570 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1571 {0x8422, SIERRA_CTLELUT_CTRL_PREG}, 1572 {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG}, 1573 {0x4111, SIERRA_DFE_SMP_RATESEL_PREG}, 1574 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1575 {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1576 {0x0186, SIERRA_DEQ_GLUT0}, 1577 {0x0186, SIERRA_DEQ_GLUT1}, 1578 {0x0186, SIERRA_DEQ_GLUT2}, 1579 {0x0186, SIERRA_DEQ_GLUT3}, 1580 {0x0186, SIERRA_DEQ_GLUT4}, 1581 {0x0861, SIERRA_DEQ_ALUT0}, 1582 {0x07E0, SIERRA_DEQ_ALUT1}, 1583 {0x079E, SIERRA_DEQ_ALUT2}, 1584 {0x071D, SIERRA_DEQ_ALUT3}, 1585 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1586 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1587 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1588 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, 1589 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1590 {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1591 {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1592 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, 1593 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1594 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} 1595 }; 1596 1597 static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = { 1598 .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs, 1599 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs), 1600 }; 1601 1602 static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = { 1603 .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs, 1604 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs), 1605 }; 1606 1607 /* PCIE PHY PCS common configuration */ 1608 static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { 1609 {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} 1610 }; 1611 1612 static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { 1613 .reg_pairs = pcie_phy_pcs_cmn_regs, 1614 .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), 1615 }; 1616 1617 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1618 static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = { 1619 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1620 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1621 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1622 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 1623 }; 1624 1625 /* 1626 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1627 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1628 */ 1629 static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { 1630 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1631 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1632 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1633 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1634 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1635 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1636 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1637 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1638 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1639 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1640 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1641 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1642 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1643 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1644 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1645 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1646 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1647 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1648 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1649 {0x0041, SIERRA_DEQ_GLUT0}, 1650 {0x0082, SIERRA_DEQ_GLUT1}, 1651 {0x00C3, SIERRA_DEQ_GLUT2}, 1652 {0x0145, SIERRA_DEQ_GLUT3}, 1653 {0x0186, SIERRA_DEQ_GLUT4}, 1654 {0x09E7, SIERRA_DEQ_ALUT0}, 1655 {0x09A6, SIERRA_DEQ_ALUT1}, 1656 {0x0965, SIERRA_DEQ_ALUT2}, 1657 {0x08E3, SIERRA_DEQ_ALUT3}, 1658 {0x00FA, SIERRA_DEQ_DFETAP0}, 1659 {0x00FA, SIERRA_DEQ_DFETAP1}, 1660 {0x00FA, SIERRA_DEQ_DFETAP2}, 1661 {0x00FA, SIERRA_DEQ_DFETAP3}, 1662 {0x00FA, SIERRA_DEQ_DFETAP4}, 1663 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1664 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1665 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1666 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1667 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1668 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1669 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1670 {0x002B, SIERRA_CPI_TRIM_PREG}, 1671 {0x0003, SIERRA_EPI_CTRL_PREG}, 1672 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1673 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1674 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1675 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1676 }; 1677 1678 static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = { 1679 .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs, 1680 .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs), 1681 }; 1682 1683 static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = { 1684 .reg_pairs = ml_pcie_100_no_ssc_ln_regs, 1685 .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs), 1686 }; 1687 1688 /* 1689 * TI J721E: 1690 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1691 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1692 */ 1693 static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { 1694 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1695 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1696 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1697 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1698 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1699 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1700 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1701 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1702 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1703 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1704 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1705 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1706 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1707 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1708 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1709 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1710 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1711 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1712 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1713 {0x0041, SIERRA_DEQ_GLUT0}, 1714 {0x0082, SIERRA_DEQ_GLUT1}, 1715 {0x00C3, SIERRA_DEQ_GLUT2}, 1716 {0x0145, SIERRA_DEQ_GLUT3}, 1717 {0x0186, SIERRA_DEQ_GLUT4}, 1718 {0x09E7, SIERRA_DEQ_ALUT0}, 1719 {0x09A6, SIERRA_DEQ_ALUT1}, 1720 {0x0965, SIERRA_DEQ_ALUT2}, 1721 {0x08E3, SIERRA_DEQ_ALUT3}, 1722 {0x00FA, SIERRA_DEQ_DFETAP0}, 1723 {0x00FA, SIERRA_DEQ_DFETAP1}, 1724 {0x00FA, SIERRA_DEQ_DFETAP2}, 1725 {0x00FA, SIERRA_DEQ_DFETAP3}, 1726 {0x00FA, SIERRA_DEQ_DFETAP4}, 1727 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1728 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1729 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1730 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1731 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1732 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1733 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1734 {0x002B, SIERRA_CPI_TRIM_PREG}, 1735 {0x0003, SIERRA_EPI_CTRL_PREG}, 1736 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1737 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1738 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1739 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 1740 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 1741 }; 1742 1743 static struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = { 1744 .reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs, 1745 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs), 1746 }; 1747 1748 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1749 static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = { 1750 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 1751 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1752 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1753 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1754 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1755 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 1756 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 1757 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 1758 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 1759 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 1760 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 1761 }; 1762 1763 /* 1764 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 1765 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1766 */ 1767 static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { 1768 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1769 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1770 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1771 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1772 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1773 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1774 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1775 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1776 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1777 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1778 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1779 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1780 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1781 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1782 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1783 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1784 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1785 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1786 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1787 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1788 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1789 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1790 {0x0041, SIERRA_DEQ_GLUT0}, 1791 {0x0082, SIERRA_DEQ_GLUT1}, 1792 {0x00C3, SIERRA_DEQ_GLUT2}, 1793 {0x0145, SIERRA_DEQ_GLUT3}, 1794 {0x0186, SIERRA_DEQ_GLUT4}, 1795 {0x09E7, SIERRA_DEQ_ALUT0}, 1796 {0x09A6, SIERRA_DEQ_ALUT1}, 1797 {0x0965, SIERRA_DEQ_ALUT2}, 1798 {0x08E3, SIERRA_DEQ_ALUT3}, 1799 {0x00FA, SIERRA_DEQ_DFETAP0}, 1800 {0x00FA, SIERRA_DEQ_DFETAP1}, 1801 {0x00FA, SIERRA_DEQ_DFETAP2}, 1802 {0x00FA, SIERRA_DEQ_DFETAP3}, 1803 {0x00FA, SIERRA_DEQ_DFETAP4}, 1804 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1805 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1806 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1807 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1808 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1809 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1810 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1811 {0x002B, SIERRA_CPI_TRIM_PREG}, 1812 {0x0003, SIERRA_EPI_CTRL_PREG}, 1813 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1814 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1815 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1816 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1817 }; 1818 1819 static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = { 1820 .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs, 1821 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs), 1822 }; 1823 1824 static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = { 1825 .reg_pairs = ml_pcie_100_int_ssc_ln_regs, 1826 .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs), 1827 }; 1828 1829 /* 1830 * TI J721E: 1831 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 1832 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1833 */ 1834 static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { 1835 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1836 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1837 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1838 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1839 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1840 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1841 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1842 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1843 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1844 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1845 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1846 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1847 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1848 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1849 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1850 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1851 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1852 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1853 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1854 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1855 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1856 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1857 {0x0041, SIERRA_DEQ_GLUT0}, 1858 {0x0082, SIERRA_DEQ_GLUT1}, 1859 {0x00C3, SIERRA_DEQ_GLUT2}, 1860 {0x0145, SIERRA_DEQ_GLUT3}, 1861 {0x0186, SIERRA_DEQ_GLUT4}, 1862 {0x09E7, SIERRA_DEQ_ALUT0}, 1863 {0x09A6, SIERRA_DEQ_ALUT1}, 1864 {0x0965, SIERRA_DEQ_ALUT2}, 1865 {0x08E3, SIERRA_DEQ_ALUT3}, 1866 {0x00FA, SIERRA_DEQ_DFETAP0}, 1867 {0x00FA, SIERRA_DEQ_DFETAP1}, 1868 {0x00FA, SIERRA_DEQ_DFETAP2}, 1869 {0x00FA, SIERRA_DEQ_DFETAP3}, 1870 {0x00FA, SIERRA_DEQ_DFETAP4}, 1871 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1872 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1873 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1874 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1875 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1876 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1877 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1878 {0x002B, SIERRA_CPI_TRIM_PREG}, 1879 {0x0003, SIERRA_EPI_CTRL_PREG}, 1880 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1881 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1882 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1883 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 1884 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 1885 }; 1886 1887 static struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = { 1888 .reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs, 1889 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs), 1890 }; 1891 1892 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1893 static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = { 1894 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1895 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1896 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1897 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1898 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 1899 }; 1900 1901 /* 1902 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 1903 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1904 */ 1905 static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { 1906 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1907 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1908 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1909 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1910 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1911 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1912 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1913 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1914 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1915 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1916 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1917 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1918 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1919 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1920 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1921 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1922 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1923 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1924 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1925 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1926 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1927 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1928 {0x0041, SIERRA_DEQ_GLUT0}, 1929 {0x0082, SIERRA_DEQ_GLUT1}, 1930 {0x00C3, SIERRA_DEQ_GLUT2}, 1931 {0x0145, SIERRA_DEQ_GLUT3}, 1932 {0x0186, SIERRA_DEQ_GLUT4}, 1933 {0x09E7, SIERRA_DEQ_ALUT0}, 1934 {0x09A6, SIERRA_DEQ_ALUT1}, 1935 {0x0965, SIERRA_DEQ_ALUT2}, 1936 {0x08E3, SIERRA_DEQ_ALUT3}, 1937 {0x00FA, SIERRA_DEQ_DFETAP0}, 1938 {0x00FA, SIERRA_DEQ_DFETAP1}, 1939 {0x00FA, SIERRA_DEQ_DFETAP2}, 1940 {0x00FA, SIERRA_DEQ_DFETAP3}, 1941 {0x00FA, SIERRA_DEQ_DFETAP4}, 1942 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1943 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1944 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1945 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1946 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1947 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1948 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1949 {0x002B, SIERRA_CPI_TRIM_PREG}, 1950 {0x0003, SIERRA_EPI_CTRL_PREG}, 1951 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1952 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1953 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1954 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1955 }; 1956 1957 static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = { 1958 .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs, 1959 .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs), 1960 }; 1961 1962 static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = { 1963 .reg_pairs = ml_pcie_100_ext_ssc_ln_regs, 1964 .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs), 1965 }; 1966 1967 /* 1968 * TI J721E: 1969 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 1970 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1971 */ 1972 static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { 1973 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1974 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1975 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1976 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1977 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1978 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1979 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1980 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1981 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1982 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1983 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1984 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1985 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1986 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1987 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1988 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1989 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1990 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1991 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1992 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1993 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1994 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1995 {0x0041, SIERRA_DEQ_GLUT0}, 1996 {0x0082, SIERRA_DEQ_GLUT1}, 1997 {0x00C3, SIERRA_DEQ_GLUT2}, 1998 {0x0145, SIERRA_DEQ_GLUT3}, 1999 {0x0186, SIERRA_DEQ_GLUT4}, 2000 {0x09E7, SIERRA_DEQ_ALUT0}, 2001 {0x09A6, SIERRA_DEQ_ALUT1}, 2002 {0x0965, SIERRA_DEQ_ALUT2}, 2003 {0x08E3, SIERRA_DEQ_ALUT3}, 2004 {0x00FA, SIERRA_DEQ_DFETAP0}, 2005 {0x00FA, SIERRA_DEQ_DFETAP1}, 2006 {0x00FA, SIERRA_DEQ_DFETAP2}, 2007 {0x00FA, SIERRA_DEQ_DFETAP3}, 2008 {0x00FA, SIERRA_DEQ_DFETAP4}, 2009 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2010 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2011 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2012 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2013 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2014 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2015 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2016 {0x002B, SIERRA_CPI_TRIM_PREG}, 2017 {0x0003, SIERRA_EPI_CTRL_PREG}, 2018 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2019 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2020 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2021 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 2022 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 2023 }; 2024 2025 static struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = { 2026 .reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs, 2027 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs), 2028 }; 2029 2030 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ 2031 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = { 2032 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2033 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2034 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2035 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 2036 }; 2037 2038 /* refclk100MHz_32b_PCIe_ln_no_ssc */ 2039 static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { 2040 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2041 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2042 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2043 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2044 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2045 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2046 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2047 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2048 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2049 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2050 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2051 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2052 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2053 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2054 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2055 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2056 {0x0041, SIERRA_DEQ_GLUT0}, 2057 {0x0082, SIERRA_DEQ_GLUT1}, 2058 {0x00C3, SIERRA_DEQ_GLUT2}, 2059 {0x0145, SIERRA_DEQ_GLUT3}, 2060 {0x0186, SIERRA_DEQ_GLUT4}, 2061 {0x09E7, SIERRA_DEQ_ALUT0}, 2062 {0x09A6, SIERRA_DEQ_ALUT1}, 2063 {0x0965, SIERRA_DEQ_ALUT2}, 2064 {0x08E3, SIERRA_DEQ_ALUT3}, 2065 {0x00FA, SIERRA_DEQ_DFETAP0}, 2066 {0x00FA, SIERRA_DEQ_DFETAP1}, 2067 {0x00FA, SIERRA_DEQ_DFETAP2}, 2068 {0x00FA, SIERRA_DEQ_DFETAP3}, 2069 {0x00FA, SIERRA_DEQ_DFETAP4}, 2070 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2071 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2072 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2073 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2074 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2075 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2076 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2077 {0x002B, SIERRA_CPI_TRIM_PREG}, 2078 {0x0003, SIERRA_EPI_CTRL_PREG}, 2079 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2080 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2081 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2082 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2083 }; 2084 2085 static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = { 2086 .reg_pairs = cdns_pcie_cmn_regs_no_ssc, 2087 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc), 2088 }; 2089 2090 static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = { 2091 .reg_pairs = cdns_pcie_ln_regs_no_ssc, 2092 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc), 2093 }; 2094 2095 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ 2096 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = { 2097 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 2098 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2099 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2100 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2101 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2102 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 2103 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 2104 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 2105 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 2106 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 2107 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 2108 }; 2109 2110 /* refclk100MHz_32b_PCIe_ln_int_ssc */ 2111 static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { 2112 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2113 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2114 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2115 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2116 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2117 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2118 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2119 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2120 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2121 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2122 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2123 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2124 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2125 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2126 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2127 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2128 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2129 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2130 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2131 {0x0041, SIERRA_DEQ_GLUT0}, 2132 {0x0082, SIERRA_DEQ_GLUT1}, 2133 {0x00C3, SIERRA_DEQ_GLUT2}, 2134 {0x0145, SIERRA_DEQ_GLUT3}, 2135 {0x0186, SIERRA_DEQ_GLUT4}, 2136 {0x09E7, SIERRA_DEQ_ALUT0}, 2137 {0x09A6, SIERRA_DEQ_ALUT1}, 2138 {0x0965, SIERRA_DEQ_ALUT2}, 2139 {0x08E3, SIERRA_DEQ_ALUT3}, 2140 {0x00FA, SIERRA_DEQ_DFETAP0}, 2141 {0x00FA, SIERRA_DEQ_DFETAP1}, 2142 {0x00FA, SIERRA_DEQ_DFETAP2}, 2143 {0x00FA, SIERRA_DEQ_DFETAP3}, 2144 {0x00FA, SIERRA_DEQ_DFETAP4}, 2145 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2146 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2147 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2148 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2149 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2150 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2151 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2152 {0x002B, SIERRA_CPI_TRIM_PREG}, 2153 {0x0003, SIERRA_EPI_CTRL_PREG}, 2154 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2155 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2156 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2157 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2158 }; 2159 2160 static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = { 2161 .reg_pairs = cdns_pcie_cmn_regs_int_ssc, 2162 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc), 2163 }; 2164 2165 static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = { 2166 .reg_pairs = cdns_pcie_ln_regs_int_ssc, 2167 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc), 2168 }; 2169 2170 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 2171 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 2172 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2173 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2174 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2175 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2176 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2177 }; 2178 2179 /* refclk100MHz_32b_PCIe_ln_ext_ssc */ 2180 static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 2181 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2182 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2183 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2184 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2185 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2186 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2187 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2188 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2189 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2190 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2191 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2192 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2193 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2194 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2195 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2196 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2197 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2198 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2199 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2200 {0x0041, SIERRA_DEQ_GLUT0}, 2201 {0x0082, SIERRA_DEQ_GLUT1}, 2202 {0x00C3, SIERRA_DEQ_GLUT2}, 2203 {0x0145, SIERRA_DEQ_GLUT3}, 2204 {0x0186, SIERRA_DEQ_GLUT4}, 2205 {0x09E7, SIERRA_DEQ_ALUT0}, 2206 {0x09A6, SIERRA_DEQ_ALUT1}, 2207 {0x0965, SIERRA_DEQ_ALUT2}, 2208 {0x08E3, SIERRA_DEQ_ALUT3}, 2209 {0x00FA, SIERRA_DEQ_DFETAP0}, 2210 {0x00FA, SIERRA_DEQ_DFETAP1}, 2211 {0x00FA, SIERRA_DEQ_DFETAP2}, 2212 {0x00FA, SIERRA_DEQ_DFETAP3}, 2213 {0x00FA, SIERRA_DEQ_DFETAP4}, 2214 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2215 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2216 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2217 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2218 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2219 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2220 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2221 {0x002B, SIERRA_CPI_TRIM_PREG}, 2222 {0x0003, SIERRA_EPI_CTRL_PREG}, 2223 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2224 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2225 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2226 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2227 }; 2228 2229 static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = { 2230 .reg_pairs = cdns_pcie_cmn_regs_ext_ssc, 2231 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 2232 }; 2233 2234 static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = { 2235 .reg_pairs = cdns_pcie_ln_regs_ext_ssc, 2236 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 2237 }; 2238 2239 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 2240 static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 2241 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2242 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2243 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2244 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2245 }; 2246 2247 /* refclk100MHz_20b_USB_ln_ext_ssc */ 2248 static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 2249 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 2250 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 2251 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 2252 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 2253 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 2254 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 2255 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 2256 {0xCF00, SIERRA_PSM_DIAG_PREG}, 2257 {0x001F, SIERRA_PSC_TX_A0_PREG}, 2258 {0x0007, SIERRA_PSC_TX_A1_PREG}, 2259 {0x0003, SIERRA_PSC_TX_A2_PREG}, 2260 {0x0003, SIERRA_PSC_TX_A3_PREG}, 2261 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 2262 {0x0003, SIERRA_PSC_RX_A1_PREG}, 2263 {0x0003, SIERRA_PSC_RX_A2_PREG}, 2264 {0x0001, SIERRA_PSC_RX_A3_PREG}, 2265 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 2266 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 2267 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 2268 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 2269 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 2270 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 2271 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2272 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2273 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2274 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 2275 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2276 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 2277 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 2278 {0x0000, SIERRA_CREQ_SPARE_PREG}, 2279 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2280 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 2281 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 2282 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 2283 {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, 2284 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 2285 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2286 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2287 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2288 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2289 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2290 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 2291 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 2292 {0x0014, SIERRA_DEQ_GLUT0}, 2293 {0x0014, SIERRA_DEQ_GLUT1}, 2294 {0x0014, SIERRA_DEQ_GLUT2}, 2295 {0x0014, SIERRA_DEQ_GLUT3}, 2296 {0x0014, SIERRA_DEQ_GLUT4}, 2297 {0x0014, SIERRA_DEQ_GLUT5}, 2298 {0x0014, SIERRA_DEQ_GLUT6}, 2299 {0x0014, SIERRA_DEQ_GLUT7}, 2300 {0x0014, SIERRA_DEQ_GLUT8}, 2301 {0x0014, SIERRA_DEQ_GLUT9}, 2302 {0x0014, SIERRA_DEQ_GLUT10}, 2303 {0x0014, SIERRA_DEQ_GLUT11}, 2304 {0x0014, SIERRA_DEQ_GLUT12}, 2305 {0x0014, SIERRA_DEQ_GLUT13}, 2306 {0x0014, SIERRA_DEQ_GLUT14}, 2307 {0x0014, SIERRA_DEQ_GLUT15}, 2308 {0x0014, SIERRA_DEQ_GLUT16}, 2309 {0x0BAE, SIERRA_DEQ_ALUT0}, 2310 {0x0AEB, SIERRA_DEQ_ALUT1}, 2311 {0x0A28, SIERRA_DEQ_ALUT2}, 2312 {0x0965, SIERRA_DEQ_ALUT3}, 2313 {0x08A2, SIERRA_DEQ_ALUT4}, 2314 {0x07DF, SIERRA_DEQ_ALUT5}, 2315 {0x071C, SIERRA_DEQ_ALUT6}, 2316 {0x0659, SIERRA_DEQ_ALUT7}, 2317 {0x0596, SIERRA_DEQ_ALUT8}, 2318 {0x0514, SIERRA_DEQ_ALUT9}, 2319 {0x0492, SIERRA_DEQ_ALUT10}, 2320 {0x0410, SIERRA_DEQ_ALUT11}, 2321 {0x038E, SIERRA_DEQ_ALUT12}, 2322 {0x030C, SIERRA_DEQ_ALUT13}, 2323 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 2324 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 2325 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 2326 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2327 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 2328 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 2329 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 2330 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 2331 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 2332 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 2333 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 2334 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 2335 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 2336 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 2337 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 2338 {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, 2339 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 2340 {0x8009, SIERRA_SDFILT_L2H_PREG}, 2341 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2342 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2343 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 2344 }; 2345 2346 static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = { 2347 .reg_pairs = cdns_usb_cmn_regs_ext_ssc, 2348 .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 2349 }; 2350 2351 static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = { 2352 .reg_pairs = cdns_usb_ln_regs_ext_ssc, 2353 .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 2354 }; 2355 2356 static const struct cdns_sierra_data cdns_map_sierra = { 2357 .id_value = SIERRA_MACRO_ID, 2358 .block_offset_shift = 0x2, 2359 .reg_offset_shift = 0x2, 2360 .pcs_cmn_vals = { 2361 [TYPE_PCIE] = { 2362 [TYPE_NONE] = { 2363 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2364 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2365 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2366 }, 2367 [TYPE_QSGMII] = { 2368 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2369 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2370 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2371 }, 2372 }, 2373 }, 2374 .pma_cmn_vals = { 2375 [TYPE_PCIE] = { 2376 [TYPE_NONE] = { 2377 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 2378 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 2379 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 2380 }, 2381 [TYPE_QSGMII] = { 2382 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2383 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2384 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2385 }, 2386 }, 2387 [TYPE_USB] = { 2388 [TYPE_NONE] = { 2389 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2390 }, 2391 }, 2392 [TYPE_QSGMII] = { 2393 [TYPE_PCIE] = { 2394 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2395 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2396 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2397 }, 2398 }, 2399 }, 2400 .pma_ln_vals = { 2401 [TYPE_PCIE] = { 2402 [TYPE_NONE] = { 2403 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 2404 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 2405 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 2406 }, 2407 [TYPE_QSGMII] = { 2408 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2409 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2410 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2411 }, 2412 }, 2413 [TYPE_USB] = { 2414 [TYPE_NONE] = { 2415 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2416 }, 2417 }, 2418 [TYPE_QSGMII] = { 2419 [TYPE_PCIE] = { 2420 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2421 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2422 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2423 }, 2424 }, 2425 }, 2426 }; 2427 2428 static const struct cdns_sierra_data cdns_ti_map_sierra = { 2429 .id_value = SIERRA_MACRO_ID, 2430 .block_offset_shift = 0x0, 2431 .reg_offset_shift = 0x1, 2432 .pcs_cmn_vals = { 2433 [TYPE_PCIE] = { 2434 [TYPE_NONE] = { 2435 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2436 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2437 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2438 }, 2439 [TYPE_QSGMII] = { 2440 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2441 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2442 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2443 }, 2444 }, 2445 }, 2446 .phy_pma_ln_vals = { 2447 [TYPE_QSGMII] = { 2448 [TYPE_PCIE] = { 2449 [NO_SSC] = &qsgmii_phy_pma_ln_vals, 2450 [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 2451 [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 2452 }, 2453 }, 2454 }, 2455 .pma_cmn_vals = { 2456 [TYPE_PCIE] = { 2457 [TYPE_NONE] = { 2458 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 2459 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 2460 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 2461 }, 2462 [TYPE_QSGMII] = { 2463 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2464 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2465 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2466 }, 2467 }, 2468 [TYPE_USB] = { 2469 [TYPE_NONE] = { 2470 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2471 }, 2472 }, 2473 [TYPE_QSGMII] = { 2474 [TYPE_PCIE] = { 2475 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2476 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2477 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2478 }, 2479 }, 2480 }, 2481 .pma_ln_vals = { 2482 [TYPE_PCIE] = { 2483 [TYPE_NONE] = { 2484 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 2485 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 2486 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 2487 }, 2488 [TYPE_QSGMII] = { 2489 [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2490 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2491 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2492 }, 2493 }, 2494 [TYPE_USB] = { 2495 [TYPE_NONE] = { 2496 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2497 }, 2498 }, 2499 [TYPE_QSGMII] = { 2500 [TYPE_PCIE] = { 2501 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2502 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2503 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2504 }, 2505 }, 2506 }, 2507 }; 2508 2509 static const struct of_device_id cdns_sierra_id_table[] = { 2510 { 2511 .compatible = "cdns,sierra-phy-t0", 2512 .data = &cdns_map_sierra, 2513 }, 2514 { 2515 .compatible = "ti,sierra-phy-t0", 2516 .data = &cdns_ti_map_sierra, 2517 }, 2518 {} 2519 }; 2520 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 2521 2522 static struct platform_driver cdns_sierra_driver = { 2523 .probe = cdns_sierra_phy_probe, 2524 .remove = cdns_sierra_phy_remove, 2525 .driver = { 2526 .name = "cdns-sierra-phy", 2527 .of_match_table = cdns_sierra_id_table, 2528 }, 2529 }; 2530 module_platform_driver(cdns_sierra_driver); 2531 2532 MODULE_ALIAS("platform:cdns_sierra"); 2533 MODULE_AUTHOR("Cadence Design Systems"); 2534 MODULE_DESCRIPTION("CDNS sierra phy driver"); 2535 MODULE_LICENSE("GPL v2"); 2536