1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <dt-bindings/phy/phy.h> 23 24 /* PHY register offsets */ 25 #define SIERRA_COMMON_CDB_OFFSET 0x0 26 #define SIERRA_MACRO_ID_REG 0x0 27 28 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 29 ((0x4000 << (block_offset)) + \ 30 (((ln) << 9) << (reg_offset))) 31 #define SIERRA_DET_STANDEC_A 0x000 32 #define SIERRA_DET_STANDEC_B 0x001 33 #define SIERRA_DET_STANDEC_C 0x002 34 #define SIERRA_DET_STANDEC_D 0x003 35 #define SIERRA_DET_STANDEC_E 0x004 36 #define SIERRA_PSM_LANECAL 0x008 37 #define SIERRA_PSM_DIAG 0x015 38 #define SIERRA_PSC_TX_A0 0x028 39 #define SIERRA_PSC_TX_A1 0x029 40 #define SIERRA_PSC_TX_A2 0x02A 41 #define SIERRA_PSC_TX_A3 0x02B 42 #define SIERRA_PSC_RX_A0 0x030 43 #define SIERRA_PSC_RX_A1 0x031 44 #define SIERRA_PSC_RX_A2 0x032 45 #define SIERRA_PSC_RX_A3 0x033 46 #define SIERRA_PLLCTRL_SUBRATE 0x03A 47 #define SIERRA_PLLCTRL_GEN_D 0x03E 48 #define SIERRA_DRVCTRL_ATTEN 0x06A 49 #define SIERRA_CLKPATHCTRL_TMR 0x081 50 #define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087 51 #define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088 52 #define SIERRA_CREQ_CCLKDET_MODE01 0x08E 53 #define SIERRA_RX_CTLE_MAINTENANCE 0x091 54 #define SIERRA_CREQ_FSMCLK_SEL 0x092 55 #define SIERRA_CTLELUT_CTRL 0x098 56 #define SIERRA_DFE_ECMP_RATESEL 0x0C0 57 #define SIERRA_DFE_SMP_RATESEL 0x0C1 58 #define SIERRA_DEQ_VGATUNE_CTRL 0x0E1 59 #define SIERRA_TMRVAL_MODE3 0x16E 60 #define SIERRA_TMRVAL_MODE2 0x16F 61 #define SIERRA_TMRVAL_MODE1 0x170 62 #define SIERRA_TMRVAL_MODE0 0x171 63 #define SIERRA_PICNT_MODE1 0x174 64 #define SIERRA_CPI_OUTBUF_RATESEL 0x17C 65 #define SIERRA_LFPSFILT_NS 0x18A 66 #define SIERRA_LFPSFILT_RD 0x18B 67 #define SIERRA_LFPSFILT_MP 0x18C 68 #define SIERRA_SDFILT_H2L_A 0x191 69 70 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ 71 (0xc000 << (block_offset)) 72 #define SIERRA_PHY_PLL_CFG 0xe 73 74 #define SIERRA_MACRO_ID 0x00007364 75 #define SIERRA_MAX_LANES 4 76 77 static const struct reg_field macro_id_type = 78 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 79 static const struct reg_field phy_pll_cfg_1 = 80 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 81 82 struct cdns_sierra_inst { 83 struct phy *phy; 84 u32 phy_type; 85 u32 num_lanes; 86 u32 mlane; 87 struct reset_control *lnk_rst; 88 }; 89 90 struct cdns_reg_pairs { 91 u16 val; 92 u32 off; 93 }; 94 95 struct cdns_sierra_data { 96 u32 id_value; 97 u8 block_offset_shift; 98 u8 reg_offset_shift; 99 u32 pcie_regs; 100 u32 usb_regs; 101 struct cdns_reg_pairs *pcie_vals; 102 struct cdns_reg_pairs *usb_vals; 103 }; 104 105 struct cdns_regmap_cdb_context { 106 struct device *dev; 107 void __iomem *base; 108 u8 reg_offset_shift; 109 }; 110 111 struct cdns_sierra_phy { 112 struct device *dev; 113 struct regmap *regmap; 114 struct cdns_sierra_data *init_data; 115 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 116 struct reset_control *phy_rst; 117 struct reset_control *apb_rst; 118 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 119 struct regmap *regmap_phy_config_ctrl; 120 struct regmap *regmap_common_cdb; 121 struct regmap_field *macro_id_type; 122 struct regmap_field *phy_pll_cfg_1; 123 struct clk *clk; 124 int nsubnodes; 125 bool autoconf; 126 }; 127 128 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 129 { 130 struct cdns_regmap_cdb_context *ctx = context; 131 u32 offset = reg << ctx->reg_offset_shift; 132 133 writew(val, ctx->base + offset); 134 135 return 0; 136 } 137 138 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 139 { 140 struct cdns_regmap_cdb_context *ctx = context; 141 u32 offset = reg << ctx->reg_offset_shift; 142 143 *val = readw(ctx->base + offset); 144 return 0; 145 } 146 147 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 148 { \ 149 .name = "sierra_lane" n "_cdb", \ 150 .reg_stride = 1, \ 151 .fast_io = true, \ 152 .reg_write = cdns_regmap_write, \ 153 .reg_read = cdns_regmap_read, \ 154 } 155 156 static struct regmap_config cdns_sierra_lane_cdb_config[] = { 157 SIERRA_LANE_CDB_REGMAP_CONF("0"), 158 SIERRA_LANE_CDB_REGMAP_CONF("1"), 159 SIERRA_LANE_CDB_REGMAP_CONF("2"), 160 SIERRA_LANE_CDB_REGMAP_CONF("3"), 161 }; 162 163 static struct regmap_config cdns_sierra_common_cdb_config = { 164 .name = "sierra_common_cdb", 165 .reg_stride = 1, 166 .fast_io = true, 167 .reg_write = cdns_regmap_write, 168 .reg_read = cdns_regmap_read, 169 }; 170 171 static struct regmap_config cdns_sierra_phy_config_ctrl_config = { 172 .name = "sierra_phy_config_ctrl", 173 .reg_stride = 1, 174 .fast_io = true, 175 .reg_write = cdns_regmap_write, 176 .reg_read = cdns_regmap_read, 177 }; 178 179 static int cdns_sierra_phy_init(struct phy *gphy) 180 { 181 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 182 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 183 struct regmap *regmap = phy->regmap; 184 int i, j; 185 struct cdns_reg_pairs *vals; 186 u32 num_regs; 187 188 /* Initialise the PHY registers, unless auto configured */ 189 if (phy->autoconf) 190 return 0; 191 192 if (ins->phy_type == PHY_TYPE_PCIE) { 193 num_regs = phy->init_data->pcie_regs; 194 vals = phy->init_data->pcie_vals; 195 } else if (ins->phy_type == PHY_TYPE_USB3) { 196 num_regs = phy->init_data->usb_regs; 197 vals = phy->init_data->usb_vals; 198 } else { 199 return -EINVAL; 200 } 201 for (i = 0; i < ins->num_lanes; i++) { 202 for (j = 0; j < num_regs ; j++) { 203 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 204 regmap_write(regmap, vals[j].off, vals[j].val); 205 } 206 } 207 208 return 0; 209 } 210 211 static int cdns_sierra_phy_on(struct phy *gphy) 212 { 213 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 214 215 /* Take the PHY lane group out of reset */ 216 return reset_control_deassert(ins->lnk_rst); 217 } 218 219 static int cdns_sierra_phy_off(struct phy *gphy) 220 { 221 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 222 223 return reset_control_assert(ins->lnk_rst); 224 } 225 226 static const struct phy_ops ops = { 227 .init = cdns_sierra_phy_init, 228 .power_on = cdns_sierra_phy_on, 229 .power_off = cdns_sierra_phy_off, 230 .owner = THIS_MODULE, 231 }; 232 233 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 234 struct device_node *child) 235 { 236 if (of_property_read_u32(child, "reg", &inst->mlane)) 237 return -EINVAL; 238 239 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 240 return -EINVAL; 241 242 if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type)) 243 return -EINVAL; 244 245 return 0; 246 } 247 248 static const struct of_device_id cdns_sierra_id_table[]; 249 250 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 251 u32 block_offset, u8 reg_offset_shift, 252 const struct regmap_config *config) 253 { 254 struct cdns_regmap_cdb_context *ctx; 255 256 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 257 if (!ctx) 258 return ERR_PTR(-ENOMEM); 259 260 ctx->dev = dev; 261 ctx->base = base + block_offset; 262 ctx->reg_offset_shift = reg_offset_shift; 263 264 return devm_regmap_init(dev, NULL, ctx, config); 265 } 266 267 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 268 { 269 struct device *dev = sp->dev; 270 struct regmap_field *field; 271 struct regmap *regmap; 272 273 regmap = sp->regmap_common_cdb; 274 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 275 if (IS_ERR(field)) { 276 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 277 return PTR_ERR(field); 278 } 279 sp->macro_id_type = field; 280 281 regmap = sp->regmap_phy_config_ctrl; 282 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 283 if (IS_ERR(field)) { 284 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 285 return PTR_ERR(field); 286 } 287 sp->phy_pll_cfg_1 = field; 288 289 return 0; 290 } 291 292 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 293 void __iomem *base, u8 block_offset_shift, 294 u8 reg_offset_shift) 295 { 296 struct device *dev = sp->dev; 297 struct regmap *regmap; 298 u32 block_offset; 299 int i; 300 301 for (i = 0; i < SIERRA_MAX_LANES; i++) { 302 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 303 reg_offset_shift); 304 regmap = cdns_regmap_init(dev, base, block_offset, 305 reg_offset_shift, 306 &cdns_sierra_lane_cdb_config[i]); 307 if (IS_ERR(regmap)) { 308 dev_err(dev, "Failed to init lane CDB regmap\n"); 309 return PTR_ERR(regmap); 310 } 311 sp->regmap_lane_cdb[i] = regmap; 312 } 313 314 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 315 reg_offset_shift, 316 &cdns_sierra_common_cdb_config); 317 if (IS_ERR(regmap)) { 318 dev_err(dev, "Failed to init common CDB regmap\n"); 319 return PTR_ERR(regmap); 320 } 321 sp->regmap_common_cdb = regmap; 322 323 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); 324 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 325 &cdns_sierra_phy_config_ctrl_config); 326 if (IS_ERR(regmap)) { 327 dev_err(dev, "Failed to init PHY config and control regmap\n"); 328 return PTR_ERR(regmap); 329 } 330 sp->regmap_phy_config_ctrl = regmap; 331 332 return 0; 333 } 334 335 static int cdns_sierra_phy_probe(struct platform_device *pdev) 336 { 337 struct cdns_sierra_phy *sp; 338 struct phy_provider *phy_provider; 339 struct device *dev = &pdev->dev; 340 const struct of_device_id *match; 341 struct cdns_sierra_data *data; 342 unsigned int id_value; 343 struct resource *res; 344 int i, ret, node = 0; 345 void __iomem *base; 346 struct device_node *dn = dev->of_node, *child; 347 348 if (of_get_child_count(dn) == 0) 349 return -ENODEV; 350 351 /* Get init data for this PHY */ 352 match = of_match_device(cdns_sierra_id_table, dev); 353 if (!match) 354 return -EINVAL; 355 356 data = (struct cdns_sierra_data *)match->data; 357 358 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 359 if (!sp) 360 return -ENOMEM; 361 dev_set_drvdata(dev, sp); 362 sp->dev = dev; 363 sp->init_data = data; 364 365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 366 base = devm_ioremap_resource(dev, res); 367 if (IS_ERR(base)) { 368 dev_err(dev, "missing \"reg\"\n"); 369 return PTR_ERR(base); 370 } 371 372 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 373 data->reg_offset_shift); 374 if (ret) 375 return ret; 376 377 ret = cdns_regfield_init(sp); 378 if (ret) 379 return ret; 380 381 platform_set_drvdata(pdev, sp); 382 383 sp->clk = devm_clk_get_optional(dev, "phy_clk"); 384 if (IS_ERR(sp->clk)) { 385 dev_err(dev, "failed to get clock phy_clk\n"); 386 return PTR_ERR(sp->clk); 387 } 388 389 sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); 390 if (IS_ERR(sp->phy_rst)) { 391 dev_err(dev, "failed to get reset\n"); 392 return PTR_ERR(sp->phy_rst); 393 } 394 395 sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); 396 if (IS_ERR(sp->apb_rst)) { 397 dev_err(dev, "failed to get apb reset\n"); 398 return PTR_ERR(sp->apb_rst); 399 } 400 401 ret = clk_prepare_enable(sp->clk); 402 if (ret) 403 return ret; 404 405 /* Enable APB */ 406 reset_control_deassert(sp->apb_rst); 407 408 /* Check that PHY is present */ 409 regmap_field_read(sp->macro_id_type, &id_value); 410 if (sp->init_data->id_value != id_value) { 411 ret = -EINVAL; 412 goto clk_disable; 413 } 414 415 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 416 417 for_each_available_child_of_node(dn, child) { 418 struct phy *gphy; 419 420 sp->phys[node].lnk_rst = 421 of_reset_control_get_exclusive_by_index(child, 0); 422 423 if (IS_ERR(sp->phys[node].lnk_rst)) { 424 dev_err(dev, "failed to get reset %s\n", 425 child->full_name); 426 ret = PTR_ERR(sp->phys[node].lnk_rst); 427 goto put_child2; 428 } 429 430 if (!sp->autoconf) { 431 ret = cdns_sierra_get_optional(&sp->phys[node], child); 432 if (ret) { 433 dev_err(dev, "missing property in node %s\n", 434 child->name); 435 goto put_child; 436 } 437 } 438 439 gphy = devm_phy_create(dev, child, &ops); 440 441 if (IS_ERR(gphy)) { 442 ret = PTR_ERR(gphy); 443 goto put_child; 444 } 445 sp->phys[node].phy = gphy; 446 phy_set_drvdata(gphy, &sp->phys[node]); 447 448 node++; 449 } 450 sp->nsubnodes = node; 451 452 /* If more than one subnode, configure the PHY as multilink */ 453 if (!sp->autoconf && sp->nsubnodes > 1) 454 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 455 456 pm_runtime_enable(dev); 457 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 458 reset_control_deassert(sp->phy_rst); 459 return PTR_ERR_OR_ZERO(phy_provider); 460 461 put_child: 462 node++; 463 put_child2: 464 for (i = 0; i < node; i++) 465 reset_control_put(sp->phys[i].lnk_rst); 466 of_node_put(child); 467 clk_disable: 468 clk_disable_unprepare(sp->clk); 469 reset_control_assert(sp->apb_rst); 470 return ret; 471 } 472 473 static int cdns_sierra_phy_remove(struct platform_device *pdev) 474 { 475 struct cdns_sierra_phy *phy = dev_get_drvdata(pdev->dev.parent); 476 int i; 477 478 reset_control_assert(phy->phy_rst); 479 reset_control_assert(phy->apb_rst); 480 pm_runtime_disable(&pdev->dev); 481 482 /* 483 * The device level resets will be put automatically. 484 * Need to put the subnode resets here though. 485 */ 486 for (i = 0; i < phy->nsubnodes; i++) { 487 reset_control_assert(phy->phys[i].lnk_rst); 488 reset_control_put(phy->phys[i].lnk_rst); 489 } 490 return 0; 491 } 492 493 static struct cdns_reg_pairs cdns_usb_regs[] = { 494 /* 495 * Write USB configuration parameters to the PHY. 496 * These values are specific to this specific hardware 497 * configuration. 498 */ 499 {0xFE0A, SIERRA_DET_STANDEC_A}, 500 {0x000F, SIERRA_DET_STANDEC_B}, 501 {0x55A5, SIERRA_DET_STANDEC_C}, 502 {0x69AD, SIERRA_DET_STANDEC_D}, 503 {0x0241, SIERRA_DET_STANDEC_E}, 504 {0x0110, SIERRA_PSM_LANECAL}, 505 {0xCF00, SIERRA_PSM_DIAG}, 506 {0x001F, SIERRA_PSC_TX_A0}, 507 {0x0007, SIERRA_PSC_TX_A1}, 508 {0x0003, SIERRA_PSC_TX_A2}, 509 {0x0003, SIERRA_PSC_TX_A3}, 510 {0x0FFF, SIERRA_PSC_RX_A0}, 511 {0x0003, SIERRA_PSC_RX_A1}, 512 {0x0003, SIERRA_PSC_RX_A2}, 513 {0x0001, SIERRA_PSC_RX_A3}, 514 {0x0001, SIERRA_PLLCTRL_SUBRATE}, 515 {0x0406, SIERRA_PLLCTRL_GEN_D}, 516 {0x0000, SIERRA_DRVCTRL_ATTEN}, 517 {0x823E, SIERRA_CLKPATHCTRL_TMR}, 518 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1}, 519 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0}, 520 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01}, 521 {0x023C, SIERRA_RX_CTLE_MAINTENANCE}, 522 {0x3232, SIERRA_CREQ_FSMCLK_SEL}, 523 {0x8452, SIERRA_CTLELUT_CTRL}, 524 {0x4121, SIERRA_DFE_ECMP_RATESEL}, 525 {0x4121, SIERRA_DFE_SMP_RATESEL}, 526 {0x9999, SIERRA_DEQ_VGATUNE_CTRL}, 527 {0x0330, SIERRA_TMRVAL_MODE0}, 528 {0x01FF, SIERRA_PICNT_MODE1}, 529 {0x0009, SIERRA_CPI_OUTBUF_RATESEL}, 530 {0x000F, SIERRA_LFPSFILT_NS}, 531 {0x0009, SIERRA_LFPSFILT_RD}, 532 {0x0001, SIERRA_LFPSFILT_MP}, 533 {0x8013, SIERRA_SDFILT_H2L_A}, 534 {0x0400, SIERRA_TMRVAL_MODE1}, 535 }; 536 537 static struct cdns_reg_pairs cdns_pcie_regs[] = { 538 /* 539 * Write PCIe configuration parameters to the PHY. 540 * These values are specific to this specific hardware 541 * configuration. 542 */ 543 {0x891f, SIERRA_DET_STANDEC_D}, 544 {0x0053, SIERRA_DET_STANDEC_E}, 545 {0x0400, SIERRA_TMRVAL_MODE2}, 546 {0x0200, SIERRA_TMRVAL_MODE3}, 547 }; 548 549 static const struct cdns_sierra_data cdns_map_sierra = { 550 SIERRA_MACRO_ID, 551 0x2, 552 0x2, 553 ARRAY_SIZE(cdns_pcie_regs), 554 ARRAY_SIZE(cdns_usb_regs), 555 cdns_pcie_regs, 556 cdns_usb_regs 557 }; 558 559 static const struct cdns_sierra_data cdns_ti_map_sierra = { 560 SIERRA_MACRO_ID, 561 0x0, 562 0x1, 563 ARRAY_SIZE(cdns_pcie_regs), 564 ARRAY_SIZE(cdns_usb_regs), 565 cdns_pcie_regs, 566 cdns_usb_regs 567 }; 568 569 static const struct of_device_id cdns_sierra_id_table[] = { 570 { 571 .compatible = "cdns,sierra-phy-t0", 572 .data = &cdns_map_sierra, 573 }, 574 { 575 .compatible = "ti,sierra-phy-t0", 576 .data = &cdns_ti_map_sierra, 577 }, 578 {} 579 }; 580 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 581 582 static struct platform_driver cdns_sierra_driver = { 583 .probe = cdns_sierra_phy_probe, 584 .remove = cdns_sierra_phy_remove, 585 .driver = { 586 .name = "cdns-sierra-phy", 587 .of_match_table = cdns_sierra_id_table, 588 }, 589 }; 590 module_platform_driver(cdns_sierra_driver); 591 592 MODULE_ALIAS("platform:cdns_sierra"); 593 MODULE_AUTHOR("Cadence Design Systems"); 594 MODULE_DESCRIPTION("CDNS sierra phy driver"); 595 MODULE_LICENSE("GPL v2"); 596