1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <dt-bindings/phy/phy.h> 23 24 /* PHY register offsets */ 25 #define SIERRA_COMMON_CDB_OFFSET 0x0 26 #define SIERRA_MACRO_ID_REG 0x0 27 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 28 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 29 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 30 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 31 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 32 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 33 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 34 35 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 36 ((0x4000 << (block_offset)) + \ 37 (((ln) << 9) << (reg_offset))) 38 39 #define SIERRA_DET_STANDEC_A_PREG 0x000 40 #define SIERRA_DET_STANDEC_B_PREG 0x001 41 #define SIERRA_DET_STANDEC_C_PREG 0x002 42 #define SIERRA_DET_STANDEC_D_PREG 0x003 43 #define SIERRA_DET_STANDEC_E_PREG 0x004 44 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 45 #define SIERRA_PSM_A0IN_TMR_PREG 0x009 46 #define SIERRA_PSM_DIAG_PREG 0x015 47 #define SIERRA_PSC_TX_A0_PREG 0x028 48 #define SIERRA_PSC_TX_A1_PREG 0x029 49 #define SIERRA_PSC_TX_A2_PREG 0x02A 50 #define SIERRA_PSC_TX_A3_PREG 0x02B 51 #define SIERRA_PSC_RX_A0_PREG 0x030 52 #define SIERRA_PSC_RX_A1_PREG 0x031 53 #define SIERRA_PSC_RX_A2_PREG 0x032 54 #define SIERRA_PSC_RX_A3_PREG 0x033 55 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 56 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 57 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 58 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 59 #define SIERRA_DFE_BIASTRIM_PREG 0x04C 60 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 61 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 62 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 63 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 64 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 65 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 66 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 67 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 68 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 69 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 70 #define SIERRA_CREQ_SPARE_PREG 0x096 71 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 72 #define SIERRA_CTLELUT_CTRL_PREG 0x098 73 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 74 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 75 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 76 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 77 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 78 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 79 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 80 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 81 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 82 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 83 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 84 #define SIERRA_DEQ_GLUT0 0x0E8 85 #define SIERRA_DEQ_GLUT1 0x0E9 86 #define SIERRA_DEQ_GLUT2 0x0EA 87 #define SIERRA_DEQ_GLUT3 0x0EB 88 #define SIERRA_DEQ_GLUT4 0x0EC 89 #define SIERRA_DEQ_GLUT5 0x0ED 90 #define SIERRA_DEQ_GLUT6 0x0EE 91 #define SIERRA_DEQ_GLUT7 0x0EF 92 #define SIERRA_DEQ_GLUT8 0x0F0 93 #define SIERRA_DEQ_GLUT9 0x0F1 94 #define SIERRA_DEQ_GLUT10 0x0F2 95 #define SIERRA_DEQ_GLUT11 0x0F3 96 #define SIERRA_DEQ_GLUT12 0x0F4 97 #define SIERRA_DEQ_GLUT13 0x0F5 98 #define SIERRA_DEQ_GLUT14 0x0F6 99 #define SIERRA_DEQ_GLUT15 0x0F7 100 #define SIERRA_DEQ_GLUT16 0x0F8 101 #define SIERRA_DEQ_ALUT0 0x108 102 #define SIERRA_DEQ_ALUT1 0x109 103 #define SIERRA_DEQ_ALUT2 0x10A 104 #define SIERRA_DEQ_ALUT3 0x10B 105 #define SIERRA_DEQ_ALUT4 0x10C 106 #define SIERRA_DEQ_ALUT5 0x10D 107 #define SIERRA_DEQ_ALUT6 0x10E 108 #define SIERRA_DEQ_ALUT7 0x10F 109 #define SIERRA_DEQ_ALUT8 0x110 110 #define SIERRA_DEQ_ALUT9 0x111 111 #define SIERRA_DEQ_ALUT10 0x112 112 #define SIERRA_DEQ_ALUT11 0x113 113 #define SIERRA_DEQ_ALUT12 0x114 114 #define SIERRA_DEQ_ALUT13 0x115 115 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 116 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 117 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 118 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 119 #define SIERRA_DEQ_PICTRL_PREG 0x161 120 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 121 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 122 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 123 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 124 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 125 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 126 #define SIERRA_LFPSFILT_NS_PREG 0x18A 127 #define SIERRA_LFPSFILT_RD_PREG 0x18B 128 #define SIERRA_LFPSFILT_MP_PREG 0x18C 129 #define SIERRA_SIGDET_SUPPORT_PREG 0x190 130 #define SIERRA_SDFILT_H2L_A_PREG 0x191 131 #define SIERRA_SDFILT_L2H_PREG 0x193 132 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 133 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 134 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 135 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 136 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 137 138 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ 139 (0xc000 << (block_offset)) 140 #define SIERRA_PHY_PLL_CFG 0xe 141 142 #define SIERRA_MACRO_ID 0x00007364 143 #define SIERRA_MAX_LANES 4 144 145 static const struct reg_field macro_id_type = 146 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 147 static const struct reg_field phy_pll_cfg_1 = 148 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 149 150 struct cdns_sierra_inst { 151 struct phy *phy; 152 u32 phy_type; 153 u32 num_lanes; 154 u32 mlane; 155 struct reset_control *lnk_rst; 156 }; 157 158 struct cdns_reg_pairs { 159 u16 val; 160 u32 off; 161 }; 162 163 struct cdns_sierra_data { 164 u32 id_value; 165 u8 block_offset_shift; 166 u8 reg_offset_shift; 167 u32 pcie_cmn_regs; 168 u32 pcie_ln_regs; 169 u32 usb_cmn_regs; 170 u32 usb_ln_regs; 171 struct cdns_reg_pairs *pcie_cmn_vals; 172 struct cdns_reg_pairs *pcie_ln_vals; 173 struct cdns_reg_pairs *usb_cmn_vals; 174 struct cdns_reg_pairs *usb_ln_vals; 175 }; 176 177 struct cdns_regmap_cdb_context { 178 struct device *dev; 179 void __iomem *base; 180 u8 reg_offset_shift; 181 }; 182 183 struct cdns_sierra_phy { 184 struct device *dev; 185 struct regmap *regmap; 186 struct cdns_sierra_data *init_data; 187 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 188 struct reset_control *phy_rst; 189 struct reset_control *apb_rst; 190 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 191 struct regmap *regmap_phy_config_ctrl; 192 struct regmap *regmap_common_cdb; 193 struct regmap_field *macro_id_type; 194 struct regmap_field *phy_pll_cfg_1; 195 struct clk *clk; 196 int nsubnodes; 197 bool autoconf; 198 }; 199 200 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 201 { 202 struct cdns_regmap_cdb_context *ctx = context; 203 u32 offset = reg << ctx->reg_offset_shift; 204 205 writew(val, ctx->base + offset); 206 207 return 0; 208 } 209 210 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 211 { 212 struct cdns_regmap_cdb_context *ctx = context; 213 u32 offset = reg << ctx->reg_offset_shift; 214 215 *val = readw(ctx->base + offset); 216 return 0; 217 } 218 219 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 220 { \ 221 .name = "sierra_lane" n "_cdb", \ 222 .reg_stride = 1, \ 223 .fast_io = true, \ 224 .reg_write = cdns_regmap_write, \ 225 .reg_read = cdns_regmap_read, \ 226 } 227 228 static struct regmap_config cdns_sierra_lane_cdb_config[] = { 229 SIERRA_LANE_CDB_REGMAP_CONF("0"), 230 SIERRA_LANE_CDB_REGMAP_CONF("1"), 231 SIERRA_LANE_CDB_REGMAP_CONF("2"), 232 SIERRA_LANE_CDB_REGMAP_CONF("3"), 233 }; 234 235 static struct regmap_config cdns_sierra_common_cdb_config = { 236 .name = "sierra_common_cdb", 237 .reg_stride = 1, 238 .fast_io = true, 239 .reg_write = cdns_regmap_write, 240 .reg_read = cdns_regmap_read, 241 }; 242 243 static struct regmap_config cdns_sierra_phy_config_ctrl_config = { 244 .name = "sierra_phy_config_ctrl", 245 .reg_stride = 1, 246 .fast_io = true, 247 .reg_write = cdns_regmap_write, 248 .reg_read = cdns_regmap_read, 249 }; 250 251 static int cdns_sierra_phy_init(struct phy *gphy) 252 { 253 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 254 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 255 struct regmap *regmap = phy->regmap; 256 int i, j; 257 struct cdns_reg_pairs *cmn_vals, *ln_vals; 258 u32 num_cmn_regs, num_ln_regs; 259 260 /* Initialise the PHY registers, unless auto configured */ 261 if (phy->autoconf) 262 return 0; 263 264 if (ins->phy_type == PHY_TYPE_PCIE) { 265 num_cmn_regs = phy->init_data->pcie_cmn_regs; 266 num_ln_regs = phy->init_data->pcie_ln_regs; 267 cmn_vals = phy->init_data->pcie_cmn_vals; 268 ln_vals = phy->init_data->pcie_ln_vals; 269 } else if (ins->phy_type == PHY_TYPE_USB3) { 270 num_cmn_regs = phy->init_data->usb_cmn_regs; 271 num_ln_regs = phy->init_data->usb_ln_regs; 272 cmn_vals = phy->init_data->usb_cmn_vals; 273 ln_vals = phy->init_data->usb_ln_vals; 274 } else { 275 return -EINVAL; 276 } 277 278 regmap = phy->regmap_common_cdb; 279 for (j = 0; j < num_cmn_regs ; j++) 280 regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); 281 282 for (i = 0; i < ins->num_lanes; i++) { 283 for (j = 0; j < num_ln_regs ; j++) { 284 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 285 regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); 286 } 287 } 288 289 return 0; 290 } 291 292 static int cdns_sierra_phy_on(struct phy *gphy) 293 { 294 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 295 296 /* Take the PHY lane group out of reset */ 297 return reset_control_deassert(ins->lnk_rst); 298 } 299 300 static int cdns_sierra_phy_off(struct phy *gphy) 301 { 302 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 303 304 return reset_control_assert(ins->lnk_rst); 305 } 306 307 static const struct phy_ops ops = { 308 .init = cdns_sierra_phy_init, 309 .power_on = cdns_sierra_phy_on, 310 .power_off = cdns_sierra_phy_off, 311 .owner = THIS_MODULE, 312 }; 313 314 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 315 struct device_node *child) 316 { 317 if (of_property_read_u32(child, "reg", &inst->mlane)) 318 return -EINVAL; 319 320 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 321 return -EINVAL; 322 323 if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type)) 324 return -EINVAL; 325 326 return 0; 327 } 328 329 static const struct of_device_id cdns_sierra_id_table[]; 330 331 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 332 u32 block_offset, u8 reg_offset_shift, 333 const struct regmap_config *config) 334 { 335 struct cdns_regmap_cdb_context *ctx; 336 337 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 338 if (!ctx) 339 return ERR_PTR(-ENOMEM); 340 341 ctx->dev = dev; 342 ctx->base = base + block_offset; 343 ctx->reg_offset_shift = reg_offset_shift; 344 345 return devm_regmap_init(dev, NULL, ctx, config); 346 } 347 348 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 349 { 350 struct device *dev = sp->dev; 351 struct regmap_field *field; 352 struct regmap *regmap; 353 354 regmap = sp->regmap_common_cdb; 355 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 356 if (IS_ERR(field)) { 357 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 358 return PTR_ERR(field); 359 } 360 sp->macro_id_type = field; 361 362 regmap = sp->regmap_phy_config_ctrl; 363 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 364 if (IS_ERR(field)) { 365 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 366 return PTR_ERR(field); 367 } 368 sp->phy_pll_cfg_1 = field; 369 370 return 0; 371 } 372 373 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 374 void __iomem *base, u8 block_offset_shift, 375 u8 reg_offset_shift) 376 { 377 struct device *dev = sp->dev; 378 struct regmap *regmap; 379 u32 block_offset; 380 int i; 381 382 for (i = 0; i < SIERRA_MAX_LANES; i++) { 383 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 384 reg_offset_shift); 385 regmap = cdns_regmap_init(dev, base, block_offset, 386 reg_offset_shift, 387 &cdns_sierra_lane_cdb_config[i]); 388 if (IS_ERR(regmap)) { 389 dev_err(dev, "Failed to init lane CDB regmap\n"); 390 return PTR_ERR(regmap); 391 } 392 sp->regmap_lane_cdb[i] = regmap; 393 } 394 395 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 396 reg_offset_shift, 397 &cdns_sierra_common_cdb_config); 398 if (IS_ERR(regmap)) { 399 dev_err(dev, "Failed to init common CDB regmap\n"); 400 return PTR_ERR(regmap); 401 } 402 sp->regmap_common_cdb = regmap; 403 404 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); 405 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 406 &cdns_sierra_phy_config_ctrl_config); 407 if (IS_ERR(regmap)) { 408 dev_err(dev, "Failed to init PHY config and control regmap\n"); 409 return PTR_ERR(regmap); 410 } 411 sp->regmap_phy_config_ctrl = regmap; 412 413 return 0; 414 } 415 416 static int cdns_sierra_phy_probe(struct platform_device *pdev) 417 { 418 struct cdns_sierra_phy *sp; 419 struct phy_provider *phy_provider; 420 struct device *dev = &pdev->dev; 421 const struct of_device_id *match; 422 struct cdns_sierra_data *data; 423 unsigned int id_value; 424 struct resource *res; 425 int i, ret, node = 0; 426 void __iomem *base; 427 struct device_node *dn = dev->of_node, *child; 428 429 if (of_get_child_count(dn) == 0) 430 return -ENODEV; 431 432 /* Get init data for this PHY */ 433 match = of_match_device(cdns_sierra_id_table, dev); 434 if (!match) 435 return -EINVAL; 436 437 data = (struct cdns_sierra_data *)match->data; 438 439 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 440 if (!sp) 441 return -ENOMEM; 442 dev_set_drvdata(dev, sp); 443 sp->dev = dev; 444 sp->init_data = data; 445 446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 447 base = devm_ioremap_resource(dev, res); 448 if (IS_ERR(base)) { 449 dev_err(dev, "missing \"reg\"\n"); 450 return PTR_ERR(base); 451 } 452 453 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 454 data->reg_offset_shift); 455 if (ret) 456 return ret; 457 458 ret = cdns_regfield_init(sp); 459 if (ret) 460 return ret; 461 462 platform_set_drvdata(pdev, sp); 463 464 sp->clk = devm_clk_get_optional(dev, "phy_clk"); 465 if (IS_ERR(sp->clk)) { 466 dev_err(dev, "failed to get clock phy_clk\n"); 467 return PTR_ERR(sp->clk); 468 } 469 470 sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); 471 if (IS_ERR(sp->phy_rst)) { 472 dev_err(dev, "failed to get reset\n"); 473 return PTR_ERR(sp->phy_rst); 474 } 475 476 sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); 477 if (IS_ERR(sp->apb_rst)) { 478 dev_err(dev, "failed to get apb reset\n"); 479 return PTR_ERR(sp->apb_rst); 480 } 481 482 ret = clk_prepare_enable(sp->clk); 483 if (ret) 484 return ret; 485 486 /* Enable APB */ 487 reset_control_deassert(sp->apb_rst); 488 489 /* Check that PHY is present */ 490 regmap_field_read(sp->macro_id_type, &id_value); 491 if (sp->init_data->id_value != id_value) { 492 ret = -EINVAL; 493 goto clk_disable; 494 } 495 496 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 497 498 for_each_available_child_of_node(dn, child) { 499 struct phy *gphy; 500 501 sp->phys[node].lnk_rst = 502 of_reset_control_array_get_exclusive(child); 503 504 if (IS_ERR(sp->phys[node].lnk_rst)) { 505 dev_err(dev, "failed to get reset %s\n", 506 child->full_name); 507 ret = PTR_ERR(sp->phys[node].lnk_rst); 508 goto put_child2; 509 } 510 511 if (!sp->autoconf) { 512 ret = cdns_sierra_get_optional(&sp->phys[node], child); 513 if (ret) { 514 dev_err(dev, "missing property in node %s\n", 515 child->name); 516 goto put_child; 517 } 518 } 519 520 gphy = devm_phy_create(dev, child, &ops); 521 522 if (IS_ERR(gphy)) { 523 ret = PTR_ERR(gphy); 524 goto put_child; 525 } 526 sp->phys[node].phy = gphy; 527 phy_set_drvdata(gphy, &sp->phys[node]); 528 529 node++; 530 } 531 sp->nsubnodes = node; 532 533 /* If more than one subnode, configure the PHY as multilink */ 534 if (!sp->autoconf && sp->nsubnodes > 1) 535 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 536 537 pm_runtime_enable(dev); 538 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 539 reset_control_deassert(sp->phy_rst); 540 return PTR_ERR_OR_ZERO(phy_provider); 541 542 put_child: 543 node++; 544 put_child2: 545 for (i = 0; i < node; i++) 546 reset_control_put(sp->phys[i].lnk_rst); 547 of_node_put(child); 548 clk_disable: 549 clk_disable_unprepare(sp->clk); 550 reset_control_assert(sp->apb_rst); 551 return ret; 552 } 553 554 static int cdns_sierra_phy_remove(struct platform_device *pdev) 555 { 556 struct cdns_sierra_phy *phy = dev_get_drvdata(pdev->dev.parent); 557 int i; 558 559 reset_control_assert(phy->phy_rst); 560 reset_control_assert(phy->apb_rst); 561 pm_runtime_disable(&pdev->dev); 562 563 /* 564 * The device level resets will be put automatically. 565 * Need to put the subnode resets here though. 566 */ 567 for (i = 0; i < phy->nsubnodes; i++) { 568 reset_control_assert(phy->phys[i].lnk_rst); 569 reset_control_put(phy->phys[i].lnk_rst); 570 } 571 return 0; 572 } 573 574 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 575 static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 576 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 577 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 578 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 579 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 580 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 581 }; 582 583 /* refclk100MHz_32b_PCIe_ln_ext_ssc */ 584 static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 585 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 586 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 587 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 588 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 589 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 590 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 591 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} 592 }; 593 594 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 595 static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 596 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 597 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 598 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 599 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 600 }; 601 602 /* refclk100MHz_20b_USB_ln_ext_ssc */ 603 static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 604 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 605 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 606 {0x00A5, SIERRA_DET_STANDEC_C_PREG}, 607 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 608 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 609 {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 610 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 611 {0xCF00, SIERRA_PSM_DIAG_PREG}, 612 {0x001F, SIERRA_PSC_TX_A0_PREG}, 613 {0x0007, SIERRA_PSC_TX_A1_PREG}, 614 {0x0003, SIERRA_PSC_TX_A2_PREG}, 615 {0x0003, SIERRA_PSC_TX_A3_PREG}, 616 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 617 {0x0619, SIERRA_PSC_RX_A1_PREG}, 618 {0x0003, SIERRA_PSC_RX_A2_PREG}, 619 {0x0001, SIERRA_PSC_RX_A3_PREG}, 620 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 621 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 622 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 623 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 624 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 625 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 626 {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG}, 627 {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 628 {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 629 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 630 {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 631 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 632 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 633 {0x8000, SIERRA_CREQ_SPARE_PREG}, 634 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 635 {0x8453, SIERRA_CTLELUT_CTRL_PREG}, 636 {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG}, 637 {0x4110, SIERRA_DFE_SMP_RATESEL_PREG}, 638 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 639 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 640 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 641 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 642 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 643 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 644 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 645 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 646 {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 647 {0x0014, SIERRA_DEQ_GLUT0}, 648 {0x0014, SIERRA_DEQ_GLUT1}, 649 {0x0014, SIERRA_DEQ_GLUT2}, 650 {0x0014, SIERRA_DEQ_GLUT3}, 651 {0x0014, SIERRA_DEQ_GLUT4}, 652 {0x0014, SIERRA_DEQ_GLUT5}, 653 {0x0014, SIERRA_DEQ_GLUT6}, 654 {0x0014, SIERRA_DEQ_GLUT7}, 655 {0x0014, SIERRA_DEQ_GLUT8}, 656 {0x0014, SIERRA_DEQ_GLUT9}, 657 {0x0014, SIERRA_DEQ_GLUT10}, 658 {0x0014, SIERRA_DEQ_GLUT11}, 659 {0x0014, SIERRA_DEQ_GLUT12}, 660 {0x0014, SIERRA_DEQ_GLUT13}, 661 {0x0014, SIERRA_DEQ_GLUT14}, 662 {0x0014, SIERRA_DEQ_GLUT15}, 663 {0x0014, SIERRA_DEQ_GLUT16}, 664 {0x0BAE, SIERRA_DEQ_ALUT0}, 665 {0x0AEB, SIERRA_DEQ_ALUT1}, 666 {0x0A28, SIERRA_DEQ_ALUT2}, 667 {0x0965, SIERRA_DEQ_ALUT3}, 668 {0x08A2, SIERRA_DEQ_ALUT4}, 669 {0x07DF, SIERRA_DEQ_ALUT5}, 670 {0x071C, SIERRA_DEQ_ALUT6}, 671 {0x0659, SIERRA_DEQ_ALUT7}, 672 {0x0596, SIERRA_DEQ_ALUT8}, 673 {0x0514, SIERRA_DEQ_ALUT9}, 674 {0x0492, SIERRA_DEQ_ALUT10}, 675 {0x0410, SIERRA_DEQ_ALUT11}, 676 {0x038E, SIERRA_DEQ_ALUT12}, 677 {0x030C, SIERRA_DEQ_ALUT13}, 678 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 679 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 680 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 681 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 682 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 683 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 684 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 685 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 686 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 687 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 688 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 689 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 690 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 691 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 692 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 693 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 694 {0x8009, SIERRA_SDFILT_L2H_PREG}, 695 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 696 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 697 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 698 }; 699 700 static const struct cdns_sierra_data cdns_map_sierra = { 701 SIERRA_MACRO_ID, 702 0x2, 703 0x2, 704 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 705 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 706 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 707 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 708 cdns_pcie_cmn_regs_ext_ssc, 709 cdns_pcie_ln_regs_ext_ssc, 710 cdns_usb_cmn_regs_ext_ssc, 711 cdns_usb_ln_regs_ext_ssc, 712 }; 713 714 static const struct cdns_sierra_data cdns_ti_map_sierra = { 715 SIERRA_MACRO_ID, 716 0x0, 717 0x1, 718 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 719 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 720 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 721 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 722 cdns_pcie_cmn_regs_ext_ssc, 723 cdns_pcie_ln_regs_ext_ssc, 724 cdns_usb_cmn_regs_ext_ssc, 725 cdns_usb_ln_regs_ext_ssc, 726 }; 727 728 static const struct of_device_id cdns_sierra_id_table[] = { 729 { 730 .compatible = "cdns,sierra-phy-t0", 731 .data = &cdns_map_sierra, 732 }, 733 { 734 .compatible = "ti,sierra-phy-t0", 735 .data = &cdns_ti_map_sierra, 736 }, 737 {} 738 }; 739 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 740 741 static struct platform_driver cdns_sierra_driver = { 742 .probe = cdns_sierra_phy_probe, 743 .remove = cdns_sierra_phy_remove, 744 .driver = { 745 .name = "cdns-sierra-phy", 746 .of_match_table = cdns_sierra_id_table, 747 }, 748 }; 749 module_platform_driver(cdns_sierra_driver); 750 751 MODULE_ALIAS("platform:cdns_sierra"); 752 MODULE_AUTHOR("Cadence Design Systems"); 753 MODULE_DESCRIPTION("CDNS sierra phy driver"); 754 MODULE_LICENSE("GPL v2"); 755