1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <dt-bindings/phy/phy.h> 23 24 /* PHY register offsets */ 25 #define SIERRA_COMMON_CDB_OFFSET 0x0 26 #define SIERRA_MACRO_ID_REG 0x0 27 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 28 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 29 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 30 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 31 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 32 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 33 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 34 35 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 36 ((0x4000 << (block_offset)) + \ 37 (((ln) << 9) << (reg_offset))) 38 39 #define SIERRA_DET_STANDEC_A_PREG 0x000 40 #define SIERRA_DET_STANDEC_B_PREG 0x001 41 #define SIERRA_DET_STANDEC_C_PREG 0x002 42 #define SIERRA_DET_STANDEC_D_PREG 0x003 43 #define SIERRA_DET_STANDEC_E_PREG 0x004 44 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 45 #define SIERRA_PSM_A0IN_TMR_PREG 0x009 46 #define SIERRA_PSM_DIAG_PREG 0x015 47 #define SIERRA_PSC_TX_A0_PREG 0x028 48 #define SIERRA_PSC_TX_A1_PREG 0x029 49 #define SIERRA_PSC_TX_A2_PREG 0x02A 50 #define SIERRA_PSC_TX_A3_PREG 0x02B 51 #define SIERRA_PSC_RX_A0_PREG 0x030 52 #define SIERRA_PSC_RX_A1_PREG 0x031 53 #define SIERRA_PSC_RX_A2_PREG 0x032 54 #define SIERRA_PSC_RX_A3_PREG 0x033 55 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 56 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 57 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 58 #define SIERRA_PLLCTRL_STATUS_PREG 0x044 59 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 60 #define SIERRA_DFE_BIASTRIM_PREG 0x04C 61 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 62 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 63 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 64 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 65 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 66 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 67 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 68 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 69 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 70 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 71 #define SIERRA_CREQ_SPARE_PREG 0x096 72 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 73 #define SIERRA_CTLELUT_CTRL_PREG 0x098 74 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 75 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 76 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 77 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 78 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 79 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 80 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 81 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 82 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 83 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 84 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 85 #define SIERRA_DEQ_GLUT0 0x0E8 86 #define SIERRA_DEQ_GLUT1 0x0E9 87 #define SIERRA_DEQ_GLUT2 0x0EA 88 #define SIERRA_DEQ_GLUT3 0x0EB 89 #define SIERRA_DEQ_GLUT4 0x0EC 90 #define SIERRA_DEQ_GLUT5 0x0ED 91 #define SIERRA_DEQ_GLUT6 0x0EE 92 #define SIERRA_DEQ_GLUT7 0x0EF 93 #define SIERRA_DEQ_GLUT8 0x0F0 94 #define SIERRA_DEQ_GLUT9 0x0F1 95 #define SIERRA_DEQ_GLUT10 0x0F2 96 #define SIERRA_DEQ_GLUT11 0x0F3 97 #define SIERRA_DEQ_GLUT12 0x0F4 98 #define SIERRA_DEQ_GLUT13 0x0F5 99 #define SIERRA_DEQ_GLUT14 0x0F6 100 #define SIERRA_DEQ_GLUT15 0x0F7 101 #define SIERRA_DEQ_GLUT16 0x0F8 102 #define SIERRA_DEQ_ALUT0 0x108 103 #define SIERRA_DEQ_ALUT1 0x109 104 #define SIERRA_DEQ_ALUT2 0x10A 105 #define SIERRA_DEQ_ALUT3 0x10B 106 #define SIERRA_DEQ_ALUT4 0x10C 107 #define SIERRA_DEQ_ALUT5 0x10D 108 #define SIERRA_DEQ_ALUT6 0x10E 109 #define SIERRA_DEQ_ALUT7 0x10F 110 #define SIERRA_DEQ_ALUT8 0x110 111 #define SIERRA_DEQ_ALUT9 0x111 112 #define SIERRA_DEQ_ALUT10 0x112 113 #define SIERRA_DEQ_ALUT11 0x113 114 #define SIERRA_DEQ_ALUT12 0x114 115 #define SIERRA_DEQ_ALUT13 0x115 116 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 117 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 118 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 119 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 120 #define SIERRA_DEQ_PICTRL_PREG 0x161 121 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 122 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 123 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 124 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 125 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 126 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 127 #define SIERRA_LFPSFILT_NS_PREG 0x18A 128 #define SIERRA_LFPSFILT_RD_PREG 0x18B 129 #define SIERRA_LFPSFILT_MP_PREG 0x18C 130 #define SIERRA_SIGDET_SUPPORT_PREG 0x190 131 #define SIERRA_SDFILT_H2L_A_PREG 0x191 132 #define SIERRA_SDFILT_L2H_PREG 0x193 133 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 134 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 135 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 136 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 137 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 138 139 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ 140 (0xc000 << (block_offset)) 141 #define SIERRA_PHY_PLL_CFG 0xe 142 143 #define SIERRA_MACRO_ID 0x00007364 144 #define SIERRA_MAX_LANES 16 145 #define PLL_LOCK_TIME 100000 146 147 static const struct reg_field macro_id_type = 148 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 149 static const struct reg_field phy_pll_cfg_1 = 150 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 151 static const struct reg_field pllctrl_lock = 152 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 153 154 struct cdns_sierra_inst { 155 struct phy *phy; 156 u32 phy_type; 157 u32 num_lanes; 158 u32 mlane; 159 struct reset_control *lnk_rst; 160 }; 161 162 struct cdns_reg_pairs { 163 u16 val; 164 u32 off; 165 }; 166 167 struct cdns_sierra_data { 168 u32 id_value; 169 u8 block_offset_shift; 170 u8 reg_offset_shift; 171 u32 pcie_cmn_regs; 172 u32 pcie_ln_regs; 173 u32 usb_cmn_regs; 174 u32 usb_ln_regs; 175 struct cdns_reg_pairs *pcie_cmn_vals; 176 struct cdns_reg_pairs *pcie_ln_vals; 177 struct cdns_reg_pairs *usb_cmn_vals; 178 struct cdns_reg_pairs *usb_ln_vals; 179 }; 180 181 struct cdns_regmap_cdb_context { 182 struct device *dev; 183 void __iomem *base; 184 u8 reg_offset_shift; 185 }; 186 187 struct cdns_sierra_phy { 188 struct device *dev; 189 struct regmap *regmap; 190 struct cdns_sierra_data *init_data; 191 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 192 struct reset_control *phy_rst; 193 struct reset_control *apb_rst; 194 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 195 struct regmap *regmap_phy_config_ctrl; 196 struct regmap *regmap_common_cdb; 197 struct regmap_field *macro_id_type; 198 struct regmap_field *phy_pll_cfg_1; 199 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 200 struct clk *clk; 201 int nsubnodes; 202 u32 num_lanes; 203 bool autoconf; 204 }; 205 206 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 207 { 208 struct cdns_regmap_cdb_context *ctx = context; 209 u32 offset = reg << ctx->reg_offset_shift; 210 211 writew(val, ctx->base + offset); 212 213 return 0; 214 } 215 216 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 217 { 218 struct cdns_regmap_cdb_context *ctx = context; 219 u32 offset = reg << ctx->reg_offset_shift; 220 221 *val = readw(ctx->base + offset); 222 return 0; 223 } 224 225 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 226 { \ 227 .name = "sierra_lane" n "_cdb", \ 228 .reg_stride = 1, \ 229 .fast_io = true, \ 230 .reg_write = cdns_regmap_write, \ 231 .reg_read = cdns_regmap_read, \ 232 } 233 234 static struct regmap_config cdns_sierra_lane_cdb_config[] = { 235 SIERRA_LANE_CDB_REGMAP_CONF("0"), 236 SIERRA_LANE_CDB_REGMAP_CONF("1"), 237 SIERRA_LANE_CDB_REGMAP_CONF("2"), 238 SIERRA_LANE_CDB_REGMAP_CONF("3"), 239 SIERRA_LANE_CDB_REGMAP_CONF("4"), 240 SIERRA_LANE_CDB_REGMAP_CONF("5"), 241 SIERRA_LANE_CDB_REGMAP_CONF("6"), 242 SIERRA_LANE_CDB_REGMAP_CONF("7"), 243 SIERRA_LANE_CDB_REGMAP_CONF("8"), 244 SIERRA_LANE_CDB_REGMAP_CONF("9"), 245 SIERRA_LANE_CDB_REGMAP_CONF("10"), 246 SIERRA_LANE_CDB_REGMAP_CONF("11"), 247 SIERRA_LANE_CDB_REGMAP_CONF("12"), 248 SIERRA_LANE_CDB_REGMAP_CONF("13"), 249 SIERRA_LANE_CDB_REGMAP_CONF("14"), 250 SIERRA_LANE_CDB_REGMAP_CONF("15"), 251 }; 252 253 static struct regmap_config cdns_sierra_common_cdb_config = { 254 .name = "sierra_common_cdb", 255 .reg_stride = 1, 256 .fast_io = true, 257 .reg_write = cdns_regmap_write, 258 .reg_read = cdns_regmap_read, 259 }; 260 261 static struct regmap_config cdns_sierra_phy_config_ctrl_config = { 262 .name = "sierra_phy_config_ctrl", 263 .reg_stride = 1, 264 .fast_io = true, 265 .reg_write = cdns_regmap_write, 266 .reg_read = cdns_regmap_read, 267 }; 268 269 static int cdns_sierra_phy_init(struct phy *gphy) 270 { 271 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 272 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 273 struct regmap *regmap = phy->regmap; 274 int i, j; 275 struct cdns_reg_pairs *cmn_vals, *ln_vals; 276 u32 num_cmn_regs, num_ln_regs; 277 278 /* Initialise the PHY registers, unless auto configured */ 279 if (phy->autoconf) 280 return 0; 281 282 if (ins->phy_type == PHY_TYPE_PCIE) { 283 num_cmn_regs = phy->init_data->pcie_cmn_regs; 284 num_ln_regs = phy->init_data->pcie_ln_regs; 285 cmn_vals = phy->init_data->pcie_cmn_vals; 286 ln_vals = phy->init_data->pcie_ln_vals; 287 } else if (ins->phy_type == PHY_TYPE_USB3) { 288 num_cmn_regs = phy->init_data->usb_cmn_regs; 289 num_ln_regs = phy->init_data->usb_ln_regs; 290 cmn_vals = phy->init_data->usb_cmn_vals; 291 ln_vals = phy->init_data->usb_ln_vals; 292 } else { 293 return -EINVAL; 294 } 295 296 regmap = phy->regmap_common_cdb; 297 for (j = 0; j < num_cmn_regs ; j++) 298 regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); 299 300 for (i = 0; i < ins->num_lanes; i++) { 301 for (j = 0; j < num_ln_regs ; j++) { 302 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 303 regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); 304 } 305 } 306 307 return 0; 308 } 309 310 static int cdns_sierra_phy_on(struct phy *gphy) 311 { 312 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 313 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 314 struct device *dev = sp->dev; 315 u32 val; 316 int ret; 317 318 /* Take the PHY lane group out of reset */ 319 ret = reset_control_deassert(ins->lnk_rst); 320 if (ret) { 321 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 322 return ret; 323 } 324 325 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 326 val, val, 1000, PLL_LOCK_TIME); 327 if (ret < 0) 328 dev_err(dev, "PLL lock of lane failed\n"); 329 330 return ret; 331 } 332 333 static int cdns_sierra_phy_off(struct phy *gphy) 334 { 335 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 336 337 return reset_control_assert(ins->lnk_rst); 338 } 339 340 static const struct phy_ops ops = { 341 .init = cdns_sierra_phy_init, 342 .power_on = cdns_sierra_phy_on, 343 .power_off = cdns_sierra_phy_off, 344 .owner = THIS_MODULE, 345 }; 346 347 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 348 struct device_node *child) 349 { 350 if (of_property_read_u32(child, "reg", &inst->mlane)) 351 return -EINVAL; 352 353 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 354 return -EINVAL; 355 356 if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type)) 357 return -EINVAL; 358 359 return 0; 360 } 361 362 static const struct of_device_id cdns_sierra_id_table[]; 363 364 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 365 u32 block_offset, u8 reg_offset_shift, 366 const struct regmap_config *config) 367 { 368 struct cdns_regmap_cdb_context *ctx; 369 370 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 371 if (!ctx) 372 return ERR_PTR(-ENOMEM); 373 374 ctx->dev = dev; 375 ctx->base = base + block_offset; 376 ctx->reg_offset_shift = reg_offset_shift; 377 378 return devm_regmap_init(dev, NULL, ctx, config); 379 } 380 381 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 382 { 383 struct device *dev = sp->dev; 384 struct regmap_field *field; 385 struct regmap *regmap; 386 int i; 387 388 regmap = sp->regmap_common_cdb; 389 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 390 if (IS_ERR(field)) { 391 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 392 return PTR_ERR(field); 393 } 394 sp->macro_id_type = field; 395 396 regmap = sp->regmap_phy_config_ctrl; 397 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 398 if (IS_ERR(field)) { 399 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 400 return PTR_ERR(field); 401 } 402 sp->phy_pll_cfg_1 = field; 403 404 for (i = 0; i < SIERRA_MAX_LANES; i++) { 405 regmap = sp->regmap_lane_cdb[i]; 406 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 407 if (IS_ERR(field)) { 408 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 409 return PTR_ERR(field); 410 } 411 sp->pllctrl_lock[i] = field; 412 } 413 414 return 0; 415 } 416 417 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 418 void __iomem *base, u8 block_offset_shift, 419 u8 reg_offset_shift) 420 { 421 struct device *dev = sp->dev; 422 struct regmap *regmap; 423 u32 block_offset; 424 int i; 425 426 for (i = 0; i < SIERRA_MAX_LANES; i++) { 427 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 428 reg_offset_shift); 429 regmap = cdns_regmap_init(dev, base, block_offset, 430 reg_offset_shift, 431 &cdns_sierra_lane_cdb_config[i]); 432 if (IS_ERR(regmap)) { 433 dev_err(dev, "Failed to init lane CDB regmap\n"); 434 return PTR_ERR(regmap); 435 } 436 sp->regmap_lane_cdb[i] = regmap; 437 } 438 439 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 440 reg_offset_shift, 441 &cdns_sierra_common_cdb_config); 442 if (IS_ERR(regmap)) { 443 dev_err(dev, "Failed to init common CDB regmap\n"); 444 return PTR_ERR(regmap); 445 } 446 sp->regmap_common_cdb = regmap; 447 448 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); 449 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 450 &cdns_sierra_phy_config_ctrl_config); 451 if (IS_ERR(regmap)) { 452 dev_err(dev, "Failed to init PHY config and control regmap\n"); 453 return PTR_ERR(regmap); 454 } 455 sp->regmap_phy_config_ctrl = regmap; 456 457 return 0; 458 } 459 460 static int cdns_sierra_phy_probe(struct platform_device *pdev) 461 { 462 struct cdns_sierra_phy *sp; 463 struct phy_provider *phy_provider; 464 struct device *dev = &pdev->dev; 465 const struct of_device_id *match; 466 struct cdns_sierra_data *data; 467 unsigned int id_value; 468 struct resource *res; 469 int i, ret, node = 0; 470 void __iomem *base; 471 struct device_node *dn = dev->of_node, *child; 472 473 if (of_get_child_count(dn) == 0) 474 return -ENODEV; 475 476 /* Get init data for this PHY */ 477 match = of_match_device(cdns_sierra_id_table, dev); 478 if (!match) 479 return -EINVAL; 480 481 data = (struct cdns_sierra_data *)match->data; 482 483 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 484 if (!sp) 485 return -ENOMEM; 486 dev_set_drvdata(dev, sp); 487 sp->dev = dev; 488 sp->init_data = data; 489 490 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 491 base = devm_ioremap_resource(dev, res); 492 if (IS_ERR(base)) { 493 dev_err(dev, "missing \"reg\"\n"); 494 return PTR_ERR(base); 495 } 496 497 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 498 data->reg_offset_shift); 499 if (ret) 500 return ret; 501 502 ret = cdns_regfield_init(sp); 503 if (ret) 504 return ret; 505 506 platform_set_drvdata(pdev, sp); 507 508 sp->clk = devm_clk_get_optional(dev, "phy_clk"); 509 if (IS_ERR(sp->clk)) { 510 dev_err(dev, "failed to get clock phy_clk\n"); 511 return PTR_ERR(sp->clk); 512 } 513 514 sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); 515 if (IS_ERR(sp->phy_rst)) { 516 dev_err(dev, "failed to get reset\n"); 517 return PTR_ERR(sp->phy_rst); 518 } 519 520 sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); 521 if (IS_ERR(sp->apb_rst)) { 522 dev_err(dev, "failed to get apb reset\n"); 523 return PTR_ERR(sp->apb_rst); 524 } 525 526 ret = clk_prepare_enable(sp->clk); 527 if (ret) 528 return ret; 529 530 /* Enable APB */ 531 reset_control_deassert(sp->apb_rst); 532 533 /* Check that PHY is present */ 534 regmap_field_read(sp->macro_id_type, &id_value); 535 if (sp->init_data->id_value != id_value) { 536 ret = -EINVAL; 537 goto clk_disable; 538 } 539 540 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 541 542 for_each_available_child_of_node(dn, child) { 543 struct phy *gphy; 544 545 sp->phys[node].lnk_rst = 546 of_reset_control_array_get_exclusive(child); 547 548 if (IS_ERR(sp->phys[node].lnk_rst)) { 549 dev_err(dev, "failed to get reset %s\n", 550 child->full_name); 551 ret = PTR_ERR(sp->phys[node].lnk_rst); 552 goto put_child2; 553 } 554 555 if (!sp->autoconf) { 556 ret = cdns_sierra_get_optional(&sp->phys[node], child); 557 if (ret) { 558 dev_err(dev, "missing property in node %s\n", 559 child->name); 560 goto put_child; 561 } 562 } 563 564 sp->num_lanes += sp->phys[node].num_lanes; 565 566 gphy = devm_phy_create(dev, child, &ops); 567 568 if (IS_ERR(gphy)) { 569 ret = PTR_ERR(gphy); 570 goto put_child; 571 } 572 sp->phys[node].phy = gphy; 573 phy_set_drvdata(gphy, &sp->phys[node]); 574 575 node++; 576 } 577 sp->nsubnodes = node; 578 579 if (sp->num_lanes > SIERRA_MAX_LANES) { 580 dev_err(dev, "Invalid lane configuration\n"); 581 goto put_child2; 582 } 583 584 /* If more than one subnode, configure the PHY as multilink */ 585 if (!sp->autoconf && sp->nsubnodes > 1) 586 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 587 588 pm_runtime_enable(dev); 589 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 590 reset_control_deassert(sp->phy_rst); 591 return PTR_ERR_OR_ZERO(phy_provider); 592 593 put_child: 594 node++; 595 put_child2: 596 for (i = 0; i < node; i++) 597 reset_control_put(sp->phys[i].lnk_rst); 598 of_node_put(child); 599 clk_disable: 600 clk_disable_unprepare(sp->clk); 601 reset_control_assert(sp->apb_rst); 602 return ret; 603 } 604 605 static int cdns_sierra_phy_remove(struct platform_device *pdev) 606 { 607 struct cdns_sierra_phy *phy = dev_get_drvdata(pdev->dev.parent); 608 int i; 609 610 reset_control_assert(phy->phy_rst); 611 reset_control_assert(phy->apb_rst); 612 pm_runtime_disable(&pdev->dev); 613 614 /* 615 * The device level resets will be put automatically. 616 * Need to put the subnode resets here though. 617 */ 618 for (i = 0; i < phy->nsubnodes; i++) { 619 reset_control_assert(phy->phys[i].lnk_rst); 620 reset_control_put(phy->phys[i].lnk_rst); 621 } 622 return 0; 623 } 624 625 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 626 static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 627 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 628 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 629 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 630 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 631 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 632 }; 633 634 /* refclk100MHz_32b_PCIe_ln_ext_ssc */ 635 static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 636 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 637 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 638 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 639 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 640 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 641 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 642 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} 643 }; 644 645 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 646 static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 647 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 648 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 649 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 650 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 651 }; 652 653 /* refclk100MHz_20b_USB_ln_ext_ssc */ 654 static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 655 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 656 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 657 {0x00A5, SIERRA_DET_STANDEC_C_PREG}, 658 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 659 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 660 {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 661 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 662 {0xCF00, SIERRA_PSM_DIAG_PREG}, 663 {0x001F, SIERRA_PSC_TX_A0_PREG}, 664 {0x0007, SIERRA_PSC_TX_A1_PREG}, 665 {0x0003, SIERRA_PSC_TX_A2_PREG}, 666 {0x0003, SIERRA_PSC_TX_A3_PREG}, 667 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 668 {0x0619, SIERRA_PSC_RX_A1_PREG}, 669 {0x0003, SIERRA_PSC_RX_A2_PREG}, 670 {0x0001, SIERRA_PSC_RX_A3_PREG}, 671 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 672 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 673 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 674 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 675 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 676 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 677 {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG}, 678 {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 679 {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 680 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 681 {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 682 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 683 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 684 {0x8000, SIERRA_CREQ_SPARE_PREG}, 685 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 686 {0x8453, SIERRA_CTLELUT_CTRL_PREG}, 687 {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG}, 688 {0x4110, SIERRA_DFE_SMP_RATESEL_PREG}, 689 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 690 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 691 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 692 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 693 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 694 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 695 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 696 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 697 {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 698 {0x0014, SIERRA_DEQ_GLUT0}, 699 {0x0014, SIERRA_DEQ_GLUT1}, 700 {0x0014, SIERRA_DEQ_GLUT2}, 701 {0x0014, SIERRA_DEQ_GLUT3}, 702 {0x0014, SIERRA_DEQ_GLUT4}, 703 {0x0014, SIERRA_DEQ_GLUT5}, 704 {0x0014, SIERRA_DEQ_GLUT6}, 705 {0x0014, SIERRA_DEQ_GLUT7}, 706 {0x0014, SIERRA_DEQ_GLUT8}, 707 {0x0014, SIERRA_DEQ_GLUT9}, 708 {0x0014, SIERRA_DEQ_GLUT10}, 709 {0x0014, SIERRA_DEQ_GLUT11}, 710 {0x0014, SIERRA_DEQ_GLUT12}, 711 {0x0014, SIERRA_DEQ_GLUT13}, 712 {0x0014, SIERRA_DEQ_GLUT14}, 713 {0x0014, SIERRA_DEQ_GLUT15}, 714 {0x0014, SIERRA_DEQ_GLUT16}, 715 {0x0BAE, SIERRA_DEQ_ALUT0}, 716 {0x0AEB, SIERRA_DEQ_ALUT1}, 717 {0x0A28, SIERRA_DEQ_ALUT2}, 718 {0x0965, SIERRA_DEQ_ALUT3}, 719 {0x08A2, SIERRA_DEQ_ALUT4}, 720 {0x07DF, SIERRA_DEQ_ALUT5}, 721 {0x071C, SIERRA_DEQ_ALUT6}, 722 {0x0659, SIERRA_DEQ_ALUT7}, 723 {0x0596, SIERRA_DEQ_ALUT8}, 724 {0x0514, SIERRA_DEQ_ALUT9}, 725 {0x0492, SIERRA_DEQ_ALUT10}, 726 {0x0410, SIERRA_DEQ_ALUT11}, 727 {0x038E, SIERRA_DEQ_ALUT12}, 728 {0x030C, SIERRA_DEQ_ALUT13}, 729 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 730 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 731 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 732 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 733 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 734 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 735 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 736 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 737 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 738 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 739 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 740 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 741 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 742 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 743 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 744 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 745 {0x8009, SIERRA_SDFILT_L2H_PREG}, 746 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 747 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 748 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 749 }; 750 751 static const struct cdns_sierra_data cdns_map_sierra = { 752 SIERRA_MACRO_ID, 753 0x2, 754 0x2, 755 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 756 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 757 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 758 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 759 cdns_pcie_cmn_regs_ext_ssc, 760 cdns_pcie_ln_regs_ext_ssc, 761 cdns_usb_cmn_regs_ext_ssc, 762 cdns_usb_ln_regs_ext_ssc, 763 }; 764 765 static const struct cdns_sierra_data cdns_ti_map_sierra = { 766 SIERRA_MACRO_ID, 767 0x0, 768 0x1, 769 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 770 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 771 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 772 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 773 cdns_pcie_cmn_regs_ext_ssc, 774 cdns_pcie_ln_regs_ext_ssc, 775 cdns_usb_cmn_regs_ext_ssc, 776 cdns_usb_ln_regs_ext_ssc, 777 }; 778 779 static const struct of_device_id cdns_sierra_id_table[] = { 780 { 781 .compatible = "cdns,sierra-phy-t0", 782 .data = &cdns_map_sierra, 783 }, 784 { 785 .compatible = "ti,sierra-phy-t0", 786 .data = &cdns_ti_map_sierra, 787 }, 788 {} 789 }; 790 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 791 792 static struct platform_driver cdns_sierra_driver = { 793 .probe = cdns_sierra_phy_probe, 794 .remove = cdns_sierra_phy_remove, 795 .driver = { 796 .name = "cdns-sierra-phy", 797 .of_match_table = cdns_sierra_id_table, 798 }, 799 }; 800 module_platform_driver(cdns_sierra_driver); 801 802 MODULE_ALIAS("platform:cdns_sierra"); 803 MODULE_AUTHOR("Cadence Design Systems"); 804 MODULE_DESCRIPTION("CDNS sierra phy driver"); 805 MODULE_LICENSE("GPL v2"); 806