1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <dt-bindings/phy/phy.h> 24 #include <dt-bindings/phy/phy-cadence.h> 25 26 #define NUM_SSC_MODE 3 27 #define NUM_PHY_TYPE 5 28 29 /* PHY register offsets */ 30 #define SIERRA_COMMON_CDB_OFFSET 0x0 31 #define SIERRA_MACRO_ID_REG 0x0 32 #define SIERRA_CMN_PLLLC_GEN_PREG 0x42 33 #define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG 0x43 34 #define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG 0x45 35 #define SIERRA_CMN_PLLLC_INIT_PREG 0x46 36 #define SIERRA_CMN_PLLLC_ITERTMR_PREG 0x47 37 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 38 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 39 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 40 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 41 #define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG 0x4C 42 #define SIERRA_CMN_PLLLC_CLK1_PREG 0x4D 43 #define SIERRA_CMN_PLLLC_CLK0_PREG 0x4E 44 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 45 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 46 #define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51 47 #define SIERRA_CMN_PLLLC_SS_PREG 0x52 48 #define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53 49 #define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54 50 #define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG 0x5D 51 #define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG 0x5E 52 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 53 #define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63 54 #define SIERRA_SDOSCCAL_CLK_CNT_PREG 0x6E 55 #define SIERRA_CMN_REFRCV_PREG 0x98 56 #define SIERRA_CMN_RESCAL_CTRLA_PREG 0xA0 57 #define SIERRA_CMN_REFRCV1_PREG 0xB8 58 #define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 59 #define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3 60 #define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5 61 #define SIERRA_CMN_PLLLC1_MODE_PREG 0xC8 62 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG 0xC9 63 #define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA 64 #define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE 65 #define SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG 0xCF 66 #define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 67 #define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 68 69 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 70 ((0x4000 << (block_offset)) + \ 71 (((ln) << 9) << (reg_offset))) 72 73 #define SIERRA_DET_STANDEC_A_PREG 0x000 74 #define SIERRA_DET_STANDEC_B_PREG 0x001 75 #define SIERRA_DET_STANDEC_C_PREG 0x002 76 #define SIERRA_DET_STANDEC_D_PREG 0x003 77 #define SIERRA_DET_STANDEC_E_PREG 0x004 78 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 79 #define SIERRA_PSM_A0IN_TMR_PREG 0x009 80 #define SIERRA_PSM_A3IN_TMR_PREG 0x00C 81 #define SIERRA_PSM_DIAG_PREG 0x015 82 #define SIERRA_PSC_LN_A3_PREG 0x023 83 #define SIERRA_PSC_LN_A4_PREG 0x024 84 #define SIERRA_PSC_LN_IDLE_PREG 0x026 85 #define SIERRA_PSC_TX_A0_PREG 0x028 86 #define SIERRA_PSC_TX_A1_PREG 0x029 87 #define SIERRA_PSC_TX_A2_PREG 0x02A 88 #define SIERRA_PSC_TX_A3_PREG 0x02B 89 #define SIERRA_PSC_RX_A0_PREG 0x030 90 #define SIERRA_PSC_RX_A1_PREG 0x031 91 #define SIERRA_PSC_RX_A2_PREG 0x032 92 #define SIERRA_PSC_RX_A3_PREG 0x033 93 #define SIERRA_PLLCTRL_FBDIV_MODE01_PREG 0x039 94 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 95 #define SIERRA_PLLCTRL_GEN_A_PREG 0x03B 96 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 97 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 98 #define SIERRA_PLLCTRL_STATUS_PREG 0x044 99 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 100 #define SIERRA_DFE_BIASTRIM_PREG 0x04C 101 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 102 #define SIERRA_DRVCTRL_BOOST_PREG 0x06F 103 #define SIERRA_LANE_TX_RECEIVER_DETECT_PREG 0x071 104 #define SIERRA_TX_RCVDET_OVRD_PREG 0x072 105 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 106 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 107 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 108 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 109 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 110 #define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C 111 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 112 #define SIERRA_RX_CTLE_CAL_PREG 0x08F 113 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 114 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 115 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 116 #define SIERRA_CREQ_SPARE_PREG 0x096 117 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 118 #define SIERRA_CTLELUT_CTRL_PREG 0x098 119 #define SIERRA_DEQ_BLK_TAU_CTRL1_PREG 0x0AC 120 #define SIERRA_DEQ_BLK_TAU_CTRL4_PREG 0x0AF 121 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 122 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 123 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 124 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 125 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 126 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 127 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 128 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 129 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 130 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 131 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 132 #define SIERRA_DEQ_GLUT0 0x0E8 133 #define SIERRA_DEQ_GLUT1 0x0E9 134 #define SIERRA_DEQ_GLUT2 0x0EA 135 #define SIERRA_DEQ_GLUT3 0x0EB 136 #define SIERRA_DEQ_GLUT4 0x0EC 137 #define SIERRA_DEQ_GLUT5 0x0ED 138 #define SIERRA_DEQ_GLUT6 0x0EE 139 #define SIERRA_DEQ_GLUT7 0x0EF 140 #define SIERRA_DEQ_GLUT8 0x0F0 141 #define SIERRA_DEQ_GLUT9 0x0F1 142 #define SIERRA_DEQ_GLUT10 0x0F2 143 #define SIERRA_DEQ_GLUT11 0x0F3 144 #define SIERRA_DEQ_GLUT12 0x0F4 145 #define SIERRA_DEQ_GLUT13 0x0F5 146 #define SIERRA_DEQ_GLUT14 0x0F6 147 #define SIERRA_DEQ_GLUT15 0x0F7 148 #define SIERRA_DEQ_GLUT16 0x0F8 149 #define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG 0x0F9 150 #define SIERRA_TAU_EN_CEPH2TO0_PREG 0x0FB 151 #define SIERRA_TAU_EN_CEPH5TO3_PREG 0x0FC 152 #define SIERRA_DEQ_ALUT0 0x108 153 #define SIERRA_DEQ_ALUT1 0x109 154 #define SIERRA_DEQ_ALUT2 0x10A 155 #define SIERRA_DEQ_ALUT3 0x10B 156 #define SIERRA_DEQ_ALUT4 0x10C 157 #define SIERRA_DEQ_ALUT5 0x10D 158 #define SIERRA_DEQ_ALUT6 0x10E 159 #define SIERRA_DEQ_ALUT7 0x10F 160 #define SIERRA_DEQ_ALUT8 0x110 161 #define SIERRA_DEQ_ALUT9 0x111 162 #define SIERRA_DEQ_ALUT10 0x112 163 #define SIERRA_DEQ_ALUT11 0x113 164 #define SIERRA_DEQ_ALUT12 0x114 165 #define SIERRA_DEQ_ALUT13 0x115 166 #define SIERRA_OEPH_EN_CTRL_PREG 0x124 167 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 168 #define SIERRA_DEQ_DFETAP0 0x129 169 #define SIERRA_DEQ_DFETAP1 0x12B 170 #define SIERRA_DEQ_DFETAP2 0x12D 171 #define SIERRA_DEQ_DFETAP3 0x12F 172 #define SIERRA_DEQ_DFETAP4 0x131 173 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 174 #define SIERRA_DEQ_PRECUR_PREG 0x138 175 #define SIERRA_DEQ_POSTCUR_PREG 0x140 176 #define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142 177 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 178 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 179 #define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 180 #define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG 0x158 181 #define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG 0x159 182 #define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x15C 183 #define SIERRA_DEQ_PICTRL_PREG 0x161 184 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 185 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 186 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 187 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 188 #define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E 189 #define SIERRA_CPI_TRIM_PREG 0x17F 190 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 191 #define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG 0x184 192 #define SIERRA_EPI_CTRL_PREG 0x187 193 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 194 #define SIERRA_LFPSFILT_NS_PREG 0x18A 195 #define SIERRA_LFPSFILT_RD_PREG 0x18B 196 #define SIERRA_LFPSFILT_MP_PREG 0x18C 197 #define SIERRA_SIGDET_SUPPORT_PREG 0x190 198 #define SIERRA_SDFILT_H2L_A_PREG 0x191 199 #define SIERRA_SDFILT_L2H_PREG 0x193 200 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 201 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 202 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 203 #define SIERRA_LN_SPARE_REG_PREG 0x1B0 204 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 205 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 206 207 /* PHY PCS common registers */ 208 #define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset) \ 209 (0xc000 << (block_offset)) 210 #define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 211 #define SIERRA_PHY_PLL_CFG 0xe 212 213 /* PHY PCS lane registers */ 214 #define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 215 ((0xD000 << (block_offset)) + \ 216 (((ln) << 8) << (reg_offset))) 217 218 #define SIERRA_PHY_ISO_LINK_CTRL 0xB 219 220 /* PHY PMA common registers */ 221 #define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset) \ 222 (0xE000 << (block_offset)) 223 #define SIERRA_PHY_PMA_CMN_CTRL 0x000 224 225 /* PHY PMA lane registers */ 226 #define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 227 ((0xF000 << (block_offset)) + \ 228 (((ln) << 8) << (reg_offset))) 229 230 #define SIERRA_PHY_PMA_XCVR_CTRL 0x000 231 232 #define SIERRA_MACRO_ID 0x00007364 233 #define SIERRA_MAX_LANES 16 234 #define PLL_LOCK_TIME 100000 235 236 #define CDNS_SIERRA_OUTPUT_CLOCKS 3 237 #define CDNS_SIERRA_INPUT_CLOCKS 3 238 enum cdns_sierra_clock_input { 239 PHY_CLK, 240 CMN_REFCLK_DIG_DIV, 241 CMN_REFCLK1_DIG_DIV, 242 }; 243 244 #define SIERRA_NUM_CMN_PLLC 2 245 #define SIERRA_NUM_CMN_PLLC_PARENTS 2 246 247 static const struct reg_field macro_id_type = 248 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 249 static const struct reg_field phy_pll_cfg_1 = 250 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 251 static const struct reg_field pma_cmn_ready = 252 REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0); 253 static const struct reg_field pllctrl_lock = 254 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 255 static const struct reg_field phy_iso_link_ctrl_1 = 256 REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); 257 static const struct reg_field cmn_plllc_clk1outdiv_preg = 258 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6); 259 static const struct reg_field cmn_plllc_clk1_en_preg = 260 REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12); 261 262 static const char * const clk_names[] = { 263 [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", 264 [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", 265 [CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der", 266 }; 267 268 enum cdns_sierra_cmn_plllc { 269 CMN_PLLLC, 270 CMN_PLLLC1, 271 }; 272 273 struct cdns_sierra_pll_mux_reg_fields { 274 struct reg_field pfdclk_sel_preg; 275 struct reg_field plllc1en_field; 276 struct reg_field termen_field; 277 }; 278 279 static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { 280 [CMN_PLLLC] = { 281 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), 282 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), 283 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), 284 }, 285 [CMN_PLLLC1] = { 286 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), 287 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), 288 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), 289 }, 290 }; 291 292 struct cdns_sierra_pll_mux { 293 struct clk_hw hw; 294 struct regmap_field *pfdclk_sel_preg; 295 struct regmap_field *plllc1en_field; 296 struct regmap_field *termen_field; 297 struct clk_init_data clk_data; 298 }; 299 300 #define to_cdns_sierra_pll_mux(_hw) \ 301 container_of(_hw, struct cdns_sierra_pll_mux, hw) 302 303 #define PLL0_REFCLK_NAME "pll0_refclk" 304 #define PLL1_REFCLK_NAME "pll1_refclk" 305 306 static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 307 [CMN_PLLLC] = { 308 { .fw_name = PLL0_REFCLK_NAME }, 309 { .fw_name = PLL1_REFCLK_NAME } 310 }, 311 [CMN_PLLLC1] = { 312 { .fw_name = PLL1_REFCLK_NAME }, 313 { .fw_name = PLL0_REFCLK_NAME } 314 }, 315 }; 316 317 static const u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = { 318 [CMN_PLLLC] = { 0, 1 }, 319 [CMN_PLLLC1] = { 1, 0 }, 320 }; 321 322 struct cdns_sierra_derived_refclk { 323 struct clk_hw hw; 324 struct regmap_field *cmn_plllc_clk1outdiv_preg; 325 struct regmap_field *cmn_plllc_clk1_en_preg; 326 struct clk_init_data clk_data; 327 }; 328 329 #define to_cdns_sierra_derived_refclk(_hw) \ 330 container_of(_hw, struct cdns_sierra_derived_refclk, hw) 331 332 enum cdns_sierra_phy_type { 333 TYPE_NONE, 334 TYPE_PCIE, 335 TYPE_USB, 336 TYPE_SGMII, 337 TYPE_QSGMII 338 }; 339 340 enum cdns_sierra_ssc_mode { 341 NO_SSC, 342 EXTERNAL_SSC, 343 INTERNAL_SSC 344 }; 345 346 struct cdns_sierra_inst { 347 struct phy *phy; 348 enum cdns_sierra_phy_type phy_type; 349 u32 num_lanes; 350 u32 mlane; 351 struct reset_control *lnk_rst; 352 enum cdns_sierra_ssc_mode ssc_mode; 353 }; 354 355 struct cdns_reg_pairs { 356 u16 val; 357 u32 off; 358 }; 359 360 struct cdns_sierra_vals { 361 const struct cdns_reg_pairs *reg_pairs; 362 u32 num_regs; 363 }; 364 365 struct cdns_sierra_data { 366 u32 id_value; 367 u8 block_offset_shift; 368 u8 reg_offset_shift; 369 const struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 370 [NUM_SSC_MODE]; 371 const struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 372 [NUM_SSC_MODE]; 373 const struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 374 [NUM_SSC_MODE]; 375 const struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 376 [NUM_SSC_MODE]; 377 }; 378 379 struct cdns_regmap_cdb_context { 380 struct device *dev; 381 void __iomem *base; 382 u8 reg_offset_shift; 383 }; 384 385 struct cdns_sierra_phy { 386 struct device *dev; 387 const struct cdns_sierra_data *init_data; 388 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 389 struct reset_control *phy_rst; 390 struct reset_control *apb_rst; 391 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 392 struct regmap *regmap_phy_pcs_common_cdb; 393 struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES]; 394 struct regmap *regmap_phy_pma_common_cdb; 395 struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES]; 396 struct regmap *regmap_common_cdb; 397 struct regmap_field *macro_id_type; 398 struct regmap_field *phy_pll_cfg_1; 399 struct regmap_field *pma_cmn_ready; 400 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 401 struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES]; 402 struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; 403 struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; 404 struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; 405 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; 406 int nsubnodes; 407 u32 num_lanes; 408 bool autoconf; 409 int already_configured; 410 struct clk *pll_clks[SIERRA_NUM_CMN_PLLC]; 411 struct clk_hw_onecell_data clk_data; 412 }; 413 414 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 415 { 416 struct cdns_regmap_cdb_context *ctx = context; 417 u32 offset = reg << ctx->reg_offset_shift; 418 419 writew(val, ctx->base + offset); 420 421 return 0; 422 } 423 424 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 425 { 426 struct cdns_regmap_cdb_context *ctx = context; 427 u32 offset = reg << ctx->reg_offset_shift; 428 429 *val = readw(ctx->base + offset); 430 return 0; 431 } 432 433 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 434 { \ 435 .name = "sierra_lane" n "_cdb", \ 436 .reg_stride = 1, \ 437 .fast_io = true, \ 438 .reg_write = cdns_regmap_write, \ 439 .reg_read = cdns_regmap_read, \ 440 } 441 442 static const struct regmap_config cdns_sierra_lane_cdb_config[] = { 443 SIERRA_LANE_CDB_REGMAP_CONF("0"), 444 SIERRA_LANE_CDB_REGMAP_CONF("1"), 445 SIERRA_LANE_CDB_REGMAP_CONF("2"), 446 SIERRA_LANE_CDB_REGMAP_CONF("3"), 447 SIERRA_LANE_CDB_REGMAP_CONF("4"), 448 SIERRA_LANE_CDB_REGMAP_CONF("5"), 449 SIERRA_LANE_CDB_REGMAP_CONF("6"), 450 SIERRA_LANE_CDB_REGMAP_CONF("7"), 451 SIERRA_LANE_CDB_REGMAP_CONF("8"), 452 SIERRA_LANE_CDB_REGMAP_CONF("9"), 453 SIERRA_LANE_CDB_REGMAP_CONF("10"), 454 SIERRA_LANE_CDB_REGMAP_CONF("11"), 455 SIERRA_LANE_CDB_REGMAP_CONF("12"), 456 SIERRA_LANE_CDB_REGMAP_CONF("13"), 457 SIERRA_LANE_CDB_REGMAP_CONF("14"), 458 SIERRA_LANE_CDB_REGMAP_CONF("15"), 459 }; 460 461 static const struct regmap_config cdns_sierra_common_cdb_config = { 462 .name = "sierra_common_cdb", 463 .reg_stride = 1, 464 .fast_io = true, 465 .reg_write = cdns_regmap_write, 466 .reg_read = cdns_regmap_read, 467 }; 468 469 static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = { 470 .name = "sierra_phy_pcs_cmn_cdb", 471 .reg_stride = 1, 472 .fast_io = true, 473 .reg_write = cdns_regmap_write, 474 .reg_read = cdns_regmap_read, 475 }; 476 477 #define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 478 { \ 479 .name = "sierra_phy_pcs_lane" n "_cdb", \ 480 .reg_stride = 1, \ 481 .fast_io = true, \ 482 .reg_write = cdns_regmap_write, \ 483 .reg_read = cdns_regmap_read, \ 484 } 485 486 static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = { 487 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 488 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 489 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 490 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 491 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"), 492 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"), 493 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"), 494 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"), 495 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"), 496 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"), 497 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"), 498 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"), 499 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"), 500 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"), 501 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"), 502 SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"), 503 }; 504 505 static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = { 506 .name = "sierra_phy_pma_cmn_cdb", 507 .reg_stride = 1, 508 .fast_io = true, 509 .reg_write = cdns_regmap_write, 510 .reg_read = cdns_regmap_read, 511 }; 512 513 #define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \ 514 { \ 515 .name = "sierra_phy_pma_lane" n "_cdb", \ 516 .reg_stride = 1, \ 517 .fast_io = true, \ 518 .reg_write = cdns_regmap_write, \ 519 .reg_read = cdns_regmap_read, \ 520 } 521 522 static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = { 523 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"), 524 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"), 525 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"), 526 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"), 527 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"), 528 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"), 529 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"), 530 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"), 531 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"), 532 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"), 533 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"), 534 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"), 535 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"), 536 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"), 537 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"), 538 SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"), 539 }; 540 541 static int cdns_sierra_phy_init(struct phy *gphy) 542 { 543 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 544 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 545 const struct cdns_sierra_data *init_data = phy->init_data; 546 const struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 547 enum cdns_sierra_phy_type phy_type = ins->phy_type; 548 const struct cdns_sierra_vals *phy_pma_ln_vals; 549 enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; 550 const struct cdns_sierra_vals *pcs_cmn_vals; 551 const struct cdns_reg_pairs *reg_pairs; 552 struct regmap *regmap; 553 u32 num_regs; 554 int i, j; 555 556 /* Initialise the PHY registers, unless auto configured */ 557 if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1) 558 return 0; 559 560 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 561 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 562 563 /* PHY PCS common registers configurations */ 564 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; 565 if (pcs_cmn_vals) { 566 reg_pairs = pcs_cmn_vals->reg_pairs; 567 num_regs = pcs_cmn_vals->num_regs; 568 regmap = phy->regmap_phy_pcs_common_cdb; 569 for (i = 0; i < num_regs; i++) 570 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 571 } 572 573 /* PHY PMA lane registers configurations */ 574 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; 575 if (phy_pma_ln_vals) { 576 reg_pairs = phy_pma_ln_vals->reg_pairs; 577 num_regs = phy_pma_ln_vals->num_regs; 578 for (i = 0; i < ins->num_lanes; i++) { 579 regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane]; 580 for (j = 0; j < num_regs; j++) 581 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 582 } 583 } 584 585 /* PMA common registers configurations */ 586 pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; 587 if (pma_cmn_vals) { 588 reg_pairs = pma_cmn_vals->reg_pairs; 589 num_regs = pma_cmn_vals->num_regs; 590 regmap = phy->regmap_common_cdb; 591 for (i = 0; i < num_regs; i++) 592 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 593 } 594 595 /* PMA lane registers configurations */ 596 pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; 597 if (pma_ln_vals) { 598 reg_pairs = pma_ln_vals->reg_pairs; 599 num_regs = pma_ln_vals->num_regs; 600 for (i = 0; i < ins->num_lanes; i++) { 601 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 602 for (j = 0; j < num_regs; j++) 603 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 604 } 605 } 606 607 return 0; 608 } 609 610 static int cdns_sierra_phy_on(struct phy *gphy) 611 { 612 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 613 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 614 struct device *dev = sp->dev; 615 u32 val; 616 int ret; 617 618 if (sp->nsubnodes == 1) { 619 /* Take the PHY out of reset */ 620 ret = reset_control_deassert(sp->phy_rst); 621 if (ret) { 622 dev_err(dev, "Failed to take the PHY out of reset\n"); 623 return ret; 624 } 625 } 626 627 /* Take the PHY lane group out of reset */ 628 ret = reset_control_deassert(ins->lnk_rst); 629 if (ret) { 630 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 631 return ret; 632 } 633 634 if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) { 635 ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane], 636 val, !val, 1000, PLL_LOCK_TIME); 637 if (ret) { 638 dev_err(dev, "Timeout waiting for PHY status ready\n"); 639 return ret; 640 } 641 } 642 643 /* 644 * Wait for cmn_ready assertion 645 * PHY_PMA_CMN_CTRL[0] == 1 646 */ 647 ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val, 648 1000, PLL_LOCK_TIME); 649 if (ret) { 650 dev_err(dev, "Timeout waiting for CMN ready\n"); 651 return ret; 652 } 653 654 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 655 val, val, 1000, PLL_LOCK_TIME); 656 if (ret < 0) 657 dev_err(dev, "PLL lock of lane failed\n"); 658 659 return ret; 660 } 661 662 static int cdns_sierra_phy_off(struct phy *gphy) 663 { 664 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 665 666 return reset_control_assert(ins->lnk_rst); 667 } 668 669 static int cdns_sierra_phy_reset(struct phy *gphy) 670 { 671 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 672 673 reset_control_assert(sp->phy_rst); 674 reset_control_deassert(sp->phy_rst); 675 return 0; 676 }; 677 678 static const struct phy_ops ops = { 679 .init = cdns_sierra_phy_init, 680 .power_on = cdns_sierra_phy_on, 681 .power_off = cdns_sierra_phy_off, 682 .reset = cdns_sierra_phy_reset, 683 .owner = THIS_MODULE, 684 }; 685 686 static int cdns_sierra_noop_phy_on(struct phy *gphy) 687 { 688 usleep_range(5000, 10000); 689 690 return 0; 691 } 692 693 static const struct phy_ops noop_ops = { 694 .power_on = cdns_sierra_noop_phy_on, 695 .owner = THIS_MODULE, 696 }; 697 698 static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) 699 { 700 struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); 701 struct regmap_field *plllc1en_field = mux->plllc1en_field; 702 struct regmap_field *termen_field = mux->termen_field; 703 struct regmap_field *field = mux->pfdclk_sel_preg; 704 unsigned int val; 705 int index; 706 707 regmap_field_read(field, &val); 708 709 if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) { 710 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val); 711 if (index == 1) { 712 regmap_field_write(plllc1en_field, 1); 713 regmap_field_write(termen_field, 1); 714 } 715 } else { 716 index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val); 717 } 718 719 return index; 720 } 721 722 static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) 723 { 724 struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw); 725 struct regmap_field *plllc1en_field = mux->plllc1en_field; 726 struct regmap_field *termen_field = mux->termen_field; 727 struct regmap_field *field = mux->pfdclk_sel_preg; 728 int val, ret; 729 730 ret = regmap_field_write(plllc1en_field, 0); 731 ret |= regmap_field_write(termen_field, 0); 732 if (index == 1) { 733 ret |= regmap_field_write(plllc1en_field, 1); 734 ret |= regmap_field_write(termen_field, 1); 735 } 736 737 if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) 738 val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index]; 739 else 740 val = cdns_sierra_pll_mux_table[CMN_PLLLC][index]; 741 742 ret |= regmap_field_write(field, val); 743 744 return ret; 745 } 746 747 static const struct clk_ops cdns_sierra_pll_mux_ops = { 748 .determine_rate = __clk_mux_determine_rate, 749 .set_parent = cdns_sierra_pll_mux_set_parent, 750 .get_parent = cdns_sierra_pll_mux_get_parent, 751 }; 752 753 static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, 754 struct regmap_field *pfdclk1_sel_field, 755 struct regmap_field *plllc1en_field, 756 struct regmap_field *termen_field, 757 int clk_index) 758 { 759 struct cdns_sierra_pll_mux *mux; 760 struct device *dev = sp->dev; 761 struct clk_init_data *init; 762 char clk_name[100]; 763 int ret; 764 765 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); 766 if (!mux) 767 return -ENOMEM; 768 769 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]); 770 771 init = &mux->clk_data; 772 773 init->ops = &cdns_sierra_pll_mux_ops; 774 init->flags = CLK_SET_RATE_NO_REPARENT; 775 init->parent_data = pll_mux_parent_data[clk_index]; 776 init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS; 777 init->name = clk_name; 778 779 mux->pfdclk_sel_preg = pfdclk1_sel_field; 780 mux->plllc1en_field = plllc1en_field; 781 mux->termen_field = termen_field; 782 mux->hw.init = init; 783 784 ret = devm_clk_hw_register(dev, &mux->hw); 785 if (ret) 786 return ret; 787 788 sp->clk_data.hws[clk_index] = &mux->hw; 789 790 sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw, 791 clk_names[clk_index]); 792 793 return 0; 794 } 795 796 static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) 797 { 798 struct regmap_field *pfdclk1_sel_field; 799 struct regmap_field *plllc1en_field; 800 struct regmap_field *termen_field; 801 struct device *dev = sp->dev; 802 int ret = 0, i, clk_index; 803 804 clk_index = CDNS_SIERRA_PLL_CMNLC; 805 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { 806 pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i]; 807 plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i]; 808 termen_field = sp->cmn_refrcv_refclk_termen_preg[i]; 809 810 ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field, 811 termen_field, clk_index); 812 if (ret) { 813 dev_err(dev, "Fail to register cmn plllc mux\n"); 814 return ret; 815 } 816 } 817 818 return 0; 819 } 820 821 static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw) 822 { 823 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 824 825 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1); 826 827 /* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */ 828 regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E); 829 830 return 0; 831 } 832 833 static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw) 834 { 835 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 836 837 regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0); 838 } 839 840 static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw) 841 { 842 struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw); 843 int val; 844 845 regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val); 846 847 return !!val; 848 } 849 850 static const struct clk_ops cdns_sierra_derived_refclk_ops = { 851 .enable = cdns_sierra_derived_refclk_enable, 852 .disable = cdns_sierra_derived_refclk_disable, 853 .is_enabled = cdns_sierra_derived_refclk_is_enabled, 854 }; 855 856 static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp) 857 { 858 struct cdns_sierra_derived_refclk *derived_refclk; 859 struct device *dev = sp->dev; 860 struct regmap_field *field; 861 struct clk_init_data *init; 862 struct regmap *regmap; 863 char clk_name[100]; 864 int ret; 865 866 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 867 if (!derived_refclk) 868 return -ENOMEM; 869 870 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 871 clk_names[CDNS_SIERRA_DERIVED_REFCLK]); 872 873 init = &derived_refclk->clk_data; 874 875 init->ops = &cdns_sierra_derived_refclk_ops; 876 init->flags = 0; 877 init->name = clk_name; 878 879 regmap = sp->regmap_common_cdb; 880 881 field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg); 882 if (IS_ERR(field)) { 883 dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n"); 884 return PTR_ERR(field); 885 } 886 derived_refclk->cmn_plllc_clk1outdiv_preg = field; 887 888 field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg); 889 if (IS_ERR(field)) { 890 dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n"); 891 return PTR_ERR(field); 892 } 893 derived_refclk->cmn_plllc_clk1_en_preg = field; 894 895 derived_refclk->hw.init = init; 896 897 ret = devm_clk_hw_register(dev, &derived_refclk->hw); 898 if (ret) 899 return ret; 900 901 sp->clk_data.hws[CDNS_SIERRA_DERIVED_REFCLK] = &derived_refclk->hw; 902 903 return 0; 904 } 905 906 static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) 907 { 908 struct device *dev = sp->dev; 909 struct device_node *node = dev->of_node; 910 911 of_clk_del_provider(node); 912 } 913 914 static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) 915 { 916 struct device *dev = sp->dev; 917 struct device_node *node = dev->of_node; 918 int ret; 919 920 ret = cdns_sierra_phy_register_pll_mux(sp); 921 if (ret) { 922 dev_err(dev, "Failed to pll mux clocks\n"); 923 return ret; 924 } 925 926 ret = cdns_sierra_derived_refclk_register(sp); 927 if (ret) { 928 dev_err(dev, "Failed to register derived refclk\n"); 929 return ret; 930 } 931 932 sp->clk_data.num = CDNS_SIERRA_OUTPUT_CLOCKS; 933 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 934 &sp->clk_data); 935 if (ret) 936 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 937 938 return ret; 939 } 940 941 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 942 struct device_node *child) 943 { 944 u32 phy_type; 945 946 if (of_property_read_u32(child, "reg", &inst->mlane)) 947 return -EINVAL; 948 949 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 950 return -EINVAL; 951 952 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) 953 return -EINVAL; 954 955 switch (phy_type) { 956 case PHY_TYPE_PCIE: 957 inst->phy_type = TYPE_PCIE; 958 break; 959 case PHY_TYPE_USB3: 960 inst->phy_type = TYPE_USB; 961 break; 962 case PHY_TYPE_SGMII: 963 inst->phy_type = TYPE_SGMII; 964 break; 965 case PHY_TYPE_QSGMII: 966 inst->phy_type = TYPE_QSGMII; 967 break; 968 default: 969 return -EINVAL; 970 } 971 972 inst->ssc_mode = EXTERNAL_SSC; 973 of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode); 974 975 return 0; 976 } 977 978 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 979 u32 block_offset, u8 reg_offset_shift, 980 const struct regmap_config *config) 981 { 982 struct cdns_regmap_cdb_context *ctx; 983 984 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 985 if (!ctx) 986 return ERR_PTR(-ENOMEM); 987 988 ctx->dev = dev; 989 ctx->base = base + block_offset; 990 ctx->reg_offset_shift = reg_offset_shift; 991 992 return devm_regmap_init(dev, NULL, ctx, config); 993 } 994 995 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 996 { 997 struct device *dev = sp->dev; 998 struct regmap_field *field; 999 struct reg_field reg_field; 1000 struct regmap *regmap; 1001 int i; 1002 1003 regmap = sp->regmap_common_cdb; 1004 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 1005 if (IS_ERR(field)) { 1006 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 1007 return PTR_ERR(field); 1008 } 1009 sp->macro_id_type = field; 1010 1011 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { 1012 reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; 1013 field = devm_regmap_field_alloc(dev, regmap, reg_field); 1014 if (IS_ERR(field)) { 1015 dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); 1016 return PTR_ERR(field); 1017 } 1018 sp->cmn_plllc_pfdclk1_sel_preg[i] = field; 1019 1020 reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; 1021 field = devm_regmap_field_alloc(dev, regmap, reg_field); 1022 if (IS_ERR(field)) { 1023 dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); 1024 return PTR_ERR(field); 1025 } 1026 sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; 1027 1028 reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; 1029 field = devm_regmap_field_alloc(dev, regmap, reg_field); 1030 if (IS_ERR(field)) { 1031 dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); 1032 return PTR_ERR(field); 1033 } 1034 sp->cmn_refrcv_refclk_termen_preg[i] = field; 1035 } 1036 1037 regmap = sp->regmap_phy_pcs_common_cdb; 1038 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 1039 if (IS_ERR(field)) { 1040 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 1041 return PTR_ERR(field); 1042 } 1043 sp->phy_pll_cfg_1 = field; 1044 1045 regmap = sp->regmap_phy_pma_common_cdb; 1046 field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready); 1047 if (IS_ERR(field)) { 1048 dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n"); 1049 return PTR_ERR(field); 1050 } 1051 sp->pma_cmn_ready = field; 1052 1053 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1054 regmap = sp->regmap_lane_cdb[i]; 1055 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 1056 if (IS_ERR(field)) { 1057 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 1058 return PTR_ERR(field); 1059 } 1060 sp->pllctrl_lock[i] = field; 1061 } 1062 1063 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1064 regmap = sp->regmap_phy_pcs_lane_cdb[i]; 1065 field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1); 1066 if (IS_ERR(field)) { 1067 dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i); 1068 return PTR_ERR(field); 1069 } 1070 sp->phy_iso_link_ctrl_1[i] = field; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 1077 void __iomem *base, u8 block_offset_shift, 1078 u8 reg_offset_shift) 1079 { 1080 struct device *dev = sp->dev; 1081 struct regmap *regmap; 1082 u32 block_offset; 1083 int i; 1084 1085 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1086 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 1087 reg_offset_shift); 1088 regmap = cdns_regmap_init(dev, base, block_offset, 1089 reg_offset_shift, 1090 &cdns_sierra_lane_cdb_config[i]); 1091 if (IS_ERR(regmap)) { 1092 dev_err(dev, "Failed to init lane CDB regmap\n"); 1093 return PTR_ERR(regmap); 1094 } 1095 sp->regmap_lane_cdb[i] = regmap; 1096 } 1097 1098 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 1099 reg_offset_shift, 1100 &cdns_sierra_common_cdb_config); 1101 if (IS_ERR(regmap)) { 1102 dev_err(dev, "Failed to init common CDB regmap\n"); 1103 return PTR_ERR(regmap); 1104 } 1105 sp->regmap_common_cdb = regmap; 1106 1107 block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift); 1108 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 1109 &cdns_sierra_phy_pcs_cmn_cdb_config); 1110 if (IS_ERR(regmap)) { 1111 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 1112 return PTR_ERR(regmap); 1113 } 1114 sp->regmap_phy_pcs_common_cdb = regmap; 1115 1116 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1117 block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 1118 reg_offset_shift); 1119 regmap = cdns_regmap_init(dev, base, block_offset, 1120 reg_offset_shift, 1121 &cdns_sierra_phy_pcs_lane_cdb_config[i]); 1122 if (IS_ERR(regmap)) { 1123 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 1124 return PTR_ERR(regmap); 1125 } 1126 sp->regmap_phy_pcs_lane_cdb[i] = regmap; 1127 } 1128 1129 block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift); 1130 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 1131 &cdns_sierra_phy_pma_cmn_cdb_config); 1132 if (IS_ERR(regmap)) { 1133 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 1134 return PTR_ERR(regmap); 1135 } 1136 sp->regmap_phy_pma_common_cdb = regmap; 1137 1138 for (i = 0; i < SIERRA_MAX_LANES; i++) { 1139 block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift, 1140 reg_offset_shift); 1141 regmap = cdns_regmap_init(dev, base, block_offset, 1142 reg_offset_shift, 1143 &cdns_sierra_phy_pma_lane_cdb_config[i]); 1144 if (IS_ERR(regmap)) { 1145 dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n"); 1146 return PTR_ERR(regmap); 1147 } 1148 sp->regmap_phy_pma_lane_cdb[i] = regmap; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 1155 struct device *dev) 1156 { 1157 struct clk *clk; 1158 int ret; 1159 1160 clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); 1161 if (IS_ERR(clk)) { 1162 dev_err(dev, "cmn_refclk_dig_div clock not found\n"); 1163 ret = PTR_ERR(clk); 1164 return ret; 1165 } 1166 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; 1167 1168 clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); 1169 if (IS_ERR(clk)) { 1170 dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); 1171 ret = PTR_ERR(clk); 1172 return ret; 1173 } 1174 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; 1175 1176 return 0; 1177 } 1178 1179 static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) 1180 { 1181 struct device *dev = sp->dev; 1182 struct clk *clk; 1183 int ret; 1184 1185 clk = devm_clk_get_optional(dev, "phy_clk"); 1186 if (IS_ERR(clk)) { 1187 dev_err(dev, "failed to get clock phy_clk\n"); 1188 return PTR_ERR(clk); 1189 } 1190 sp->input_clks[PHY_CLK] = clk; 1191 1192 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); 1193 if (ret) 1194 return ret; 1195 1196 return 0; 1197 } 1198 1199 static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp) 1200 { 1201 int ret; 1202 1203 ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); 1204 if (ret) 1205 return ret; 1206 1207 ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); 1208 if (ret) 1209 goto err_pll_cmnlc1; 1210 1211 return 0; 1212 1213 err_pll_cmnlc1: 1214 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); 1215 1216 return ret; 1217 } 1218 1219 static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp) 1220 { 1221 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]); 1222 clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]); 1223 if (!sp->already_configured) 1224 clk_disable_unprepare(sp->input_clks[PHY_CLK]); 1225 } 1226 1227 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, 1228 struct device *dev) 1229 { 1230 struct reset_control *rst; 1231 1232 rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); 1233 if (IS_ERR(rst)) { 1234 dev_err(dev, "failed to get reset\n"); 1235 return PTR_ERR(rst); 1236 } 1237 sp->phy_rst = rst; 1238 1239 rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); 1240 if (IS_ERR(rst)) { 1241 dev_err(dev, "failed to get apb reset\n"); 1242 return PTR_ERR(rst); 1243 } 1244 sp->apb_rst = rst; 1245 1246 return 0; 1247 } 1248 1249 static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) 1250 { 1251 const struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 1252 const struct cdns_sierra_data *init_data = sp->init_data; 1253 const struct cdns_sierra_vals *phy_pma_ln_vals; 1254 const struct cdns_sierra_vals *pcs_cmn_vals; 1255 enum cdns_sierra_phy_type phy_t1, phy_t2; 1256 const struct cdns_reg_pairs *reg_pairs; 1257 int i, j, node, mlane, num_lanes, ret; 1258 enum cdns_sierra_ssc_mode ssc; 1259 struct regmap *regmap; 1260 u32 num_regs; 1261 1262 /* Maximum 2 links (subnodes) are supported */ 1263 if (sp->nsubnodes != 2) 1264 return -EINVAL; 1265 1266 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 1267 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 1268 1269 /* PHY configured to use both PLL LC and LC1 */ 1270 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 1271 1272 phy_t1 = sp->phys[0].phy_type; 1273 phy_t2 = sp->phys[1].phy_type; 1274 1275 /* 1276 * PHY configuration for multi-link operation is done in two steps. 1277 * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. 1278 * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe 1279 * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. 1280 * 1281 * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII 1282 * So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. 1283 * This will configure PHY registers associated for PCIe (i.e. first protocol) 1284 * involving PLLLC registers and registers for first 2 lanes of PHY. 1285 * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now, 1286 * phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as 1287 * [TYPE_QSGMII][TYPE_PCIE][ssc]. 1288 * This will configure PHY registers associated for QSGMII (i.e. second protocol) 1289 * involving PLLLC1 registers and registers for other 2 lanes of PHY. 1290 * 1291 * This completes the PHY configuration for multilink operation. This approach enables 1292 * dividing the large number of PHY register configurations into protocol specific 1293 * smaller groups. 1294 */ 1295 for (node = 0; node < sp->nsubnodes; node++) { 1296 if (node == 1) { 1297 /* 1298 * If first link with phy_t1 is configured, then configure the PHY for 1299 * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc]. 1300 */ 1301 swap(phy_t1, phy_t2); 1302 } 1303 1304 mlane = sp->phys[node].mlane; 1305 ssc = sp->phys[node].ssc_mode; 1306 num_lanes = sp->phys[node].num_lanes; 1307 1308 /* PHY PCS common registers configurations */ 1309 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; 1310 if (pcs_cmn_vals) { 1311 reg_pairs = pcs_cmn_vals->reg_pairs; 1312 num_regs = pcs_cmn_vals->num_regs; 1313 regmap = sp->regmap_phy_pcs_common_cdb; 1314 for (i = 0; i < num_regs; i++) 1315 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 1316 } 1317 1318 /* PHY PMA lane registers configurations */ 1319 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; 1320 if (phy_pma_ln_vals) { 1321 reg_pairs = phy_pma_ln_vals->reg_pairs; 1322 num_regs = phy_pma_ln_vals->num_regs; 1323 for (i = 0; i < num_lanes; i++) { 1324 regmap = sp->regmap_phy_pma_lane_cdb[i + mlane]; 1325 for (j = 0; j < num_regs; j++) 1326 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 1327 } 1328 } 1329 1330 /* PMA common registers configurations */ 1331 pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; 1332 if (pma_cmn_vals) { 1333 reg_pairs = pma_cmn_vals->reg_pairs; 1334 num_regs = pma_cmn_vals->num_regs; 1335 regmap = sp->regmap_common_cdb; 1336 for (i = 0; i < num_regs; i++) 1337 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 1338 } 1339 1340 /* PMA lane registers configurations */ 1341 pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc]; 1342 if (pma_ln_vals) { 1343 reg_pairs = pma_ln_vals->reg_pairs; 1344 num_regs = pma_ln_vals->num_regs; 1345 for (i = 0; i < num_lanes; i++) { 1346 regmap = sp->regmap_lane_cdb[i + mlane]; 1347 for (j = 0; j < num_regs; j++) 1348 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 1349 } 1350 } 1351 1352 if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII) 1353 reset_control_deassert(sp->phys[node].lnk_rst); 1354 } 1355 1356 /* Take the PHY out of reset */ 1357 ret = reset_control_deassert(sp->phy_rst); 1358 if (ret) 1359 return ret; 1360 1361 return 0; 1362 } 1363 1364 static int cdns_sierra_phy_probe(struct platform_device *pdev) 1365 { 1366 struct cdns_sierra_phy *sp; 1367 struct phy_provider *phy_provider; 1368 struct device *dev = &pdev->dev; 1369 const struct cdns_sierra_data *data; 1370 unsigned int id_value; 1371 int ret, node = 0; 1372 void __iomem *base; 1373 struct device_node *dn = dev->of_node; 1374 1375 if (of_get_child_count(dn) == 0) 1376 return -ENODEV; 1377 1378 /* Get init data for this PHY */ 1379 data = of_device_get_match_data(dev); 1380 if (!data) 1381 return -EINVAL; 1382 1383 sp = devm_kzalloc(dev, struct_size(sp, clk_data.hws, 1384 CDNS_SIERRA_OUTPUT_CLOCKS), 1385 GFP_KERNEL); 1386 if (!sp) 1387 return -ENOMEM; 1388 dev_set_drvdata(dev, sp); 1389 sp->dev = dev; 1390 sp->init_data = data; 1391 1392 base = devm_platform_ioremap_resource(pdev, 0); 1393 if (IS_ERR(base)) { 1394 dev_err(dev, "missing \"reg\"\n"); 1395 return PTR_ERR(base); 1396 } 1397 1398 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 1399 data->reg_offset_shift); 1400 if (ret) 1401 return ret; 1402 1403 ret = cdns_regfield_init(sp); 1404 if (ret) 1405 return ret; 1406 1407 platform_set_drvdata(pdev, sp); 1408 1409 ret = cdns_sierra_phy_get_clocks(sp, dev); 1410 if (ret) 1411 return ret; 1412 1413 ret = cdns_sierra_clk_register(sp); 1414 if (ret) 1415 return ret; 1416 1417 ret = cdns_sierra_phy_enable_clocks(sp); 1418 if (ret) 1419 goto unregister_clk; 1420 1421 regmap_field_read(sp->pma_cmn_ready, &sp->already_configured); 1422 1423 if (!sp->already_configured) { 1424 ret = cdns_sierra_phy_clk(sp); 1425 if (ret) 1426 goto clk_disable; 1427 1428 ret = cdns_sierra_phy_get_resets(sp, dev); 1429 if (ret) 1430 goto clk_disable; 1431 1432 /* Enable APB */ 1433 reset_control_deassert(sp->apb_rst); 1434 } 1435 1436 /* Check that PHY is present */ 1437 regmap_field_read(sp->macro_id_type, &id_value); 1438 if (sp->init_data->id_value != id_value) { 1439 ret = -EINVAL; 1440 goto ctrl_assert; 1441 } 1442 1443 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 1444 1445 for_each_available_child_of_node_scoped(dn, child) { 1446 struct phy *gphy; 1447 1448 if (!(of_node_name_eq(child, "phy") || 1449 of_node_name_eq(child, "link"))) 1450 continue; 1451 1452 sp->phys[node].lnk_rst = 1453 of_reset_control_array_get_exclusive(child); 1454 1455 if (IS_ERR(sp->phys[node].lnk_rst)) { 1456 dev_err(dev, "failed to get reset %s\n", 1457 child->full_name); 1458 ret = PTR_ERR(sp->phys[node].lnk_rst); 1459 goto put_control; 1460 } 1461 1462 if (!sp->autoconf) { 1463 ret = cdns_sierra_get_optional(&sp->phys[node], child); 1464 if (ret) { 1465 dev_err(dev, "missing property in node %s\n", 1466 child->name); 1467 reset_control_put(sp->phys[node].lnk_rst); 1468 goto put_control; 1469 } 1470 } 1471 1472 sp->num_lanes += sp->phys[node].num_lanes; 1473 1474 if (!sp->already_configured) 1475 gphy = devm_phy_create(dev, child, &ops); 1476 else 1477 gphy = devm_phy_create(dev, child, &noop_ops); 1478 if (IS_ERR(gphy)) { 1479 ret = PTR_ERR(gphy); 1480 reset_control_put(sp->phys[node].lnk_rst); 1481 goto put_control; 1482 } 1483 sp->phys[node].phy = gphy; 1484 phy_set_drvdata(gphy, &sp->phys[node]); 1485 1486 node++; 1487 } 1488 sp->nsubnodes = node; 1489 1490 if (sp->num_lanes > SIERRA_MAX_LANES) { 1491 ret = -EINVAL; 1492 dev_err(dev, "Invalid lane configuration\n"); 1493 goto put_control; 1494 } 1495 1496 /* If more than one subnode, configure the PHY as multilink */ 1497 if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) { 1498 ret = cdns_sierra_phy_configure_multilink(sp); 1499 if (ret) 1500 goto put_control; 1501 } 1502 1503 pm_runtime_enable(dev); 1504 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1505 if (IS_ERR(phy_provider)) { 1506 ret = PTR_ERR(phy_provider); 1507 goto put_control; 1508 } 1509 1510 return 0; 1511 1512 put_control: 1513 while (--node >= 0) 1514 reset_control_put(sp->phys[node].lnk_rst); 1515 ctrl_assert: 1516 if (!sp->already_configured) 1517 reset_control_assert(sp->apb_rst); 1518 clk_disable: 1519 cdns_sierra_phy_disable_clocks(sp); 1520 unregister_clk: 1521 cdns_sierra_clk_unregister(sp); 1522 return ret; 1523 } 1524 1525 static void cdns_sierra_phy_remove(struct platform_device *pdev) 1526 { 1527 struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); 1528 int i; 1529 1530 reset_control_assert(phy->phy_rst); 1531 reset_control_assert(phy->apb_rst); 1532 pm_runtime_disable(&pdev->dev); 1533 1534 cdns_sierra_phy_disable_clocks(phy); 1535 /* 1536 * The device level resets will be put automatically. 1537 * Need to put the subnode resets here though. 1538 */ 1539 for (i = 0; i < phy->nsubnodes; i++) { 1540 reset_control_assert(phy->phys[i].lnk_rst); 1541 reset_control_put(phy->phys[i].lnk_rst); 1542 } 1543 1544 cdns_sierra_clk_unregister(phy); 1545 } 1546 1547 /* USB refclk 100MHz, 20b, SuperSpeed opt2, ext ssc, PLL LC1, multilink */ 1548 static const struct cdns_reg_pairs usb_100_ext_ssc_plllc1_cmn_regs[] = { 1549 {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, 1550 {0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG}, 1551 {0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1552 {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}, 1553 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG}, 1554 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1555 {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1556 }; 1557 1558 /* USB refclk 100MHz, 20b, SuperSpeed opt2, int ssc, PLL LC1, multilink */ 1559 static const struct cdns_reg_pairs usb_100_int_ssc_plllc1_cmn_regs[] = { 1560 {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, 1561 {0x000E, SIERRA_CMN_PLLLC1_MODE_PREG}, 1562 {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG} 1563 }; 1564 1565 static const struct cdns_reg_pairs usb_100_ml_ln_regs[] = { 1566 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 1567 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 1568 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 1569 {0x69AD, SIERRA_DET_STANDEC_D_PREG}, 1570 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 1571 {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 1572 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 1573 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1574 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1575 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1576 {0x001F, SIERRA_PSC_TX_A0_PREG}, 1577 {0x0007, SIERRA_PSC_TX_A1_PREG}, 1578 {0x0003, SIERRA_PSC_TX_A2_PREG}, 1579 {0x0003, SIERRA_PSC_TX_A3_PREG}, 1580 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 1581 {0x0619, SIERRA_PSC_RX_A1_PREG}, 1582 {0x0003, SIERRA_PSC_RX_A2_PREG}, 1583 {0x0001, SIERRA_PSC_RX_A3_PREG}, 1584 {0x0606, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, 1585 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 1586 {0x0003, SIERRA_PLLCTRL_GEN_A_PREG}, 1587 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 1588 {0x5211, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1589 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 1590 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 1591 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1592 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1593 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1594 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1595 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1596 {0x023F, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1597 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1598 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1599 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1600 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 1601 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 1602 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 1603 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1604 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 1605 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1606 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1607 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1608 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1609 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 1610 {0xA9A9, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1611 {0x0014, SIERRA_DEQ_GLUT0}, 1612 {0x0014, SIERRA_DEQ_GLUT1}, 1613 {0x0014, SIERRA_DEQ_GLUT2}, 1614 {0x0014, SIERRA_DEQ_GLUT3}, 1615 {0x0014, SIERRA_DEQ_GLUT4}, 1616 {0x0014, SIERRA_DEQ_GLUT5}, 1617 {0x0014, SIERRA_DEQ_GLUT6}, 1618 {0x0014, SIERRA_DEQ_GLUT7}, 1619 {0x0014, SIERRA_DEQ_GLUT8}, 1620 {0x0014, SIERRA_DEQ_GLUT9}, 1621 {0x0014, SIERRA_DEQ_GLUT10}, 1622 {0x0014, SIERRA_DEQ_GLUT11}, 1623 {0x0014, SIERRA_DEQ_GLUT12}, 1624 {0x0014, SIERRA_DEQ_GLUT13}, 1625 {0x0014, SIERRA_DEQ_GLUT14}, 1626 {0x0014, SIERRA_DEQ_GLUT15}, 1627 {0x0014, SIERRA_DEQ_GLUT16}, 1628 {0x0BAE, SIERRA_DEQ_ALUT0}, 1629 {0x0AEB, SIERRA_DEQ_ALUT1}, 1630 {0x0A28, SIERRA_DEQ_ALUT2}, 1631 {0x0965, SIERRA_DEQ_ALUT3}, 1632 {0x08A2, SIERRA_DEQ_ALUT4}, 1633 {0x07DF, SIERRA_DEQ_ALUT5}, 1634 {0x071C, SIERRA_DEQ_ALUT6}, 1635 {0x0659, SIERRA_DEQ_ALUT7}, 1636 {0x0596, SIERRA_DEQ_ALUT8}, 1637 {0x0514, SIERRA_DEQ_ALUT9}, 1638 {0x0492, SIERRA_DEQ_ALUT10}, 1639 {0x0410, SIERRA_DEQ_ALUT11}, 1640 {0x038E, SIERRA_DEQ_ALUT12}, 1641 {0x030C, SIERRA_DEQ_ALUT13}, 1642 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1643 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 1644 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1645 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1646 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 1647 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1648 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1649 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 1650 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1651 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 1652 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 1653 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 1654 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 1655 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 1656 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 1657 {0x8009, SIERRA_SDFILT_L2H_PREG}, 1658 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1659 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1660 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 1661 }; 1662 1663 static const struct cdns_sierra_vals usb_100_ext_ssc_plllc1_cmn_vals = { 1664 .reg_pairs = usb_100_ext_ssc_plllc1_cmn_regs, 1665 .num_regs = ARRAY_SIZE(usb_100_ext_ssc_plllc1_cmn_regs), 1666 }; 1667 1668 static const struct cdns_sierra_vals usb_100_int_ssc_plllc1_cmn_vals = { 1669 .reg_pairs = usb_100_int_ssc_plllc1_cmn_regs, 1670 .num_regs = ARRAY_SIZE(usb_100_int_ssc_plllc1_cmn_regs), 1671 }; 1672 1673 static const struct cdns_sierra_vals usb_100_ml_ln_vals = { 1674 .reg_pairs = usb_100_ml_ln_regs, 1675 .num_regs = ARRAY_SIZE(usb_100_ml_ln_regs), 1676 }; 1677 1678 /* SGMII PHY PMA lane configuration */ 1679 static const struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = { 1680 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} 1681 }; 1682 1683 static const struct cdns_sierra_vals sgmii_phy_pma_ln_vals = { 1684 .reg_pairs = sgmii_phy_pma_ln_regs, 1685 .num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs), 1686 }; 1687 1688 /* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */ 1689 static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = { 1690 {0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG}, 1691 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1692 {0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}, 1693 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1694 {0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1695 }; 1696 1697 static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = { 1698 {0x688E, SIERRA_DET_STANDEC_D_PREG}, 1699 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1700 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 1701 {0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, 1702 {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG}, 1703 {0x0003, SIERRA_PLLCTRL_GEN_A_PREG}, 1704 {0x0106, SIERRA_PLLCTRL_GEN_D_PREG}, 1705 {0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG }, 1706 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1707 {0x9702, SIERRA_DRVCTRL_BOOST_PREG}, 1708 {0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1709 {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1710 {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1711 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1712 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1713 {0x0186, SIERRA_DEQ_GLUT0}, 1714 {0x0186, SIERRA_DEQ_GLUT1}, 1715 {0x0186, SIERRA_DEQ_GLUT2}, 1716 {0x0186, SIERRA_DEQ_GLUT3}, 1717 {0x0186, SIERRA_DEQ_GLUT4}, 1718 {0x0861, SIERRA_DEQ_ALUT0}, 1719 {0x07E0, SIERRA_DEQ_ALUT1}, 1720 {0x079E, SIERRA_DEQ_ALUT2}, 1721 {0x071D, SIERRA_DEQ_ALUT3}, 1722 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1723 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1724 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1725 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, 1726 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1727 {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1728 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, 1729 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1730 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} 1731 }; 1732 1733 static const struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = { 1734 .reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs, 1735 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs), 1736 }; 1737 1738 static const struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = { 1739 .reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs, 1740 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs), 1741 }; 1742 1743 /* QSGMII PHY PMA lane configuration */ 1744 static const struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = { 1745 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} 1746 }; 1747 1748 static const struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = { 1749 .reg_pairs = qsgmii_phy_pma_ln_regs, 1750 .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs), 1751 }; 1752 1753 /* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ 1754 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = { 1755 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1756 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1757 {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1758 }; 1759 1760 static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = { 1761 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1762 {0x0252, SIERRA_DET_STANDEC_E_PREG}, 1763 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1764 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 1765 {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG}, 1766 {0x0001, SIERRA_PLLCTRL_GEN_A_PREG}, 1767 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1768 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1769 {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1770 {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1771 {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1772 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1773 {0x8422, SIERRA_CTLELUT_CTRL_PREG}, 1774 {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG}, 1775 {0x4111, SIERRA_DFE_SMP_RATESEL_PREG}, 1776 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1777 {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1778 {0x0186, SIERRA_DEQ_GLUT0}, 1779 {0x0186, SIERRA_DEQ_GLUT1}, 1780 {0x0186, SIERRA_DEQ_GLUT2}, 1781 {0x0186, SIERRA_DEQ_GLUT3}, 1782 {0x0186, SIERRA_DEQ_GLUT4}, 1783 {0x0861, SIERRA_DEQ_ALUT0}, 1784 {0x07E0, SIERRA_DEQ_ALUT1}, 1785 {0x079E, SIERRA_DEQ_ALUT2}, 1786 {0x071D, SIERRA_DEQ_ALUT3}, 1787 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1788 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1789 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1790 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, 1791 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1792 {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1793 {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1794 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, 1795 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1796 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} 1797 }; 1798 1799 static const struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = { 1800 .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs, 1801 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs), 1802 }; 1803 1804 static const struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = { 1805 .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs, 1806 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs), 1807 }; 1808 1809 /* PCIE PHY PCS common configuration */ 1810 static const struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { 1811 {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} 1812 }; 1813 1814 static const struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { 1815 .reg_pairs = pcie_phy_pcs_cmn_regs, 1816 .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), 1817 }; 1818 1819 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1820 static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = { 1821 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1822 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1823 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1824 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 1825 }; 1826 1827 /* 1828 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1829 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1830 */ 1831 static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { 1832 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1833 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1834 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1835 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1836 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1837 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1838 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1839 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1840 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1841 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1842 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1843 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1844 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1845 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1846 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1847 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1848 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1849 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1850 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1851 {0x0041, SIERRA_DEQ_GLUT0}, 1852 {0x0082, SIERRA_DEQ_GLUT1}, 1853 {0x00C3, SIERRA_DEQ_GLUT2}, 1854 {0x0145, SIERRA_DEQ_GLUT3}, 1855 {0x0186, SIERRA_DEQ_GLUT4}, 1856 {0x09E7, SIERRA_DEQ_ALUT0}, 1857 {0x09A6, SIERRA_DEQ_ALUT1}, 1858 {0x0965, SIERRA_DEQ_ALUT2}, 1859 {0x08E3, SIERRA_DEQ_ALUT3}, 1860 {0x00FA, SIERRA_DEQ_DFETAP0}, 1861 {0x00FA, SIERRA_DEQ_DFETAP1}, 1862 {0x00FA, SIERRA_DEQ_DFETAP2}, 1863 {0x00FA, SIERRA_DEQ_DFETAP3}, 1864 {0x00FA, SIERRA_DEQ_DFETAP4}, 1865 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1866 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1867 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1868 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1869 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1870 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1871 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 1872 {0x002B, SIERRA_CPI_TRIM_PREG}, 1873 {0x0003, SIERRA_EPI_CTRL_PREG}, 1874 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1875 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1876 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1877 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1878 }; 1879 1880 static const struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = { 1881 .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs, 1882 .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs), 1883 }; 1884 1885 static const struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = { 1886 .reg_pairs = ml_pcie_100_no_ssc_ln_regs, 1887 .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs), 1888 }; 1889 1890 /* 1891 * TI J721E: 1892 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1893 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1894 */ 1895 static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { 1896 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1897 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1898 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1899 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1900 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1901 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1902 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1903 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1904 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1905 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1906 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1907 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1908 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1909 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1910 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1911 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1912 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1913 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1914 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1915 {0x0041, SIERRA_DEQ_GLUT0}, 1916 {0x0082, SIERRA_DEQ_GLUT1}, 1917 {0x00C3, SIERRA_DEQ_GLUT2}, 1918 {0x0145, SIERRA_DEQ_GLUT3}, 1919 {0x0186, SIERRA_DEQ_GLUT4}, 1920 {0x09E7, SIERRA_DEQ_ALUT0}, 1921 {0x09A6, SIERRA_DEQ_ALUT1}, 1922 {0x0965, SIERRA_DEQ_ALUT2}, 1923 {0x08E3, SIERRA_DEQ_ALUT3}, 1924 {0x00FA, SIERRA_DEQ_DFETAP0}, 1925 {0x00FA, SIERRA_DEQ_DFETAP1}, 1926 {0x00FA, SIERRA_DEQ_DFETAP2}, 1927 {0x00FA, SIERRA_DEQ_DFETAP3}, 1928 {0x00FA, SIERRA_DEQ_DFETAP4}, 1929 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1930 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1931 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1932 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1933 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1934 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1935 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 1936 {0x002B, SIERRA_CPI_TRIM_PREG}, 1937 {0x0003, SIERRA_EPI_CTRL_PREG}, 1938 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1939 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1940 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1941 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 1942 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 1943 }; 1944 1945 static const struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = { 1946 .reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs, 1947 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs), 1948 }; 1949 1950 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1951 static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = { 1952 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 1953 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1954 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1955 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1956 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1957 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 1958 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 1959 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 1960 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 1961 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 1962 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 1963 }; 1964 1965 /* 1966 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 1967 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1968 */ 1969 static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { 1970 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1971 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1972 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1973 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1974 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1975 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1976 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1977 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1978 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1979 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1980 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1981 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1982 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1983 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1984 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1985 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1986 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1987 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1988 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1989 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1990 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1991 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1992 {0x0041, SIERRA_DEQ_GLUT0}, 1993 {0x0082, SIERRA_DEQ_GLUT1}, 1994 {0x00C3, SIERRA_DEQ_GLUT2}, 1995 {0x0145, SIERRA_DEQ_GLUT3}, 1996 {0x0186, SIERRA_DEQ_GLUT4}, 1997 {0x09E7, SIERRA_DEQ_ALUT0}, 1998 {0x09A6, SIERRA_DEQ_ALUT1}, 1999 {0x0965, SIERRA_DEQ_ALUT2}, 2000 {0x08E3, SIERRA_DEQ_ALUT3}, 2001 {0x00FA, SIERRA_DEQ_DFETAP0}, 2002 {0x00FA, SIERRA_DEQ_DFETAP1}, 2003 {0x00FA, SIERRA_DEQ_DFETAP2}, 2004 {0x00FA, SIERRA_DEQ_DFETAP3}, 2005 {0x00FA, SIERRA_DEQ_DFETAP4}, 2006 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2007 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2008 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2009 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2010 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2011 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2012 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2013 {0x002B, SIERRA_CPI_TRIM_PREG}, 2014 {0x0003, SIERRA_EPI_CTRL_PREG}, 2015 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2016 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2017 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2018 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2019 }; 2020 2021 static const struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = { 2022 .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs, 2023 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs), 2024 }; 2025 2026 static const struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = { 2027 .reg_pairs = ml_pcie_100_int_ssc_ln_regs, 2028 .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs), 2029 }; 2030 2031 /* 2032 * TI J721E: 2033 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 2034 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 2035 */ 2036 static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { 2037 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2038 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2039 {0x0004, SIERRA_PSC_LN_A3_PREG}, 2040 {0x0004, SIERRA_PSC_LN_A4_PREG}, 2041 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 2042 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2043 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2044 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2045 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2046 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2047 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2048 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2049 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2050 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2051 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2052 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2053 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2054 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2055 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2056 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2057 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2058 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2059 {0x0041, SIERRA_DEQ_GLUT0}, 2060 {0x0082, SIERRA_DEQ_GLUT1}, 2061 {0x00C3, SIERRA_DEQ_GLUT2}, 2062 {0x0145, SIERRA_DEQ_GLUT3}, 2063 {0x0186, SIERRA_DEQ_GLUT4}, 2064 {0x09E7, SIERRA_DEQ_ALUT0}, 2065 {0x09A6, SIERRA_DEQ_ALUT1}, 2066 {0x0965, SIERRA_DEQ_ALUT2}, 2067 {0x08E3, SIERRA_DEQ_ALUT3}, 2068 {0x00FA, SIERRA_DEQ_DFETAP0}, 2069 {0x00FA, SIERRA_DEQ_DFETAP1}, 2070 {0x00FA, SIERRA_DEQ_DFETAP2}, 2071 {0x00FA, SIERRA_DEQ_DFETAP3}, 2072 {0x00FA, SIERRA_DEQ_DFETAP4}, 2073 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2074 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2075 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2076 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2077 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2078 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2079 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2080 {0x002B, SIERRA_CPI_TRIM_PREG}, 2081 {0x0003, SIERRA_EPI_CTRL_PREG}, 2082 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2083 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2084 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2085 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 2086 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 2087 }; 2088 2089 static const struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = { 2090 .reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs, 2091 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs), 2092 }; 2093 2094 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ 2095 static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = { 2096 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2097 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2098 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2099 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2100 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2101 }; 2102 2103 /* 2104 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 2105 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 2106 */ 2107 static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { 2108 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2109 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2110 {0x0004, SIERRA_PSC_LN_A3_PREG}, 2111 {0x0004, SIERRA_PSC_LN_A4_PREG}, 2112 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 2113 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2114 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2115 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2116 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2117 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2118 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2119 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2120 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2121 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2122 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2123 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2124 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2125 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2126 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2127 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2128 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2129 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2130 {0x0041, SIERRA_DEQ_GLUT0}, 2131 {0x0082, SIERRA_DEQ_GLUT1}, 2132 {0x00C3, SIERRA_DEQ_GLUT2}, 2133 {0x0145, SIERRA_DEQ_GLUT3}, 2134 {0x0186, SIERRA_DEQ_GLUT4}, 2135 {0x09E7, SIERRA_DEQ_ALUT0}, 2136 {0x09A6, SIERRA_DEQ_ALUT1}, 2137 {0x0965, SIERRA_DEQ_ALUT2}, 2138 {0x08E3, SIERRA_DEQ_ALUT3}, 2139 {0x00FA, SIERRA_DEQ_DFETAP0}, 2140 {0x00FA, SIERRA_DEQ_DFETAP1}, 2141 {0x00FA, SIERRA_DEQ_DFETAP2}, 2142 {0x00FA, SIERRA_DEQ_DFETAP3}, 2143 {0x00FA, SIERRA_DEQ_DFETAP4}, 2144 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2145 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2146 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2147 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2148 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2149 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2150 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2151 {0x002B, SIERRA_CPI_TRIM_PREG}, 2152 {0x0003, SIERRA_EPI_CTRL_PREG}, 2153 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2154 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2155 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2156 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2157 }; 2158 2159 static const struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = { 2160 .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs, 2161 .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs), 2162 }; 2163 2164 static const struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = { 2165 .reg_pairs = ml_pcie_100_ext_ssc_ln_regs, 2166 .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs), 2167 }; 2168 2169 /* 2170 * TI J721E: 2171 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 2172 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 2173 */ 2174 static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { 2175 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2176 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2177 {0x0004, SIERRA_PSC_LN_A3_PREG}, 2178 {0x0004, SIERRA_PSC_LN_A4_PREG}, 2179 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 2180 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2181 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2182 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2183 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2184 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2185 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2186 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2187 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2188 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2189 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2190 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2191 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2192 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2193 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2194 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2195 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2196 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2197 {0x0041, SIERRA_DEQ_GLUT0}, 2198 {0x0082, SIERRA_DEQ_GLUT1}, 2199 {0x00C3, SIERRA_DEQ_GLUT2}, 2200 {0x0145, SIERRA_DEQ_GLUT3}, 2201 {0x0186, SIERRA_DEQ_GLUT4}, 2202 {0x09E7, SIERRA_DEQ_ALUT0}, 2203 {0x09A6, SIERRA_DEQ_ALUT1}, 2204 {0x0965, SIERRA_DEQ_ALUT2}, 2205 {0x08E3, SIERRA_DEQ_ALUT3}, 2206 {0x00FA, SIERRA_DEQ_DFETAP0}, 2207 {0x00FA, SIERRA_DEQ_DFETAP1}, 2208 {0x00FA, SIERRA_DEQ_DFETAP2}, 2209 {0x00FA, SIERRA_DEQ_DFETAP3}, 2210 {0x00FA, SIERRA_DEQ_DFETAP4}, 2211 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2212 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2213 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2214 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2215 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2216 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2217 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2218 {0x002B, SIERRA_CPI_TRIM_PREG}, 2219 {0x0003, SIERRA_EPI_CTRL_PREG}, 2220 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2221 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2222 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2223 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}, 2224 {0x0002, SIERRA_TX_RCVDET_OVRD_PREG} 2225 }; 2226 2227 static const struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = { 2228 .reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs, 2229 .num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs), 2230 }; 2231 2232 /* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ 2233 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = { 2234 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2235 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2236 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2237 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 2238 }; 2239 2240 /* refclk100MHz_32b_PCIe_ln_no_ssc */ 2241 static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { 2242 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2243 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2244 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2245 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2246 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2247 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2248 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2249 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2250 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2251 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2252 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2253 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2254 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2255 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2256 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2257 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2258 {0x0041, SIERRA_DEQ_GLUT0}, 2259 {0x0082, SIERRA_DEQ_GLUT1}, 2260 {0x00C3, SIERRA_DEQ_GLUT2}, 2261 {0x0145, SIERRA_DEQ_GLUT3}, 2262 {0x0186, SIERRA_DEQ_GLUT4}, 2263 {0x09E7, SIERRA_DEQ_ALUT0}, 2264 {0x09A6, SIERRA_DEQ_ALUT1}, 2265 {0x0965, SIERRA_DEQ_ALUT2}, 2266 {0x08E3, SIERRA_DEQ_ALUT3}, 2267 {0x00FA, SIERRA_DEQ_DFETAP0}, 2268 {0x00FA, SIERRA_DEQ_DFETAP1}, 2269 {0x00FA, SIERRA_DEQ_DFETAP2}, 2270 {0x00FA, SIERRA_DEQ_DFETAP3}, 2271 {0x00FA, SIERRA_DEQ_DFETAP4}, 2272 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2273 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2274 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2275 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2276 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2277 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2278 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2279 {0x002B, SIERRA_CPI_TRIM_PREG}, 2280 {0x0003, SIERRA_EPI_CTRL_PREG}, 2281 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2282 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2283 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2284 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2285 }; 2286 2287 static const struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = { 2288 .reg_pairs = cdns_pcie_cmn_regs_no_ssc, 2289 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc), 2290 }; 2291 2292 static const struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = { 2293 .reg_pairs = cdns_pcie_ln_regs_no_ssc, 2294 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc), 2295 }; 2296 2297 /* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ 2298 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = { 2299 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 2300 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2301 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2302 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2303 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2304 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 2305 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 2306 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 2307 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 2308 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 2309 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 2310 }; 2311 2312 /* refclk100MHz_32b_PCIe_ln_int_ssc */ 2313 static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { 2314 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2315 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2316 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2317 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2318 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2319 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2320 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2321 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2322 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2323 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2324 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2325 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2326 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2327 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2328 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2329 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2330 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2331 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2332 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2333 {0x0041, SIERRA_DEQ_GLUT0}, 2334 {0x0082, SIERRA_DEQ_GLUT1}, 2335 {0x00C3, SIERRA_DEQ_GLUT2}, 2336 {0x0145, SIERRA_DEQ_GLUT3}, 2337 {0x0186, SIERRA_DEQ_GLUT4}, 2338 {0x09E7, SIERRA_DEQ_ALUT0}, 2339 {0x09A6, SIERRA_DEQ_ALUT1}, 2340 {0x0965, SIERRA_DEQ_ALUT2}, 2341 {0x08E3, SIERRA_DEQ_ALUT3}, 2342 {0x00FA, SIERRA_DEQ_DFETAP0}, 2343 {0x00FA, SIERRA_DEQ_DFETAP1}, 2344 {0x00FA, SIERRA_DEQ_DFETAP2}, 2345 {0x00FA, SIERRA_DEQ_DFETAP3}, 2346 {0x00FA, SIERRA_DEQ_DFETAP4}, 2347 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2348 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2349 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2350 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2351 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2352 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2353 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2354 {0x002B, SIERRA_CPI_TRIM_PREG}, 2355 {0x0003, SIERRA_EPI_CTRL_PREG}, 2356 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2357 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2358 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2359 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2360 }; 2361 2362 static const struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = { 2363 .reg_pairs = cdns_pcie_cmn_regs_int_ssc, 2364 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc), 2365 }; 2366 2367 static const struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = { 2368 .reg_pairs = cdns_pcie_ln_regs_int_ssc, 2369 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc), 2370 }; 2371 2372 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 2373 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 2374 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2375 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2376 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 2377 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2378 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2379 }; 2380 2381 /* refclk100MHz_32b_PCIe_ln_ext_ssc */ 2382 static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 2383 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 2384 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 2385 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 2386 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 2387 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2388 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 2389 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 2390 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2391 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2392 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 2393 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 2394 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2395 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2396 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2397 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2398 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2399 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2400 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2401 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 2402 {0x0041, SIERRA_DEQ_GLUT0}, 2403 {0x0082, SIERRA_DEQ_GLUT1}, 2404 {0x00C3, SIERRA_DEQ_GLUT2}, 2405 {0x0145, SIERRA_DEQ_GLUT3}, 2406 {0x0186, SIERRA_DEQ_GLUT4}, 2407 {0x09E7, SIERRA_DEQ_ALUT0}, 2408 {0x09A6, SIERRA_DEQ_ALUT1}, 2409 {0x0965, SIERRA_DEQ_ALUT2}, 2410 {0x08E3, SIERRA_DEQ_ALUT3}, 2411 {0x00FA, SIERRA_DEQ_DFETAP0}, 2412 {0x00FA, SIERRA_DEQ_DFETAP1}, 2413 {0x00FA, SIERRA_DEQ_DFETAP2}, 2414 {0x00FA, SIERRA_DEQ_DFETAP3}, 2415 {0x00FA, SIERRA_DEQ_DFETAP4}, 2416 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 2417 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 2418 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 2419 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2420 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 2421 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 2422 {0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG}, 2423 {0x002B, SIERRA_CPI_TRIM_PREG}, 2424 {0x0003, SIERRA_EPI_CTRL_PREG}, 2425 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 2426 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2427 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2428 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 2429 }; 2430 2431 static const struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = { 2432 .reg_pairs = cdns_pcie_cmn_regs_ext_ssc, 2433 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 2434 }; 2435 2436 static const struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = { 2437 .reg_pairs = cdns_pcie_ln_regs_ext_ssc, 2438 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 2439 }; 2440 2441 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 2442 static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 2443 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 2444 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2445 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2446 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 2447 }; 2448 2449 /* refclk100MHz_20b_USB_ln_ext_ssc */ 2450 static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 2451 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 2452 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 2453 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 2454 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 2455 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 2456 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 2457 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 2458 {0xCF00, SIERRA_PSM_DIAG_PREG}, 2459 {0x001F, SIERRA_PSC_TX_A0_PREG}, 2460 {0x0007, SIERRA_PSC_TX_A1_PREG}, 2461 {0x0003, SIERRA_PSC_TX_A2_PREG}, 2462 {0x0003, SIERRA_PSC_TX_A3_PREG}, 2463 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 2464 {0x0003, SIERRA_PSC_RX_A1_PREG}, 2465 {0x0003, SIERRA_PSC_RX_A2_PREG}, 2466 {0x0001, SIERRA_PSC_RX_A3_PREG}, 2467 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 2468 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 2469 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 2470 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 2471 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 2472 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 2473 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 2474 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 2475 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2476 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 2477 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 2478 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 2479 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 2480 {0x0000, SIERRA_CREQ_SPARE_PREG}, 2481 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 2482 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 2483 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 2484 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 2485 {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, 2486 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 2487 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2488 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 2489 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 2490 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 2491 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 2492 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 2493 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 2494 {0x0014, SIERRA_DEQ_GLUT0}, 2495 {0x0014, SIERRA_DEQ_GLUT1}, 2496 {0x0014, SIERRA_DEQ_GLUT2}, 2497 {0x0014, SIERRA_DEQ_GLUT3}, 2498 {0x0014, SIERRA_DEQ_GLUT4}, 2499 {0x0014, SIERRA_DEQ_GLUT5}, 2500 {0x0014, SIERRA_DEQ_GLUT6}, 2501 {0x0014, SIERRA_DEQ_GLUT7}, 2502 {0x0014, SIERRA_DEQ_GLUT8}, 2503 {0x0014, SIERRA_DEQ_GLUT9}, 2504 {0x0014, SIERRA_DEQ_GLUT10}, 2505 {0x0014, SIERRA_DEQ_GLUT11}, 2506 {0x0014, SIERRA_DEQ_GLUT12}, 2507 {0x0014, SIERRA_DEQ_GLUT13}, 2508 {0x0014, SIERRA_DEQ_GLUT14}, 2509 {0x0014, SIERRA_DEQ_GLUT15}, 2510 {0x0014, SIERRA_DEQ_GLUT16}, 2511 {0x0BAE, SIERRA_DEQ_ALUT0}, 2512 {0x0AEB, SIERRA_DEQ_ALUT1}, 2513 {0x0A28, SIERRA_DEQ_ALUT2}, 2514 {0x0965, SIERRA_DEQ_ALUT3}, 2515 {0x08A2, SIERRA_DEQ_ALUT4}, 2516 {0x07DF, SIERRA_DEQ_ALUT5}, 2517 {0x071C, SIERRA_DEQ_ALUT6}, 2518 {0x0659, SIERRA_DEQ_ALUT7}, 2519 {0x0596, SIERRA_DEQ_ALUT8}, 2520 {0x0514, SIERRA_DEQ_ALUT9}, 2521 {0x0492, SIERRA_DEQ_ALUT10}, 2522 {0x0410, SIERRA_DEQ_ALUT11}, 2523 {0x038E, SIERRA_DEQ_ALUT12}, 2524 {0x030C, SIERRA_DEQ_ALUT13}, 2525 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 2526 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 2527 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 2528 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 2529 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 2530 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 2531 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 2532 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 2533 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 2534 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 2535 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 2536 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 2537 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 2538 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 2539 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 2540 {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, 2541 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 2542 {0x8009, SIERRA_SDFILT_L2H_PREG}, 2543 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 2544 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 2545 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 2546 }; 2547 2548 static const struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = { 2549 .reg_pairs = cdns_usb_cmn_regs_ext_ssc, 2550 .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 2551 }; 2552 2553 static const struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = { 2554 .reg_pairs = cdns_usb_ln_regs_ext_ssc, 2555 .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 2556 }; 2557 2558 /* SGMII PHY common configuration */ 2559 static const struct cdns_reg_pairs sgmii_pma_cmn_vals[] = { 2560 {0x0180, SIERRA_SDOSCCAL_CLK_CNT_PREG}, 2561 {0x6000, SIERRA_CMN_REFRCV_PREG}, 2562 {0x0031, SIERRA_CMN_RESCAL_CTRLA_PREG}, 2563 {0x001C, SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG}, 2564 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 2565 {0x0000, SIERRA_CMN_PLLLC_LOCKSEARCH_PREG}, 2566 {0x8103, SIERRA_CMN_PLLLC_CLK0_PREG}, 2567 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 2568 {0x0027, SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG}, 2569 {0x0062, SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG}, 2570 {0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 2571 {0x0000, SIERRA_CMN_PLLLC_INIT_PREG}, 2572 {0x0000, SIERRA_CMN_PLLLC_ITERTMR_PREG}, 2573 {0x0020, SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG}, 2574 {0x0013, SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG}, 2575 {0x0013, SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG}, 2576 }; 2577 2578 static const struct cdns_sierra_vals sgmii_cmn_vals = { 2579 .reg_pairs = sgmii_pma_cmn_vals, 2580 .num_regs = ARRAY_SIZE(sgmii_pma_cmn_vals), 2581 }; 2582 2583 /* SGMII PHY lane configuration */ 2584 static const struct cdns_reg_pairs sgmii_ln_regs[] = { 2585 {0x691E, SIERRA_DET_STANDEC_D_PREG}, 2586 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 2587 {0x0104, SIERRA_PLLCTRL_FBDIV_MODE01_PREG}, 2588 {0x0013, SIERRA_PLLCTRL_SUBRATE_PREG}, 2589 {0x0106, SIERRA_PLLCTRL_GEN_D_PREG}, 2590 {0x5234, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 2591 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 2592 {0x00AB, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 2593 {0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 2594 {0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG}, 2595 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 2596 {0x6320, SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG}, 2597 {0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 2598 {0x15A2, SIERRA_LN_SPARE_REG_PREG}, 2599 {0x7900, SIERRA_DEQ_BLK_TAU_CTRL1_PREG}, 2600 {0x2202, SIERRA_DEQ_BLK_TAU_CTRL4_PREG}, 2601 {0x2206, SIERRA_DEQ_TAU_CTRL2_PREG}, 2602 {0x0005, SIERRA_LANE_TX_RECEIVER_DETECT_PREG}, 2603 {0x8001, SIERRA_CREQ_SPARE_PREG}, 2604 {0x0000, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 2605 {0xD004, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 2606 {0x0101, SIERRA_DEQ_GLUT9}, 2607 {0x0101, SIERRA_DEQ_GLUT10}, 2608 {0x0101, SIERRA_DEQ_GLUT11}, 2609 {0x0101, SIERRA_DEQ_GLUT12}, 2610 {0x0000, SIERRA_DEQ_GLUT13}, 2611 {0x0000, SIERRA_DEQ_GLUT16}, 2612 {0x0000, SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG}, 2613 {0x0000, SIERRA_TAU_EN_CEPH2TO0_PREG}, 2614 {0x0003, SIERRA_TAU_EN_CEPH5TO3_PREG}, 2615 {0x0101, SIERRA_DEQ_ALUT8}, 2616 {0x0101, SIERRA_DEQ_ALUT9}, 2617 {0x0100, SIERRA_DEQ_ALUT10}, 2618 {0x0000, SIERRA_OEPH_EN_CTRL_PREG}, 2619 {0x5425, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 2620 {0x7458, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 2621 {0x321F, SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG}, 2622 }; 2623 2624 static const struct cdns_sierra_vals sgmii_pma_ln_vals = { 2625 .reg_pairs = sgmii_ln_regs, 2626 .num_regs = ARRAY_SIZE(sgmii_ln_regs), 2627 }; 2628 2629 static const struct cdns_sierra_data cdns_map_sierra = { 2630 .id_value = SIERRA_MACRO_ID, 2631 .block_offset_shift = 0x2, 2632 .reg_offset_shift = 0x2, 2633 .pcs_cmn_vals = { 2634 [TYPE_PCIE] = { 2635 [TYPE_NONE] = { 2636 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2637 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2638 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2639 }, 2640 [TYPE_SGMII] = { 2641 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2642 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2643 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2644 }, 2645 [TYPE_QSGMII] = { 2646 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2647 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2648 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2649 }, 2650 [TYPE_USB] = { 2651 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2652 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2653 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2654 }, 2655 }, 2656 }, 2657 .pma_cmn_vals = { 2658 [TYPE_PCIE] = { 2659 [TYPE_NONE] = { 2660 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 2661 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 2662 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 2663 }, 2664 [TYPE_SGMII] = { 2665 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2666 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2667 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2668 }, 2669 [TYPE_QSGMII] = { 2670 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2671 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2672 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2673 }, 2674 [TYPE_USB] = { 2675 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2676 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2677 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2678 }, 2679 }, 2680 [TYPE_USB] = { 2681 [TYPE_NONE] = { 2682 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2683 }, 2684 [TYPE_PCIE] = { 2685 [EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals, 2686 [INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals, 2687 }, 2688 }, 2689 [TYPE_SGMII] = { 2690 [TYPE_NONE] = { 2691 [NO_SSC] = &sgmii_cmn_vals, 2692 }, 2693 [TYPE_PCIE] = { 2694 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2695 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2696 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2697 }, 2698 }, 2699 [TYPE_QSGMII] = { 2700 [TYPE_PCIE] = { 2701 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2702 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2703 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2704 }, 2705 }, 2706 }, 2707 .pma_ln_vals = { 2708 [TYPE_PCIE] = { 2709 [TYPE_NONE] = { 2710 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 2711 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 2712 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 2713 }, 2714 [TYPE_SGMII] = { 2715 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2716 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2717 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2718 }, 2719 [TYPE_QSGMII] = { 2720 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2721 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2722 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2723 }, 2724 [TYPE_USB] = { 2725 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 2726 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 2727 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 2728 }, 2729 }, 2730 [TYPE_USB] = { 2731 [TYPE_NONE] = { 2732 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2733 }, 2734 [TYPE_PCIE] = { 2735 [EXTERNAL_SSC] = &usb_100_ml_ln_vals, 2736 [INTERNAL_SSC] = &usb_100_ml_ln_vals, 2737 }, 2738 }, 2739 [TYPE_SGMII] = { 2740 [TYPE_NONE] = { 2741 [NO_SSC] = &sgmii_pma_ln_vals, 2742 }, 2743 [TYPE_PCIE] = { 2744 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2745 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2746 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2747 }, 2748 }, 2749 [TYPE_QSGMII] = { 2750 [TYPE_PCIE] = { 2751 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2752 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2753 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2754 }, 2755 }, 2756 }, 2757 }; 2758 2759 static const struct cdns_sierra_data cdns_ti_map_sierra = { 2760 .id_value = SIERRA_MACRO_ID, 2761 .block_offset_shift = 0x0, 2762 .reg_offset_shift = 0x1, 2763 .pcs_cmn_vals = { 2764 [TYPE_PCIE] = { 2765 [TYPE_NONE] = { 2766 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2767 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2768 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2769 }, 2770 [TYPE_SGMII] = { 2771 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2772 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2773 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2774 }, 2775 [TYPE_QSGMII] = { 2776 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2777 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2778 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2779 }, 2780 [TYPE_USB] = { 2781 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 2782 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2783 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 2784 }, 2785 }, 2786 }, 2787 .phy_pma_ln_vals = { 2788 [TYPE_SGMII] = { 2789 [TYPE_PCIE] = { 2790 [NO_SSC] = &sgmii_phy_pma_ln_vals, 2791 [EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals, 2792 [INTERNAL_SSC] = &sgmii_phy_pma_ln_vals, 2793 }, 2794 }, 2795 [TYPE_QSGMII] = { 2796 [TYPE_PCIE] = { 2797 [NO_SSC] = &qsgmii_phy_pma_ln_vals, 2798 [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 2799 [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 2800 }, 2801 }, 2802 }, 2803 .pma_cmn_vals = { 2804 [TYPE_PCIE] = { 2805 [TYPE_NONE] = { 2806 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 2807 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 2808 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 2809 }, 2810 [TYPE_SGMII] = { 2811 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2812 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2813 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2814 }, 2815 [TYPE_QSGMII] = { 2816 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2817 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2818 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2819 }, 2820 [TYPE_USB] = { 2821 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 2822 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 2823 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 2824 }, 2825 }, 2826 [TYPE_USB] = { 2827 [TYPE_NONE] = { 2828 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 2829 }, 2830 [TYPE_PCIE] = { 2831 [EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals, 2832 [INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals, 2833 }, 2834 }, 2835 [TYPE_SGMII] = { 2836 [TYPE_PCIE] = { 2837 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2838 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2839 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals, 2840 }, 2841 }, 2842 [TYPE_QSGMII] = { 2843 [TYPE_PCIE] = { 2844 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2845 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2846 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 2847 }, 2848 }, 2849 }, 2850 .pma_ln_vals = { 2851 [TYPE_PCIE] = { 2852 [TYPE_NONE] = { 2853 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 2854 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 2855 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 2856 }, 2857 [TYPE_SGMII] = { 2858 [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2859 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2860 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2861 }, 2862 [TYPE_QSGMII] = { 2863 [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2864 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2865 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2866 }, 2867 [TYPE_USB] = { 2868 [NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals, 2869 [EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals, 2870 [INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals, 2871 }, 2872 }, 2873 [TYPE_USB] = { 2874 [TYPE_NONE] = { 2875 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 2876 }, 2877 [TYPE_PCIE] = { 2878 [EXTERNAL_SSC] = &usb_100_ml_ln_vals, 2879 [INTERNAL_SSC] = &usb_100_ml_ln_vals, 2880 }, 2881 }, 2882 [TYPE_SGMII] = { 2883 [TYPE_PCIE] = { 2884 [NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2885 [EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2886 [INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals, 2887 }, 2888 }, 2889 [TYPE_QSGMII] = { 2890 [TYPE_PCIE] = { 2891 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2892 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2893 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 2894 }, 2895 }, 2896 }, 2897 }; 2898 2899 static const struct of_device_id cdns_sierra_id_table[] = { 2900 { 2901 .compatible = "cdns,sierra-phy-t0", 2902 .data = &cdns_map_sierra, 2903 }, 2904 { 2905 .compatible = "ti,sierra-phy-t0", 2906 .data = &cdns_ti_map_sierra, 2907 }, 2908 {} 2909 }; 2910 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 2911 2912 static struct platform_driver cdns_sierra_driver = { 2913 .probe = cdns_sierra_phy_probe, 2914 .remove = cdns_sierra_phy_remove, 2915 .driver = { 2916 .name = "cdns-sierra-phy", 2917 .of_match_table = cdns_sierra_id_table, 2918 }, 2919 }; 2920 module_platform_driver(cdns_sierra_driver); 2921 2922 MODULE_ALIAS("platform:cdns_sierra"); 2923 MODULE_AUTHOR("Cadence Design Systems"); 2924 MODULE_DESCRIPTION("CDNS sierra phy driver"); 2925 MODULE_LICENSE("GPL v2"); 2926