1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <dt-bindings/phy/phy.h> 23 24 /* PHY register offsets */ 25 #define SIERRA_COMMON_CDB_OFFSET 0x0 26 #define SIERRA_MACRO_ID_REG 0x0 27 28 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 29 ((0x4000 << (block_offset)) + \ 30 (((ln) << 9) << (reg_offset))) 31 #define SIERRA_DET_STANDEC_A 0x000 32 #define SIERRA_DET_STANDEC_B 0x001 33 #define SIERRA_DET_STANDEC_C 0x002 34 #define SIERRA_DET_STANDEC_D 0x003 35 #define SIERRA_DET_STANDEC_E 0x004 36 #define SIERRA_PSM_LANECAL 0x008 37 #define SIERRA_PSM_DIAG 0x015 38 #define SIERRA_PSC_TX_A0 0x028 39 #define SIERRA_PSC_TX_A1 0x029 40 #define SIERRA_PSC_TX_A2 0x02A 41 #define SIERRA_PSC_TX_A3 0x02B 42 #define SIERRA_PSC_RX_A0 0x030 43 #define SIERRA_PSC_RX_A1 0x031 44 #define SIERRA_PSC_RX_A2 0x032 45 #define SIERRA_PSC_RX_A3 0x033 46 #define SIERRA_PLLCTRL_SUBRATE 0x03A 47 #define SIERRA_PLLCTRL_GEN_D 0x03E 48 #define SIERRA_DRVCTRL_ATTEN 0x06A 49 #define SIERRA_CLKPATHCTRL_TMR 0x081 50 #define SIERRA_RX_CREQ_FLTR_A_MODE1 0x087 51 #define SIERRA_RX_CREQ_FLTR_A_MODE0 0x088 52 #define SIERRA_CREQ_CCLKDET_MODE01 0x08E 53 #define SIERRA_RX_CTLE_MAINTENANCE 0x091 54 #define SIERRA_CREQ_FSMCLK_SEL 0x092 55 #define SIERRA_CTLELUT_CTRL 0x098 56 #define SIERRA_DFE_ECMP_RATESEL 0x0C0 57 #define SIERRA_DFE_SMP_RATESEL 0x0C1 58 #define SIERRA_DEQ_VGATUNE_CTRL 0x0E1 59 #define SIERRA_TMRVAL_MODE3 0x16E 60 #define SIERRA_TMRVAL_MODE2 0x16F 61 #define SIERRA_TMRVAL_MODE1 0x170 62 #define SIERRA_TMRVAL_MODE0 0x171 63 #define SIERRA_PICNT_MODE1 0x174 64 #define SIERRA_CPI_OUTBUF_RATESEL 0x17C 65 #define SIERRA_LFPSFILT_NS 0x18A 66 #define SIERRA_LFPSFILT_RD 0x18B 67 #define SIERRA_LFPSFILT_MP 0x18C 68 #define SIERRA_SDFILT_H2L_A 0x191 69 70 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ 71 (0xc000 << (block_offset)) 72 #define SIERRA_PHY_PLL_CFG 0xe 73 74 #define SIERRA_MACRO_ID 0x00007364 75 #define SIERRA_MAX_LANES 4 76 77 static const struct reg_field macro_id_type = 78 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 79 static const struct reg_field phy_pll_cfg_1 = 80 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 81 82 struct cdns_sierra_inst { 83 struct phy *phy; 84 u32 phy_type; 85 u32 num_lanes; 86 u32 mlane; 87 struct reset_control *lnk_rst; 88 }; 89 90 struct cdns_reg_pairs { 91 u16 val; 92 u32 off; 93 }; 94 95 struct cdns_sierra_data { 96 u32 id_value; 97 u8 block_offset_shift; 98 u8 reg_offset_shift; 99 u32 pcie_regs; 100 u32 usb_regs; 101 struct cdns_reg_pairs *pcie_vals; 102 struct cdns_reg_pairs *usb_vals; 103 }; 104 105 struct cdns_regmap_cdb_context { 106 struct device *dev; 107 void __iomem *base; 108 u8 reg_offset_shift; 109 }; 110 111 struct cdns_sierra_phy { 112 struct device *dev; 113 struct regmap *regmap; 114 struct cdns_sierra_data *init_data; 115 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 116 struct reset_control *phy_rst; 117 struct reset_control *apb_rst; 118 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 119 struct regmap *regmap_phy_config_ctrl; 120 struct regmap *regmap_common_cdb; 121 struct regmap_field *macro_id_type; 122 struct regmap_field *phy_pll_cfg_1; 123 struct clk *clk; 124 int nsubnodes; 125 bool autoconf; 126 }; 127 128 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 129 { 130 struct cdns_regmap_cdb_context *ctx = context; 131 u32 offset = reg << ctx->reg_offset_shift; 132 133 writew(val, ctx->base + offset); 134 135 return 0; 136 } 137 138 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 139 { 140 struct cdns_regmap_cdb_context *ctx = context; 141 u32 offset = reg << ctx->reg_offset_shift; 142 143 *val = readw(ctx->base + offset); 144 return 0; 145 } 146 147 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 148 { \ 149 .name = "sierra_lane" n "_cdb", \ 150 .reg_stride = 1, \ 151 .fast_io = true, \ 152 .reg_write = cdns_regmap_write, \ 153 .reg_read = cdns_regmap_read, \ 154 } 155 156 static struct regmap_config cdns_sierra_lane_cdb_config[] = { 157 SIERRA_LANE_CDB_REGMAP_CONF("0"), 158 SIERRA_LANE_CDB_REGMAP_CONF("1"), 159 SIERRA_LANE_CDB_REGMAP_CONF("2"), 160 SIERRA_LANE_CDB_REGMAP_CONF("3"), 161 }; 162 163 static struct regmap_config cdns_sierra_common_cdb_config = { 164 .name = "sierra_common_cdb", 165 .reg_stride = 1, 166 .fast_io = true, 167 .reg_write = cdns_regmap_write, 168 .reg_read = cdns_regmap_read, 169 }; 170 171 static struct regmap_config cdns_sierra_phy_config_ctrl_config = { 172 .name = "sierra_phy_config_ctrl", 173 .reg_stride = 1, 174 .fast_io = true, 175 .reg_write = cdns_regmap_write, 176 .reg_read = cdns_regmap_read, 177 }; 178 179 static void cdns_sierra_phy_init(struct phy *gphy) 180 { 181 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 182 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 183 struct regmap *regmap = phy->regmap; 184 int i, j; 185 struct cdns_reg_pairs *vals; 186 u32 num_regs; 187 188 if (ins->phy_type == PHY_TYPE_PCIE) { 189 num_regs = phy->init_data->pcie_regs; 190 vals = phy->init_data->pcie_vals; 191 } else if (ins->phy_type == PHY_TYPE_USB3) { 192 num_regs = phy->init_data->usb_regs; 193 vals = phy->init_data->usb_vals; 194 } else { 195 return; 196 } 197 for (i = 0; i < ins->num_lanes; i++) { 198 for (j = 0; j < num_regs ; j++) { 199 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 200 regmap_write(regmap, vals[j].off, vals[j].val); 201 } 202 } 203 } 204 205 static int cdns_sierra_phy_on(struct phy *gphy) 206 { 207 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 208 209 /* Take the PHY lane group out of reset */ 210 return reset_control_deassert(ins->lnk_rst); 211 } 212 213 static int cdns_sierra_phy_off(struct phy *gphy) 214 { 215 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 216 217 return reset_control_assert(ins->lnk_rst); 218 } 219 220 static const struct phy_ops ops = { 221 .power_on = cdns_sierra_phy_on, 222 .power_off = cdns_sierra_phy_off, 223 .owner = THIS_MODULE, 224 }; 225 226 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 227 struct device_node *child) 228 { 229 if (of_property_read_u32(child, "reg", &inst->mlane)) 230 return -EINVAL; 231 232 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 233 return -EINVAL; 234 235 if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type)) 236 return -EINVAL; 237 238 return 0; 239 } 240 241 static const struct of_device_id cdns_sierra_id_table[]; 242 243 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 244 u32 block_offset, u8 reg_offset_shift, 245 const struct regmap_config *config) 246 { 247 struct cdns_regmap_cdb_context *ctx; 248 249 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 250 if (!ctx) 251 return ERR_PTR(-ENOMEM); 252 253 ctx->dev = dev; 254 ctx->base = base + block_offset; 255 ctx->reg_offset_shift = reg_offset_shift; 256 257 return devm_regmap_init(dev, NULL, ctx, config); 258 } 259 260 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 261 { 262 struct device *dev = sp->dev; 263 struct regmap_field *field; 264 struct regmap *regmap; 265 266 regmap = sp->regmap_common_cdb; 267 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 268 if (IS_ERR(field)) { 269 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 270 return PTR_ERR(field); 271 } 272 sp->macro_id_type = field; 273 274 regmap = sp->regmap_phy_config_ctrl; 275 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 276 if (IS_ERR(field)) { 277 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 278 return PTR_ERR(field); 279 } 280 sp->phy_pll_cfg_1 = field; 281 282 return 0; 283 } 284 285 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 286 void __iomem *base, u8 block_offset_shift, 287 u8 reg_offset_shift) 288 { 289 struct device *dev = sp->dev; 290 struct regmap *regmap; 291 u32 block_offset; 292 int i; 293 294 for (i = 0; i < SIERRA_MAX_LANES; i++) { 295 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 296 reg_offset_shift); 297 regmap = cdns_regmap_init(dev, base, block_offset, 298 reg_offset_shift, 299 &cdns_sierra_lane_cdb_config[i]); 300 if (IS_ERR(regmap)) { 301 dev_err(dev, "Failed to init lane CDB regmap\n"); 302 return PTR_ERR(regmap); 303 } 304 sp->regmap_lane_cdb[i] = regmap; 305 } 306 307 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 308 reg_offset_shift, 309 &cdns_sierra_common_cdb_config); 310 if (IS_ERR(regmap)) { 311 dev_err(dev, "Failed to init common CDB regmap\n"); 312 return PTR_ERR(regmap); 313 } 314 sp->regmap_common_cdb = regmap; 315 316 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); 317 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 318 &cdns_sierra_phy_config_ctrl_config); 319 if (IS_ERR(regmap)) { 320 dev_err(dev, "Failed to init PHY config and control regmap\n"); 321 return PTR_ERR(regmap); 322 } 323 sp->regmap_phy_config_ctrl = regmap; 324 325 return 0; 326 } 327 328 static int cdns_sierra_phy_probe(struct platform_device *pdev) 329 { 330 struct cdns_sierra_phy *sp; 331 struct phy_provider *phy_provider; 332 struct device *dev = &pdev->dev; 333 const struct of_device_id *match; 334 struct cdns_sierra_data *data; 335 unsigned int id_value; 336 struct resource *res; 337 int i, ret, node = 0; 338 void __iomem *base; 339 struct device_node *dn = dev->of_node, *child; 340 341 if (of_get_child_count(dn) == 0) 342 return -ENODEV; 343 344 /* Get init data for this PHY */ 345 match = of_match_device(cdns_sierra_id_table, dev); 346 if (!match) 347 return -EINVAL; 348 349 data = (struct cdns_sierra_data *)match->data; 350 351 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 352 if (!sp) 353 return -ENOMEM; 354 dev_set_drvdata(dev, sp); 355 sp->dev = dev; 356 sp->init_data = data; 357 358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 359 base = devm_ioremap_resource(dev, res); 360 if (IS_ERR(base)) { 361 dev_err(dev, "missing \"reg\"\n"); 362 return PTR_ERR(base); 363 } 364 365 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 366 data->reg_offset_shift); 367 if (ret) 368 return ret; 369 370 ret = cdns_regfield_init(sp); 371 if (ret) 372 return ret; 373 374 platform_set_drvdata(pdev, sp); 375 376 sp->clk = devm_clk_get_optional(dev, "phy_clk"); 377 if (IS_ERR(sp->clk)) { 378 dev_err(dev, "failed to get clock phy_clk\n"); 379 return PTR_ERR(sp->clk); 380 } 381 382 sp->phy_rst = devm_reset_control_get(dev, "sierra_reset"); 383 if (IS_ERR(sp->phy_rst)) { 384 dev_err(dev, "failed to get reset\n"); 385 return PTR_ERR(sp->phy_rst); 386 } 387 388 sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb"); 389 if (IS_ERR(sp->apb_rst)) { 390 dev_err(dev, "failed to get apb reset\n"); 391 return PTR_ERR(sp->apb_rst); 392 } 393 394 ret = clk_prepare_enable(sp->clk); 395 if (ret) 396 return ret; 397 398 /* Enable APB */ 399 reset_control_deassert(sp->apb_rst); 400 401 /* Check that PHY is present */ 402 regmap_field_read(sp->macro_id_type, &id_value); 403 if (sp->init_data->id_value != id_value) { 404 ret = -EINVAL; 405 goto clk_disable; 406 } 407 408 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 409 410 for_each_available_child_of_node(dn, child) { 411 struct phy *gphy; 412 413 sp->phys[node].lnk_rst = 414 of_reset_control_get_exclusive_by_index(child, 0); 415 416 if (IS_ERR(sp->phys[node].lnk_rst)) { 417 dev_err(dev, "failed to get reset %s\n", 418 child->full_name); 419 ret = PTR_ERR(sp->phys[node].lnk_rst); 420 goto put_child2; 421 } 422 423 if (!sp->autoconf) { 424 ret = cdns_sierra_get_optional(&sp->phys[node], child); 425 if (ret) { 426 dev_err(dev, "missing property in node %s\n", 427 child->name); 428 goto put_child; 429 } 430 } 431 432 gphy = devm_phy_create(dev, child, &ops); 433 434 if (IS_ERR(gphy)) { 435 ret = PTR_ERR(gphy); 436 goto put_child; 437 } 438 sp->phys[node].phy = gphy; 439 phy_set_drvdata(gphy, &sp->phys[node]); 440 441 /* Initialise the PHY registers, unless auto configured */ 442 if (!sp->autoconf) 443 cdns_sierra_phy_init(gphy); 444 445 node++; 446 } 447 sp->nsubnodes = node; 448 449 /* If more than one subnode, configure the PHY as multilink */ 450 if (!sp->autoconf && sp->nsubnodes > 1) 451 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 452 453 pm_runtime_enable(dev); 454 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 455 reset_control_deassert(sp->phy_rst); 456 return PTR_ERR_OR_ZERO(phy_provider); 457 458 put_child: 459 node++; 460 put_child2: 461 for (i = 0; i < node; i++) 462 reset_control_put(sp->phys[i].lnk_rst); 463 of_node_put(child); 464 clk_disable: 465 clk_disable_unprepare(sp->clk); 466 reset_control_assert(sp->apb_rst); 467 return ret; 468 } 469 470 static int cdns_sierra_phy_remove(struct platform_device *pdev) 471 { 472 struct cdns_sierra_phy *phy = dev_get_drvdata(pdev->dev.parent); 473 int i; 474 475 reset_control_assert(phy->phy_rst); 476 reset_control_assert(phy->apb_rst); 477 pm_runtime_disable(&pdev->dev); 478 479 /* 480 * The device level resets will be put automatically. 481 * Need to put the subnode resets here though. 482 */ 483 for (i = 0; i < phy->nsubnodes; i++) { 484 reset_control_assert(phy->phys[i].lnk_rst); 485 reset_control_put(phy->phys[i].lnk_rst); 486 } 487 return 0; 488 } 489 490 static struct cdns_reg_pairs cdns_usb_regs[] = { 491 /* 492 * Write USB configuration parameters to the PHY. 493 * These values are specific to this specific hardware 494 * configuration. 495 */ 496 {0xFE0A, SIERRA_DET_STANDEC_A}, 497 {0x000F, SIERRA_DET_STANDEC_B}, 498 {0x55A5, SIERRA_DET_STANDEC_C}, 499 {0x69AD, SIERRA_DET_STANDEC_D}, 500 {0x0241, SIERRA_DET_STANDEC_E}, 501 {0x0110, SIERRA_PSM_LANECAL}, 502 {0xCF00, SIERRA_PSM_DIAG}, 503 {0x001F, SIERRA_PSC_TX_A0}, 504 {0x0007, SIERRA_PSC_TX_A1}, 505 {0x0003, SIERRA_PSC_TX_A2}, 506 {0x0003, SIERRA_PSC_TX_A3}, 507 {0x0FFF, SIERRA_PSC_RX_A0}, 508 {0x0003, SIERRA_PSC_RX_A1}, 509 {0x0003, SIERRA_PSC_RX_A2}, 510 {0x0001, SIERRA_PSC_RX_A3}, 511 {0x0001, SIERRA_PLLCTRL_SUBRATE}, 512 {0x0406, SIERRA_PLLCTRL_GEN_D}, 513 {0x0000, SIERRA_DRVCTRL_ATTEN}, 514 {0x823E, SIERRA_CLKPATHCTRL_TMR}, 515 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1}, 516 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0}, 517 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01}, 518 {0x023C, SIERRA_RX_CTLE_MAINTENANCE}, 519 {0x3232, SIERRA_CREQ_FSMCLK_SEL}, 520 {0x8452, SIERRA_CTLELUT_CTRL}, 521 {0x4121, SIERRA_DFE_ECMP_RATESEL}, 522 {0x4121, SIERRA_DFE_SMP_RATESEL}, 523 {0x9999, SIERRA_DEQ_VGATUNE_CTRL}, 524 {0x0330, SIERRA_TMRVAL_MODE0}, 525 {0x01FF, SIERRA_PICNT_MODE1}, 526 {0x0009, SIERRA_CPI_OUTBUF_RATESEL}, 527 {0x000F, SIERRA_LFPSFILT_NS}, 528 {0x0009, SIERRA_LFPSFILT_RD}, 529 {0x0001, SIERRA_LFPSFILT_MP}, 530 {0x8013, SIERRA_SDFILT_H2L_A}, 531 {0x0400, SIERRA_TMRVAL_MODE1}, 532 }; 533 534 static struct cdns_reg_pairs cdns_pcie_regs[] = { 535 /* 536 * Write PCIe configuration parameters to the PHY. 537 * These values are specific to this specific hardware 538 * configuration. 539 */ 540 {0x891f, SIERRA_DET_STANDEC_D}, 541 {0x0053, SIERRA_DET_STANDEC_E}, 542 {0x0400, SIERRA_TMRVAL_MODE2}, 543 {0x0200, SIERRA_TMRVAL_MODE3}, 544 }; 545 546 static const struct cdns_sierra_data cdns_map_sierra = { 547 SIERRA_MACRO_ID, 548 0x2, 549 0x2, 550 ARRAY_SIZE(cdns_pcie_regs), 551 ARRAY_SIZE(cdns_usb_regs), 552 cdns_pcie_regs, 553 cdns_usb_regs 554 }; 555 556 static const struct of_device_id cdns_sierra_id_table[] = { 557 { 558 .compatible = "cdns,sierra-phy-t0", 559 .data = &cdns_map_sierra, 560 }, 561 {} 562 }; 563 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 564 565 static struct platform_driver cdns_sierra_driver = { 566 .probe = cdns_sierra_phy_probe, 567 .remove = cdns_sierra_phy_remove, 568 .driver = { 569 .name = "cdns-sierra-phy", 570 .of_match_table = cdns_sierra_id_table, 571 }, 572 }; 573 module_platform_driver(cdns_sierra_driver); 574 575 MODULE_ALIAS("platform:cdns_sierra"); 576 MODULE_AUTHOR("Cadence Design Systems"); 577 MODULE_DESCRIPTION("CDNS sierra phy driver"); 578 MODULE_LICENSE("GPL v2"); 579