1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cadence Sierra PHY Driver 4 * 5 * Copyright (c) 2018 Cadence Design Systems 6 * Author: Alan Douglas <adouglas@cadence.com> 7 * 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_platform.h> 22 #include <dt-bindings/phy/phy.h> 23 24 /* PHY register offsets */ 25 #define SIERRA_COMMON_CDB_OFFSET 0x0 26 #define SIERRA_MACRO_ID_REG 0x0 27 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 28 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 29 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 30 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 31 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 32 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 33 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 34 35 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 36 ((0x4000 << (block_offset)) + \ 37 (((ln) << 9) << (reg_offset))) 38 39 #define SIERRA_DET_STANDEC_A_PREG 0x000 40 #define SIERRA_DET_STANDEC_B_PREG 0x001 41 #define SIERRA_DET_STANDEC_C_PREG 0x002 42 #define SIERRA_DET_STANDEC_D_PREG 0x003 43 #define SIERRA_DET_STANDEC_E_PREG 0x004 44 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 45 #define SIERRA_PSM_A0IN_TMR_PREG 0x009 46 #define SIERRA_PSM_DIAG_PREG 0x015 47 #define SIERRA_PSC_TX_A0_PREG 0x028 48 #define SIERRA_PSC_TX_A1_PREG 0x029 49 #define SIERRA_PSC_TX_A2_PREG 0x02A 50 #define SIERRA_PSC_TX_A3_PREG 0x02B 51 #define SIERRA_PSC_RX_A0_PREG 0x030 52 #define SIERRA_PSC_RX_A1_PREG 0x031 53 #define SIERRA_PSC_RX_A2_PREG 0x032 54 #define SIERRA_PSC_RX_A3_PREG 0x033 55 #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 56 #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 57 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 58 #define SIERRA_PLLCTRL_STATUS_PREG 0x044 59 #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 60 #define SIERRA_DFE_BIASTRIM_PREG 0x04C 61 #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 62 #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 63 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 64 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 65 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 66 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 67 #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 68 #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 69 #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 70 #define SIERRA_CREQ_EQ_CTRL_PREG 0x093 71 #define SIERRA_CREQ_SPARE_PREG 0x096 72 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 73 #define SIERRA_CTLELUT_CTRL_PREG 0x098 74 #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 75 #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 76 #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 77 #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 78 #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 79 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 80 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 81 #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 82 #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 83 #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 84 #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 85 #define SIERRA_DEQ_GLUT0 0x0E8 86 #define SIERRA_DEQ_GLUT1 0x0E9 87 #define SIERRA_DEQ_GLUT2 0x0EA 88 #define SIERRA_DEQ_GLUT3 0x0EB 89 #define SIERRA_DEQ_GLUT4 0x0EC 90 #define SIERRA_DEQ_GLUT5 0x0ED 91 #define SIERRA_DEQ_GLUT6 0x0EE 92 #define SIERRA_DEQ_GLUT7 0x0EF 93 #define SIERRA_DEQ_GLUT8 0x0F0 94 #define SIERRA_DEQ_GLUT9 0x0F1 95 #define SIERRA_DEQ_GLUT10 0x0F2 96 #define SIERRA_DEQ_GLUT11 0x0F3 97 #define SIERRA_DEQ_GLUT12 0x0F4 98 #define SIERRA_DEQ_GLUT13 0x0F5 99 #define SIERRA_DEQ_GLUT14 0x0F6 100 #define SIERRA_DEQ_GLUT15 0x0F7 101 #define SIERRA_DEQ_GLUT16 0x0F8 102 #define SIERRA_DEQ_ALUT0 0x108 103 #define SIERRA_DEQ_ALUT1 0x109 104 #define SIERRA_DEQ_ALUT2 0x10A 105 #define SIERRA_DEQ_ALUT3 0x10B 106 #define SIERRA_DEQ_ALUT4 0x10C 107 #define SIERRA_DEQ_ALUT5 0x10D 108 #define SIERRA_DEQ_ALUT6 0x10E 109 #define SIERRA_DEQ_ALUT7 0x10F 110 #define SIERRA_DEQ_ALUT8 0x110 111 #define SIERRA_DEQ_ALUT9 0x111 112 #define SIERRA_DEQ_ALUT10 0x112 113 #define SIERRA_DEQ_ALUT11 0x113 114 #define SIERRA_DEQ_ALUT12 0x114 115 #define SIERRA_DEQ_ALUT13 0x115 116 #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 117 #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 118 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 119 #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 120 #define SIERRA_DEQ_PICTRL_PREG 0x161 121 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 122 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 123 #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 124 #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 125 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 126 #define SIERRA_LFPSDET_SUPPORT_PREG 0x188 127 #define SIERRA_LFPSFILT_NS_PREG 0x18A 128 #define SIERRA_LFPSFILT_RD_PREG 0x18B 129 #define SIERRA_LFPSFILT_MP_PREG 0x18C 130 #define SIERRA_SIGDET_SUPPORT_PREG 0x190 131 #define SIERRA_SDFILT_H2L_A_PREG 0x191 132 #define SIERRA_SDFILT_L2H_PREG 0x193 133 #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 134 #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 135 #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 136 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 137 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 138 139 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ 140 (0xc000 << (block_offset)) 141 #define SIERRA_PHY_PLL_CFG 0xe 142 143 #define SIERRA_MACRO_ID 0x00007364 144 #define SIERRA_MAX_LANES 16 145 #define PLL_LOCK_TIME 100000 146 147 #define CDNS_SIERRA_INPUT_CLOCKS 3 148 enum cdns_sierra_clock_input { 149 PHY_CLK, 150 CMN_REFCLK_DIG_DIV, 151 CMN_REFCLK1_DIG_DIV, 152 }; 153 154 static const struct reg_field macro_id_type = 155 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 156 static const struct reg_field phy_pll_cfg_1 = 157 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 158 static const struct reg_field pllctrl_lock = 159 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 160 161 struct cdns_sierra_inst { 162 struct phy *phy; 163 u32 phy_type; 164 u32 num_lanes; 165 u32 mlane; 166 struct reset_control *lnk_rst; 167 }; 168 169 struct cdns_reg_pairs { 170 u16 val; 171 u32 off; 172 }; 173 174 struct cdns_sierra_data { 175 u32 id_value; 176 u8 block_offset_shift; 177 u8 reg_offset_shift; 178 u32 pcie_cmn_regs; 179 u32 pcie_ln_regs; 180 u32 usb_cmn_regs; 181 u32 usb_ln_regs; 182 const struct cdns_reg_pairs *pcie_cmn_vals; 183 const struct cdns_reg_pairs *pcie_ln_vals; 184 const struct cdns_reg_pairs *usb_cmn_vals; 185 const struct cdns_reg_pairs *usb_ln_vals; 186 }; 187 188 struct cdns_regmap_cdb_context { 189 struct device *dev; 190 void __iomem *base; 191 u8 reg_offset_shift; 192 }; 193 194 struct cdns_sierra_phy { 195 struct device *dev; 196 struct regmap *regmap; 197 struct cdns_sierra_data *init_data; 198 struct cdns_sierra_inst phys[SIERRA_MAX_LANES]; 199 struct reset_control *phy_rst; 200 struct reset_control *apb_rst; 201 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 202 struct regmap *regmap_phy_config_ctrl; 203 struct regmap *regmap_common_cdb; 204 struct regmap_field *macro_id_type; 205 struct regmap_field *phy_pll_cfg_1; 206 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 207 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; 208 int nsubnodes; 209 u32 num_lanes; 210 bool autoconf; 211 }; 212 213 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 214 { 215 struct cdns_regmap_cdb_context *ctx = context; 216 u32 offset = reg << ctx->reg_offset_shift; 217 218 writew(val, ctx->base + offset); 219 220 return 0; 221 } 222 223 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 224 { 225 struct cdns_regmap_cdb_context *ctx = context; 226 u32 offset = reg << ctx->reg_offset_shift; 227 228 *val = readw(ctx->base + offset); 229 return 0; 230 } 231 232 #define SIERRA_LANE_CDB_REGMAP_CONF(n) \ 233 { \ 234 .name = "sierra_lane" n "_cdb", \ 235 .reg_stride = 1, \ 236 .fast_io = true, \ 237 .reg_write = cdns_regmap_write, \ 238 .reg_read = cdns_regmap_read, \ 239 } 240 241 static const struct regmap_config cdns_sierra_lane_cdb_config[] = { 242 SIERRA_LANE_CDB_REGMAP_CONF("0"), 243 SIERRA_LANE_CDB_REGMAP_CONF("1"), 244 SIERRA_LANE_CDB_REGMAP_CONF("2"), 245 SIERRA_LANE_CDB_REGMAP_CONF("3"), 246 SIERRA_LANE_CDB_REGMAP_CONF("4"), 247 SIERRA_LANE_CDB_REGMAP_CONF("5"), 248 SIERRA_LANE_CDB_REGMAP_CONF("6"), 249 SIERRA_LANE_CDB_REGMAP_CONF("7"), 250 SIERRA_LANE_CDB_REGMAP_CONF("8"), 251 SIERRA_LANE_CDB_REGMAP_CONF("9"), 252 SIERRA_LANE_CDB_REGMAP_CONF("10"), 253 SIERRA_LANE_CDB_REGMAP_CONF("11"), 254 SIERRA_LANE_CDB_REGMAP_CONF("12"), 255 SIERRA_LANE_CDB_REGMAP_CONF("13"), 256 SIERRA_LANE_CDB_REGMAP_CONF("14"), 257 SIERRA_LANE_CDB_REGMAP_CONF("15"), 258 }; 259 260 static const struct regmap_config cdns_sierra_common_cdb_config = { 261 .name = "sierra_common_cdb", 262 .reg_stride = 1, 263 .fast_io = true, 264 .reg_write = cdns_regmap_write, 265 .reg_read = cdns_regmap_read, 266 }; 267 268 static const struct regmap_config cdns_sierra_phy_config_ctrl_config = { 269 .name = "sierra_phy_config_ctrl", 270 .reg_stride = 1, 271 .fast_io = true, 272 .reg_write = cdns_regmap_write, 273 .reg_read = cdns_regmap_read, 274 }; 275 276 static int cdns_sierra_phy_init(struct phy *gphy) 277 { 278 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 279 struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); 280 struct regmap *regmap; 281 int i, j; 282 const struct cdns_reg_pairs *cmn_vals, *ln_vals; 283 u32 num_cmn_regs, num_ln_regs; 284 285 /* Initialise the PHY registers, unless auto configured */ 286 if (phy->autoconf) 287 return 0; 288 289 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 290 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 291 if (ins->phy_type == PHY_TYPE_PCIE) { 292 num_cmn_regs = phy->init_data->pcie_cmn_regs; 293 num_ln_regs = phy->init_data->pcie_ln_regs; 294 cmn_vals = phy->init_data->pcie_cmn_vals; 295 ln_vals = phy->init_data->pcie_ln_vals; 296 } else if (ins->phy_type == PHY_TYPE_USB3) { 297 num_cmn_regs = phy->init_data->usb_cmn_regs; 298 num_ln_regs = phy->init_data->usb_ln_regs; 299 cmn_vals = phy->init_data->usb_cmn_vals; 300 ln_vals = phy->init_data->usb_ln_vals; 301 } else { 302 return -EINVAL; 303 } 304 305 regmap = phy->regmap_common_cdb; 306 for (j = 0; j < num_cmn_regs ; j++) 307 regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val); 308 309 for (i = 0; i < ins->num_lanes; i++) { 310 for (j = 0; j < num_ln_regs ; j++) { 311 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 312 regmap_write(regmap, ln_vals[j].off, ln_vals[j].val); 313 } 314 } 315 316 return 0; 317 } 318 319 static int cdns_sierra_phy_on(struct phy *gphy) 320 { 321 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 322 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 323 struct device *dev = sp->dev; 324 u32 val; 325 int ret; 326 327 ret = reset_control_deassert(sp->phy_rst); 328 if (ret) { 329 dev_err(dev, "Failed to take the PHY out of reset\n"); 330 return ret; 331 } 332 333 /* Take the PHY lane group out of reset */ 334 ret = reset_control_deassert(ins->lnk_rst); 335 if (ret) { 336 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 337 return ret; 338 } 339 340 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 341 val, val, 1000, PLL_LOCK_TIME); 342 if (ret < 0) 343 dev_err(dev, "PLL lock of lane failed\n"); 344 345 return ret; 346 } 347 348 static int cdns_sierra_phy_off(struct phy *gphy) 349 { 350 struct cdns_sierra_inst *ins = phy_get_drvdata(gphy); 351 352 return reset_control_assert(ins->lnk_rst); 353 } 354 355 static int cdns_sierra_phy_reset(struct phy *gphy) 356 { 357 struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent); 358 359 reset_control_assert(sp->phy_rst); 360 reset_control_deassert(sp->phy_rst); 361 return 0; 362 }; 363 364 static const struct phy_ops ops = { 365 .init = cdns_sierra_phy_init, 366 .power_on = cdns_sierra_phy_on, 367 .power_off = cdns_sierra_phy_off, 368 .reset = cdns_sierra_phy_reset, 369 .owner = THIS_MODULE, 370 }; 371 372 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 373 struct device_node *child) 374 { 375 if (of_property_read_u32(child, "reg", &inst->mlane)) 376 return -EINVAL; 377 378 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 379 return -EINVAL; 380 381 if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type)) 382 return -EINVAL; 383 384 return 0; 385 } 386 387 static const struct of_device_id cdns_sierra_id_table[]; 388 389 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 390 u32 block_offset, u8 reg_offset_shift, 391 const struct regmap_config *config) 392 { 393 struct cdns_regmap_cdb_context *ctx; 394 395 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 396 if (!ctx) 397 return ERR_PTR(-ENOMEM); 398 399 ctx->dev = dev; 400 ctx->base = base + block_offset; 401 ctx->reg_offset_shift = reg_offset_shift; 402 403 return devm_regmap_init(dev, NULL, ctx, config); 404 } 405 406 static int cdns_regfield_init(struct cdns_sierra_phy *sp) 407 { 408 struct device *dev = sp->dev; 409 struct regmap_field *field; 410 struct regmap *regmap; 411 int i; 412 413 regmap = sp->regmap_common_cdb; 414 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 415 if (IS_ERR(field)) { 416 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 417 return PTR_ERR(field); 418 } 419 sp->macro_id_type = field; 420 421 regmap = sp->regmap_phy_config_ctrl; 422 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 423 if (IS_ERR(field)) { 424 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 425 return PTR_ERR(field); 426 } 427 sp->phy_pll_cfg_1 = field; 428 429 for (i = 0; i < SIERRA_MAX_LANES; i++) { 430 regmap = sp->regmap_lane_cdb[i]; 431 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 432 if (IS_ERR(field)) { 433 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 434 return PTR_ERR(field); 435 } 436 sp->pllctrl_lock[i] = field; 437 } 438 439 return 0; 440 } 441 442 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 443 void __iomem *base, u8 block_offset_shift, 444 u8 reg_offset_shift) 445 { 446 struct device *dev = sp->dev; 447 struct regmap *regmap; 448 u32 block_offset; 449 int i; 450 451 for (i = 0; i < SIERRA_MAX_LANES; i++) { 452 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, 453 reg_offset_shift); 454 regmap = cdns_regmap_init(dev, base, block_offset, 455 reg_offset_shift, 456 &cdns_sierra_lane_cdb_config[i]); 457 if (IS_ERR(regmap)) { 458 dev_err(dev, "Failed to init lane CDB regmap\n"); 459 return PTR_ERR(regmap); 460 } 461 sp->regmap_lane_cdb[i] = regmap; 462 } 463 464 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 465 reg_offset_shift, 466 &cdns_sierra_common_cdb_config); 467 if (IS_ERR(regmap)) { 468 dev_err(dev, "Failed to init common CDB regmap\n"); 469 return PTR_ERR(regmap); 470 } 471 sp->regmap_common_cdb = regmap; 472 473 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); 474 regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift, 475 &cdns_sierra_phy_config_ctrl_config); 476 if (IS_ERR(regmap)) { 477 dev_err(dev, "Failed to init PHY config and control regmap\n"); 478 return PTR_ERR(regmap); 479 } 480 sp->regmap_phy_config_ctrl = regmap; 481 482 return 0; 483 } 484 485 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 486 struct device *dev) 487 { 488 struct clk *clk; 489 int ret; 490 491 clk = devm_clk_get_optional(dev, "phy_clk"); 492 if (IS_ERR(clk)) { 493 dev_err(dev, "failed to get clock phy_clk\n"); 494 return PTR_ERR(clk); 495 } 496 sp->input_clks[PHY_CLK] = clk; 497 498 clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); 499 if (IS_ERR(clk)) { 500 dev_err(dev, "cmn_refclk_dig_div clock not found\n"); 501 ret = PTR_ERR(clk); 502 return ret; 503 } 504 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; 505 506 clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); 507 if (IS_ERR(clk)) { 508 dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); 509 ret = PTR_ERR(clk); 510 return ret; 511 } 512 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; 513 514 return 0; 515 } 516 517 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, 518 struct device *dev) 519 { 520 struct reset_control *rst; 521 522 rst = devm_reset_control_get_exclusive(dev, "sierra_reset"); 523 if (IS_ERR(rst)) { 524 dev_err(dev, "failed to get reset\n"); 525 return PTR_ERR(rst); 526 } 527 sp->phy_rst = rst; 528 529 rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb"); 530 if (IS_ERR(rst)) { 531 dev_err(dev, "failed to get apb reset\n"); 532 return PTR_ERR(rst); 533 } 534 sp->apb_rst = rst; 535 536 return 0; 537 } 538 539 static int cdns_sierra_phy_probe(struct platform_device *pdev) 540 { 541 struct cdns_sierra_phy *sp; 542 struct phy_provider *phy_provider; 543 struct device *dev = &pdev->dev; 544 const struct of_device_id *match; 545 struct cdns_sierra_data *data; 546 unsigned int id_value; 547 int i, ret, node = 0; 548 void __iomem *base; 549 struct device_node *dn = dev->of_node, *child; 550 551 if (of_get_child_count(dn) == 0) 552 return -ENODEV; 553 554 /* Get init data for this PHY */ 555 match = of_match_device(cdns_sierra_id_table, dev); 556 if (!match) 557 return -EINVAL; 558 559 data = (struct cdns_sierra_data *)match->data; 560 561 sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); 562 if (!sp) 563 return -ENOMEM; 564 dev_set_drvdata(dev, sp); 565 sp->dev = dev; 566 sp->init_data = data; 567 568 base = devm_platform_ioremap_resource(pdev, 0); 569 if (IS_ERR(base)) { 570 dev_err(dev, "missing \"reg\"\n"); 571 return PTR_ERR(base); 572 } 573 574 ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift, 575 data->reg_offset_shift); 576 if (ret) 577 return ret; 578 579 ret = cdns_regfield_init(sp); 580 if (ret) 581 return ret; 582 583 platform_set_drvdata(pdev, sp); 584 585 ret = cdns_sierra_phy_get_clocks(sp, dev); 586 if (ret) 587 return ret; 588 589 ret = cdns_sierra_phy_get_resets(sp, dev); 590 if (ret) 591 return ret; 592 593 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); 594 if (ret) 595 return ret; 596 597 /* Enable APB */ 598 reset_control_deassert(sp->apb_rst); 599 600 /* Check that PHY is present */ 601 regmap_field_read(sp->macro_id_type, &id_value); 602 if (sp->init_data->id_value != id_value) { 603 ret = -EINVAL; 604 goto clk_disable; 605 } 606 607 sp->autoconf = of_property_read_bool(dn, "cdns,autoconf"); 608 609 for_each_available_child_of_node(dn, child) { 610 struct phy *gphy; 611 612 if (!(of_node_name_eq(child, "phy") || 613 of_node_name_eq(child, "link"))) 614 continue; 615 616 sp->phys[node].lnk_rst = 617 of_reset_control_array_get_exclusive(child); 618 619 if (IS_ERR(sp->phys[node].lnk_rst)) { 620 dev_err(dev, "failed to get reset %s\n", 621 child->full_name); 622 ret = PTR_ERR(sp->phys[node].lnk_rst); 623 goto put_child2; 624 } 625 626 if (!sp->autoconf) { 627 ret = cdns_sierra_get_optional(&sp->phys[node], child); 628 if (ret) { 629 dev_err(dev, "missing property in node %s\n", 630 child->name); 631 goto put_child; 632 } 633 } 634 635 sp->num_lanes += sp->phys[node].num_lanes; 636 637 gphy = devm_phy_create(dev, child, &ops); 638 639 if (IS_ERR(gphy)) { 640 ret = PTR_ERR(gphy); 641 goto put_child; 642 } 643 sp->phys[node].phy = gphy; 644 phy_set_drvdata(gphy, &sp->phys[node]); 645 646 node++; 647 } 648 sp->nsubnodes = node; 649 650 if (sp->num_lanes > SIERRA_MAX_LANES) { 651 dev_err(dev, "Invalid lane configuration\n"); 652 goto put_child2; 653 } 654 655 /* If more than one subnode, configure the PHY as multilink */ 656 if (!sp->autoconf && sp->nsubnodes > 1) 657 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 658 659 pm_runtime_enable(dev); 660 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 661 return PTR_ERR_OR_ZERO(phy_provider); 662 663 put_child: 664 node++; 665 put_child2: 666 for (i = 0; i < node; i++) 667 reset_control_put(sp->phys[i].lnk_rst); 668 of_node_put(child); 669 clk_disable: 670 clk_disable_unprepare(sp->input_clks[PHY_CLK]); 671 reset_control_assert(sp->apb_rst); 672 return ret; 673 } 674 675 static int cdns_sierra_phy_remove(struct platform_device *pdev) 676 { 677 struct cdns_sierra_phy *phy = platform_get_drvdata(pdev); 678 int i; 679 680 reset_control_assert(phy->phy_rst); 681 reset_control_assert(phy->apb_rst); 682 pm_runtime_disable(&pdev->dev); 683 684 /* 685 * The device level resets will be put automatically. 686 * Need to put the subnode resets here though. 687 */ 688 for (i = 0; i < phy->nsubnodes; i++) { 689 reset_control_assert(phy->phys[i].lnk_rst); 690 reset_control_put(phy->phys[i].lnk_rst); 691 } 692 693 clk_disable_unprepare(phy->input_clks[PHY_CLK]); 694 695 return 0; 696 } 697 698 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 699 static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 700 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 701 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 702 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 703 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 704 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 705 }; 706 707 /* refclk100MHz_32b_PCIe_ln_ext_ssc */ 708 static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 709 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 710 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 711 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 712 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 713 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 714 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 715 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG} 716 }; 717 718 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 719 static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 720 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 721 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 722 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 723 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 724 }; 725 726 /* refclk100MHz_20b_USB_ln_ext_ssc */ 727 static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 728 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 729 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 730 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 731 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 732 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 733 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 734 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 735 {0xCF00, SIERRA_PSM_DIAG_PREG}, 736 {0x001F, SIERRA_PSC_TX_A0_PREG}, 737 {0x0007, SIERRA_PSC_TX_A1_PREG}, 738 {0x0003, SIERRA_PSC_TX_A2_PREG}, 739 {0x0003, SIERRA_PSC_TX_A3_PREG}, 740 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 741 {0x0003, SIERRA_PSC_RX_A1_PREG}, 742 {0x0003, SIERRA_PSC_RX_A2_PREG}, 743 {0x0001, SIERRA_PSC_RX_A3_PREG}, 744 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 745 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 746 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 747 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 748 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 749 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 750 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 751 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 752 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 753 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 754 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 755 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 756 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 757 {0x0000, SIERRA_CREQ_SPARE_PREG}, 758 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 759 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 760 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 761 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 762 {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, 763 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 764 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 765 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 766 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 767 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 768 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 769 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 770 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 771 {0x0014, SIERRA_DEQ_GLUT0}, 772 {0x0014, SIERRA_DEQ_GLUT1}, 773 {0x0014, SIERRA_DEQ_GLUT2}, 774 {0x0014, SIERRA_DEQ_GLUT3}, 775 {0x0014, SIERRA_DEQ_GLUT4}, 776 {0x0014, SIERRA_DEQ_GLUT5}, 777 {0x0014, SIERRA_DEQ_GLUT6}, 778 {0x0014, SIERRA_DEQ_GLUT7}, 779 {0x0014, SIERRA_DEQ_GLUT8}, 780 {0x0014, SIERRA_DEQ_GLUT9}, 781 {0x0014, SIERRA_DEQ_GLUT10}, 782 {0x0014, SIERRA_DEQ_GLUT11}, 783 {0x0014, SIERRA_DEQ_GLUT12}, 784 {0x0014, SIERRA_DEQ_GLUT13}, 785 {0x0014, SIERRA_DEQ_GLUT14}, 786 {0x0014, SIERRA_DEQ_GLUT15}, 787 {0x0014, SIERRA_DEQ_GLUT16}, 788 {0x0BAE, SIERRA_DEQ_ALUT0}, 789 {0x0AEB, SIERRA_DEQ_ALUT1}, 790 {0x0A28, SIERRA_DEQ_ALUT2}, 791 {0x0965, SIERRA_DEQ_ALUT3}, 792 {0x08A2, SIERRA_DEQ_ALUT4}, 793 {0x07DF, SIERRA_DEQ_ALUT5}, 794 {0x071C, SIERRA_DEQ_ALUT6}, 795 {0x0659, SIERRA_DEQ_ALUT7}, 796 {0x0596, SIERRA_DEQ_ALUT8}, 797 {0x0514, SIERRA_DEQ_ALUT9}, 798 {0x0492, SIERRA_DEQ_ALUT10}, 799 {0x0410, SIERRA_DEQ_ALUT11}, 800 {0x038E, SIERRA_DEQ_ALUT12}, 801 {0x030C, SIERRA_DEQ_ALUT13}, 802 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 803 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 804 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 805 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 806 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 807 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 808 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 809 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 810 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 811 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 812 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 813 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 814 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 815 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 816 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 817 {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, 818 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 819 {0x8009, SIERRA_SDFILT_L2H_PREG}, 820 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 821 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 822 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 823 }; 824 825 static const struct cdns_sierra_data cdns_map_sierra = { 826 SIERRA_MACRO_ID, 827 0x2, 828 0x2, 829 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 830 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 831 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 832 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 833 cdns_pcie_cmn_regs_ext_ssc, 834 cdns_pcie_ln_regs_ext_ssc, 835 cdns_usb_cmn_regs_ext_ssc, 836 cdns_usb_ln_regs_ext_ssc, 837 }; 838 839 static const struct cdns_sierra_data cdns_ti_map_sierra = { 840 SIERRA_MACRO_ID, 841 0x0, 842 0x1, 843 ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 844 ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 845 ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 846 ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 847 cdns_pcie_cmn_regs_ext_ssc, 848 cdns_pcie_ln_regs_ext_ssc, 849 cdns_usb_cmn_regs_ext_ssc, 850 cdns_usb_ln_regs_ext_ssc, 851 }; 852 853 static const struct of_device_id cdns_sierra_id_table[] = { 854 { 855 .compatible = "cdns,sierra-phy-t0", 856 .data = &cdns_map_sierra, 857 }, 858 { 859 .compatible = "ti,sierra-phy-t0", 860 .data = &cdns_ti_map_sierra, 861 }, 862 {} 863 }; 864 MODULE_DEVICE_TABLE(of, cdns_sierra_id_table); 865 866 static struct platform_driver cdns_sierra_driver = { 867 .probe = cdns_sierra_phy_probe, 868 .remove = cdns_sierra_phy_remove, 869 .driver = { 870 .name = "cdns-sierra-phy", 871 .of_match_table = cdns_sierra_id_table, 872 }, 873 }; 874 module_platform_driver(cdns_sierra_driver); 875 876 MODULE_ALIAS("platform:cdns_sierra"); 877 MODULE_AUTHOR("Cadence Design Systems"); 878 MODULE_DESCRIPTION("CDNS sierra phy driver"); 879 MODULE_LICENSE("GPL v2"); 880