1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright: 2017-2018 Cadence Design Systems, Inc. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitops.h> 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 16 #include <linux/phy/phy.h> 17 #include <linux/phy/phy-mipi-dphy.h> 18 19 #define REG_WAKEUP_TIME_NS 800 20 #define DPHY_PLL_RATE_HZ 108000000 21 #define POLL_TIMEOUT_US 1000 22 23 /* DPHY registers */ 24 #define DPHY_PMA_CMN(reg) (reg) 25 #define DPHY_PMA_LCLK(reg) (0x100 + (reg)) 26 #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg)) 27 #define DPHY_PMA_RCLK(reg) (0x600 + (reg)) 28 #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) 29 #define DPHY_PCS(reg) (0xb00 + (reg)) 30 31 #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) 32 #define DPHY_CMN_SSM_EN BIT(0) 33 #define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1) 34 #define DPHY_CMN_TX_MODE_EN BIT(9) 35 36 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) 37 #define DPHY_CMN_PWM_DIV(x) ((x) << 20) 38 #define DPHY_CMN_PWM_LOW(x) ((x) << 10) 39 #define DPHY_CMN_PWM_HIGH(x) (x) 40 41 #define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c) 42 #define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22)) 43 #define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21)) 44 45 #define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50) 46 #define DPHY_CMN_IPDIV_FROM_REG BIT(0) 47 #define DPHY_CMN_IPDIV(x) ((x) << 1) 48 #define DPHY_CMN_OPDIV_FROM_REG BIT(6) 49 #define DPHY_CMN_OPDIV(x) ((x) << 7) 50 51 #define DPHY_BAND_CFG DPHY_PCS(0x0) 52 #define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) 53 #define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) 54 55 #define DPHY_PSM_CFG DPHY_PCS(0x4) 56 #define DPHY_PSM_CFG_FROM_REG BIT(0) 57 #define DPHY_PSM_CLK_DIV(x) ((x) << 1) 58 59 #define DPHY_TX_J721E_WIZ_PLL_CTRL 0xF04 60 #define DPHY_TX_J721E_WIZ_STATUS 0xF08 61 #define DPHY_TX_J721E_WIZ_RST_CTRL 0xF0C 62 #define DPHY_TX_J721E_WIZ_PSM_FREQ 0xF10 63 64 #define DPHY_TX_J721E_WIZ_IPDIV GENMASK(4, 0) 65 #define DPHY_TX_J721E_WIZ_OPDIV GENMASK(13, 8) 66 #define DPHY_TX_J721E_WIZ_FBDIV GENMASK(25, 16) 67 #define DPHY_TX_J721E_WIZ_LANE_RSTB BIT(31) 68 #define DPHY_TX_WIZ_PLL_LOCK BIT(31) 69 #define DPHY_TX_WIZ_O_CMN_READY BIT(31) 70 71 struct cdns_dphy_cfg { 72 u8 pll_ipdiv; 73 u8 pll_opdiv; 74 u16 pll_fbdiv; 75 u32 hs_clk_rate; 76 unsigned int nlanes; 77 }; 78 79 enum cdns_dphy_clk_lane_cfg { 80 DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0, 81 DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1, 82 DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2, 83 DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3, 84 }; 85 86 struct cdns_dphy; 87 struct cdns_dphy_ops { 88 int (*probe)(struct cdns_dphy *dphy); 89 void (*remove)(struct cdns_dphy *dphy); 90 void (*set_psm_div)(struct cdns_dphy *dphy, u8 div); 91 void (*set_clk_lane_cfg)(struct cdns_dphy *dphy, 92 enum cdns_dphy_clk_lane_cfg cfg); 93 void (*set_pll_cfg)(struct cdns_dphy *dphy, 94 const struct cdns_dphy_cfg *cfg); 95 unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy); 96 int (*wait_for_pll_lock)(struct cdns_dphy *dphy); 97 int (*wait_for_cmn_ready)(struct cdns_dphy *dphy); 98 }; 99 100 struct cdns_dphy { 101 struct cdns_dphy_cfg cfg; 102 void __iomem *regs; 103 struct clk *psm_clk; 104 struct clk *pll_ref_clk; 105 const struct cdns_dphy_ops *ops; 106 struct phy *phy; 107 bool is_configured; 108 bool is_powered; 109 }; 110 111 /* Order of bands is important since the index is the band number. */ 112 static const unsigned int tx_bands[] = { 113 80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770, 114 870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500 115 }; 116 117 static int cdns_dphy_get_pll_cfg(struct cdns_dphy *dphy, 118 struct cdns_dphy_cfg *cfg, 119 struct phy_configure_opts_mipi_dphy *opts) 120 { 121 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); 122 u64 dlane_bps; 123 124 memset(cfg, 0, sizeof(*cfg)); 125 126 if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000) 127 return -EINVAL; 128 else if (pll_ref_hz < 19200000) 129 cfg->pll_ipdiv = 1; 130 else if (pll_ref_hz < 38400000) 131 cfg->pll_ipdiv = 2; 132 else if (pll_ref_hz < 76800000) 133 cfg->pll_ipdiv = 4; 134 else 135 cfg->pll_ipdiv = 8; 136 137 dlane_bps = opts->hs_clk_rate; 138 139 if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL) 140 return -EINVAL; 141 else if (dlane_bps >= 1250000000) 142 cfg->pll_opdiv = 1; 143 else if (dlane_bps >= 630000000) 144 cfg->pll_opdiv = 2; 145 else if (dlane_bps >= 320000000) 146 cfg->pll_opdiv = 4; 147 else if (dlane_bps >= 160000000) 148 cfg->pll_opdiv = 8; 149 150 cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv * 151 cfg->pll_ipdiv, 152 pll_ref_hz); 153 154 cfg->hs_clk_rate = div_u64((u64)pll_ref_hz * cfg->pll_fbdiv, 155 2 * cfg->pll_opdiv * cfg->pll_ipdiv); 156 157 return 0; 158 } 159 160 static int cdns_dphy_setup_psm(struct cdns_dphy *dphy) 161 { 162 unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk); 163 unsigned long psm_div; 164 165 if (!psm_clk_hz || psm_clk_hz > 100000000) 166 return -EINVAL; 167 168 psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000); 169 if (dphy->ops->set_psm_div) 170 dphy->ops->set_psm_div(dphy, psm_div); 171 172 return 0; 173 } 174 175 static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy, 176 enum cdns_dphy_clk_lane_cfg cfg) 177 { 178 if (dphy->ops->set_clk_lane_cfg) 179 dphy->ops->set_clk_lane_cfg(dphy, cfg); 180 } 181 182 static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy, 183 const struct cdns_dphy_cfg *cfg) 184 { 185 if (dphy->ops->set_pll_cfg) 186 dphy->ops->set_pll_cfg(dphy, cfg); 187 } 188 189 static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy) 190 { 191 return dphy->ops->get_wakeup_time_ns(dphy); 192 } 193 194 static int cdns_dphy_wait_for_pll_lock(struct cdns_dphy *dphy) 195 { 196 return dphy->ops->wait_for_pll_lock ? dphy->ops->wait_for_pll_lock(dphy) : 0; 197 } 198 199 static int cdns_dphy_wait_for_cmn_ready(struct cdns_dphy *dphy) 200 { 201 return dphy->ops->wait_for_cmn_ready ? dphy->ops->wait_for_cmn_ready(dphy) : 0; 202 } 203 204 static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy) 205 { 206 /* Default wakeup time is 800 ns (in a simulated environment). */ 207 return 800; 208 } 209 210 static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy, 211 const struct cdns_dphy_cfg *cfg) 212 { 213 u32 fbdiv_low, fbdiv_high; 214 215 fbdiv_low = (cfg->pll_fbdiv / 4) - 2; 216 fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2; 217 218 writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG | 219 DPHY_CMN_IPDIV(cfg->pll_ipdiv) | 220 DPHY_CMN_OPDIV(cfg->pll_opdiv), 221 dphy->regs + DPHY_CMN_OPIPDIV); 222 writel(DPHY_CMN_FBDIV_FROM_REG | 223 DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high), 224 dphy->regs + DPHY_CMN_FBDIV); 225 writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) | 226 DPHY_CMN_PWM_DIV(0x8), 227 dphy->regs + DPHY_CMN_PWM); 228 } 229 230 static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div) 231 { 232 writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div), 233 dphy->regs + DPHY_PSM_CFG); 234 } 235 236 static unsigned long cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy *dphy) 237 { 238 /* Minimum wakeup time as per MIPI D-PHY spec v1.2 */ 239 return 1000000; 240 } 241 242 static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy, 243 const struct cdns_dphy_cfg *cfg) 244 { 245 246 /* 247 * set the PWM and PLL Byteclk divider settings to recommended values 248 * which is same as that of in ref ops 249 */ 250 writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) | 251 DPHY_CMN_PWM_DIV(0x8), 252 dphy->regs + DPHY_CMN_PWM); 253 254 writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) | 255 FIELD_PREP(DPHY_TX_J721E_WIZ_OPDIV, cfg->pll_opdiv) | 256 FIELD_PREP(DPHY_TX_J721E_WIZ_FBDIV, cfg->pll_fbdiv)), 257 dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL); 258 259 writel(DPHY_TX_J721E_WIZ_LANE_RSTB, 260 dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL); 261 } 262 263 static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div) 264 { 265 writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ); 266 } 267 268 static int cdns_dphy_j721e_wait_for_pll_lock(struct cdns_dphy *dphy) 269 { 270 u32 status; 271 272 return readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status, 273 status & DPHY_TX_WIZ_PLL_LOCK, 0, POLL_TIMEOUT_US); 274 } 275 276 static int cdns_dphy_j721e_wait_for_cmn_ready(struct cdns_dphy *dphy) 277 { 278 u32 status; 279 280 return readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status, 281 status & DPHY_TX_WIZ_O_CMN_READY, 0, 282 POLL_TIMEOUT_US); 283 } 284 285 /* 286 * This is the reference implementation of DPHY hooks. Specific integration of 287 * this IP may have to re-implement some of them depending on how they decided 288 * to wire things in the SoC. 289 */ 290 static const struct cdns_dphy_ops ref_dphy_ops = { 291 .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, 292 .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, 293 .set_psm_div = cdns_dphy_ref_set_psm_div, 294 }; 295 296 static const struct cdns_dphy_ops j721e_dphy_ops = { 297 .get_wakeup_time_ns = cdns_dphy_j721e_get_wakeup_time_ns, 298 .set_pll_cfg = cdns_dphy_j721e_set_pll_cfg, 299 .set_psm_div = cdns_dphy_j721e_set_psm_div, 300 .wait_for_pll_lock = cdns_dphy_j721e_wait_for_pll_lock, 301 .wait_for_cmn_ready = cdns_dphy_j721e_wait_for_cmn_ready, 302 }; 303 304 static int cdns_dphy_config_from_opts(struct phy *phy, 305 struct phy_configure_opts_mipi_dphy *opts, 306 struct cdns_dphy_cfg *cfg) 307 { 308 struct cdns_dphy *dphy = phy_get_drvdata(phy); 309 int ret; 310 311 ret = phy_mipi_dphy_config_validate(opts); 312 if (ret) 313 return ret; 314 315 ret = cdns_dphy_get_pll_cfg(dphy, cfg, opts); 316 if (ret) 317 return ret; 318 319 opts->hs_clk_rate = cfg->hs_clk_rate; 320 opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000; 321 322 return 0; 323 } 324 325 static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate) 326 { 327 unsigned int rate; 328 int i; 329 330 rate = hs_clk_rate / 1000000UL; 331 332 if (rate < tx_bands[0]) 333 return -EOPNOTSUPP; 334 335 for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) { 336 if (rate >= tx_bands[i] && rate < tx_bands[i + 1]) 337 return i; 338 } 339 340 return -EOPNOTSUPP; 341 } 342 343 static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, 344 union phy_configure_opts *opts) 345 { 346 struct cdns_dphy_cfg cfg = { 0 }; 347 348 if (mode != PHY_MODE_MIPI_DPHY) 349 return -EINVAL; 350 351 return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); 352 } 353 354 static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) 355 { 356 struct cdns_dphy *dphy = phy_get_drvdata(phy); 357 int ret; 358 359 ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &dphy->cfg); 360 if (!ret) 361 dphy->is_configured = true; 362 363 return ret; 364 } 365 366 static int cdns_dphy_power_on(struct phy *phy) 367 { 368 struct cdns_dphy *dphy = phy_get_drvdata(phy); 369 int ret; 370 u32 reg; 371 372 if (!dphy->is_configured || dphy->is_powered) 373 return -EINVAL; 374 375 clk_prepare_enable(dphy->psm_clk); 376 clk_prepare_enable(dphy->pll_ref_clk); 377 378 /* 379 * Configure the internal PSM clk divider so that the DPHY has a 380 * 1MHz clk (or something close). 381 */ 382 ret = cdns_dphy_setup_psm(dphy); 383 if (ret) { 384 dev_err(&dphy->phy->dev, "Failed to setup PSM with error %d\n", ret); 385 goto err_power_on; 386 } 387 388 /* 389 * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes 390 * and 8 data lanes, each clk lane can be attache different set of 391 * data lanes. The 2 groups are named 'left' and 'right', so here we 392 * just say that we want the 'left' clk lane to drive the 'left' data 393 * lanes. 394 */ 395 cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT); 396 397 /* 398 * Configure the DPHY PLL that will be used to generate the TX byte 399 * clk. 400 */ 401 cdns_dphy_set_pll_cfg(dphy, &dphy->cfg); 402 403 ret = cdns_dphy_tx_get_band_ctrl(dphy->cfg.hs_clk_rate); 404 if (ret < 0) { 405 dev_err(&dphy->phy->dev, "Failed to get band control value with error %d\n", ret); 406 goto err_power_on; 407 } 408 409 reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, ret) | 410 FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, ret); 411 writel(reg, dphy->regs + DPHY_BAND_CFG); 412 413 /* Start TX state machine. */ 414 reg = readl(dphy->regs + DPHY_CMN_SSM); 415 writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN, 416 dphy->regs + DPHY_CMN_SSM); 417 418 ret = cdns_dphy_wait_for_pll_lock(dphy); 419 if (ret) { 420 dev_err(&dphy->phy->dev, "Failed to lock PLL with error %d\n", ret); 421 goto err_power_on; 422 } 423 424 ret = cdns_dphy_wait_for_cmn_ready(dphy); 425 if (ret) { 426 dev_err(&dphy->phy->dev, "O_CMN_READY signal failed to assert with error %d\n", 427 ret); 428 goto err_power_on; 429 } 430 431 dphy->is_powered = true; 432 433 return 0; 434 435 err_power_on: 436 clk_disable_unprepare(dphy->pll_ref_clk); 437 clk_disable_unprepare(dphy->psm_clk); 438 439 return ret; 440 } 441 442 static int cdns_dphy_power_off(struct phy *phy) 443 { 444 struct cdns_dphy *dphy = phy_get_drvdata(phy); 445 u32 reg; 446 447 clk_disable_unprepare(dphy->pll_ref_clk); 448 clk_disable_unprepare(dphy->psm_clk); 449 450 /* Stop TX state machine. */ 451 reg = readl(dphy->regs + DPHY_CMN_SSM); 452 writel(reg & ~DPHY_CMN_SSM_EN, dphy->regs + DPHY_CMN_SSM); 453 454 dphy->is_powered = false; 455 456 return 0; 457 } 458 459 static const struct phy_ops cdns_dphy_ops = { 460 .configure = cdns_dphy_configure, 461 .validate = cdns_dphy_validate, 462 .power_on = cdns_dphy_power_on, 463 .power_off = cdns_dphy_power_off, 464 }; 465 466 static int cdns_dphy_probe(struct platform_device *pdev) 467 { 468 struct phy_provider *phy_provider; 469 struct cdns_dphy *dphy; 470 int ret; 471 472 dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); 473 if (!dphy) 474 return -ENOMEM; 475 dev_set_drvdata(&pdev->dev, dphy); 476 477 dphy->ops = of_device_get_match_data(&pdev->dev); 478 if (!dphy->ops) 479 return -EINVAL; 480 481 dphy->regs = devm_platform_ioremap_resource(pdev, 0); 482 if (IS_ERR(dphy->regs)) 483 return PTR_ERR(dphy->regs); 484 485 dphy->psm_clk = devm_clk_get(&pdev->dev, "psm"); 486 if (IS_ERR(dphy->psm_clk)) 487 return PTR_ERR(dphy->psm_clk); 488 489 dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); 490 if (IS_ERR(dphy->pll_ref_clk)) 491 return PTR_ERR(dphy->pll_ref_clk); 492 493 if (dphy->ops->probe) { 494 ret = dphy->ops->probe(dphy); 495 if (ret) 496 return ret; 497 } 498 499 dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops); 500 if (IS_ERR(dphy->phy)) { 501 dev_err(&pdev->dev, "failed to create PHY\n"); 502 if (dphy->ops->remove) 503 dphy->ops->remove(dphy); 504 return PTR_ERR(dphy->phy); 505 } 506 507 phy_set_drvdata(dphy->phy, dphy); 508 phy_provider = devm_of_phy_provider_register(&pdev->dev, 509 of_phy_simple_xlate); 510 511 return PTR_ERR_OR_ZERO(phy_provider); 512 } 513 514 static void cdns_dphy_remove(struct platform_device *pdev) 515 { 516 struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev); 517 518 if (dphy->ops->remove) 519 dphy->ops->remove(dphy); 520 } 521 522 static const struct of_device_id cdns_dphy_of_match[] = { 523 { .compatible = "cdns,dphy", .data = &ref_dphy_ops }, 524 { .compatible = "ti,j721e-dphy", .data = &j721e_dphy_ops }, 525 { /* sentinel */ }, 526 }; 527 MODULE_DEVICE_TABLE(of, cdns_dphy_of_match); 528 529 static struct platform_driver cdns_dphy_platform_driver = { 530 .probe = cdns_dphy_probe, 531 .remove = cdns_dphy_remove, 532 .driver = { 533 .name = "cdns-mipi-dphy", 534 .of_match_table = cdns_dphy_of_match, 535 }, 536 }; 537 module_platform_driver(cdns_dphy_platform_driver); 538 539 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>"); 540 MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver"); 541 MODULE_LICENSE("GPL"); 542