1 /* 2 * Broadcom SATA3 AHCI Controller PHY Driver 3 * 4 * Copyright (C) 2016 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 28 #define SATA_PCB_BANK_OFFSET 0x23c 29 #define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4) 30 31 #define MAX_PORTS 2 32 33 /* Register offset between PHYs in PCB space */ 34 #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000 35 36 /* The older SATA PHY registers duplicated per port registers within the map, 37 * rather than having a separate map per port. 38 */ 39 #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10 40 41 /* Register offset between PHYs in PHY control space */ 42 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8 43 44 enum brcm_sata_phy_version { 45 BRCM_SATA_PHY_STB_28NM, 46 BRCM_SATA_PHY_STB_40NM, 47 BRCM_SATA_PHY_IPROC_NS2, 48 BRCM_SATA_PHY_IPROC_NSP, 49 BRCM_SATA_PHY_IPROC_SR, 50 }; 51 52 enum brcm_sata_phy_rxaeq_mode { 53 RXAEQ_MODE_OFF = 0, 54 RXAEQ_MODE_AUTO, 55 RXAEQ_MODE_MANUAL, 56 }; 57 58 static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m) 59 { 60 if (!strcmp(m, "auto")) 61 return RXAEQ_MODE_AUTO; 62 else if (!strcmp(m, "manual")) 63 return RXAEQ_MODE_MANUAL; 64 else 65 return RXAEQ_MODE_OFF; 66 } 67 68 struct brcm_sata_port { 69 int portnum; 70 struct phy *phy; 71 struct brcm_sata_phy *phy_priv; 72 bool ssc_en; 73 enum brcm_sata_phy_rxaeq_mode rxaeq_mode; 74 u32 rxaeq_val; 75 }; 76 77 struct brcm_sata_phy { 78 struct device *dev; 79 void __iomem *phy_base; 80 void __iomem *ctrl_base; 81 enum brcm_sata_phy_version version; 82 83 struct brcm_sata_port phys[MAX_PORTS]; 84 }; 85 86 enum sata_phy_regs { 87 BLOCK0_REG_BANK = 0x000, 88 BLOCK0_XGXSSTATUS = 0x81, 89 BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12), 90 BLOCK0_SPARE = 0x8d, 91 BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3, 92 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1, 93 94 PLL_REG_BANK_0 = 0x050, 95 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81, 96 PLLCONTROL_0_FREQ_DET_RESTART = BIT(13), 97 PLLCONTROL_0_FREQ_MONITOR = BIT(12), 98 PLLCONTROL_0_SEQ_START = BIT(15), 99 PLL_CAP_CONTROL = 0x85, 100 PLL_ACTRL2 = 0x8b, 101 PLL_ACTRL2_SELDIV_MASK = 0x1f, 102 PLL_ACTRL2_SELDIV_SHIFT = 9, 103 PLL_ACTRL6 = 0x86, 104 105 PLL1_REG_BANK = 0x060, 106 PLL1_ACTRL2 = 0x82, 107 PLL1_ACTRL3 = 0x83, 108 PLL1_ACTRL4 = 0x84, 109 110 TX_REG_BANK = 0x070, 111 TX_ACTRL0 = 0x80, 112 TX_ACTRL0_TXPOL_FLIP = BIT(6), 113 114 AEQRX_REG_BANK_0 = 0xd0, 115 AEQ_CONTROL1 = 0x81, 116 AEQ_CONTROL1_ENABLE = BIT(2), 117 AEQ_CONTROL1_FREEZE = BIT(3), 118 AEQ_FRC_EQ = 0x83, 119 AEQ_FRC_EQ_FORCE = BIT(0), 120 AEQ_FRC_EQ_FORCE_VAL = BIT(1), 121 AEQRX_REG_BANK_1 = 0xe0, 122 123 OOB_REG_BANK = 0x150, 124 OOB1_REG_BANK = 0x160, 125 OOB_CTRL1 = 0x80, 126 OOB_CTRL1_BURST_MAX_MASK = 0xf, 127 OOB_CTRL1_BURST_MAX_SHIFT = 12, 128 OOB_CTRL1_BURST_MIN_MASK = 0xf, 129 OOB_CTRL1_BURST_MIN_SHIFT = 8, 130 OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf, 131 OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4, 132 OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf, 133 OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0, 134 OOB_CTRL2 = 0x81, 135 OOB_CTRL2_SEL_ENA_SHIFT = 15, 136 OOB_CTRL2_SEL_ENA_RC_SHIFT = 14, 137 OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f, 138 OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8, 139 OOB_CTRL2_BURST_CNT_MASK = 0x3, 140 OOB_CTRL2_BURST_CNT_SHIFT = 6, 141 OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f, 142 OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0, 143 144 TXPMD_REG_BANK = 0x1a0, 145 TXPMD_CONTROL1 = 0x81, 146 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0), 147 TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1), 148 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82, 149 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83, 150 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff, 151 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84, 152 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff, 153 }; 154 155 enum sata_phy_ctrl_regs { 156 PHY_CTRL_1 = 0x0, 157 PHY_CTRL_1_RESET = BIT(0), 158 }; 159 160 static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port) 161 { 162 struct brcm_sata_phy *priv = port->phy_priv; 163 u32 size = 0; 164 165 switch (priv->version) { 166 case BRCM_SATA_PHY_STB_28NM: 167 case BRCM_SATA_PHY_IPROC_NS2: 168 size = SATA_PCB_REG_28NM_SPACE_SIZE; 169 break; 170 case BRCM_SATA_PHY_STB_40NM: 171 size = SATA_PCB_REG_40NM_SPACE_SIZE; 172 break; 173 default: 174 dev_err(priv->dev, "invalid phy version\n"); 175 break; 176 } 177 178 return priv->phy_base + (port->portnum * size); 179 } 180 181 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port) 182 { 183 struct brcm_sata_phy *priv = port->phy_priv; 184 u32 size = 0; 185 186 switch (priv->version) { 187 case BRCM_SATA_PHY_IPROC_NS2: 188 size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE; 189 break; 190 default: 191 dev_err(priv->dev, "invalid phy version\n"); 192 break; 193 } 194 195 return priv->ctrl_base + (port->portnum * size); 196 } 197 198 static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank, 199 u32 ofs, u32 msk, u32 value) 200 { 201 u32 tmp; 202 203 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); 204 tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs)); 205 tmp = (tmp & msk) | value; 206 writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs)); 207 } 208 209 static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs) 210 { 211 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); 212 return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs)); 213 } 214 215 /* These defaults were characterized by H/W group */ 216 #define STB_FMIN_VAL_DEFAULT 0x3df 217 #define STB_FMAX_VAL_DEFAULT 0x3df 218 #define STB_FMAX_VAL_SSC 0x83 219 220 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port) 221 { 222 void __iomem *base = brcm_sata_pcb_base(port); 223 struct brcm_sata_phy *priv = port->phy_priv; 224 u32 tmp; 225 226 /* override the TX spread spectrum setting */ 227 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC; 228 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp); 229 230 /* set fixed min freq */ 231 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2, 232 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK, 233 STB_FMIN_VAL_DEFAULT); 234 235 /* set fixed max freq depending on SSC config */ 236 if (port->ssc_en) { 237 dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum); 238 tmp = STB_FMAX_VAL_SSC; 239 } else { 240 tmp = STB_FMAX_VAL_DEFAULT; 241 } 242 243 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3, 244 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp); 245 } 246 247 #define AEQ_FRC_EQ_VAL_SHIFT 2 248 #define AEQ_FRC_EQ_VAL_MASK 0x3f 249 250 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port) 251 { 252 void __iomem *base = brcm_sata_pcb_base(port); 253 u32 tmp = 0, reg = 0; 254 255 switch (port->rxaeq_mode) { 256 case RXAEQ_MODE_OFF: 257 return 0; 258 259 case RXAEQ_MODE_AUTO: 260 reg = AEQ_CONTROL1; 261 tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE; 262 break; 263 264 case RXAEQ_MODE_MANUAL: 265 reg = AEQ_FRC_EQ; 266 tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL; 267 if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK) 268 return -EINVAL; 269 tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT; 270 break; 271 } 272 273 brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp); 274 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp); 275 276 return 0; 277 } 278 279 static int brcm_stb_sata_init(struct brcm_sata_port *port) 280 { 281 brcm_stb_sata_ssc_init(port); 282 283 return brcm_stb_sata_rxaeq_init(port); 284 } 285 286 /* NS2 SATA PLL1 defaults were characterized by H/W group */ 287 #define NS2_PLL1_ACTRL2_MAGIC 0x1df8 288 #define NS2_PLL1_ACTRL3_MAGIC 0x2b00 289 #define NS2_PLL1_ACTRL4_MAGIC 0x8824 290 291 static int brcm_ns2_sata_init(struct brcm_sata_port *port) 292 { 293 int try; 294 unsigned int val; 295 void __iomem *base = brcm_sata_pcb_base(port); 296 void __iomem *ctrl_base = brcm_sata_ctrl_base(port); 297 struct device *dev = port->phy_priv->dev; 298 299 /* Configure OOB control */ 300 val = 0x0; 301 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT); 302 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT); 303 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); 304 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); 305 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); 306 val = 0x0; 307 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); 308 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT); 309 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); 310 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); 311 312 /* Configure PHY PLL register bank 1 */ 313 val = NS2_PLL1_ACTRL2_MAGIC; 314 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); 315 val = NS2_PLL1_ACTRL3_MAGIC; 316 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); 317 val = NS2_PLL1_ACTRL4_MAGIC; 318 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); 319 320 /* Configure PHY BLOCK0 register bank */ 321 /* Set oob_clk_sel to refclk/2 */ 322 brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE, 323 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK, 324 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2); 325 326 /* Strobe PHY reset using PHY control register */ 327 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1); 328 mdelay(1); 329 writel(0x0, ctrl_base + PHY_CTRL_1); 330 mdelay(1); 331 332 /* Wait for PHY PLL lock by polling pll_lock bit */ 333 try = 50; 334 while (try) { 335 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 336 BLOCK0_XGXSSTATUS); 337 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 338 break; 339 msleep(20); 340 try--; 341 } 342 if (!try) { 343 /* PLL did not lock; give up */ 344 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 345 return -ETIMEDOUT; 346 } 347 348 dev_dbg(dev, "port%d initialized\n", port->portnum); 349 350 return 0; 351 } 352 353 static int brcm_nsp_sata_init(struct brcm_sata_port *port) 354 { 355 struct brcm_sata_phy *priv = port->phy_priv; 356 struct device *dev = port->phy_priv->dev; 357 void __iomem *base = priv->phy_base; 358 unsigned int oob_bank; 359 unsigned int val, try; 360 361 /* Configure OOB control */ 362 if (port->portnum == 0) 363 oob_bank = OOB_REG_BANK; 364 else if (port->portnum == 1) 365 oob_bank = OOB1_REG_BANK; 366 else 367 return -EINVAL; 368 369 val = 0x0; 370 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT); 371 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT); 372 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); 373 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); 374 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val); 375 376 val = 0x0; 377 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); 378 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT); 379 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); 380 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val); 381 382 383 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2, 384 ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT), 385 0x0c << PLL_ACTRL2_SELDIV_SHIFT); 386 387 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL, 388 0xff0, 0x4f0); 389 390 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR; 391 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 392 ~val, val); 393 val = PLLCONTROL_0_SEQ_START; 394 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 395 ~val, 0); 396 mdelay(10); 397 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 398 ~val, val); 399 400 /* Wait for pll_seq_done bit */ 401 try = 50; 402 while (--try) { 403 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 404 BLOCK0_XGXSSTATUS); 405 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 406 break; 407 msleep(20); 408 } 409 if (!try) { 410 /* PLL did not lock; give up */ 411 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 412 return -ETIMEDOUT; 413 } 414 415 dev_dbg(dev, "port%d initialized\n", port->portnum); 416 417 return 0; 418 } 419 420 /* SR PHY PLL0 registers */ 421 #define SR_PLL0_ACTRL6_MAGIC 0xa 422 423 /* SR PHY PLL1 registers */ 424 #define SR_PLL1_ACTRL2_MAGIC 0x32 425 #define SR_PLL1_ACTRL3_MAGIC 0x2 426 #define SR_PLL1_ACTRL4_MAGIC 0x3e8 427 428 static int brcm_sr_sata_init(struct brcm_sata_port *port) 429 { 430 struct brcm_sata_phy *priv = port->phy_priv; 431 struct device *dev = port->phy_priv->dev; 432 void __iomem *base = priv->phy_base; 433 unsigned int val, try; 434 435 /* Configure PHY PLL register bank 1 */ 436 val = SR_PLL1_ACTRL2_MAGIC; 437 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); 438 val = SR_PLL1_ACTRL3_MAGIC; 439 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); 440 val = SR_PLL1_ACTRL4_MAGIC; 441 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); 442 443 /* Configure PHY PLL register bank 0 */ 444 val = SR_PLL0_ACTRL6_MAGIC; 445 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val); 446 447 /* Wait for PHY PLL lock by polling pll_lock bit */ 448 try = 50; 449 do { 450 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 451 BLOCK0_XGXSSTATUS); 452 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 453 break; 454 msleep(20); 455 try--; 456 } while (try); 457 458 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) { 459 /* PLL did not lock; give up */ 460 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 461 return -ETIMEDOUT; 462 } 463 464 /* Invert Tx polarity */ 465 brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0, 466 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP); 467 468 /* Configure OOB control to handle 100MHz reference clock */ 469 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) | 470 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) | 471 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) | 472 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT)); 473 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); 474 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) | 475 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) | 476 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT)); 477 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); 478 479 return 0; 480 } 481 482 static int brcm_sata_phy_init(struct phy *phy) 483 { 484 int rc; 485 struct brcm_sata_port *port = phy_get_drvdata(phy); 486 487 switch (port->phy_priv->version) { 488 case BRCM_SATA_PHY_STB_28NM: 489 case BRCM_SATA_PHY_STB_40NM: 490 rc = brcm_stb_sata_init(port); 491 break; 492 case BRCM_SATA_PHY_IPROC_NS2: 493 rc = brcm_ns2_sata_init(port); 494 break; 495 case BRCM_SATA_PHY_IPROC_NSP: 496 rc = brcm_nsp_sata_init(port); 497 break; 498 case BRCM_SATA_PHY_IPROC_SR: 499 rc = brcm_sr_sata_init(port); 500 break; 501 default: 502 rc = -ENODEV; 503 } 504 505 return rc; 506 } 507 508 static const struct phy_ops phy_ops = { 509 .init = brcm_sata_phy_init, 510 .owner = THIS_MODULE, 511 }; 512 513 static const struct of_device_id brcm_sata_phy_of_match[] = { 514 { .compatible = "brcm,bcm7445-sata-phy", 515 .data = (void *)BRCM_SATA_PHY_STB_28NM }, 516 { .compatible = "brcm,bcm7425-sata-phy", 517 .data = (void *)BRCM_SATA_PHY_STB_40NM }, 518 { .compatible = "brcm,iproc-ns2-sata-phy", 519 .data = (void *)BRCM_SATA_PHY_IPROC_NS2 }, 520 { .compatible = "brcm,iproc-nsp-sata-phy", 521 .data = (void *)BRCM_SATA_PHY_IPROC_NSP }, 522 { .compatible = "brcm,iproc-sr-sata-phy", 523 .data = (void *)BRCM_SATA_PHY_IPROC_SR }, 524 {}, 525 }; 526 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match); 527 528 static int brcm_sata_phy_probe(struct platform_device *pdev) 529 { 530 const char *rxaeq_mode; 531 struct device *dev = &pdev->dev; 532 struct device_node *dn = dev->of_node, *child; 533 const struct of_device_id *of_id; 534 struct brcm_sata_phy *priv; 535 struct resource *res; 536 struct phy_provider *provider; 537 int ret, count = 0; 538 539 if (of_get_child_count(dn) == 0) 540 return -ENODEV; 541 542 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 543 if (!priv) 544 return -ENOMEM; 545 dev_set_drvdata(dev, priv); 546 priv->dev = dev; 547 548 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 549 priv->phy_base = devm_ioremap_resource(dev, res); 550 if (IS_ERR(priv->phy_base)) 551 return PTR_ERR(priv->phy_base); 552 553 of_id = of_match_node(brcm_sata_phy_of_match, dn); 554 if (of_id) 555 priv->version = (enum brcm_sata_phy_version)of_id->data; 556 else 557 priv->version = BRCM_SATA_PHY_STB_28NM; 558 559 if (priv->version == BRCM_SATA_PHY_IPROC_NS2) { 560 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 561 "phy-ctrl"); 562 priv->ctrl_base = devm_ioremap_resource(dev, res); 563 if (IS_ERR(priv->ctrl_base)) 564 return PTR_ERR(priv->ctrl_base); 565 } 566 567 for_each_available_child_of_node(dn, child) { 568 unsigned int id; 569 struct brcm_sata_port *port; 570 571 if (of_property_read_u32(child, "reg", &id)) { 572 dev_err(dev, "missing reg property in node %s\n", 573 child->name); 574 ret = -EINVAL; 575 goto put_child; 576 } 577 578 if (id >= MAX_PORTS) { 579 dev_err(dev, "invalid reg: %u\n", id); 580 ret = -EINVAL; 581 goto put_child; 582 } 583 if (priv->phys[id].phy) { 584 dev_err(dev, "already registered port %u\n", id); 585 ret = -EINVAL; 586 goto put_child; 587 } 588 589 port = &priv->phys[id]; 590 port->portnum = id; 591 port->phy_priv = priv; 592 port->phy = devm_phy_create(dev, child, &phy_ops); 593 port->rxaeq_mode = RXAEQ_MODE_OFF; 594 if (!of_property_read_string(child, "brcm,rxaeq-mode", 595 &rxaeq_mode)) 596 port->rxaeq_mode = rxaeq_to_val(rxaeq_mode); 597 if (port->rxaeq_mode == RXAEQ_MODE_MANUAL) 598 of_property_read_u32(child, "brcm,rxaeq-value", 599 &port->rxaeq_val); 600 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc"); 601 if (IS_ERR(port->phy)) { 602 dev_err(dev, "failed to create PHY\n"); 603 ret = PTR_ERR(port->phy); 604 goto put_child; 605 } 606 607 phy_set_drvdata(port->phy, port); 608 count++; 609 } 610 611 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 612 if (IS_ERR(provider)) { 613 dev_err(dev, "could not register PHY provider\n"); 614 return PTR_ERR(provider); 615 } 616 617 dev_info(dev, "registered %d port(s)\n", count); 618 619 return 0; 620 put_child: 621 of_node_put(child); 622 return ret; 623 } 624 625 static struct platform_driver brcm_sata_phy_driver = { 626 .probe = brcm_sata_phy_probe, 627 .driver = { 628 .of_match_table = brcm_sata_phy_of_match, 629 .name = "brcm-sata-phy", 630 } 631 }; 632 module_platform_driver(brcm_sata_phy_driver); 633 634 MODULE_DESCRIPTION("Broadcom SATA PHY driver"); 635 MODULE_LICENSE("GPL"); 636 MODULE_AUTHOR("Marc Carino"); 637 MODULE_AUTHOR("Brian Norris"); 638 MODULE_ALIAS("platform:phy-brcm-sata"); 639