1 /* 2 * Broadcom SATA3 AHCI Controller PHY Driver 3 * 4 * Copyright (C) 2016 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/device.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 28 #define SATA_PCB_BANK_OFFSET 0x23c 29 #define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4) 30 31 #define MAX_PORTS 2 32 33 /* Register offset between PHYs in PCB space */ 34 #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000 35 36 /* The older SATA PHY registers duplicated per port registers within the map, 37 * rather than having a separate map per port. 38 */ 39 #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10 40 41 /* Register offset between PHYs in PHY control space */ 42 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8 43 44 enum brcm_sata_phy_version { 45 BRCM_SATA_PHY_STB_28NM, 46 BRCM_SATA_PHY_STB_40NM, 47 BRCM_SATA_PHY_IPROC_NS2, 48 BRCM_SATA_PHY_IPROC_NSP, 49 BRCM_SATA_PHY_IPROC_SR, 50 }; 51 52 enum brcm_sata_phy_rxaeq_mode { 53 RXAEQ_MODE_OFF = 0, 54 RXAEQ_MODE_AUTO, 55 RXAEQ_MODE_MANUAL, 56 }; 57 58 static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m) 59 { 60 if (!strcmp(m, "auto")) 61 return RXAEQ_MODE_AUTO; 62 else if (!strcmp(m, "manual")) 63 return RXAEQ_MODE_MANUAL; 64 else 65 return RXAEQ_MODE_OFF; 66 } 67 68 struct brcm_sata_port { 69 int portnum; 70 struct phy *phy; 71 struct brcm_sata_phy *phy_priv; 72 bool ssc_en; 73 enum brcm_sata_phy_rxaeq_mode rxaeq_mode; 74 u32 rxaeq_val; 75 }; 76 77 struct brcm_sata_phy { 78 struct device *dev; 79 void __iomem *phy_base; 80 void __iomem *ctrl_base; 81 enum brcm_sata_phy_version version; 82 83 struct brcm_sata_port phys[MAX_PORTS]; 84 }; 85 86 enum sata_phy_regs { 87 BLOCK0_REG_BANK = 0x000, 88 BLOCK0_XGXSSTATUS = 0x81, 89 BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12), 90 BLOCK0_SPARE = 0x8d, 91 BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3, 92 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1, 93 94 PLL_REG_BANK_0 = 0x050, 95 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81, 96 PLLCONTROL_0_FREQ_DET_RESTART = BIT(13), 97 PLLCONTROL_0_FREQ_MONITOR = BIT(12), 98 PLLCONTROL_0_SEQ_START = BIT(15), 99 PLL_CAP_CONTROL = 0x85, 100 PLL_ACTRL2 = 0x8b, 101 PLL_ACTRL2_SELDIV_MASK = 0x1f, 102 PLL_ACTRL2_SELDIV_SHIFT = 9, 103 PLL_ACTRL6 = 0x86, 104 105 PLL1_REG_BANK = 0x060, 106 PLL1_ACTRL2 = 0x82, 107 PLL1_ACTRL3 = 0x83, 108 PLL1_ACTRL4 = 0x84, 109 110 TX_REG_BANK = 0x070, 111 TX_ACTRL0 = 0x80, 112 TX_ACTRL0_TXPOL_FLIP = BIT(6), 113 114 AEQRX_REG_BANK_0 = 0xd0, 115 AEQ_CONTROL1 = 0x81, 116 AEQ_CONTROL1_ENABLE = BIT(2), 117 AEQ_CONTROL1_FREEZE = BIT(3), 118 AEQ_FRC_EQ = 0x83, 119 AEQ_FRC_EQ_FORCE = BIT(0), 120 AEQ_FRC_EQ_FORCE_VAL = BIT(1), 121 AEQRX_REG_BANK_1 = 0xe0, 122 123 OOB_REG_BANK = 0x150, 124 OOB1_REG_BANK = 0x160, 125 OOB_CTRL1 = 0x80, 126 OOB_CTRL1_BURST_MAX_MASK = 0xf, 127 OOB_CTRL1_BURST_MAX_SHIFT = 12, 128 OOB_CTRL1_BURST_MIN_MASK = 0xf, 129 OOB_CTRL1_BURST_MIN_SHIFT = 8, 130 OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf, 131 OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4, 132 OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf, 133 OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0, 134 OOB_CTRL2 = 0x81, 135 OOB_CTRL2_SEL_ENA_SHIFT = 15, 136 OOB_CTRL2_SEL_ENA_RC_SHIFT = 14, 137 OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f, 138 OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8, 139 OOB_CTRL2_BURST_CNT_MASK = 0x3, 140 OOB_CTRL2_BURST_CNT_SHIFT = 6, 141 OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f, 142 OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0, 143 144 TXPMD_REG_BANK = 0x1a0, 145 TXPMD_CONTROL1 = 0x81, 146 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0), 147 TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1), 148 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82, 149 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83, 150 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff, 151 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84, 152 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff, 153 154 RXPMD_REG_BANK = 0x1c0, 155 RXPMD_RX_FREQ_MON_CONTROL1 = 0x87, 156 }; 157 158 enum sata_phy_ctrl_regs { 159 PHY_CTRL_1 = 0x0, 160 PHY_CTRL_1_RESET = BIT(0), 161 }; 162 163 static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port) 164 { 165 struct brcm_sata_phy *priv = port->phy_priv; 166 u32 size = 0; 167 168 switch (priv->version) { 169 case BRCM_SATA_PHY_STB_28NM: 170 case BRCM_SATA_PHY_IPROC_NS2: 171 size = SATA_PCB_REG_28NM_SPACE_SIZE; 172 break; 173 case BRCM_SATA_PHY_STB_40NM: 174 size = SATA_PCB_REG_40NM_SPACE_SIZE; 175 break; 176 default: 177 dev_err(priv->dev, "invalid phy version\n"); 178 break; 179 } 180 181 return priv->phy_base + (port->portnum * size); 182 } 183 184 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port) 185 { 186 struct brcm_sata_phy *priv = port->phy_priv; 187 u32 size = 0; 188 189 switch (priv->version) { 190 case BRCM_SATA_PHY_IPROC_NS2: 191 size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE; 192 break; 193 default: 194 dev_err(priv->dev, "invalid phy version\n"); 195 break; 196 } 197 198 return priv->ctrl_base + (port->portnum * size); 199 } 200 201 static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank, 202 u32 ofs, u32 msk, u32 value) 203 { 204 u32 tmp; 205 206 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); 207 tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs)); 208 tmp = (tmp & msk) | value; 209 writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs)); 210 } 211 212 static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs) 213 { 214 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET); 215 return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs)); 216 } 217 218 /* These defaults were characterized by H/W group */ 219 #define STB_FMIN_VAL_DEFAULT 0x3df 220 #define STB_FMAX_VAL_DEFAULT 0x3df 221 #define STB_FMAX_VAL_SSC 0x83 222 223 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port) 224 { 225 void __iomem *base = brcm_sata_pcb_base(port); 226 struct brcm_sata_phy *priv = port->phy_priv; 227 u32 tmp; 228 229 /* override the TX spread spectrum setting */ 230 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC; 231 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp); 232 233 /* set fixed min freq */ 234 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2, 235 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK, 236 STB_FMIN_VAL_DEFAULT); 237 238 /* set fixed max freq depending on SSC config */ 239 if (port->ssc_en) { 240 dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum); 241 tmp = STB_FMAX_VAL_SSC; 242 } else { 243 tmp = STB_FMAX_VAL_DEFAULT; 244 } 245 246 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3, 247 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp); 248 } 249 250 #define AEQ_FRC_EQ_VAL_SHIFT 2 251 #define AEQ_FRC_EQ_VAL_MASK 0x3f 252 253 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port) 254 { 255 void __iomem *base = brcm_sata_pcb_base(port); 256 u32 tmp = 0, reg = 0; 257 258 switch (port->rxaeq_mode) { 259 case RXAEQ_MODE_OFF: 260 return 0; 261 262 case RXAEQ_MODE_AUTO: 263 reg = AEQ_CONTROL1; 264 tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE; 265 break; 266 267 case RXAEQ_MODE_MANUAL: 268 reg = AEQ_FRC_EQ; 269 tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL; 270 if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK) 271 return -EINVAL; 272 tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT; 273 break; 274 } 275 276 brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp); 277 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp); 278 279 return 0; 280 } 281 282 static int brcm_stb_sata_init(struct brcm_sata_port *port) 283 { 284 brcm_stb_sata_ssc_init(port); 285 286 return brcm_stb_sata_rxaeq_init(port); 287 } 288 289 /* NS2 SATA PLL1 defaults were characterized by H/W group */ 290 #define NS2_PLL1_ACTRL2_MAGIC 0x1df8 291 #define NS2_PLL1_ACTRL3_MAGIC 0x2b00 292 #define NS2_PLL1_ACTRL4_MAGIC 0x8824 293 294 static int brcm_ns2_sata_init(struct brcm_sata_port *port) 295 { 296 int try; 297 unsigned int val; 298 void __iomem *base = brcm_sata_pcb_base(port); 299 void __iomem *ctrl_base = brcm_sata_ctrl_base(port); 300 struct device *dev = port->phy_priv->dev; 301 302 /* Configure OOB control */ 303 val = 0x0; 304 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT); 305 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT); 306 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); 307 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); 308 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); 309 val = 0x0; 310 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); 311 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT); 312 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); 313 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); 314 315 /* Configure PHY PLL register bank 1 */ 316 val = NS2_PLL1_ACTRL2_MAGIC; 317 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); 318 val = NS2_PLL1_ACTRL3_MAGIC; 319 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); 320 val = NS2_PLL1_ACTRL4_MAGIC; 321 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); 322 323 /* Configure PHY BLOCK0 register bank */ 324 /* Set oob_clk_sel to refclk/2 */ 325 brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE, 326 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK, 327 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2); 328 329 /* Strobe PHY reset using PHY control register */ 330 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1); 331 mdelay(1); 332 writel(0x0, ctrl_base + PHY_CTRL_1); 333 mdelay(1); 334 335 /* Wait for PHY PLL lock by polling pll_lock bit */ 336 try = 50; 337 while (try) { 338 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 339 BLOCK0_XGXSSTATUS); 340 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 341 break; 342 msleep(20); 343 try--; 344 } 345 if (!try) { 346 /* PLL did not lock; give up */ 347 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 348 return -ETIMEDOUT; 349 } 350 351 dev_dbg(dev, "port%d initialized\n", port->portnum); 352 353 return 0; 354 } 355 356 static int brcm_nsp_sata_init(struct brcm_sata_port *port) 357 { 358 struct brcm_sata_phy *priv = port->phy_priv; 359 struct device *dev = port->phy_priv->dev; 360 void __iomem *base = priv->phy_base; 361 unsigned int oob_bank; 362 unsigned int val, try; 363 364 /* Configure OOB control */ 365 if (port->portnum == 0) 366 oob_bank = OOB_REG_BANK; 367 else if (port->portnum == 1) 368 oob_bank = OOB1_REG_BANK; 369 else 370 return -EINVAL; 371 372 val = 0x0; 373 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT); 374 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT); 375 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT); 376 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT); 377 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val); 378 379 val = 0x0; 380 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT); 381 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT); 382 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT); 383 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val); 384 385 386 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2, 387 ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT), 388 0x0c << PLL_ACTRL2_SELDIV_SHIFT); 389 390 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL, 391 0xff0, 0x4f0); 392 393 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR; 394 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 395 ~val, val); 396 val = PLLCONTROL_0_SEQ_START; 397 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 398 ~val, 0); 399 mdelay(10); 400 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0, 401 ~val, val); 402 403 /* Wait for pll_seq_done bit */ 404 try = 50; 405 while (--try) { 406 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 407 BLOCK0_XGXSSTATUS); 408 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 409 break; 410 msleep(20); 411 } 412 if (!try) { 413 /* PLL did not lock; give up */ 414 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 415 return -ETIMEDOUT; 416 } 417 418 dev_dbg(dev, "port%d initialized\n", port->portnum); 419 420 return 0; 421 } 422 423 /* SR PHY PLL0 registers */ 424 #define SR_PLL0_ACTRL6_MAGIC 0xa 425 426 /* SR PHY PLL1 registers */ 427 #define SR_PLL1_ACTRL2_MAGIC 0x32 428 #define SR_PLL1_ACTRL3_MAGIC 0x2 429 #define SR_PLL1_ACTRL4_MAGIC 0x3e8 430 431 static int brcm_sr_sata_init(struct brcm_sata_port *port) 432 { 433 struct brcm_sata_phy *priv = port->phy_priv; 434 struct device *dev = port->phy_priv->dev; 435 void __iomem *base = priv->phy_base; 436 unsigned int val, try; 437 438 /* Configure PHY PLL register bank 1 */ 439 val = SR_PLL1_ACTRL2_MAGIC; 440 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val); 441 val = SR_PLL1_ACTRL3_MAGIC; 442 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val); 443 val = SR_PLL1_ACTRL4_MAGIC; 444 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val); 445 446 /* Configure PHY PLL register bank 0 */ 447 val = SR_PLL0_ACTRL6_MAGIC; 448 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val); 449 450 /* Wait for PHY PLL lock by polling pll_lock bit */ 451 try = 50; 452 do { 453 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK, 454 BLOCK0_XGXSSTATUS); 455 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK) 456 break; 457 msleep(20); 458 try--; 459 } while (try); 460 461 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) { 462 /* PLL did not lock; give up */ 463 dev_err(dev, "port%d PLL did not lock\n", port->portnum); 464 return -ETIMEDOUT; 465 } 466 467 /* Invert Tx polarity */ 468 brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0, 469 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP); 470 471 /* Configure OOB control to handle 100MHz reference clock */ 472 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) | 473 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) | 474 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) | 475 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT)); 476 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val); 477 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) | 478 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) | 479 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT)); 480 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val); 481 482 return 0; 483 } 484 485 static int brcm_sata_phy_init(struct phy *phy) 486 { 487 int rc; 488 struct brcm_sata_port *port = phy_get_drvdata(phy); 489 490 switch (port->phy_priv->version) { 491 case BRCM_SATA_PHY_STB_28NM: 492 case BRCM_SATA_PHY_STB_40NM: 493 rc = brcm_stb_sata_init(port); 494 break; 495 case BRCM_SATA_PHY_IPROC_NS2: 496 rc = brcm_ns2_sata_init(port); 497 break; 498 case BRCM_SATA_PHY_IPROC_NSP: 499 rc = brcm_nsp_sata_init(port); 500 break; 501 case BRCM_SATA_PHY_IPROC_SR: 502 rc = brcm_sr_sata_init(port); 503 break; 504 default: 505 rc = -ENODEV; 506 } 507 508 return rc; 509 } 510 511 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port) 512 { 513 void __iomem *base = brcm_sata_pcb_base(port); 514 u32 tmp = BIT(8); 515 516 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1, 517 ~tmp, tmp); 518 } 519 520 static int brcm_sata_phy_calibrate(struct phy *phy) 521 { 522 struct brcm_sata_port *port = phy_get_drvdata(phy); 523 int rc = -EOPNOTSUPP; 524 525 switch (port->phy_priv->version) { 526 case BRCM_SATA_PHY_STB_28NM: 527 case BRCM_SATA_PHY_STB_40NM: 528 brcm_stb_sata_calibrate(port); 529 rc = 0; 530 break; 531 default: 532 break; 533 } 534 535 return rc; 536 } 537 538 static const struct phy_ops phy_ops = { 539 .init = brcm_sata_phy_init, 540 .calibrate = brcm_sata_phy_calibrate, 541 .owner = THIS_MODULE, 542 }; 543 544 static const struct of_device_id brcm_sata_phy_of_match[] = { 545 { .compatible = "brcm,bcm7445-sata-phy", 546 .data = (void *)BRCM_SATA_PHY_STB_28NM }, 547 { .compatible = "brcm,bcm7425-sata-phy", 548 .data = (void *)BRCM_SATA_PHY_STB_40NM }, 549 { .compatible = "brcm,iproc-ns2-sata-phy", 550 .data = (void *)BRCM_SATA_PHY_IPROC_NS2 }, 551 { .compatible = "brcm,iproc-nsp-sata-phy", 552 .data = (void *)BRCM_SATA_PHY_IPROC_NSP }, 553 { .compatible = "brcm,iproc-sr-sata-phy", 554 .data = (void *)BRCM_SATA_PHY_IPROC_SR }, 555 {}, 556 }; 557 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match); 558 559 static int brcm_sata_phy_probe(struct platform_device *pdev) 560 { 561 const char *rxaeq_mode; 562 struct device *dev = &pdev->dev; 563 struct device_node *dn = dev->of_node, *child; 564 const struct of_device_id *of_id; 565 struct brcm_sata_phy *priv; 566 struct resource *res; 567 struct phy_provider *provider; 568 int ret, count = 0; 569 570 if (of_get_child_count(dn) == 0) 571 return -ENODEV; 572 573 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 574 if (!priv) 575 return -ENOMEM; 576 dev_set_drvdata(dev, priv); 577 priv->dev = dev; 578 579 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 580 priv->phy_base = devm_ioremap_resource(dev, res); 581 if (IS_ERR(priv->phy_base)) 582 return PTR_ERR(priv->phy_base); 583 584 of_id = of_match_node(brcm_sata_phy_of_match, dn); 585 if (of_id) 586 priv->version = (enum brcm_sata_phy_version)of_id->data; 587 else 588 priv->version = BRCM_SATA_PHY_STB_28NM; 589 590 if (priv->version == BRCM_SATA_PHY_IPROC_NS2) { 591 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 592 "phy-ctrl"); 593 priv->ctrl_base = devm_ioremap_resource(dev, res); 594 if (IS_ERR(priv->ctrl_base)) 595 return PTR_ERR(priv->ctrl_base); 596 } 597 598 for_each_available_child_of_node(dn, child) { 599 unsigned int id; 600 struct brcm_sata_port *port; 601 602 if (of_property_read_u32(child, "reg", &id)) { 603 dev_err(dev, "missing reg property in node %s\n", 604 child->name); 605 ret = -EINVAL; 606 goto put_child; 607 } 608 609 if (id >= MAX_PORTS) { 610 dev_err(dev, "invalid reg: %u\n", id); 611 ret = -EINVAL; 612 goto put_child; 613 } 614 if (priv->phys[id].phy) { 615 dev_err(dev, "already registered port %u\n", id); 616 ret = -EINVAL; 617 goto put_child; 618 } 619 620 port = &priv->phys[id]; 621 port->portnum = id; 622 port->phy_priv = priv; 623 port->phy = devm_phy_create(dev, child, &phy_ops); 624 port->rxaeq_mode = RXAEQ_MODE_OFF; 625 if (!of_property_read_string(child, "brcm,rxaeq-mode", 626 &rxaeq_mode)) 627 port->rxaeq_mode = rxaeq_to_val(rxaeq_mode); 628 if (port->rxaeq_mode == RXAEQ_MODE_MANUAL) 629 of_property_read_u32(child, "brcm,rxaeq-value", 630 &port->rxaeq_val); 631 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc"); 632 if (IS_ERR(port->phy)) { 633 dev_err(dev, "failed to create PHY\n"); 634 ret = PTR_ERR(port->phy); 635 goto put_child; 636 } 637 638 phy_set_drvdata(port->phy, port); 639 count++; 640 } 641 642 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 643 if (IS_ERR(provider)) { 644 dev_err(dev, "could not register PHY provider\n"); 645 return PTR_ERR(provider); 646 } 647 648 dev_info(dev, "registered %d port(s)\n", count); 649 650 return 0; 651 put_child: 652 of_node_put(child); 653 return ret; 654 } 655 656 static struct platform_driver brcm_sata_phy_driver = { 657 .probe = brcm_sata_phy_probe, 658 .driver = { 659 .of_match_table = brcm_sata_phy_of_match, 660 .name = "brcm-sata-phy", 661 } 662 }; 663 module_platform_driver(brcm_sata_phy_driver); 664 665 MODULE_DESCRIPTION("Broadcom SATA PHY driver"); 666 MODULE_LICENSE("GPL"); 667 MODULE_AUTHOR("Marc Carino"); 668 MODULE_AUTHOR("Brian Norris"); 669 MODULE_ALIAS("platform:phy-brcm-sata"); 670