1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Meson G12A USB2 PHY driver 4 * 5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 6 * Copyright (C) 2017 Amlogic, Inc. All rights reserved 7 * Copyright (C) 2019 BayLibre, SAS 8 * Author: Neil Armstrong <narmstrong@baylibre.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/phy/phy.h> 21 #include <linux/platform_device.h> 22 23 #define PHY_CTRL_R0 0x0 24 #define PHY_CTRL_R1 0x4 25 #define PHY_CTRL_R2 0x8 26 #define PHY_CTRL_R3 0xc 27 #define PHY_CTRL_R3_SQUELCH_REF GENMASK(1, 0) 28 #define PHY_CTRL_R3_HSDIC_REF GENMASK(3, 2) 29 #define PHY_CTRL_R3_DISC_THRESH GENMASK(7, 4) 30 31 #define PHY_CTRL_R4 0x10 32 #define PHY_CTRL_R4_CALIB_CODE_7_0 GENMASK(7, 0) 33 #define PHY_CTRL_R4_CALIB_CODE_15_8 GENMASK(15, 8) 34 #define PHY_CTRL_R4_CALIB_CODE_23_16 GENMASK(23, 16) 35 #define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24) 36 #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25) 37 #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26) 38 #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27) 39 #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0 GENMASK(29, 28) 40 #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2 GENMASK(31, 30) 41 42 #define PHY_CTRL_R5 0x14 43 #define PHY_CTRL_R6 0x18 44 #define PHY_CTRL_R7 0x1c 45 #define PHY_CTRL_R8 0x20 46 #define PHY_CTRL_R9 0x24 47 #define PHY_CTRL_R10 0x28 48 #define PHY_CTRL_R11 0x2c 49 #define PHY_CTRL_R12 0x30 50 #define PHY_CTRL_R13 0x34 51 #define PHY_CTRL_R13_CUSTOM_PATTERN_19 GENMASK(7, 0) 52 #define PHY_CTRL_R13_LOAD_STAT BIT(14) 53 #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15) 54 #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16) 55 #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21) 56 #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22) 57 #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN BIT(23) 58 #define PHY_CTRL_R13_I_C2L_HS_EN BIT(24) 59 #define PHY_CTRL_R13_I_C2L_FS_EN BIT(25) 60 #define PHY_CTRL_R13_I_C2L_LS_EN BIT(26) 61 #define PHY_CTRL_R13_I_C2L_HS_OE BIT(27) 62 #define PHY_CTRL_R13_I_C2L_FS_OE BIT(28) 63 #define PHY_CTRL_R13_I_C2L_HS_RX_EN BIT(29) 64 #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN BIT(30) 65 66 #define PHY_CTRL_R14 0x38 67 #define PHY_CTRL_R14_I_RDP_EN BIT(0) 68 #define PHY_CTRL_R14_I_RPU_SW1_EN BIT(1) 69 #define PHY_CTRL_R14_I_RPU_SW2_EN GENMASK(2, 3) 70 #define PHY_CTRL_R14_PG_RSTN BIT(4) 71 #define PHY_CTRL_R14_I_C2L_DATA_16_8 BIT(5) 72 #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO BIT(6) 73 #define PHY_CTRL_R14_BYPASS_CTRL_7_0 GENMASK(15, 8) 74 #define PHY_CTRL_R14_BYPASS_CTRL_15_8 GENMASK(23, 16) 75 76 #define PHY_CTRL_R15 0x3c 77 #define PHY_CTRL_R16 0x40 78 #define PHY_CTRL_R16_MPLL_M GENMASK(8, 0) 79 #define PHY_CTRL_R16_MPLL_N GENMASK(14, 10) 80 #define PHY_CTRL_R16_MPLL_TDC_MODE BIT(20) 81 #define PHY_CTRL_R16_MPLL_SDM_EN BIT(21) 82 #define PHY_CTRL_R16_MPLL_LOAD BIT(22) 83 #define PHY_CTRL_R16_MPLL_DCO_SDM_EN BIT(23) 84 #define PHY_CTRL_R16_MPLL_LOCK_LONG GENMASK(25, 24) 85 #define PHY_CTRL_R16_MPLL_LOCK_F BIT(26) 86 #define PHY_CTRL_R16_MPLL_FAST_LOCK BIT(27) 87 #define PHY_CTRL_R16_MPLL_EN BIT(28) 88 #define PHY_CTRL_R16_MPLL_RESET BIT(29) 89 #define PHY_CTRL_R16_MPLL_LOCK BIT(30) 90 #define PHY_CTRL_R16_MPLL_LOCK_DIG BIT(31) 91 92 #define PHY_CTRL_R17 0x44 93 #define PHY_CTRL_R17_MPLL_FRAC_IN GENMASK(13, 0) 94 #define PHY_CTRL_R17_MPLL_FIX_EN BIT(16) 95 #define PHY_CTRL_R17_MPLL_LAMBDA1 GENMASK(19, 17) 96 #define PHY_CTRL_R17_MPLL_LAMBDA0 GENMASK(22, 20) 97 #define PHY_CTRL_R17_MPLL_FILTER_MODE BIT(23) 98 #define PHY_CTRL_R17_MPLL_FILTER_PVT2 GENMASK(27, 24) 99 #define PHY_CTRL_R17_MPLL_FILTER_PVT1 GENMASK(31, 28) 100 101 #define PHY_CTRL_R18 0x48 102 #define PHY_CTRL_R18_MPLL_LKW_SEL GENMASK(1, 0) 103 #define PHY_CTRL_R18_MPLL_LK_W GENMASK(5, 2) 104 #define PHY_CTRL_R18_MPLL_LK_S GENMASK(11, 6) 105 #define PHY_CTRL_R18_MPLL_DCO_M_EN BIT(12) 106 #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL BIT(13) 107 #define PHY_CTRL_R18_MPLL_PFD_GAIN GENMASK(15, 14) 108 #define PHY_CTRL_R18_MPLL_ROU GENMASK(18, 16) 109 #define PHY_CTRL_R18_MPLL_DATA_SEL GENMASK(21, 19) 110 #define PHY_CTRL_R18_MPLL_BIAS_ADJ GENMASK(23, 22) 111 #define PHY_CTRL_R18_MPLL_BB_MODE GENMASK(25, 24) 112 #define PHY_CTRL_R18_MPLL_ALPHA GENMASK(28, 26) 113 #define PHY_CTRL_R18_MPLL_ADJ_LDO GENMASK(30, 29) 114 #define PHY_CTRL_R18_MPLL_ACG_RANGE BIT(31) 115 116 #define PHY_CTRL_R19 0x4c 117 #define PHY_CTRL_R20 0x50 118 #define PHY_CTRL_R20_USB2_IDDET_EN BIT(0) 119 #define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0 GENMASK(3, 1) 120 #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN BIT(4) 121 #define PHY_CTRL_R20_USB2_AMON_EN BIT(5) 122 #define PHY_CTRL_R20_USB2_CAL_CODE_R5 BIT(6) 123 #define PHY_CTRL_R20_BYPASS_OTG_DET BIT(7) 124 #define PHY_CTRL_R20_USB2_DMON_EN BIT(8) 125 #define PHY_CTRL_R20_USB2_DMON_SEL_3_0 GENMASK(12, 9) 126 #define PHY_CTRL_R20_USB2_EDGE_DRV_EN BIT(13) 127 #define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0 GENMASK(15, 14) 128 #define PHY_CTRL_R20_USB2_BGR_ADJ_4_0 GENMASK(20, 16) 129 #define PHY_CTRL_R20_USB2_BGR_START BIT(21) 130 #define PHY_CTRL_R20_USB2_BGR_VREF_4_0 GENMASK(28, 24) 131 #define PHY_CTRL_R20_USB2_BGR_DBG_1_0 GENMASK(30, 29) 132 #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5 BIT(31) 133 134 #define PHY_CTRL_R21 0x54 135 #define PHY_CTRL_R21_USB2_BGR_FORCE BIT(0) 136 #define PHY_CTRL_R21_USB2_CAL_ACK_EN BIT(1) 137 #define PHY_CTRL_R21_USB2_OTG_ACA_EN BIT(2) 138 #define PHY_CTRL_R21_USB2_TX_STRG_PD BIT(3) 139 #define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0 GENMASK(5, 4) 140 #define PHY_CTRL_R21_BYPASS_UTMI_CNTR GENMASK(15, 6) 141 #define PHY_CTRL_R21_BYPASS_UTMI_REG GENMASK(25, 20) 142 143 #define PHY_CTRL_R22 0x58 144 #define PHY_CTRL_R23 0x5c 145 146 #define RESET_COMPLETE_TIME 1000 147 #define PLL_RESET_COMPLETE_TIME 100 148 149 struct phy_meson_g12a_usb2_priv { 150 struct device *dev; 151 struct regmap *regmap; 152 struct clk *clk; 153 struct reset_control *reset; 154 }; 155 156 static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = { 157 .reg_bits = 8, 158 .val_bits = 32, 159 .reg_stride = 4, 160 .max_register = PHY_CTRL_R23, 161 }; 162 163 static int phy_meson_g12a_usb2_init(struct phy *phy) 164 { 165 struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy); 166 int ret; 167 168 ret = reset_control_reset(priv->reset); 169 if (ret) 170 return ret; 171 172 udelay(RESET_COMPLETE_TIME); 173 174 /* usb2_otg_aca_en == 0 */ 175 regmap_update_bits(priv->regmap, PHY_CTRL_R21, 176 PHY_CTRL_R21_USB2_OTG_ACA_EN, 0); 177 178 /* PLL Setup : 24MHz * 20 / 1 = 480MHz */ 179 regmap_write(priv->regmap, PHY_CTRL_R16, 180 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | 181 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | 182 PHY_CTRL_R16_MPLL_LOAD | 183 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | 184 PHY_CTRL_R16_MPLL_FAST_LOCK | 185 PHY_CTRL_R16_MPLL_EN | 186 PHY_CTRL_R16_MPLL_RESET); 187 188 regmap_write(priv->regmap, PHY_CTRL_R17, 189 FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | 190 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | 191 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | 192 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | 193 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); 194 195 regmap_write(priv->regmap, PHY_CTRL_R18, 196 FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | 197 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | 198 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | 199 FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | 200 FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | 201 FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) | 202 FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) | 203 FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | 204 FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | 205 FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | 206 PHY_CTRL_R18_MPLL_ACG_RANGE); 207 208 udelay(PLL_RESET_COMPLETE_TIME); 209 210 /* UnReset PLL */ 211 regmap_write(priv->regmap, PHY_CTRL_R16, 212 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | 213 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | 214 PHY_CTRL_R16_MPLL_LOAD | 215 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | 216 PHY_CTRL_R16_MPLL_FAST_LOCK | 217 PHY_CTRL_R16_MPLL_EN); 218 219 /* PHY Tuning */ 220 regmap_write(priv->regmap, PHY_CTRL_R20, 221 FIELD_PREP(PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0, 4) | 222 PHY_CTRL_R20_USB2_OTG_VBUSDET_EN | 223 FIELD_PREP(PHY_CTRL_R20_USB2_DMON_SEL_3_0, 15) | 224 PHY_CTRL_R20_USB2_EDGE_DRV_EN | 225 FIELD_PREP(PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0, 3) | 226 FIELD_PREP(PHY_CTRL_R20_USB2_BGR_ADJ_4_0, 0) | 227 FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) | 228 FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0)); 229 230 regmap_write(priv->regmap, PHY_CTRL_R4, 231 FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) | 232 FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) | 233 FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) | 234 PHY_CTRL_R4_TEST_BYPASS_MODE_EN | 235 FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) | 236 FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0)); 237 238 /* Tuning Disconnect Threshold */ 239 regmap_write(priv->regmap, PHY_CTRL_R3, 240 FIELD_PREP(PHY_CTRL_R3_SQUELCH_REF, 0) | 241 FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) | 242 FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3)); 243 244 /* Analog Settings */ 245 regmap_write(priv->regmap, PHY_CTRL_R14, 0); 246 regmap_write(priv->regmap, PHY_CTRL_R13, 247 PHY_CTRL_R13_UPDATE_PMA_SIGNALS | 248 FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7)); 249 250 return 0; 251 } 252 253 static int phy_meson_g12a_usb2_exit(struct phy *phy) 254 { 255 struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy); 256 257 return reset_control_reset(priv->reset); 258 } 259 260 /* set_mode is not needed, mode setting is handled via the UTMI bus */ 261 static const struct phy_ops phy_meson_g12a_usb2_ops = { 262 .init = phy_meson_g12a_usb2_init, 263 .exit = phy_meson_g12a_usb2_exit, 264 .owner = THIS_MODULE, 265 }; 266 267 static int phy_meson_g12a_usb2_probe(struct platform_device *pdev) 268 { 269 struct device *dev = &pdev->dev; 270 struct phy_provider *phy_provider; 271 struct resource *res; 272 struct phy_meson_g12a_usb2_priv *priv; 273 struct phy *phy; 274 void __iomem *base; 275 int ret; 276 277 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 278 if (!priv) 279 return -ENOMEM; 280 281 priv->dev = dev; 282 platform_set_drvdata(pdev, priv); 283 284 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 285 base = devm_ioremap_resource(dev, res); 286 if (IS_ERR(base)) 287 return PTR_ERR(base); 288 289 priv->regmap = devm_regmap_init_mmio(dev, base, 290 &phy_meson_g12a_usb2_regmap_conf); 291 if (IS_ERR(priv->regmap)) 292 return PTR_ERR(priv->regmap); 293 294 priv->clk = devm_clk_get(dev, "xtal"); 295 if (IS_ERR(priv->clk)) 296 return PTR_ERR(priv->clk); 297 298 priv->reset = devm_reset_control_get(dev, "phy"); 299 if (IS_ERR(priv->reset)) 300 return PTR_ERR(priv->reset); 301 302 ret = reset_control_deassert(priv->reset); 303 if (ret) 304 return ret; 305 306 phy = devm_phy_create(dev, NULL, &phy_meson_g12a_usb2_ops); 307 if (IS_ERR(phy)) { 308 ret = PTR_ERR(phy); 309 if (ret != -EPROBE_DEFER) 310 dev_err(dev, "failed to create PHY\n"); 311 312 return ret; 313 } 314 315 phy_set_bus_width(phy, 8); 316 phy_set_drvdata(phy, priv); 317 318 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 319 320 return PTR_ERR_OR_ZERO(phy_provider); 321 } 322 323 static const struct of_device_id phy_meson_g12a_usb2_of_match[] = { 324 { .compatible = "amlogic,g12a-usb2-phy", }, 325 { }, 326 }; 327 MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match); 328 329 static struct platform_driver phy_meson_g12a_usb2_driver = { 330 .probe = phy_meson_g12a_usb2_probe, 331 .driver = { 332 .name = "phy-meson-g12a-usb2", 333 .of_match_table = phy_meson_g12a_usb2_of_match, 334 }, 335 }; 336 module_platform_driver(phy_meson_g12a_usb2_driver); 337 338 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); 339 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 340 MODULE_DESCRIPTION("Meson G12A USB2 PHY driver"); 341 MODULE_LICENSE("GPL v2"); 342