1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Meson AXG MIPI DPHY driver 4 * 5 * Copyright (C) 2018 Amlogic, Inc. All rights reserved 6 * Copyright (C) 2020 BayLibre, SAS 7 * Author: Neil Armstrong <narmstrong@baylibre.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 22 /* [31] soft reset for the phy. 23 * 1: reset. 0: dessert the reset. 24 * [30] clock lane soft reset. 25 * [29] data byte lane 3 soft reset. 26 * [28] data byte lane 2 soft reset. 27 * [27] data byte lane 1 soft reset. 28 * [26] data byte lane 0 soft reset. 29 * [25] mipi dsi pll clock selection. 30 * 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL. 31 * [12] mipi HSbyteclk enable. 32 * [11] mipi divider clk selection. 33 * 1: select the mipi DDRCLKHS from clock divider. 34 * 0: from PLL clock. 35 * [10] mipi clock divider control. 36 * 1: /4. 0: /2. 37 * [9] mipi divider output enable. 38 * [8] mipi divider counter enable. 39 * [7] PLL clock enable. 40 * [5] LPDT data endian. 41 * 1 = transfer the high bit first. 0 : transfer the low bit first. 42 * [4] HS data endian. 43 * [3] force data byte lane in stop mode. 44 * [2] force data byte lane 0 in receiver mode. 45 * [1] write 1 to sync the txclkesc input. the internal logic have to 46 * use txclkesc to decide Txvalid and Txready. 47 * [0] enalbe the MIPI DPHY TxDDRClk. 48 */ 49 #define MIPI_DSI_PHY_CTRL 0x0 50 51 /* [31] clk lane tx_hs_en control selection. 52 * 1: from register. 0: use clk lane state machine. 53 * [30] register bit for clock lane tx_hs_en. 54 * [29] clk lane tx_lp_en contrl selection. 55 * 1: from register. 0: from clk lane state machine. 56 * [28] register bit for clock lane tx_lp_en. 57 * [27] chan0 tx_hs_en control selection. 58 * 1: from register. 0: from chan0 state machine. 59 * [26] register bit for chan0 tx_hs_en. 60 * [25] chan0 tx_lp_en control selection. 61 * 1: from register. 0: from chan0 state machine. 62 * [24] register bit from chan0 tx_lp_en. 63 * [23] chan0 rx_lp_en control selection. 64 * 1: from register. 0: from chan0 state machine. 65 * [22] register bit from chan0 rx_lp_en. 66 * [21] chan0 contention detection enable control selection. 67 * 1: from register. 0: from chan0 state machine. 68 * [20] register bit from chan0 contention dectection enable. 69 * [19] chan1 tx_hs_en control selection. 70 * 1: from register. 0: from chan0 state machine. 71 * [18] register bit for chan1 tx_hs_en. 72 * [17] chan1 tx_lp_en control selection. 73 * 1: from register. 0: from chan0 state machine. 74 * [16] register bit from chan1 tx_lp_en. 75 * [15] chan2 tx_hs_en control selection. 76 * 1: from register. 0: from chan0 state machine. 77 * [14] register bit for chan2 tx_hs_en. 78 * [13] chan2 tx_lp_en control selection. 79 * 1: from register. 0: from chan0 state machine. 80 * [12] register bit from chan2 tx_lp_en. 81 * [11] chan3 tx_hs_en control selection. 82 * 1: from register. 0: from chan0 state machine. 83 * [10] register bit for chan3 tx_hs_en. 84 * [9] chan3 tx_lp_en control selection. 85 * 1: from register. 0: from chan0 state machine. 86 * [8] register bit from chan3 tx_lp_en. 87 * [4] clk chan power down. this bit is also used as the power down 88 * of the whole MIPI_DSI_PHY. 89 * [3] chan3 power down. 90 * [2] chan2 power down. 91 * [1] chan1 power down. 92 * [0] chan0 power down. 93 */ 94 #define MIPI_DSI_CHAN_CTRL 0x4 95 96 /* [24] rx turn watch dog triggered. 97 * [23] rx esc watchdog triggered. 98 * [22] mbias ready. 99 * [21] txclkesc synced and ready. 100 * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active} 101 * [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active} 102 * [12:9] chan2 state.{0, tx_stop, tx_ulps, tx_hs_active} 103 * [8:5] chan1 state. {0, tx_stop, tx_ulps, tx_hs_active} 104 * [4:0] chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc} 105 */ 106 #define MIPI_DSI_CHAN_STS 0x8 107 108 /* [31:24] TCLK_PREPARE. 109 * [23:16] TCLK_ZERO. 110 * [15:8] TCLK_POST. 111 * [7:0] TCLK_TRAIL. 112 */ 113 #define MIPI_DSI_CLK_TIM 0xc 114 115 /* [31:24] THS_PREPARE. 116 * [23:16] THS_ZERO. 117 * [15:8] THS_TRAIL. 118 * [7:0] THS_EXIT. 119 */ 120 #define MIPI_DSI_HS_TIM 0x10 121 122 /* [31:24] tTA_GET. 123 * [23:16] tTA_GO. 124 * [15:8] tTA_SURE. 125 * [7:0] tLPX. 126 */ 127 #define MIPI_DSI_LP_TIM 0x14 128 129 /* wait time to MIPI DIS analog ready. */ 130 #define MIPI_DSI_ANA_UP_TIM 0x18 131 132 /* TINIT. */ 133 #define MIPI_DSI_INIT_TIM 0x1c 134 135 /* TWAKEUP. */ 136 #define MIPI_DSI_WAKEUP_TIM 0x20 137 138 /* when in RxULPS check state, after the the logic enable the analog, 139 * how long we should wait to check the lP state . 140 */ 141 #define MIPI_DSI_LPOK_TIM 0x24 142 143 /* Watchdog for RX low power state no finished. */ 144 #define MIPI_DSI_LP_WCHDOG 0x28 145 146 /* tMBIAS, after send power up signals to analog, 147 * how long we should wait for analog powered up. 148 */ 149 #define MIPI_DSI_ANA_CTRL 0x2c 150 151 /* [31:8] reserved for future. 152 * [7:0] tCLK_PRE. 153 */ 154 #define MIPI_DSI_CLK_TIM1 0x30 155 156 /* watchdog for turn around waiting time. */ 157 #define MIPI_DSI_TURN_WCHDOG 0x34 158 159 /* When in RxULPS state, how frequency we should to check 160 * if the TX side out of ULPS state. 161 */ 162 #define MIPI_DSI_ULPS_CHECK 0x38 163 #define MIPI_DSI_TEST_CTRL0 0x3c 164 #define MIPI_DSI_TEST_CTRL1 0x40 165 166 struct phy_meson_axg_mipi_dphy_priv { 167 struct device *dev; 168 struct regmap *regmap; 169 struct clk *clk; 170 struct reset_control *reset; 171 struct phy *analog; 172 struct phy_configure_opts_mipi_dphy config; 173 }; 174 175 static const struct regmap_config phy_meson_axg_mipi_dphy_regmap_conf = { 176 .reg_bits = 8, 177 .val_bits = 32, 178 .reg_stride = 4, 179 .max_register = MIPI_DSI_TEST_CTRL1, 180 }; 181 182 static int phy_meson_axg_mipi_dphy_init(struct phy *phy) 183 { 184 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); 185 int ret; 186 187 ret = phy_init(priv->analog); 188 if (ret) 189 return ret; 190 191 ret = reset_control_reset(priv->reset); 192 if (ret) 193 return ret; 194 195 return 0; 196 } 197 198 static int phy_meson_axg_mipi_dphy_configure(struct phy *phy, 199 union phy_configure_opts *opts) 200 { 201 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); 202 int ret; 203 204 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 205 if (ret) 206 return ret; 207 208 ret = phy_configure(priv->analog, opts); 209 if (ret) 210 return ret; 211 212 memcpy(&priv->config, opts, sizeof(priv->config)); 213 214 return 0; 215 } 216 217 static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy) 218 { 219 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); 220 int ret; 221 unsigned long temp; 222 223 ret = phy_power_on(priv->analog); 224 if (ret) 225 return ret; 226 227 /* enable phy clock */ 228 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1); 229 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 230 BIT(0) | /* enable the DSI PLL clock . */ 231 BIT(7) | /* enable pll clock which connected to DDR clock path */ 232 BIT(8)); /* enable the clock divider counter */ 233 234 /* enable the divider clock out */ 235 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9)); 236 237 /* enable the byte clock generation. */ 238 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12)); 239 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31)); 240 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0); 241 242 /* Calculate lanebyteclk period in ps */ 243 temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000); 244 temp = temp * 8 * 10; 245 246 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM, 247 DIV_ROUND_UP(priv->config.clk_trail, temp) | 248 (DIV_ROUND_UP(priv->config.clk_post + 249 priv->config.hs_trail, temp) << 8) | 250 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | 251 (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24)); 252 regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1, 253 DIV_ROUND_UP(priv->config.clk_pre, temp)); 254 255 regmap_write(priv->regmap, MIPI_DSI_HS_TIM, 256 DIV_ROUND_UP(priv->config.hs_exit, temp) | 257 (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) | 258 (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) | 259 (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24)); 260 261 regmap_write(priv->regmap, MIPI_DSI_LP_TIM, 262 DIV_ROUND_UP(priv->config.lpx, temp) | 263 (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) | 264 (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) | 265 (DIV_ROUND_UP(priv->config.ta_get, temp) << 24)); 266 267 regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100); 268 regmap_write(priv->regmap, MIPI_DSI_INIT_TIM, 269 DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp)); 270 regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM, 271 DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp)); 272 regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C); 273 regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C); 274 regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000); 275 regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000); 276 277 /* Powerup the analog circuit */ 278 switch (priv->config.lanes) { 279 case 1: 280 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe); 281 break; 282 case 2: 283 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc); 284 break; 285 case 3: 286 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8); 287 break; 288 case 4: 289 default: 290 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0); 291 break; 292 } 293 294 /* Trigger a sync active for esc_clk */ 295 regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1)); 296 297 return 0; 298 } 299 300 static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy) 301 { 302 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); 303 304 regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf); 305 regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31)); 306 307 phy_power_off(priv->analog); 308 309 return 0; 310 } 311 312 static int phy_meson_axg_mipi_dphy_exit(struct phy *phy) 313 { 314 struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy); 315 int ret; 316 317 ret = phy_exit(priv->analog); 318 if (ret) 319 return ret; 320 321 return reset_control_reset(priv->reset); 322 } 323 324 static const struct phy_ops phy_meson_axg_mipi_dphy_ops = { 325 .configure = phy_meson_axg_mipi_dphy_configure, 326 .init = phy_meson_axg_mipi_dphy_init, 327 .exit = phy_meson_axg_mipi_dphy_exit, 328 .power_on = phy_meson_axg_mipi_dphy_power_on, 329 .power_off = phy_meson_axg_mipi_dphy_power_off, 330 .owner = THIS_MODULE, 331 }; 332 333 static int phy_meson_axg_mipi_dphy_probe(struct platform_device *pdev) 334 { 335 struct device *dev = &pdev->dev; 336 struct phy_provider *phy_provider; 337 struct resource *res; 338 struct phy_meson_axg_mipi_dphy_priv *priv; 339 struct phy *phy; 340 void __iomem *base; 341 int ret; 342 343 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 344 if (!priv) 345 return -ENOMEM; 346 347 priv->dev = dev; 348 platform_set_drvdata(pdev, priv); 349 350 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 351 base = devm_ioremap_resource(dev, res); 352 if (IS_ERR(base)) 353 return PTR_ERR(base); 354 355 priv->regmap = devm_regmap_init_mmio(dev, base, 356 &phy_meson_axg_mipi_dphy_regmap_conf); 357 if (IS_ERR(priv->regmap)) 358 return PTR_ERR(priv->regmap); 359 360 priv->clk = devm_clk_get(dev, "pclk"); 361 if (IS_ERR(priv->clk)) 362 return PTR_ERR(priv->clk); 363 364 priv->reset = devm_reset_control_get(dev, "phy"); 365 if (IS_ERR(priv->reset)) 366 return PTR_ERR(priv->reset); 367 368 priv->analog = devm_phy_get(dev, "analog"); 369 if (IS_ERR(priv->analog)) 370 return PTR_ERR(priv->analog); 371 372 ret = clk_prepare_enable(priv->clk); 373 if (ret) 374 return ret; 375 376 ret = reset_control_deassert(priv->reset); 377 if (ret) 378 return ret; 379 380 phy = devm_phy_create(dev, NULL, &phy_meson_axg_mipi_dphy_ops); 381 if (IS_ERR(phy)) { 382 ret = PTR_ERR(phy); 383 if (ret != -EPROBE_DEFER) 384 dev_err(dev, "failed to create PHY\n"); 385 386 return ret; 387 } 388 389 phy_set_drvdata(phy, priv); 390 391 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 392 393 return PTR_ERR_OR_ZERO(phy_provider); 394 } 395 396 static const struct of_device_id phy_meson_axg_mipi_dphy_of_match[] = { 397 { .compatible = "amlogic,axg-mipi-dphy", }, 398 { }, 399 }; 400 MODULE_DEVICE_TABLE(of, phy_meson_axg_mipi_dphy_of_match); 401 402 static struct platform_driver phy_meson_axg_mipi_dphy_driver = { 403 .probe = phy_meson_axg_mipi_dphy_probe, 404 .driver = { 405 .name = "phy-meson-axg-mipi-dphy", 406 .of_match_table = phy_meson_axg_mipi_dphy_of_match, 407 }, 408 }; 409 module_platform_driver(phy_meson_axg_mipi_dphy_driver); 410 411 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 412 MODULE_DESCRIPTION("Meson AXG MIPI DPHY driver"); 413 MODULE_LICENSE("GPL v2"); 414