1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. 4 * 5 * ARMv7 support: Jean Pihet <jpihet@mvista.com> 6 * 2010 (c) MontaVista Software, LLC. 7 * 8 * Copied from ARMv6 code, with the low level code inspired 9 * by the ARMv7 Oprofile code. 10 * 11 * Cortex-A8 has up to 4 configurable performance counters and 12 * a single cycle counter. 13 * Cortex-A9 has up to 31 configurable performance counters and 14 * a single cycle counter. 15 * 16 * All counters can be enabled/disabled and IRQ masked separately. The cycle 17 * counter and all 4 performance counters together can be reset separately. 18 */ 19 20 #include <asm/cp15.h> 21 #include <asm/cputype.h> 22 #include <asm/irq_regs.h> 23 #include <asm/vfp.h> 24 #include "../vfp/vfpinstr.h" 25 26 #include <linux/of.h> 27 #include <linux/perf/arm_pmu.h> 28 #include <linux/platform_device.h> 29 30 /* 31 * Common ARMv7 event types 32 * 33 * Note: An implementation may not be able to count all of these events 34 * but the encodings are considered to be `reserved' in the case that 35 * they are not available. 36 */ 37 #define ARMV7_PERFCTR_PMNC_SW_INCR 0x00 38 #define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01 39 #define ARMV7_PERFCTR_ITLB_REFILL 0x02 40 #define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03 41 #define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04 42 #define ARMV7_PERFCTR_DTLB_REFILL 0x05 43 #define ARMV7_PERFCTR_MEM_READ 0x06 44 #define ARMV7_PERFCTR_MEM_WRITE 0x07 45 #define ARMV7_PERFCTR_INSTR_EXECUTED 0x08 46 #define ARMV7_PERFCTR_EXC_TAKEN 0x09 47 #define ARMV7_PERFCTR_EXC_EXECUTED 0x0A 48 #define ARMV7_PERFCTR_CID_WRITE 0x0B 49 50 /* 51 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. 52 * It counts: 53 * - all (taken) branch instructions, 54 * - instructions that explicitly write the PC, 55 * - exception generating instructions. 56 */ 57 #define ARMV7_PERFCTR_PC_WRITE 0x0C 58 #define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D 59 #define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E 60 #define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F 61 #define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10 62 #define ARMV7_PERFCTR_CLOCK_CYCLES 0x11 63 #define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12 64 65 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ 66 #define ARMV7_PERFCTR_MEM_ACCESS 0x13 67 #define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14 68 #define ARMV7_PERFCTR_L1_DCACHE_WB 0x15 69 #define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16 70 #define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17 71 #define ARMV7_PERFCTR_L2_CACHE_WB 0x18 72 #define ARMV7_PERFCTR_BUS_ACCESS 0x19 73 #define ARMV7_PERFCTR_MEM_ERROR 0x1A 74 #define ARMV7_PERFCTR_INSTR_SPEC 0x1B 75 #define ARMV7_PERFCTR_TTBR_WRITE 0x1C 76 #define ARMV7_PERFCTR_BUS_CYCLES 0x1D 77 78 #define ARMV7_PERFCTR_CPU_CYCLES 0xFF 79 80 /* ARMv7 Cortex-A8 specific event types */ 81 #define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43 82 #define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44 83 #define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50 84 #define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56 85 86 /* ARMv7 Cortex-A9 specific event types */ 87 #define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68 88 #define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60 89 #define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66 90 91 /* ARMv7 Cortex-A5 specific event types */ 92 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2 93 #define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3 94 95 /* ARMv7 Cortex-A15 specific event types */ 96 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 97 #define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 98 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42 99 #define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43 100 101 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C 102 #define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D 103 104 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50 105 #define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 106 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52 107 #define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53 108 109 #define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76 110 111 /* ARMv7 Cortex-A12 specific event types */ 112 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 113 #define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 114 115 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50 116 #define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 117 118 #define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76 119 120 #define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7 121 122 /* ARMv7 Krait specific event types */ 123 #define KRAIT_PMRESR0_GROUP0 0xcc 124 #define KRAIT_PMRESR1_GROUP0 0xd0 125 #define KRAIT_PMRESR2_GROUP0 0xd4 126 #define KRAIT_VPMRESR0_GROUP0 0xd8 127 128 #define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011 129 #define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010 130 131 #define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222 132 #define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210 133 134 /* ARMv7 Scorpion specific event types */ 135 #define SCORPION_LPM0_GROUP0 0x4c 136 #define SCORPION_LPM1_GROUP0 0x50 137 #define SCORPION_LPM2_GROUP0 0x54 138 #define SCORPION_L2LPM_GROUP0 0x58 139 #define SCORPION_VLPM_GROUP0 0x5c 140 141 #define SCORPION_ICACHE_ACCESS 0x10053 142 #define SCORPION_ICACHE_MISS 0x10052 143 144 #define SCORPION_DTLB_ACCESS 0x12013 145 #define SCORPION_DTLB_MISS 0x12012 146 147 #define SCORPION_ITLB_MISS 0x12021 148 149 /* 150 * Cortex-A8 HW events mapping 151 * 152 * The hardware events that we support. We do support cache operations but 153 * we have harvard caches and no way to combine instruction and data 154 * accesses/misses in hardware. 155 */ 156 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { 157 PERF_MAP_ALL_UNSUPPORTED, 158 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 159 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 160 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 161 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 162 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 163 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 164 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, 165 }; 166 167 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 168 [PERF_COUNT_HW_CACHE_OP_MAX] 169 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 170 PERF_CACHE_MAP_ALL_UNSUPPORTED, 171 172 /* 173 * The performance counters don't differentiate between read and write 174 * accesses/misses so this isn't strictly correct, but it's the best we 175 * can do. Writes and reads get combined. 176 */ 177 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 178 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 179 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 180 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 181 182 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, 183 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 184 185 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, 186 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, 187 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, 188 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, 189 190 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 191 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 192 193 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 194 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 195 196 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 197 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 198 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 199 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 200 }; 201 202 /* 203 * Cortex-A9 HW events mapping 204 */ 205 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { 206 PERF_MAP_ALL_UNSUPPORTED, 207 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 208 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, 209 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 210 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 211 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 212 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 213 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, 214 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, 215 }; 216 217 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 218 [PERF_COUNT_HW_CACHE_OP_MAX] 219 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 220 PERF_CACHE_MAP_ALL_UNSUPPORTED, 221 222 /* 223 * The performance counters don't differentiate between read and write 224 * accesses/misses so this isn't strictly correct, but it's the best we 225 * can do. Writes and reads get combined. 226 */ 227 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 228 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 229 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 230 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 231 232 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 233 234 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 235 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 236 237 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 238 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 239 240 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 241 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 242 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 243 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 244 }; 245 246 /* 247 * Cortex-A5 HW events mapping 248 */ 249 static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { 250 PERF_MAP_ALL_UNSUPPORTED, 251 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 252 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 253 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 254 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 255 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 256 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 257 }; 258 259 static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 260 [PERF_COUNT_HW_CACHE_OP_MAX] 261 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 262 PERF_CACHE_MAP_ALL_UNSUPPORTED, 263 264 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 265 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 266 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 267 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 268 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 269 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 270 271 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 272 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 273 /* 274 * The prefetch counters don't differentiate between the I side and the 275 * D side. 276 */ 277 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 278 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 279 280 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 281 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 282 283 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 284 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 285 286 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 287 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 288 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 289 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 290 }; 291 292 /* 293 * Cortex-A15 HW events mapping 294 */ 295 static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { 296 PERF_MAP_ALL_UNSUPPORTED, 297 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 298 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 299 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 300 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 301 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, 302 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 303 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 304 }; 305 306 static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 307 [PERF_COUNT_HW_CACHE_OP_MAX] 308 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 309 PERF_CACHE_MAP_ALL_UNSUPPORTED, 310 311 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, 312 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, 313 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, 314 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, 315 316 /* 317 * Not all performance counters differentiate between read and write 318 * accesses/misses so we're not always strictly correct, but it's the 319 * best we can do. Writes and reads get combined in these cases. 320 */ 321 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 322 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 323 324 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ, 325 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ, 326 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE, 327 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE, 328 329 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ, 330 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE, 331 332 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 333 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 334 335 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 336 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 337 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 338 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 339 }; 340 341 /* 342 * Cortex-A7 HW events mapping 343 */ 344 static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { 345 PERF_MAP_ALL_UNSUPPORTED, 346 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 347 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 348 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 349 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 350 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 351 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 352 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 353 }; 354 355 static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 356 [PERF_COUNT_HW_CACHE_OP_MAX] 357 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 358 PERF_CACHE_MAP_ALL_UNSUPPORTED, 359 360 /* 361 * The performance counters don't differentiate between read and write 362 * accesses/misses so this isn't strictly correct, but it's the best we 363 * can do. Writes and reads get combined. 364 */ 365 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 366 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 367 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 368 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 369 370 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 371 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 372 373 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, 374 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 375 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, 376 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 377 378 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 379 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 380 381 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 382 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 383 384 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 385 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 386 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 387 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 388 }; 389 390 /* 391 * Cortex-A12 HW events mapping 392 */ 393 static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { 394 PERF_MAP_ALL_UNSUPPORTED, 395 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 396 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 397 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 398 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 399 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, 400 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 401 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 402 }; 403 404 static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 405 [PERF_COUNT_HW_CACHE_OP_MAX] 406 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 407 PERF_CACHE_MAP_ALL_UNSUPPORTED, 408 409 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, 410 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 411 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, 412 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 413 414 /* 415 * Not all performance counters differentiate between read and write 416 * accesses/misses so we're not always strictly correct, but it's the 417 * best we can do. Writes and reads get combined in these cases. 418 */ 419 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 420 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 421 422 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, 423 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 424 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, 425 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 426 427 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 428 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 429 [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, 430 431 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 432 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 433 434 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 435 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 436 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 437 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 438 }; 439 440 /* 441 * Krait HW events mapping 442 */ 443 static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { 444 PERF_MAP_ALL_UNSUPPORTED, 445 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 446 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 447 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 448 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 449 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 450 }; 451 452 static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { 453 PERF_MAP_ALL_UNSUPPORTED, 454 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 455 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 456 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 457 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 458 }; 459 460 static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 461 [PERF_COUNT_HW_CACHE_OP_MAX] 462 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 463 PERF_CACHE_MAP_ALL_UNSUPPORTED, 464 465 /* 466 * The performance counters don't differentiate between read and write 467 * accesses/misses so this isn't strictly correct, but it's the best we 468 * can do. Writes and reads get combined. 469 */ 470 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 471 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 472 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 473 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 474 475 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, 476 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, 477 478 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, 479 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, 480 481 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, 482 [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, 483 484 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 485 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 486 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 487 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 488 }; 489 490 /* 491 * Scorpion HW events mapping 492 */ 493 static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = { 494 PERF_MAP_ALL_UNSUPPORTED, 495 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 496 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 497 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 498 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 499 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 500 }; 501 502 static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 503 [PERF_COUNT_HW_CACHE_OP_MAX] 504 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 505 PERF_CACHE_MAP_ALL_UNSUPPORTED, 506 /* 507 * The performance counters don't differentiate between read and write 508 * accesses/misses so this isn't strictly correct, but it's the best we 509 * can do. Writes and reads get combined. 510 */ 511 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 512 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 513 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 514 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 515 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, 516 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, 517 /* 518 * Only ITLB misses and DTLB refills are supported. If users want the 519 * DTLB refills misses a raw counter must be used. 520 */ 521 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, 522 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, 523 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, 524 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, 525 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, 526 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, 527 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 528 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 529 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 530 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 531 }; 532 533 PMU_FORMAT_ATTR(event, "config:0-7"); 534 535 static struct attribute *armv7_pmu_format_attrs[] = { 536 &format_attr_event.attr, 537 NULL, 538 }; 539 540 static struct attribute_group armv7_pmu_format_attr_group = { 541 .name = "format", 542 .attrs = armv7_pmu_format_attrs, 543 }; 544 545 #define ARMV7_EVENT_ATTR_RESOLVE(m) #m 546 #define ARMV7_EVENT_ATTR(name, config) \ 547 PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \ 548 "event=" ARMV7_EVENT_ATTR_RESOLVE(config)) 549 550 ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR); 551 ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL); 552 ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL); 553 ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL); 554 ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS); 555 ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL); 556 ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ); 557 ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE); 558 ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED); 559 ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN); 560 ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED); 561 ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE); 562 ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE); 563 ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH); 564 ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN); 565 ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS); 566 ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED); 567 ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES); 568 ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED); 569 570 static struct attribute *armv7_pmuv1_event_attrs[] = { 571 &armv7_event_attr_sw_incr.attr.attr, 572 &armv7_event_attr_l1i_cache_refill.attr.attr, 573 &armv7_event_attr_l1i_tlb_refill.attr.attr, 574 &armv7_event_attr_l1d_cache_refill.attr.attr, 575 &armv7_event_attr_l1d_cache.attr.attr, 576 &armv7_event_attr_l1d_tlb_refill.attr.attr, 577 &armv7_event_attr_ld_retired.attr.attr, 578 &armv7_event_attr_st_retired.attr.attr, 579 &armv7_event_attr_inst_retired.attr.attr, 580 &armv7_event_attr_exc_taken.attr.attr, 581 &armv7_event_attr_exc_return.attr.attr, 582 &armv7_event_attr_cid_write_retired.attr.attr, 583 &armv7_event_attr_pc_write_retired.attr.attr, 584 &armv7_event_attr_br_immed_retired.attr.attr, 585 &armv7_event_attr_br_return_retired.attr.attr, 586 &armv7_event_attr_unaligned_ldst_retired.attr.attr, 587 &armv7_event_attr_br_mis_pred.attr.attr, 588 &armv7_event_attr_cpu_cycles.attr.attr, 589 &armv7_event_attr_br_pred.attr.attr, 590 NULL, 591 }; 592 593 static struct attribute_group armv7_pmuv1_events_attr_group = { 594 .name = "events", 595 .attrs = armv7_pmuv1_event_attrs, 596 }; 597 598 ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS); 599 ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS); 600 ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB); 601 ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS); 602 ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL); 603 ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB); 604 ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS); 605 ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR); 606 ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC); 607 ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE); 608 ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES); 609 610 static struct attribute *armv7_pmuv2_event_attrs[] = { 611 &armv7_event_attr_sw_incr.attr.attr, 612 &armv7_event_attr_l1i_cache_refill.attr.attr, 613 &armv7_event_attr_l1i_tlb_refill.attr.attr, 614 &armv7_event_attr_l1d_cache_refill.attr.attr, 615 &armv7_event_attr_l1d_cache.attr.attr, 616 &armv7_event_attr_l1d_tlb_refill.attr.attr, 617 &armv7_event_attr_ld_retired.attr.attr, 618 &armv7_event_attr_st_retired.attr.attr, 619 &armv7_event_attr_inst_retired.attr.attr, 620 &armv7_event_attr_exc_taken.attr.attr, 621 &armv7_event_attr_exc_return.attr.attr, 622 &armv7_event_attr_cid_write_retired.attr.attr, 623 &armv7_event_attr_pc_write_retired.attr.attr, 624 &armv7_event_attr_br_immed_retired.attr.attr, 625 &armv7_event_attr_br_return_retired.attr.attr, 626 &armv7_event_attr_unaligned_ldst_retired.attr.attr, 627 &armv7_event_attr_br_mis_pred.attr.attr, 628 &armv7_event_attr_cpu_cycles.attr.attr, 629 &armv7_event_attr_br_pred.attr.attr, 630 &armv7_event_attr_mem_access.attr.attr, 631 &armv7_event_attr_l1i_cache.attr.attr, 632 &armv7_event_attr_l1d_cache_wb.attr.attr, 633 &armv7_event_attr_l2d_cache.attr.attr, 634 &armv7_event_attr_l2d_cache_refill.attr.attr, 635 &armv7_event_attr_l2d_cache_wb.attr.attr, 636 &armv7_event_attr_bus_access.attr.attr, 637 &armv7_event_attr_memory_error.attr.attr, 638 &armv7_event_attr_inst_spec.attr.attr, 639 &armv7_event_attr_ttbr_write_retired.attr.attr, 640 &armv7_event_attr_bus_cycles.attr.attr, 641 NULL, 642 }; 643 644 static struct attribute_group armv7_pmuv2_events_attr_group = { 645 .name = "events", 646 .attrs = armv7_pmuv2_event_attrs, 647 }; 648 649 /* 650 * Perf Events' indices 651 */ 652 #define ARMV7_IDX_CYCLE_COUNTER 31 653 #define ARMV7_IDX_COUNTER_MAX 31 654 /* 655 * ARMv7 low level PMNC access 656 */ 657 658 /* 659 * Per-CPU PMNC: config reg 660 */ 661 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ 662 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ 663 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ 664 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ 665 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ 666 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 667 #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ 668 #define ARMV7_PMNC_N_MASK 0x1f 669 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ 670 671 /* 672 * FLAG: counters overflow flag status reg 673 */ 674 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ 675 #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK 676 677 /* 678 * PMXEVTYPER: Event selection reg 679 */ 680 #define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */ 681 #define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ 682 683 /* 684 * Event filters for PMUv2 685 */ 686 #define ARMV7_EXCLUDE_PL1 BIT(31) 687 #define ARMV7_EXCLUDE_USER BIT(30) 688 #define ARMV7_INCLUDE_HYP BIT(27) 689 690 /* 691 * Secure debug enable reg 692 */ 693 #define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */ 694 695 static inline u32 armv7_pmnc_read(void) 696 { 697 u32 val; 698 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); 699 return val; 700 } 701 702 static inline void armv7_pmnc_write(u32 val) 703 { 704 val &= ARMV7_PMNC_MASK; 705 isb(); 706 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); 707 } 708 709 static inline int armv7_pmnc_has_overflowed(u32 pmnc) 710 { 711 return pmnc & ARMV7_OVERFLOWED_MASK; 712 } 713 714 static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx) 715 { 716 return test_bit(idx, cpu_pmu->cntr_mask); 717 } 718 719 static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx) 720 { 721 return pmnc & BIT(idx); 722 } 723 724 static inline void armv7_pmnc_select_counter(int idx) 725 { 726 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx)); 727 isb(); 728 } 729 730 static inline u64 armv7pmu_read_counter(struct perf_event *event) 731 { 732 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 733 struct hw_perf_event *hwc = &event->hw; 734 int idx = hwc->idx; 735 u32 value = 0; 736 737 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 738 pr_err("CPU%u reading wrong counter %d\n", 739 smp_processor_id(), idx); 740 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { 741 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); 742 } else { 743 armv7_pmnc_select_counter(idx); 744 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); 745 } 746 747 return value; 748 } 749 750 static inline void armv7pmu_write_counter(struct perf_event *event, u64 value) 751 { 752 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 753 struct hw_perf_event *hwc = &event->hw; 754 int idx = hwc->idx; 755 756 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 757 pr_err("CPU%u writing wrong counter %d\n", 758 smp_processor_id(), idx); 759 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { 760 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value)); 761 } else { 762 armv7_pmnc_select_counter(idx); 763 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value)); 764 } 765 } 766 767 static inline void armv7_pmnc_write_evtsel(int idx, u32 val) 768 { 769 armv7_pmnc_select_counter(idx); 770 val &= ARMV7_EVTYPE_MASK; 771 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); 772 } 773 774 static inline void armv7_pmnc_enable_counter(int idx) 775 { 776 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(idx))); 777 } 778 779 static inline void armv7_pmnc_disable_counter(int idx) 780 { 781 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(idx))); 782 } 783 784 static inline void armv7_pmnc_enable_intens(int idx) 785 { 786 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(idx))); 787 } 788 789 static inline void armv7_pmnc_disable_intens(int idx) 790 { 791 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(idx))); 792 isb(); 793 /* Clear the overflow flag in case an interrupt is pending. */ 794 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(idx))); 795 isb(); 796 } 797 798 static inline u32 armv7_pmnc_getreset_flags(void) 799 { 800 u32 val; 801 802 /* Read */ 803 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); 804 805 /* Write to clear flags */ 806 val &= ARMV7_FLAG_MASK; 807 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); 808 809 return val; 810 } 811 812 #ifdef DEBUG 813 static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu) 814 { 815 u32 val; 816 unsigned int cnt; 817 818 pr_info("PMNC registers dump:\n"); 819 820 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); 821 pr_info("PMNC =0x%08x\n", val); 822 823 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); 824 pr_info("CNTENS=0x%08x\n", val); 825 826 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); 827 pr_info("INTENS=0x%08x\n", val); 828 829 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); 830 pr_info("FLAGS =0x%08x\n", val); 831 832 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); 833 pr_info("SELECT=0x%08x\n", val); 834 835 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); 836 pr_info("CCNT =0x%08x\n", val); 837 838 for_each_set_bit(cnt, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 839 armv7_pmnc_select_counter(cnt); 840 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); 841 pr_info("CNT[%d] count =0x%08x\n", cnt, val); 842 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); 843 pr_info("CNT[%d] evtsel=0x%08x\n", cnt, val); 844 } 845 } 846 #endif 847 848 static void armv7pmu_enable_event(struct perf_event *event) 849 { 850 struct hw_perf_event *hwc = &event->hw; 851 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 852 int idx = hwc->idx; 853 854 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 855 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", 856 smp_processor_id(), idx); 857 return; 858 } 859 860 /* 861 * Set event (if destined for PMNx counters) 862 * We only need to set the event for the cycle counter if we 863 * have the ability to perform event filtering. 864 */ 865 if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER) 866 armv7_pmnc_write_evtsel(idx, hwc->config_base); 867 868 armv7_pmnc_enable_intens(idx); 869 armv7_pmnc_enable_counter(idx); 870 } 871 872 static void armv7pmu_disable_event(struct perf_event *event) 873 { 874 struct hw_perf_event *hwc = &event->hw; 875 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 876 int idx = hwc->idx; 877 878 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 879 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", 880 smp_processor_id(), idx); 881 return; 882 } 883 884 armv7_pmnc_disable_counter(idx); 885 armv7_pmnc_disable_intens(idx); 886 } 887 888 static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu) 889 { 890 u32 pmnc; 891 struct perf_sample_data data; 892 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 893 struct pt_regs *regs; 894 int idx; 895 896 /* 897 * Get and reset the IRQ flags 898 */ 899 pmnc = armv7_pmnc_getreset_flags(); 900 901 /* 902 * Did an overflow occur? 903 */ 904 if (!armv7_pmnc_has_overflowed(pmnc)) 905 return IRQ_NONE; 906 907 /* 908 * Handle the counter(s) overflow(s) 909 */ 910 regs = get_irq_regs(); 911 912 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { 913 struct perf_event *event = cpuc->events[idx]; 914 struct hw_perf_event *hwc; 915 916 /* Ignore if we don't have an event. */ 917 if (!event) 918 continue; 919 920 /* 921 * We have a single interrupt for all counters. Check that 922 * each counter has overflowed before we process it. 923 */ 924 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) 925 continue; 926 927 hwc = &event->hw; 928 armpmu_event_update(event); 929 perf_sample_data_init(&data, 0, hwc->last_period); 930 if (!armpmu_event_set_period(event)) 931 continue; 932 933 if (perf_event_overflow(event, &data, regs)) 934 cpu_pmu->disable(event); 935 } 936 937 /* 938 * Handle the pending perf events. 939 * 940 * Note: this call *must* be run with interrupts disabled. For 941 * platforms that can have the PMU interrupts raised as an NMI, this 942 * will not work. 943 */ 944 irq_work_run(); 945 946 return IRQ_HANDLED; 947 } 948 949 static void armv7pmu_start(struct arm_pmu *cpu_pmu) 950 { 951 /* Enable all counters */ 952 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); 953 } 954 955 static void armv7pmu_stop(struct arm_pmu *cpu_pmu) 956 { 957 /* Disable all counters */ 958 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); 959 } 960 961 static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, 962 struct perf_event *event) 963 { 964 int idx; 965 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 966 struct hw_perf_event *hwc = &event->hw; 967 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; 968 969 /* Always place a cycle counter into the cycle counter. */ 970 if (evtype == ARMV7_PERFCTR_CPU_CYCLES) { 971 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask)) 972 return -EAGAIN; 973 974 return ARMV7_IDX_CYCLE_COUNTER; 975 } 976 977 /* 978 * For anything other than a cycle counter, try and use 979 * the events counters 980 */ 981 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 982 if (!test_and_set_bit(idx, cpuc->used_mask)) 983 return idx; 984 } 985 986 /* The counters are all in use. */ 987 return -EAGAIN; 988 } 989 990 static void armv7pmu_clear_event_idx(struct pmu_hw_events *cpuc, 991 struct perf_event *event) 992 { 993 clear_bit(event->hw.idx, cpuc->used_mask); 994 } 995 996 /* 997 * Add an event filter to a given event. This will only work for PMUv2 PMUs. 998 */ 999 static int armv7pmu_set_event_filter(struct hw_perf_event *event, 1000 struct perf_event_attr *attr) 1001 { 1002 unsigned long config_base = 0; 1003 1004 if (attr->exclude_idle) { 1005 pr_debug("ARM performance counters do not support mode exclusion\n"); 1006 return -EOPNOTSUPP; 1007 } 1008 if (attr->exclude_user) 1009 config_base |= ARMV7_EXCLUDE_USER; 1010 if (attr->exclude_kernel) 1011 config_base |= ARMV7_EXCLUDE_PL1; 1012 if (!attr->exclude_hv) 1013 config_base |= ARMV7_INCLUDE_HYP; 1014 1015 /* 1016 * Install the filter into config_base as this is used to 1017 * construct the event type. 1018 */ 1019 event->config_base = config_base; 1020 1021 return 0; 1022 } 1023 1024 static void armv7pmu_reset(void *info) 1025 { 1026 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 1027 u32 idx, val; 1028 1029 if (cpu_pmu->secure_access) { 1030 asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); 1031 val |= ARMV7_SDER_SUNIDEN; 1032 asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); 1033 } 1034 1035 /* The counter and interrupt enable registers are unknown at reset. */ 1036 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { 1037 armv7_pmnc_disable_counter(idx); 1038 armv7_pmnc_disable_intens(idx); 1039 } 1040 1041 /* Initialize & Reset PMNC: C and P bits */ 1042 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); 1043 } 1044 1045 static int armv7_a8_map_event(struct perf_event *event) 1046 { 1047 return armpmu_map_event(event, &armv7_a8_perf_map, 1048 &armv7_a8_perf_cache_map, 0xFF); 1049 } 1050 1051 static int armv7_a9_map_event(struct perf_event *event) 1052 { 1053 return armpmu_map_event(event, &armv7_a9_perf_map, 1054 &armv7_a9_perf_cache_map, 0xFF); 1055 } 1056 1057 static int armv7_a5_map_event(struct perf_event *event) 1058 { 1059 return armpmu_map_event(event, &armv7_a5_perf_map, 1060 &armv7_a5_perf_cache_map, 0xFF); 1061 } 1062 1063 static int armv7_a15_map_event(struct perf_event *event) 1064 { 1065 return armpmu_map_event(event, &armv7_a15_perf_map, 1066 &armv7_a15_perf_cache_map, 0xFF); 1067 } 1068 1069 static int armv7_a7_map_event(struct perf_event *event) 1070 { 1071 return armpmu_map_event(event, &armv7_a7_perf_map, 1072 &armv7_a7_perf_cache_map, 0xFF); 1073 } 1074 1075 static int armv7_a12_map_event(struct perf_event *event) 1076 { 1077 return armpmu_map_event(event, &armv7_a12_perf_map, 1078 &armv7_a12_perf_cache_map, 0xFF); 1079 } 1080 1081 static int krait_map_event(struct perf_event *event) 1082 { 1083 return armpmu_map_event(event, &krait_perf_map, 1084 &krait_perf_cache_map, 0xFFFFF); 1085 } 1086 1087 static int krait_map_event_no_branch(struct perf_event *event) 1088 { 1089 return armpmu_map_event(event, &krait_perf_map_no_branch, 1090 &krait_perf_cache_map, 0xFFFFF); 1091 } 1092 1093 static int scorpion_map_event(struct perf_event *event) 1094 { 1095 return armpmu_map_event(event, &scorpion_perf_map, 1096 &scorpion_perf_cache_map, 0xFFFFF); 1097 } 1098 1099 static void armv7pmu_init(struct arm_pmu *cpu_pmu) 1100 { 1101 cpu_pmu->handle_irq = armv7pmu_handle_irq; 1102 cpu_pmu->enable = armv7pmu_enable_event; 1103 cpu_pmu->disable = armv7pmu_disable_event; 1104 cpu_pmu->read_counter = armv7pmu_read_counter; 1105 cpu_pmu->write_counter = armv7pmu_write_counter; 1106 cpu_pmu->get_event_idx = armv7pmu_get_event_idx; 1107 cpu_pmu->clear_event_idx = armv7pmu_clear_event_idx; 1108 cpu_pmu->start = armv7pmu_start; 1109 cpu_pmu->stop = armv7pmu_stop; 1110 cpu_pmu->reset = armv7pmu_reset; 1111 }; 1112 1113 static void armv7_read_num_pmnc_events(void *info) 1114 { 1115 int nb_cnt; 1116 struct arm_pmu *cpu_pmu = info; 1117 1118 /* Read the nb of CNTx counters supported from PMNC */ 1119 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; 1120 bitmap_set(cpu_pmu->cntr_mask, 0, nb_cnt); 1121 1122 /* Add the CPU cycles counter */ 1123 set_bit(ARMV7_IDX_CYCLE_COUNTER, cpu_pmu->cntr_mask); 1124 } 1125 1126 static int armv7_probe_num_events(struct arm_pmu *arm_pmu) 1127 { 1128 return smp_call_function_any(&arm_pmu->supported_cpus, 1129 armv7_read_num_pmnc_events, 1130 arm_pmu, 1); 1131 } 1132 1133 static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) 1134 { 1135 armv7pmu_init(cpu_pmu); 1136 cpu_pmu->name = "armv7_cortex_a8"; 1137 cpu_pmu->map_event = armv7_a8_map_event; 1138 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1139 &armv7_pmuv1_events_attr_group; 1140 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1141 &armv7_pmu_format_attr_group; 1142 return armv7_probe_num_events(cpu_pmu); 1143 } 1144 1145 static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) 1146 { 1147 armv7pmu_init(cpu_pmu); 1148 cpu_pmu->name = "armv7_cortex_a9"; 1149 cpu_pmu->map_event = armv7_a9_map_event; 1150 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1151 &armv7_pmuv1_events_attr_group; 1152 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1153 &armv7_pmu_format_attr_group; 1154 return armv7_probe_num_events(cpu_pmu); 1155 } 1156 1157 static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) 1158 { 1159 armv7pmu_init(cpu_pmu); 1160 cpu_pmu->name = "armv7_cortex_a5"; 1161 cpu_pmu->map_event = armv7_a5_map_event; 1162 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1163 &armv7_pmuv1_events_attr_group; 1164 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1165 &armv7_pmu_format_attr_group; 1166 return armv7_probe_num_events(cpu_pmu); 1167 } 1168 1169 static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) 1170 { 1171 armv7pmu_init(cpu_pmu); 1172 cpu_pmu->name = "armv7_cortex_a15"; 1173 cpu_pmu->map_event = armv7_a15_map_event; 1174 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1175 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1176 &armv7_pmuv2_events_attr_group; 1177 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1178 &armv7_pmu_format_attr_group; 1179 return armv7_probe_num_events(cpu_pmu); 1180 } 1181 1182 static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) 1183 { 1184 armv7pmu_init(cpu_pmu); 1185 cpu_pmu->name = "armv7_cortex_a7"; 1186 cpu_pmu->map_event = armv7_a7_map_event; 1187 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1188 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1189 &armv7_pmuv2_events_attr_group; 1190 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1191 &armv7_pmu_format_attr_group; 1192 return armv7_probe_num_events(cpu_pmu); 1193 } 1194 1195 static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) 1196 { 1197 armv7pmu_init(cpu_pmu); 1198 cpu_pmu->name = "armv7_cortex_a12"; 1199 cpu_pmu->map_event = armv7_a12_map_event; 1200 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1201 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1202 &armv7_pmuv2_events_attr_group; 1203 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1204 &armv7_pmu_format_attr_group; 1205 return armv7_probe_num_events(cpu_pmu); 1206 } 1207 1208 static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) 1209 { 1210 int ret = armv7_a12_pmu_init(cpu_pmu); 1211 cpu_pmu->name = "armv7_cortex_a17"; 1212 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1213 &armv7_pmuv2_events_attr_group; 1214 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1215 &armv7_pmu_format_attr_group; 1216 return ret; 1217 } 1218 1219 /* 1220 * Krait Performance Monitor Region Event Selection Register (PMRESRn) 1221 * 1222 * 31 30 24 16 8 0 1223 * +--------------------------------+ 1224 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0 1225 * +--------------------------------+ 1226 * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1 1227 * +--------------------------------+ 1228 * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2 1229 * +--------------------------------+ 1230 * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ? 1231 * +--------------------------------+ 1232 * EN | G=3 | G=2 | G=1 | G=0 1233 * 1234 * Event Encoding: 1235 * 1236 * hwc->config_base = 0xNRCCG 1237 * 1238 * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR) 1239 * R = region register 1240 * CC = class of events the group G is choosing from 1241 * G = group or particular event 1242 * 1243 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2 1244 * 1245 * A region (R) corresponds to a piece of the CPU (execution unit, instruction 1246 * unit, etc.) while the event code (CC) corresponds to a particular class of 1247 * events (interrupts for example). An event code is broken down into 1248 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for 1249 * example). 1250 */ 1251 1252 #define KRAIT_EVENT (1 << 16) 1253 #define VENUM_EVENT (2 << 16) 1254 #define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT) 1255 #define PMRESRn_EN BIT(31) 1256 1257 #define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */ 1258 #define EVENT_GROUP(event) ((event) & 0xf) /* G */ 1259 #define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */ 1260 #define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */ 1261 #define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */ 1262 1263 static u32 krait_read_pmresrn(int n) 1264 { 1265 u32 val; 1266 1267 switch (n) { 1268 case 0: 1269 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); 1270 break; 1271 case 1: 1272 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); 1273 break; 1274 case 2: 1275 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); 1276 break; 1277 default: 1278 BUG(); /* Should be validated in krait_pmu_get_event_idx() */ 1279 } 1280 1281 return val; 1282 } 1283 1284 static void krait_write_pmresrn(int n, u32 val) 1285 { 1286 switch (n) { 1287 case 0: 1288 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); 1289 break; 1290 case 1: 1291 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); 1292 break; 1293 case 2: 1294 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); 1295 break; 1296 default: 1297 BUG(); /* Should be validated in krait_pmu_get_event_idx() */ 1298 } 1299 } 1300 1301 static u32 venum_read_pmresr(void) 1302 { 1303 u32 val; 1304 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); 1305 return val; 1306 } 1307 1308 static void venum_write_pmresr(u32 val) 1309 { 1310 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); 1311 } 1312 1313 static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val) 1314 { 1315 u32 venum_new_val; 1316 u32 fp_new_val; 1317 1318 BUG_ON(preemptible()); 1319 /* CPACR Enable CP10 and CP11 access */ 1320 *venum_orig_val = get_copro_access(); 1321 venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11); 1322 set_copro_access(venum_new_val); 1323 1324 /* Enable FPEXC */ 1325 *fp_orig_val = fmrx(FPEXC); 1326 fp_new_val = *fp_orig_val | FPEXC_EN; 1327 fmxr(FPEXC, fp_new_val); 1328 } 1329 1330 static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val) 1331 { 1332 BUG_ON(preemptible()); 1333 /* Restore FPEXC */ 1334 fmxr(FPEXC, fp_orig_val); 1335 isb(); 1336 /* Restore CPACR */ 1337 set_copro_access(venum_orig_val); 1338 } 1339 1340 static u32 krait_get_pmresrn_event(unsigned int region) 1341 { 1342 static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0, 1343 KRAIT_PMRESR1_GROUP0, 1344 KRAIT_PMRESR2_GROUP0 }; 1345 return pmresrn_table[region]; 1346 } 1347 1348 static void krait_evt_setup(int idx, u32 config_base) 1349 { 1350 u32 val; 1351 u32 mask; 1352 u32 vval, fval; 1353 unsigned int region = EVENT_REGION(config_base); 1354 unsigned int group = EVENT_GROUP(config_base); 1355 unsigned int code = EVENT_CODE(config_base); 1356 unsigned int group_shift; 1357 bool venum_event = EVENT_VENUM(config_base); 1358 1359 group_shift = group * 8; 1360 mask = 0xff << group_shift; 1361 1362 /* Configure evtsel for the region and group */ 1363 if (venum_event) 1364 val = KRAIT_VPMRESR0_GROUP0; 1365 else 1366 val = krait_get_pmresrn_event(region); 1367 val += group; 1368 /* Mix in mode-exclusion bits */ 1369 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); 1370 armv7_pmnc_write_evtsel(idx, val); 1371 1372 if (venum_event) { 1373 venum_pre_pmresr(&vval, &fval); 1374 val = venum_read_pmresr(); 1375 val &= ~mask; 1376 val |= code << group_shift; 1377 val |= PMRESRn_EN; 1378 venum_write_pmresr(val); 1379 venum_post_pmresr(vval, fval); 1380 } else { 1381 val = krait_read_pmresrn(region); 1382 val &= ~mask; 1383 val |= code << group_shift; 1384 val |= PMRESRn_EN; 1385 krait_write_pmresrn(region, val); 1386 } 1387 } 1388 1389 static u32 clear_pmresrn_group(u32 val, int group) 1390 { 1391 u32 mask; 1392 int group_shift; 1393 1394 group_shift = group * 8; 1395 mask = 0xff << group_shift; 1396 val &= ~mask; 1397 1398 /* Don't clear enable bit if entire region isn't disabled */ 1399 if (val & ~PMRESRn_EN) 1400 return val |= PMRESRn_EN; 1401 1402 return 0; 1403 } 1404 1405 static void krait_clearpmu(u32 config_base) 1406 { 1407 u32 val; 1408 u32 vval, fval; 1409 unsigned int region = EVENT_REGION(config_base); 1410 unsigned int group = EVENT_GROUP(config_base); 1411 bool venum_event = EVENT_VENUM(config_base); 1412 1413 if (venum_event) { 1414 venum_pre_pmresr(&vval, &fval); 1415 val = venum_read_pmresr(); 1416 val = clear_pmresrn_group(val, group); 1417 venum_write_pmresr(val); 1418 venum_post_pmresr(vval, fval); 1419 } else { 1420 val = krait_read_pmresrn(region); 1421 val = clear_pmresrn_group(val, group); 1422 krait_write_pmresrn(region, val); 1423 } 1424 } 1425 1426 static void krait_pmu_disable_event(struct perf_event *event) 1427 { 1428 struct hw_perf_event *hwc = &event->hw; 1429 int idx = hwc->idx; 1430 1431 /* Disable counter and interrupt */ 1432 1433 /* Disable counter */ 1434 armv7_pmnc_disable_counter(idx); 1435 1436 /* 1437 * Clear pmresr code (if destined for PMNx counters) 1438 */ 1439 if (hwc->config_base & KRAIT_EVENT_MASK) 1440 krait_clearpmu(hwc->config_base); 1441 1442 /* Disable interrupt for this counter */ 1443 armv7_pmnc_disable_intens(idx); 1444 } 1445 1446 static void krait_pmu_enable_event(struct perf_event *event) 1447 { 1448 struct hw_perf_event *hwc = &event->hw; 1449 int idx = hwc->idx; 1450 1451 /* 1452 * Set event (if destined for PMNx counters) 1453 * We set the event for the cycle counter because we 1454 * have the ability to perform event filtering. 1455 */ 1456 if (hwc->config_base & KRAIT_EVENT_MASK) 1457 krait_evt_setup(idx, hwc->config_base); 1458 else 1459 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1460 1461 armv7_pmnc_enable_intens(idx); 1462 armv7_pmnc_enable_counter(idx); 1463 } 1464 1465 static void krait_pmu_reset(void *info) 1466 { 1467 u32 vval, fval; 1468 struct arm_pmu *cpu_pmu = info; 1469 u32 idx; 1470 1471 armv7pmu_reset(info); 1472 1473 /* Clear all pmresrs */ 1474 krait_write_pmresrn(0, 0); 1475 krait_write_pmresrn(1, 0); 1476 krait_write_pmresrn(2, 0); 1477 1478 venum_pre_pmresr(&vval, &fval); 1479 venum_write_pmresr(0); 1480 venum_post_pmresr(vval, fval); 1481 1482 /* Reset PMxEVNCTCR to sane default */ 1483 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 1484 armv7_pmnc_select_counter(idx); 1485 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1486 } 1487 1488 } 1489 1490 static int krait_event_to_bit(struct perf_event *event, unsigned int region, 1491 unsigned int group) 1492 { 1493 int bit; 1494 struct hw_perf_event *hwc = &event->hw; 1495 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1496 1497 if (hwc->config_base & VENUM_EVENT) 1498 bit = KRAIT_VPMRESR0_GROUP0; 1499 else 1500 bit = krait_get_pmresrn_event(region); 1501 bit -= krait_get_pmresrn_event(0); 1502 bit += group; 1503 /* 1504 * Lower bits are reserved for use by the counters (see 1505 * armv7pmu_get_event_idx() for more info) 1506 */ 1507 bit += bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); 1508 1509 return bit; 1510 } 1511 1512 /* 1513 * We check for column exclusion constraints here. 1514 * Two events cant use the same group within a pmresr register. 1515 */ 1516 static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc, 1517 struct perf_event *event) 1518 { 1519 int idx; 1520 int bit = -1; 1521 struct hw_perf_event *hwc = &event->hw; 1522 unsigned int region = EVENT_REGION(hwc->config_base); 1523 unsigned int code = EVENT_CODE(hwc->config_base); 1524 unsigned int group = EVENT_GROUP(hwc->config_base); 1525 bool venum_event = EVENT_VENUM(hwc->config_base); 1526 bool krait_event = EVENT_CPU(hwc->config_base); 1527 1528 if (venum_event || krait_event) { 1529 /* Ignore invalid events */ 1530 if (group > 3 || region > 2) 1531 return -EINVAL; 1532 if (venum_event && (code & 0xe0)) 1533 return -EINVAL; 1534 1535 bit = krait_event_to_bit(event, region, group); 1536 if (test_and_set_bit(bit, cpuc->used_mask)) 1537 return -EAGAIN; 1538 } 1539 1540 idx = armv7pmu_get_event_idx(cpuc, event); 1541 if (idx < 0 && bit >= 0) 1542 clear_bit(bit, cpuc->used_mask); 1543 1544 return idx; 1545 } 1546 1547 static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1548 struct perf_event *event) 1549 { 1550 int bit; 1551 struct hw_perf_event *hwc = &event->hw; 1552 unsigned int region = EVENT_REGION(hwc->config_base); 1553 unsigned int group = EVENT_GROUP(hwc->config_base); 1554 bool venum_event = EVENT_VENUM(hwc->config_base); 1555 bool krait_event = EVENT_CPU(hwc->config_base); 1556 1557 armv7pmu_clear_event_idx(cpuc, event); 1558 if (venum_event || krait_event) { 1559 bit = krait_event_to_bit(event, region, group); 1560 clear_bit(bit, cpuc->used_mask); 1561 } 1562 } 1563 1564 static int krait_pmu_init(struct arm_pmu *cpu_pmu) 1565 { 1566 armv7pmu_init(cpu_pmu); 1567 cpu_pmu->name = "armv7_krait"; 1568 /* Some early versions of Krait don't support PC write events */ 1569 if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, 1570 "qcom,no-pc-write")) 1571 cpu_pmu->map_event = krait_map_event_no_branch; 1572 else 1573 cpu_pmu->map_event = krait_map_event; 1574 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1575 cpu_pmu->reset = krait_pmu_reset; 1576 cpu_pmu->enable = krait_pmu_enable_event; 1577 cpu_pmu->disable = krait_pmu_disable_event; 1578 cpu_pmu->get_event_idx = krait_pmu_get_event_idx; 1579 cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; 1580 return armv7_probe_num_events(cpu_pmu); 1581 } 1582 1583 /* 1584 * Scorpion Local Performance Monitor Register (LPMn) 1585 * 1586 * 31 30 24 16 8 0 1587 * +--------------------------------+ 1588 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0 1589 * +--------------------------------+ 1590 * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1 1591 * +--------------------------------+ 1592 * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2 1593 * +--------------------------------+ 1594 * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3 1595 * +--------------------------------+ 1596 * VLPM | EN | CC | CC | CC | CC | N = 2, R = ? 1597 * +--------------------------------+ 1598 * EN | G=3 | G=2 | G=1 | G=0 1599 * 1600 * 1601 * Event Encoding: 1602 * 1603 * hwc->config_base = 0xNRCCG 1604 * 1605 * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM) 1606 * R = region register 1607 * CC = class of events the group G is choosing from 1608 * G = group or particular event 1609 * 1610 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2 1611 * 1612 * A region (R) corresponds to a piece of the CPU (execution unit, instruction 1613 * unit, etc.) while the event code (CC) corresponds to a particular class of 1614 * events (interrupts for example). An event code is broken down into 1615 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for 1616 * example). 1617 */ 1618 1619 static u32 scorpion_read_pmresrn(int n) 1620 { 1621 u32 val; 1622 1623 switch (n) { 1624 case 0: 1625 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); 1626 break; 1627 case 1: 1628 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); 1629 break; 1630 case 2: 1631 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); 1632 break; 1633 case 3: 1634 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); 1635 break; 1636 default: 1637 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ 1638 } 1639 1640 return val; 1641 } 1642 1643 static void scorpion_write_pmresrn(int n, u32 val) 1644 { 1645 switch (n) { 1646 case 0: 1647 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); 1648 break; 1649 case 1: 1650 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); 1651 break; 1652 case 2: 1653 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); 1654 break; 1655 case 3: 1656 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); 1657 break; 1658 default: 1659 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ 1660 } 1661 } 1662 1663 static u32 scorpion_get_pmresrn_event(unsigned int region) 1664 { 1665 static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0, 1666 SCORPION_LPM1_GROUP0, 1667 SCORPION_LPM2_GROUP0, 1668 SCORPION_L2LPM_GROUP0 }; 1669 return pmresrn_table[region]; 1670 } 1671 1672 static void scorpion_evt_setup(int idx, u32 config_base) 1673 { 1674 u32 val; 1675 u32 mask; 1676 u32 vval, fval; 1677 unsigned int region = EVENT_REGION(config_base); 1678 unsigned int group = EVENT_GROUP(config_base); 1679 unsigned int code = EVENT_CODE(config_base); 1680 unsigned int group_shift; 1681 bool venum_event = EVENT_VENUM(config_base); 1682 1683 group_shift = group * 8; 1684 mask = 0xff << group_shift; 1685 1686 /* Configure evtsel for the region and group */ 1687 if (venum_event) 1688 val = SCORPION_VLPM_GROUP0; 1689 else 1690 val = scorpion_get_pmresrn_event(region); 1691 val += group; 1692 /* Mix in mode-exclusion bits */ 1693 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); 1694 armv7_pmnc_write_evtsel(idx, val); 1695 1696 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1697 1698 if (venum_event) { 1699 venum_pre_pmresr(&vval, &fval); 1700 val = venum_read_pmresr(); 1701 val &= ~mask; 1702 val |= code << group_shift; 1703 val |= PMRESRn_EN; 1704 venum_write_pmresr(val); 1705 venum_post_pmresr(vval, fval); 1706 } else { 1707 val = scorpion_read_pmresrn(region); 1708 val &= ~mask; 1709 val |= code << group_shift; 1710 val |= PMRESRn_EN; 1711 scorpion_write_pmresrn(region, val); 1712 } 1713 } 1714 1715 static void scorpion_clearpmu(u32 config_base) 1716 { 1717 u32 val; 1718 u32 vval, fval; 1719 unsigned int region = EVENT_REGION(config_base); 1720 unsigned int group = EVENT_GROUP(config_base); 1721 bool venum_event = EVENT_VENUM(config_base); 1722 1723 if (venum_event) { 1724 venum_pre_pmresr(&vval, &fval); 1725 val = venum_read_pmresr(); 1726 val = clear_pmresrn_group(val, group); 1727 venum_write_pmresr(val); 1728 venum_post_pmresr(vval, fval); 1729 } else { 1730 val = scorpion_read_pmresrn(region); 1731 val = clear_pmresrn_group(val, group); 1732 scorpion_write_pmresrn(region, val); 1733 } 1734 } 1735 1736 static void scorpion_pmu_disable_event(struct perf_event *event) 1737 { 1738 struct hw_perf_event *hwc = &event->hw; 1739 int idx = hwc->idx; 1740 1741 /* Disable counter and interrupt */ 1742 1743 /* Disable counter */ 1744 armv7_pmnc_disable_counter(idx); 1745 1746 /* 1747 * Clear pmresr code (if destined for PMNx counters) 1748 */ 1749 if (hwc->config_base & KRAIT_EVENT_MASK) 1750 scorpion_clearpmu(hwc->config_base); 1751 1752 /* Disable interrupt for this counter */ 1753 armv7_pmnc_disable_intens(idx); 1754 } 1755 1756 static void scorpion_pmu_enable_event(struct perf_event *event) 1757 { 1758 struct hw_perf_event *hwc = &event->hw; 1759 int idx = hwc->idx; 1760 1761 /* 1762 * Set event (if destined for PMNx counters) 1763 * We don't set the event for the cycle counter because we 1764 * don't have the ability to perform event filtering. 1765 */ 1766 if (hwc->config_base & KRAIT_EVENT_MASK) 1767 scorpion_evt_setup(idx, hwc->config_base); 1768 else if (idx != ARMV7_IDX_CYCLE_COUNTER) 1769 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1770 1771 armv7_pmnc_enable_intens(idx); 1772 armv7_pmnc_enable_counter(idx); 1773 } 1774 1775 static void scorpion_pmu_reset(void *info) 1776 { 1777 u32 vval, fval; 1778 struct arm_pmu *cpu_pmu = info; 1779 u32 idx; 1780 1781 armv7pmu_reset(info); 1782 1783 /* Clear all pmresrs */ 1784 scorpion_write_pmresrn(0, 0); 1785 scorpion_write_pmresrn(1, 0); 1786 scorpion_write_pmresrn(2, 0); 1787 scorpion_write_pmresrn(3, 0); 1788 1789 venum_pre_pmresr(&vval, &fval); 1790 venum_write_pmresr(0); 1791 venum_post_pmresr(vval, fval); 1792 1793 /* Reset PMxEVNCTCR to sane default */ 1794 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 1795 armv7_pmnc_select_counter(idx); 1796 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1797 } 1798 } 1799 1800 static int scorpion_event_to_bit(struct perf_event *event, unsigned int region, 1801 unsigned int group) 1802 { 1803 int bit; 1804 struct hw_perf_event *hwc = &event->hw; 1805 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1806 1807 if (hwc->config_base & VENUM_EVENT) 1808 bit = SCORPION_VLPM_GROUP0; 1809 else 1810 bit = scorpion_get_pmresrn_event(region); 1811 bit -= scorpion_get_pmresrn_event(0); 1812 bit += group; 1813 /* 1814 * Lower bits are reserved for use by the counters (see 1815 * armv7pmu_get_event_idx() for more info) 1816 */ 1817 bit += bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); 1818 1819 return bit; 1820 } 1821 1822 /* 1823 * We check for column exclusion constraints here. 1824 * Two events cant use the same group within a pmresr register. 1825 */ 1826 static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc, 1827 struct perf_event *event) 1828 { 1829 int idx; 1830 int bit = -1; 1831 struct hw_perf_event *hwc = &event->hw; 1832 unsigned int region = EVENT_REGION(hwc->config_base); 1833 unsigned int group = EVENT_GROUP(hwc->config_base); 1834 bool venum_event = EVENT_VENUM(hwc->config_base); 1835 bool scorpion_event = EVENT_CPU(hwc->config_base); 1836 1837 if (venum_event || scorpion_event) { 1838 /* Ignore invalid events */ 1839 if (group > 3 || region > 3) 1840 return -EINVAL; 1841 1842 bit = scorpion_event_to_bit(event, region, group); 1843 if (test_and_set_bit(bit, cpuc->used_mask)) 1844 return -EAGAIN; 1845 } 1846 1847 idx = armv7pmu_get_event_idx(cpuc, event); 1848 if (idx < 0 && bit >= 0) 1849 clear_bit(bit, cpuc->used_mask); 1850 1851 return idx; 1852 } 1853 1854 static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1855 struct perf_event *event) 1856 { 1857 int bit; 1858 struct hw_perf_event *hwc = &event->hw; 1859 unsigned int region = EVENT_REGION(hwc->config_base); 1860 unsigned int group = EVENT_GROUP(hwc->config_base); 1861 bool venum_event = EVENT_VENUM(hwc->config_base); 1862 bool scorpion_event = EVENT_CPU(hwc->config_base); 1863 1864 armv7pmu_clear_event_idx(cpuc, event); 1865 if (venum_event || scorpion_event) { 1866 bit = scorpion_event_to_bit(event, region, group); 1867 clear_bit(bit, cpuc->used_mask); 1868 } 1869 } 1870 1871 static int scorpion_pmu_init(struct arm_pmu *cpu_pmu) 1872 { 1873 armv7pmu_init(cpu_pmu); 1874 cpu_pmu->name = "armv7_scorpion"; 1875 cpu_pmu->map_event = scorpion_map_event; 1876 cpu_pmu->reset = scorpion_pmu_reset; 1877 cpu_pmu->enable = scorpion_pmu_enable_event; 1878 cpu_pmu->disable = scorpion_pmu_disable_event; 1879 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; 1880 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; 1881 return armv7_probe_num_events(cpu_pmu); 1882 } 1883 1884 static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) 1885 { 1886 armv7pmu_init(cpu_pmu); 1887 cpu_pmu->name = "armv7_scorpion_mp"; 1888 cpu_pmu->map_event = scorpion_map_event; 1889 cpu_pmu->reset = scorpion_pmu_reset; 1890 cpu_pmu->enable = scorpion_pmu_enable_event; 1891 cpu_pmu->disable = scorpion_pmu_disable_event; 1892 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; 1893 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; 1894 return armv7_probe_num_events(cpu_pmu); 1895 } 1896 1897 static const struct of_device_id armv7_pmu_of_device_ids[] = { 1898 {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init}, 1899 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, 1900 {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, 1901 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, 1902 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, 1903 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, 1904 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, 1905 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, 1906 {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, 1907 {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, 1908 {}, 1909 }; 1910 1911 static int armv7_pmu_device_probe(struct platform_device *pdev) 1912 { 1913 return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, NULL); 1914 } 1915 1916 static struct platform_driver armv7_pmu_driver = { 1917 .driver = { 1918 .name = "armv7-pmu", 1919 .of_match_table = armv7_pmu_of_device_ids, 1920 .suppress_bind_attrs = true, 1921 }, 1922 .probe = armv7_pmu_device_probe, 1923 }; 1924 1925 builtin_platform_driver(armv7_pmu_driver); 1926