1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Perf support for the Statistical Profiling Extension, introduced as 4 * part of ARMv8.2. 5 * 6 * Copyright (C) 2016 ARM Limited 7 * 8 * Author: Will Deacon <will.deacon@arm.com> 9 */ 10 11 #define PMUNAME "arm_spe" 12 #define DRVNAME PMUNAME "_pmu" 13 #define pr_fmt(fmt) DRVNAME ": " fmt 14 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/capability.h> 18 #include <linux/cpuhotplug.h> 19 #include <linux/cpumask.h> 20 #include <linux/device.h> 21 #include <linux/errno.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/module.h> 27 #include <linux/of_address.h> 28 #include <linux/of_device.h> 29 #include <linux/perf_event.h> 30 #include <linux/perf/arm_pmu.h> 31 #include <linux/platform_device.h> 32 #include <linux/printk.h> 33 #include <linux/slab.h> 34 #include <linux/smp.h> 35 #include <linux/vmalloc.h> 36 37 #include <asm/barrier.h> 38 #include <asm/cpufeature.h> 39 #include <asm/mmu.h> 40 #include <asm/sysreg.h> 41 42 #define ARM_SPE_BUF_PAD_BYTE 0 43 44 struct arm_spe_pmu_buf { 45 int nr_pages; 46 bool snapshot; 47 void *base; 48 }; 49 50 struct arm_spe_pmu { 51 struct pmu pmu; 52 struct platform_device *pdev; 53 cpumask_t supported_cpus; 54 struct hlist_node hotplug_node; 55 56 int irq; /* PPI */ 57 u16 pmsver; 58 u16 min_period; 59 u16 counter_sz; 60 61 #define SPE_PMU_FEAT_FILT_EVT (1UL << 0) 62 #define SPE_PMU_FEAT_FILT_TYP (1UL << 1) 63 #define SPE_PMU_FEAT_FILT_LAT (1UL << 2) 64 #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) 65 #define SPE_PMU_FEAT_LDS (1UL << 4) 66 #define SPE_PMU_FEAT_ERND (1UL << 5) 67 #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) 68 u64 features; 69 70 u16 max_record_sz; 71 u16 align; 72 struct perf_output_handle __percpu *handle; 73 }; 74 75 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu)) 76 77 /* Convert a free-running index from perf into an SPE buffer offset */ 78 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) 79 80 /* Keep track of our dynamic hotplug state */ 81 static enum cpuhp_state arm_spe_pmu_online; 82 83 enum arm_spe_pmu_buf_fault_action { 84 SPE_PMU_BUF_FAULT_ACT_SPURIOUS, 85 SPE_PMU_BUF_FAULT_ACT_FATAL, 86 SPE_PMU_BUF_FAULT_ACT_OK, 87 }; 88 89 /* This sysfs gunk was really good fun to write. */ 90 enum arm_spe_pmu_capabilities { 91 SPE_PMU_CAP_ARCH_INST = 0, 92 SPE_PMU_CAP_ERND, 93 SPE_PMU_CAP_FEAT_MAX, 94 SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX, 95 SPE_PMU_CAP_MIN_IVAL, 96 }; 97 98 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = { 99 [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST, 100 [SPE_PMU_CAP_ERND] = SPE_PMU_FEAT_ERND, 101 }; 102 103 static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap) 104 { 105 if (cap < SPE_PMU_CAP_FEAT_MAX) 106 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]); 107 108 switch (cap) { 109 case SPE_PMU_CAP_CNT_SZ: 110 return spe_pmu->counter_sz; 111 case SPE_PMU_CAP_MIN_IVAL: 112 return spe_pmu->min_period; 113 default: 114 WARN(1, "unknown cap %d\n", cap); 115 } 116 117 return 0; 118 } 119 120 static ssize_t arm_spe_pmu_cap_show(struct device *dev, 121 struct device_attribute *attr, 122 char *buf) 123 { 124 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); 125 struct dev_ext_attribute *ea = 126 container_of(attr, struct dev_ext_attribute, attr); 127 int cap = (long)ea->var; 128 129 return sysfs_emit(buf, "%u\n", arm_spe_pmu_cap_get(spe_pmu, cap)); 130 } 131 132 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var) \ 133 &((struct dev_ext_attribute[]) { \ 134 { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var } \ 135 })[0].attr.attr 136 137 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var) \ 138 SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var) 139 140 static struct attribute *arm_spe_pmu_cap_attr[] = { 141 SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST), 142 SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND), 143 SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ), 144 SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL), 145 NULL, 146 }; 147 148 static const struct attribute_group arm_spe_pmu_cap_group = { 149 .name = "caps", 150 .attrs = arm_spe_pmu_cap_attr, 151 }; 152 153 /* User ABI */ 154 #define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */ 155 #define ATTR_CFG_FLD_ts_enable_LO 0 156 #define ATTR_CFG_FLD_ts_enable_HI 0 157 #define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */ 158 #define ATTR_CFG_FLD_pa_enable_LO 1 159 #define ATTR_CFG_FLD_pa_enable_HI 1 160 #define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */ 161 #define ATTR_CFG_FLD_pct_enable_LO 2 162 #define ATTR_CFG_FLD_pct_enable_HI 2 163 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */ 164 #define ATTR_CFG_FLD_jitter_LO 16 165 #define ATTR_CFG_FLD_jitter_HI 16 166 #define ATTR_CFG_FLD_branch_filter_CFG config /* PMSFCR_EL1.B */ 167 #define ATTR_CFG_FLD_branch_filter_LO 32 168 #define ATTR_CFG_FLD_branch_filter_HI 32 169 #define ATTR_CFG_FLD_load_filter_CFG config /* PMSFCR_EL1.LD */ 170 #define ATTR_CFG_FLD_load_filter_LO 33 171 #define ATTR_CFG_FLD_load_filter_HI 33 172 #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */ 173 #define ATTR_CFG_FLD_store_filter_LO 34 174 #define ATTR_CFG_FLD_store_filter_HI 34 175 176 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */ 177 #define ATTR_CFG_FLD_event_filter_LO 0 178 #define ATTR_CFG_FLD_event_filter_HI 63 179 180 #define ATTR_CFG_FLD_min_latency_CFG config2 /* PMSLATFR_EL1.MINLAT */ 181 #define ATTR_CFG_FLD_min_latency_LO 0 182 #define ATTR_CFG_FLD_min_latency_HI 11 183 184 /* Why does everything I do descend into this? */ 185 #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ 186 (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi 187 188 #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ 189 __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) 190 191 #define GEN_PMU_FORMAT_ATTR(name) \ 192 PMU_FORMAT_ATTR(name, \ 193 _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \ 194 ATTR_CFG_FLD_##name##_LO, \ 195 ATTR_CFG_FLD_##name##_HI)) 196 197 #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \ 198 ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0)) 199 200 #define ATTR_CFG_GET_FLD(attr, name) \ 201 _ATTR_CFG_GET_FLD(attr, \ 202 ATTR_CFG_FLD_##name##_CFG, \ 203 ATTR_CFG_FLD_##name##_LO, \ 204 ATTR_CFG_FLD_##name##_HI) 205 206 GEN_PMU_FORMAT_ATTR(ts_enable); 207 GEN_PMU_FORMAT_ATTR(pa_enable); 208 GEN_PMU_FORMAT_ATTR(pct_enable); 209 GEN_PMU_FORMAT_ATTR(jitter); 210 GEN_PMU_FORMAT_ATTR(branch_filter); 211 GEN_PMU_FORMAT_ATTR(load_filter); 212 GEN_PMU_FORMAT_ATTR(store_filter); 213 GEN_PMU_FORMAT_ATTR(event_filter); 214 GEN_PMU_FORMAT_ATTR(min_latency); 215 216 static struct attribute *arm_spe_pmu_formats_attr[] = { 217 &format_attr_ts_enable.attr, 218 &format_attr_pa_enable.attr, 219 &format_attr_pct_enable.attr, 220 &format_attr_jitter.attr, 221 &format_attr_branch_filter.attr, 222 &format_attr_load_filter.attr, 223 &format_attr_store_filter.attr, 224 &format_attr_event_filter.attr, 225 &format_attr_min_latency.attr, 226 NULL, 227 }; 228 229 static const struct attribute_group arm_spe_pmu_format_group = { 230 .name = "format", 231 .attrs = arm_spe_pmu_formats_attr, 232 }; 233 234 static ssize_t arm_spe_pmu_get_attr_cpumask(struct device *dev, 235 struct device_attribute *attr, 236 char *buf) 237 { 238 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); 239 240 return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus); 241 } 242 static DEVICE_ATTR(cpumask, S_IRUGO, arm_spe_pmu_get_attr_cpumask, NULL); 243 244 static struct attribute *arm_spe_pmu_attrs[] = { 245 &dev_attr_cpumask.attr, 246 NULL, 247 }; 248 249 static const struct attribute_group arm_spe_pmu_group = { 250 .attrs = arm_spe_pmu_attrs, 251 }; 252 253 static const struct attribute_group *arm_spe_pmu_attr_groups[] = { 254 &arm_spe_pmu_group, 255 &arm_spe_pmu_cap_group, 256 &arm_spe_pmu_format_group, 257 NULL, 258 }; 259 260 /* Convert between user ABI and register values */ 261 static u64 arm_spe_event_to_pmscr(struct perf_event *event) 262 { 263 struct perf_event_attr *attr = &event->attr; 264 u64 reg = 0; 265 266 reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; 267 reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; 268 reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; 269 270 if (!attr->exclude_user) 271 reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); 272 273 if (!attr->exclude_kernel) 274 reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); 275 276 if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable()) 277 reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); 278 279 return reg; 280 } 281 282 static void arm_spe_event_sanitise_period(struct perf_event *event) 283 { 284 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 285 u64 period = event->hw.sample_period; 286 u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK 287 << SYS_PMSIRR_EL1_INTERVAL_SHIFT; 288 289 if (period < spe_pmu->min_period) 290 period = spe_pmu->min_period; 291 else if (period > max_period) 292 period = max_period; 293 else 294 period &= max_period; 295 296 event->hw.sample_period = period; 297 } 298 299 static u64 arm_spe_event_to_pmsirr(struct perf_event *event) 300 { 301 struct perf_event_attr *attr = &event->attr; 302 u64 reg = 0; 303 304 arm_spe_event_sanitise_period(event); 305 306 reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; 307 reg |= event->hw.sample_period; 308 309 return reg; 310 } 311 312 static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) 313 { 314 struct perf_event_attr *attr = &event->attr; 315 u64 reg = 0; 316 317 reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; 318 reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; 319 reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; 320 321 if (reg) 322 reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT); 323 324 if (ATTR_CFG_GET_FLD(attr, event_filter)) 325 reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT); 326 327 if (ATTR_CFG_GET_FLD(attr, min_latency)) 328 reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT); 329 330 return reg; 331 } 332 333 static u64 arm_spe_event_to_pmsevfr(struct perf_event *event) 334 { 335 struct perf_event_attr *attr = &event->attr; 336 return ATTR_CFG_GET_FLD(attr, event_filter); 337 } 338 339 static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) 340 { 341 struct perf_event_attr *attr = &event->attr; 342 return ATTR_CFG_GET_FLD(attr, min_latency) 343 << SYS_PMSLATFR_EL1_MINLAT_SHIFT; 344 } 345 346 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) 347 { 348 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 349 u64 head = PERF_IDX2OFF(handle->head, buf); 350 351 memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len); 352 if (!buf->snapshot) 353 perf_aux_output_skip(handle, len); 354 } 355 356 static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle) 357 { 358 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 359 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu); 360 u64 head = PERF_IDX2OFF(handle->head, buf); 361 u64 limit = buf->nr_pages * PAGE_SIZE; 362 363 /* 364 * The trace format isn't parseable in reverse, so clamp 365 * the limit to half of the buffer size in snapshot mode 366 * so that the worst case is half a buffer of records, as 367 * opposed to a single record. 368 */ 369 if (head < limit >> 1) 370 limit >>= 1; 371 372 /* 373 * If we're within max_record_sz of the limit, we must 374 * pad, move the head index and recompute the limit. 375 */ 376 if (limit - head < spe_pmu->max_record_sz) { 377 arm_spe_pmu_pad_buf(handle, limit - head); 378 handle->head = PERF_IDX2OFF(limit, buf); 379 limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head; 380 } 381 382 return limit; 383 } 384 385 static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle) 386 { 387 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu); 388 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 389 const u64 bufsize = buf->nr_pages * PAGE_SIZE; 390 u64 limit = bufsize; 391 u64 head, tail, wakeup; 392 393 /* 394 * The head can be misaligned for two reasons: 395 * 396 * 1. The hardware left PMBPTR pointing to the first byte after 397 * a record when generating a buffer management event. 398 * 399 * 2. We used perf_aux_output_skip to consume handle->size bytes 400 * and CIRC_SPACE was used to compute the size, which always 401 * leaves one entry free. 402 * 403 * Deal with this by padding to the next alignment boundary and 404 * moving the head index. If we run out of buffer space, we'll 405 * reduce handle->size to zero and end up reporting truncation. 406 */ 407 head = PERF_IDX2OFF(handle->head, buf); 408 if (!IS_ALIGNED(head, spe_pmu->align)) { 409 unsigned long delta = roundup(head, spe_pmu->align) - head; 410 411 delta = min(delta, handle->size); 412 arm_spe_pmu_pad_buf(handle, delta); 413 head = PERF_IDX2OFF(handle->head, buf); 414 } 415 416 /* If we've run out of free space, then nothing more to do */ 417 if (!handle->size) 418 goto no_space; 419 420 /* Compute the tail and wakeup indices now that we've aligned head */ 421 tail = PERF_IDX2OFF(handle->head + handle->size, buf); 422 wakeup = PERF_IDX2OFF(handle->wakeup, buf); 423 424 /* 425 * Avoid clobbering unconsumed data. We know we have space, so 426 * if we see head == tail we know that the buffer is empty. If 427 * head > tail, then there's nothing to clobber prior to 428 * wrapping. 429 */ 430 if (head < tail) 431 limit = round_down(tail, PAGE_SIZE); 432 433 /* 434 * Wakeup may be arbitrarily far into the future. If it's not in 435 * the current generation, either we'll wrap before hitting it, 436 * or it's in the past and has been handled already. 437 * 438 * If there's a wakeup before we wrap, arrange to be woken up by 439 * the page boundary following it. Keep the tail boundary if 440 * that's lower. 441 */ 442 if (handle->wakeup < (handle->head + handle->size) && head <= wakeup) 443 limit = min(limit, round_up(wakeup, PAGE_SIZE)); 444 445 if (limit > head) 446 return limit; 447 448 arm_spe_pmu_pad_buf(handle, handle->size); 449 no_space: 450 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 451 perf_aux_output_end(handle, 0); 452 return 0; 453 } 454 455 static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle) 456 { 457 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 458 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu); 459 u64 limit = __arm_spe_pmu_next_off(handle); 460 u64 head = PERF_IDX2OFF(handle->head, buf); 461 462 /* 463 * If the head has come too close to the end of the buffer, 464 * then pad to the end and recompute the limit. 465 */ 466 if (limit && (limit - head < spe_pmu->max_record_sz)) { 467 arm_spe_pmu_pad_buf(handle, limit - head); 468 limit = __arm_spe_pmu_next_off(handle); 469 } 470 471 return limit; 472 } 473 474 static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, 475 struct perf_event *event) 476 { 477 u64 base, limit; 478 struct arm_spe_pmu_buf *buf; 479 480 /* Start a new aux session */ 481 buf = perf_aux_output_begin(handle, event); 482 if (!buf) { 483 event->hw.state |= PERF_HES_STOPPED; 484 /* 485 * We still need to clear the limit pointer, since the 486 * profiler might only be disabled by virtue of a fault. 487 */ 488 limit = 0; 489 goto out_write_limit; 490 } 491 492 limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) 493 : arm_spe_pmu_next_off(handle); 494 if (limit) 495 limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT); 496 497 limit += (u64)buf->base; 498 base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); 499 write_sysreg_s(base, SYS_PMBPTR_EL1); 500 501 out_write_limit: 502 write_sysreg_s(limit, SYS_PMBLIMITR_EL1); 503 } 504 505 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle) 506 { 507 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 508 u64 offset, size; 509 510 offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base; 511 size = offset - PERF_IDX2OFF(handle->head, buf); 512 513 if (buf->snapshot) 514 handle->head = offset; 515 516 perf_aux_output_end(handle, size); 517 } 518 519 static void arm_spe_pmu_disable_and_drain_local(void) 520 { 521 /* Disable profiling at EL0 and EL1 */ 522 write_sysreg_s(0, SYS_PMSCR_EL1); 523 isb(); 524 525 /* Drain any buffered data */ 526 psb_csync(); 527 dsb(nsh); 528 529 /* Disable the profiling buffer */ 530 write_sysreg_s(0, SYS_PMBLIMITR_EL1); 531 isb(); 532 } 533 534 /* IRQ handling */ 535 static enum arm_spe_pmu_buf_fault_action 536 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) 537 { 538 const char *err_str; 539 u64 pmbsr; 540 enum arm_spe_pmu_buf_fault_action ret; 541 542 /* 543 * Ensure new profiling data is visible to the CPU and any external 544 * aborts have been resolved. 545 */ 546 psb_csync(); 547 dsb(nsh); 548 549 /* Ensure hardware updates to PMBPTR_EL1 are visible */ 550 isb(); 551 552 /* Service required? */ 553 pmbsr = read_sysreg_s(SYS_PMBSR_EL1); 554 if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) 555 return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; 556 557 /* 558 * If we've lost data, disable profiling and also set the PARTIAL 559 * flag to indicate that the last record is corrupted. 560 */ 561 if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) 562 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | 563 PERF_AUX_FLAG_PARTIAL); 564 565 /* Report collisions to userspace so that it can up the period */ 566 if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) 567 perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); 568 569 /* We only expect buffer management events */ 570 switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) { 571 case SYS_PMBSR_EL1_EC_BUF: 572 /* Handled below */ 573 break; 574 case SYS_PMBSR_EL1_EC_FAULT_S1: 575 case SYS_PMBSR_EL1_EC_FAULT_S2: 576 err_str = "Unexpected buffer fault"; 577 goto out_err; 578 default: 579 err_str = "Unknown error code"; 580 goto out_err; 581 } 582 583 /* Buffer management event */ 584 switch (pmbsr & 585 (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) { 586 case SYS_PMBSR_EL1_BUF_BSC_FULL: 587 ret = SPE_PMU_BUF_FAULT_ACT_OK; 588 goto out_stop; 589 default: 590 err_str = "Unknown buffer status code"; 591 } 592 593 out_err: 594 pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n", 595 err_str, smp_processor_id(), pmbsr, 596 read_sysreg_s(SYS_PMBPTR_EL1), 597 read_sysreg_s(SYS_PMBLIMITR_EL1)); 598 ret = SPE_PMU_BUF_FAULT_ACT_FATAL; 599 600 out_stop: 601 arm_spe_perf_aux_output_end(handle); 602 return ret; 603 } 604 605 static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev) 606 { 607 struct perf_output_handle *handle = dev; 608 struct perf_event *event = handle->event; 609 enum arm_spe_pmu_buf_fault_action act; 610 611 if (!perf_get_aux(handle)) 612 return IRQ_NONE; 613 614 act = arm_spe_pmu_buf_get_fault_act(handle); 615 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS) 616 return IRQ_NONE; 617 618 /* 619 * Ensure perf callbacks have completed, which may disable the 620 * profiling buffer in response to a TRUNCATION flag. 621 */ 622 irq_work_run(); 623 624 switch (act) { 625 case SPE_PMU_BUF_FAULT_ACT_FATAL: 626 /* 627 * If a fatal exception occurred then leaving the profiling 628 * buffer enabled is a recipe waiting to happen. Since 629 * fatal faults don't always imply truncation, make sure 630 * that the profiling buffer is disabled explicitly before 631 * clearing the syndrome register. 632 */ 633 arm_spe_pmu_disable_and_drain_local(); 634 break; 635 case SPE_PMU_BUF_FAULT_ACT_OK: 636 /* 637 * We handled the fault (the buffer was full), so resume 638 * profiling as long as we didn't detect truncation. 639 * PMBPTR might be misaligned, but we'll burn that bridge 640 * when we get to it. 641 */ 642 if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) { 643 arm_spe_perf_aux_output_begin(handle, event); 644 isb(); 645 } 646 break; 647 case SPE_PMU_BUF_FAULT_ACT_SPURIOUS: 648 /* We've seen you before, but GCC has the memory of a sieve. */ 649 break; 650 } 651 652 /* The buffer pointers are now sane, so resume profiling. */ 653 write_sysreg_s(0, SYS_PMBSR_EL1); 654 return IRQ_HANDLED; 655 } 656 657 static u64 arm_spe_pmsevfr_res0(u16 pmsver) 658 { 659 switch (pmsver) { 660 case ID_AA64DFR0_PMSVER_8_2: 661 return SYS_PMSEVFR_EL1_RES0_8_2; 662 case ID_AA64DFR0_PMSVER_8_3: 663 /* Return the highest version we support in default */ 664 default: 665 return SYS_PMSEVFR_EL1_RES0_8_3; 666 } 667 } 668 669 /* Perf callbacks */ 670 static int arm_spe_pmu_event_init(struct perf_event *event) 671 { 672 u64 reg; 673 struct perf_event_attr *attr = &event->attr; 674 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 675 676 /* This is, of course, deeply driver-specific */ 677 if (attr->type != event->pmu->type) 678 return -ENOENT; 679 680 if (event->cpu >= 0 && 681 !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus)) 682 return -ENOENT; 683 684 if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver)) 685 return -EOPNOTSUPP; 686 687 if (attr->exclude_idle) 688 return -EOPNOTSUPP; 689 690 /* 691 * Feedback-directed frequency throttling doesn't work when we 692 * have a buffer of samples. We'd need to manually count the 693 * samples in the buffer when it fills up and adjust the event 694 * count to reflect that. Instead, just force the user to specify 695 * a sample period. 696 */ 697 if (attr->freq) 698 return -EINVAL; 699 700 reg = arm_spe_event_to_pmsfcr(event); 701 if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && 702 !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) 703 return -EOPNOTSUPP; 704 705 if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && 706 !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) 707 return -EOPNOTSUPP; 708 709 if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && 710 !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) 711 return -EOPNOTSUPP; 712 713 reg = arm_spe_event_to_pmscr(event); 714 if (!perfmon_capable() && 715 (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | 716 BIT(SYS_PMSCR_EL1_CX_SHIFT) | 717 BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) 718 return -EACCES; 719 720 return 0; 721 } 722 723 static void arm_spe_pmu_start(struct perf_event *event, int flags) 724 { 725 u64 reg; 726 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 727 struct hw_perf_event *hwc = &event->hw; 728 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle); 729 730 hwc->state = 0; 731 arm_spe_perf_aux_output_begin(handle, event); 732 if (hwc->state) 733 return; 734 735 reg = arm_spe_event_to_pmsfcr(event); 736 write_sysreg_s(reg, SYS_PMSFCR_EL1); 737 738 reg = arm_spe_event_to_pmsevfr(event); 739 write_sysreg_s(reg, SYS_PMSEVFR_EL1); 740 741 reg = arm_spe_event_to_pmslatfr(event); 742 write_sysreg_s(reg, SYS_PMSLATFR_EL1); 743 744 if (flags & PERF_EF_RELOAD) { 745 reg = arm_spe_event_to_pmsirr(event); 746 write_sysreg_s(reg, SYS_PMSIRR_EL1); 747 isb(); 748 reg = local64_read(&hwc->period_left); 749 write_sysreg_s(reg, SYS_PMSICR_EL1); 750 } 751 752 reg = arm_spe_event_to_pmscr(event); 753 isb(); 754 write_sysreg_s(reg, SYS_PMSCR_EL1); 755 } 756 757 static void arm_spe_pmu_stop(struct perf_event *event, int flags) 758 { 759 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 760 struct hw_perf_event *hwc = &event->hw; 761 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle); 762 763 /* If we're already stopped, then nothing to do */ 764 if (hwc->state & PERF_HES_STOPPED) 765 return; 766 767 /* Stop all trace generation */ 768 arm_spe_pmu_disable_and_drain_local(); 769 770 if (flags & PERF_EF_UPDATE) { 771 /* 772 * If there's a fault pending then ensure we contain it 773 * to this buffer, since we might be on the context-switch 774 * path. 775 */ 776 if (perf_get_aux(handle)) { 777 enum arm_spe_pmu_buf_fault_action act; 778 779 act = arm_spe_pmu_buf_get_fault_act(handle); 780 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS) 781 arm_spe_perf_aux_output_end(handle); 782 else 783 write_sysreg_s(0, SYS_PMBSR_EL1); 784 } 785 786 /* 787 * This may also contain ECOUNT, but nobody else should 788 * be looking at period_left, since we forbid frequency 789 * based sampling. 790 */ 791 local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1)); 792 hwc->state |= PERF_HES_UPTODATE; 793 } 794 795 hwc->state |= PERF_HES_STOPPED; 796 } 797 798 static int arm_spe_pmu_add(struct perf_event *event, int flags) 799 { 800 int ret = 0; 801 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 802 struct hw_perf_event *hwc = &event->hw; 803 int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu; 804 805 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus)) 806 return -ENOENT; 807 808 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 809 810 if (flags & PERF_EF_START) { 811 arm_spe_pmu_start(event, PERF_EF_RELOAD); 812 if (hwc->state & PERF_HES_STOPPED) 813 ret = -EINVAL; 814 } 815 816 return ret; 817 } 818 819 static void arm_spe_pmu_del(struct perf_event *event, int flags) 820 { 821 arm_spe_pmu_stop(event, PERF_EF_UPDATE); 822 } 823 824 static void arm_spe_pmu_read(struct perf_event *event) 825 { 826 } 827 828 static void *arm_spe_pmu_setup_aux(struct perf_event *event, void **pages, 829 int nr_pages, bool snapshot) 830 { 831 int i, cpu = event->cpu; 832 struct page **pglist; 833 struct arm_spe_pmu_buf *buf; 834 835 /* We need at least two pages for this to work. */ 836 if (nr_pages < 2) 837 return NULL; 838 839 /* 840 * We require an even number of pages for snapshot mode, so that 841 * we can effectively treat the buffer as consisting of two equal 842 * parts and give userspace a fighting chance of getting some 843 * useful data out of it. 844 */ 845 if (snapshot && (nr_pages & 1)) 846 return NULL; 847 848 if (cpu == -1) 849 cpu = raw_smp_processor_id(); 850 851 buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu)); 852 if (!buf) 853 return NULL; 854 855 pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL); 856 if (!pglist) 857 goto out_free_buf; 858 859 for (i = 0; i < nr_pages; ++i) 860 pglist[i] = virt_to_page(pages[i]); 861 862 buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL); 863 if (!buf->base) 864 goto out_free_pglist; 865 866 buf->nr_pages = nr_pages; 867 buf->snapshot = snapshot; 868 869 kfree(pglist); 870 return buf; 871 872 out_free_pglist: 873 kfree(pglist); 874 out_free_buf: 875 kfree(buf); 876 return NULL; 877 } 878 879 static void arm_spe_pmu_free_aux(void *aux) 880 { 881 struct arm_spe_pmu_buf *buf = aux; 882 883 vunmap(buf->base); 884 kfree(buf); 885 } 886 887 /* Initialisation and teardown functions */ 888 static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu) 889 { 890 static atomic_t pmu_idx = ATOMIC_INIT(-1); 891 892 int idx; 893 char *name; 894 struct device *dev = &spe_pmu->pdev->dev; 895 896 spe_pmu->pmu = (struct pmu) { 897 .module = THIS_MODULE, 898 .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, 899 .attr_groups = arm_spe_pmu_attr_groups, 900 /* 901 * We hitch a ride on the software context here, so that 902 * we can support per-task profiling (which is not possible 903 * with the invalid context as it doesn't get sched callbacks). 904 * This requires that userspace either uses a dummy event for 905 * perf_event_open, since the aux buffer is not setup until 906 * a subsequent mmap, or creates the profiling event in a 907 * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it 908 * once the buffer has been created. 909 */ 910 .task_ctx_nr = perf_sw_context, 911 .event_init = arm_spe_pmu_event_init, 912 .add = arm_spe_pmu_add, 913 .del = arm_spe_pmu_del, 914 .start = arm_spe_pmu_start, 915 .stop = arm_spe_pmu_stop, 916 .read = arm_spe_pmu_read, 917 .setup_aux = arm_spe_pmu_setup_aux, 918 .free_aux = arm_spe_pmu_free_aux, 919 }; 920 921 idx = atomic_inc_return(&pmu_idx); 922 name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx); 923 if (!name) { 924 dev_err(dev, "failed to allocate name for pmu %d\n", idx); 925 return -ENOMEM; 926 } 927 928 return perf_pmu_register(&spe_pmu->pmu, name, -1); 929 } 930 931 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu) 932 { 933 perf_pmu_unregister(&spe_pmu->pmu); 934 } 935 936 static void __arm_spe_pmu_dev_probe(void *info) 937 { 938 int fld; 939 u64 reg; 940 struct arm_spe_pmu *spe_pmu = info; 941 struct device *dev = &spe_pmu->pdev->dev; 942 943 fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1), 944 ID_AA64DFR0_PMSVER_SHIFT); 945 if (!fld) { 946 dev_err(dev, 947 "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n", 948 fld, smp_processor_id()); 949 return; 950 } 951 spe_pmu->pmsver = (u16)fld; 952 953 /* Read PMBIDR first to determine whether or not we have access */ 954 reg = read_sysreg_s(SYS_PMBIDR_EL1); 955 if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { 956 dev_err(dev, 957 "profiling buffer owned by higher exception level\n"); 958 return; 959 } 960 961 /* Minimum alignment. If it's out-of-range, then fail the probe */ 962 fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; 963 spe_pmu->align = 1 << fld; 964 if (spe_pmu->align > SZ_2K) { 965 dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", 966 fld, smp_processor_id()); 967 return; 968 } 969 970 /* It's now safe to read PMSIDR and figure out what we've got */ 971 reg = read_sysreg_s(SYS_PMSIDR_EL1); 972 if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) 973 spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; 974 975 if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) 976 spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP; 977 978 if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) 979 spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT; 980 981 if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) 982 spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST; 983 984 if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) 985 spe_pmu->features |= SPE_PMU_FEAT_LDS; 986 987 if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) 988 spe_pmu->features |= SPE_PMU_FEAT_ERND; 989 990 /* This field has a spaced out encoding, so just use a look-up */ 991 fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK; 992 switch (fld) { 993 case 0: 994 spe_pmu->min_period = 256; 995 break; 996 case 2: 997 spe_pmu->min_period = 512; 998 break; 999 case 3: 1000 spe_pmu->min_period = 768; 1001 break; 1002 case 4: 1003 spe_pmu->min_period = 1024; 1004 break; 1005 case 5: 1006 spe_pmu->min_period = 1536; 1007 break; 1008 case 6: 1009 spe_pmu->min_period = 2048; 1010 break; 1011 case 7: 1012 spe_pmu->min_period = 3072; 1013 break; 1014 default: 1015 dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n", 1016 fld); 1017 fallthrough; 1018 case 8: 1019 spe_pmu->min_period = 4096; 1020 } 1021 1022 /* Maximum record size. If it's out-of-range, then fail the probe */ 1023 fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; 1024 spe_pmu->max_record_sz = 1 << fld; 1025 if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { 1026 dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", 1027 fld, smp_processor_id()); 1028 return; 1029 } 1030 1031 fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK; 1032 switch (fld) { 1033 default: 1034 dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", 1035 fld); 1036 fallthrough; 1037 case 2: 1038 spe_pmu->counter_sz = 12; 1039 } 1040 1041 dev_info(dev, 1042 "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n", 1043 cpumask_pr_args(&spe_pmu->supported_cpus), 1044 spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features); 1045 1046 spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED; 1047 return; 1048 } 1049 1050 static void __arm_spe_pmu_reset_local(void) 1051 { 1052 /* 1053 * This is probably overkill, as we have no idea where we're 1054 * draining any buffered data to... 1055 */ 1056 arm_spe_pmu_disable_and_drain_local(); 1057 1058 /* Reset the buffer base pointer */ 1059 write_sysreg_s(0, SYS_PMBPTR_EL1); 1060 isb(); 1061 1062 /* Clear any pending management interrupts */ 1063 write_sysreg_s(0, SYS_PMBSR_EL1); 1064 isb(); 1065 } 1066 1067 static void __arm_spe_pmu_setup_one(void *info) 1068 { 1069 struct arm_spe_pmu *spe_pmu = info; 1070 1071 __arm_spe_pmu_reset_local(); 1072 enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE); 1073 } 1074 1075 static void __arm_spe_pmu_stop_one(void *info) 1076 { 1077 struct arm_spe_pmu *spe_pmu = info; 1078 1079 disable_percpu_irq(spe_pmu->irq); 1080 __arm_spe_pmu_reset_local(); 1081 } 1082 1083 static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node) 1084 { 1085 struct arm_spe_pmu *spe_pmu; 1086 1087 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node); 1088 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus)) 1089 return 0; 1090 1091 __arm_spe_pmu_setup_one(spe_pmu); 1092 return 0; 1093 } 1094 1095 static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node) 1096 { 1097 struct arm_spe_pmu *spe_pmu; 1098 1099 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node); 1100 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus)) 1101 return 0; 1102 1103 __arm_spe_pmu_stop_one(spe_pmu); 1104 return 0; 1105 } 1106 1107 static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu) 1108 { 1109 int ret; 1110 cpumask_t *mask = &spe_pmu->supported_cpus; 1111 1112 /* Make sure we probe the hardware on a relevant CPU */ 1113 ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1); 1114 if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED)) 1115 return -ENXIO; 1116 1117 /* Request our PPIs (note that the IRQ is still disabled) */ 1118 ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME, 1119 spe_pmu->handle); 1120 if (ret) 1121 return ret; 1122 1123 /* 1124 * Register our hotplug notifier now so we don't miss any events. 1125 * This will enable the IRQ for any supported CPUs that are already 1126 * up. 1127 */ 1128 ret = cpuhp_state_add_instance(arm_spe_pmu_online, 1129 &spe_pmu->hotplug_node); 1130 if (ret) 1131 free_percpu_irq(spe_pmu->irq, spe_pmu->handle); 1132 1133 return ret; 1134 } 1135 1136 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu) 1137 { 1138 cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node); 1139 free_percpu_irq(spe_pmu->irq, spe_pmu->handle); 1140 } 1141 1142 /* Driver and device probing */ 1143 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu) 1144 { 1145 struct platform_device *pdev = spe_pmu->pdev; 1146 int irq = platform_get_irq(pdev, 0); 1147 1148 if (irq < 0) 1149 return -ENXIO; 1150 1151 if (!irq_is_percpu(irq)) { 1152 dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq); 1153 return -EINVAL; 1154 } 1155 1156 if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) { 1157 dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq); 1158 return -EINVAL; 1159 } 1160 1161 spe_pmu->irq = irq; 1162 return 0; 1163 } 1164 1165 static const struct of_device_id arm_spe_pmu_of_match[] = { 1166 { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 }, 1167 { /* Sentinel */ }, 1168 }; 1169 MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match); 1170 1171 static const struct platform_device_id arm_spe_match[] = { 1172 { ARMV8_SPE_PDEV_NAME, 0}, 1173 { } 1174 }; 1175 MODULE_DEVICE_TABLE(platform, arm_spe_match); 1176 1177 static int arm_spe_pmu_device_probe(struct platform_device *pdev) 1178 { 1179 int ret; 1180 struct arm_spe_pmu *spe_pmu; 1181 struct device *dev = &pdev->dev; 1182 1183 /* 1184 * If kernelspace is unmapped when running at EL0, then the SPE 1185 * buffer will fault and prematurely terminate the AUX session. 1186 */ 1187 if (arm64_kernel_unmapped_at_el0()) { 1188 dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n"); 1189 return -EPERM; 1190 } 1191 1192 spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL); 1193 if (!spe_pmu) { 1194 dev_err(dev, "failed to allocate spe_pmu\n"); 1195 return -ENOMEM; 1196 } 1197 1198 spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle)); 1199 if (!spe_pmu->handle) 1200 return -ENOMEM; 1201 1202 spe_pmu->pdev = pdev; 1203 platform_set_drvdata(pdev, spe_pmu); 1204 1205 ret = arm_spe_pmu_irq_probe(spe_pmu); 1206 if (ret) 1207 goto out_free_handle; 1208 1209 ret = arm_spe_pmu_dev_init(spe_pmu); 1210 if (ret) 1211 goto out_free_handle; 1212 1213 ret = arm_spe_pmu_perf_init(spe_pmu); 1214 if (ret) 1215 goto out_teardown_dev; 1216 1217 return 0; 1218 1219 out_teardown_dev: 1220 arm_spe_pmu_dev_teardown(spe_pmu); 1221 out_free_handle: 1222 free_percpu(spe_pmu->handle); 1223 return ret; 1224 } 1225 1226 static int arm_spe_pmu_device_remove(struct platform_device *pdev) 1227 { 1228 struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev); 1229 1230 arm_spe_pmu_perf_destroy(spe_pmu); 1231 arm_spe_pmu_dev_teardown(spe_pmu); 1232 free_percpu(spe_pmu->handle); 1233 return 0; 1234 } 1235 1236 static struct platform_driver arm_spe_pmu_driver = { 1237 .id_table = arm_spe_match, 1238 .driver = { 1239 .name = DRVNAME, 1240 .of_match_table = of_match_ptr(arm_spe_pmu_of_match), 1241 .suppress_bind_attrs = true, 1242 }, 1243 .probe = arm_spe_pmu_device_probe, 1244 .remove = arm_spe_pmu_device_remove, 1245 }; 1246 1247 static int __init arm_spe_pmu_init(void) 1248 { 1249 int ret; 1250 1251 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME, 1252 arm_spe_pmu_cpu_startup, 1253 arm_spe_pmu_cpu_teardown); 1254 if (ret < 0) 1255 return ret; 1256 arm_spe_pmu_online = ret; 1257 1258 ret = platform_driver_register(&arm_spe_pmu_driver); 1259 if (ret) 1260 cpuhp_remove_multi_state(arm_spe_pmu_online); 1261 1262 return ret; 1263 } 1264 1265 static void __exit arm_spe_pmu_exit(void) 1266 { 1267 platform_driver_unregister(&arm_spe_pmu_driver); 1268 cpuhp_remove_multi_state(arm_spe_pmu_online); 1269 } 1270 1271 module_init(arm_spe_pmu_init); 1272 module_exit(arm_spe_pmu_exit); 1273 1274 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension"); 1275 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); 1276 MODULE_LICENSE("GPL v2"); 1277