1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Perf support for the Statistical Profiling Extension, introduced as 4 * part of ARMv8.2. 5 * 6 * Copyright (C) 2016 ARM Limited 7 * 8 * Author: Will Deacon <will.deacon@arm.com> 9 */ 10 11 #define PMUNAME "arm_spe" 12 #define DRVNAME PMUNAME "_pmu" 13 #define pr_fmt(fmt) DRVNAME ": " fmt 14 15 #include <linux/bitops.h> 16 #include <linux/bug.h> 17 #include <linux/capability.h> 18 #include <linux/cpuhotplug.h> 19 #include <linux/cpumask.h> 20 #include <linux/device.h> 21 #include <linux/errno.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/kernel.h> 25 #include <linux/list.h> 26 #include <linux/module.h> 27 #include <linux/of_address.h> 28 #include <linux/of_device.h> 29 #include <linux/perf_event.h> 30 #include <linux/perf/arm_pmu.h> 31 #include <linux/platform_device.h> 32 #include <linux/printk.h> 33 #include <linux/slab.h> 34 #include <linux/smp.h> 35 #include <linux/vmalloc.h> 36 37 #include <asm/barrier.h> 38 #include <asm/cpufeature.h> 39 #include <asm/mmu.h> 40 #include <asm/sysreg.h> 41 42 #define ARM_SPE_BUF_PAD_BYTE 0 43 44 struct arm_spe_pmu_buf { 45 int nr_pages; 46 bool snapshot; 47 void *base; 48 }; 49 50 struct arm_spe_pmu { 51 struct pmu pmu; 52 struct platform_device *pdev; 53 cpumask_t supported_cpus; 54 struct hlist_node hotplug_node; 55 56 int irq; /* PPI */ 57 u16 pmsver; 58 u16 min_period; 59 u16 counter_sz; 60 61 #define SPE_PMU_FEAT_FILT_EVT (1UL << 0) 62 #define SPE_PMU_FEAT_FILT_TYP (1UL << 1) 63 #define SPE_PMU_FEAT_FILT_LAT (1UL << 2) 64 #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) 65 #define SPE_PMU_FEAT_LDS (1UL << 4) 66 #define SPE_PMU_FEAT_ERND (1UL << 5) 67 #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) 68 u64 features; 69 70 u16 max_record_sz; 71 u16 align; 72 struct perf_output_handle __percpu *handle; 73 }; 74 75 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu)) 76 77 /* Convert a free-running index from perf into an SPE buffer offset */ 78 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) 79 80 /* Keep track of our dynamic hotplug state */ 81 static enum cpuhp_state arm_spe_pmu_online; 82 83 enum arm_spe_pmu_buf_fault_action { 84 SPE_PMU_BUF_FAULT_ACT_SPURIOUS, 85 SPE_PMU_BUF_FAULT_ACT_FATAL, 86 SPE_PMU_BUF_FAULT_ACT_OK, 87 }; 88 89 /* This sysfs gunk was really good fun to write. */ 90 enum arm_spe_pmu_capabilities { 91 SPE_PMU_CAP_ARCH_INST = 0, 92 SPE_PMU_CAP_ERND, 93 SPE_PMU_CAP_FEAT_MAX, 94 SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX, 95 SPE_PMU_CAP_MIN_IVAL, 96 }; 97 98 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = { 99 [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST, 100 [SPE_PMU_CAP_ERND] = SPE_PMU_FEAT_ERND, 101 }; 102 103 static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap) 104 { 105 if (cap < SPE_PMU_CAP_FEAT_MAX) 106 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]); 107 108 switch (cap) { 109 case SPE_PMU_CAP_CNT_SZ: 110 return spe_pmu->counter_sz; 111 case SPE_PMU_CAP_MIN_IVAL: 112 return spe_pmu->min_period; 113 default: 114 WARN(1, "unknown cap %d\n", cap); 115 } 116 117 return 0; 118 } 119 120 static ssize_t arm_spe_pmu_cap_show(struct device *dev, 121 struct device_attribute *attr, 122 char *buf) 123 { 124 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); 125 struct dev_ext_attribute *ea = 126 container_of(attr, struct dev_ext_attribute, attr); 127 int cap = (long)ea->var; 128 129 return sysfs_emit(buf, "%u\n", arm_spe_pmu_cap_get(spe_pmu, cap)); 130 } 131 132 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var) \ 133 &((struct dev_ext_attribute[]) { \ 134 { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var } \ 135 })[0].attr.attr 136 137 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var) \ 138 SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var) 139 140 static struct attribute *arm_spe_pmu_cap_attr[] = { 141 SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST), 142 SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND), 143 SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ), 144 SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL), 145 NULL, 146 }; 147 148 static const struct attribute_group arm_spe_pmu_cap_group = { 149 .name = "caps", 150 .attrs = arm_spe_pmu_cap_attr, 151 }; 152 153 /* User ABI */ 154 #define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */ 155 #define ATTR_CFG_FLD_ts_enable_LO 0 156 #define ATTR_CFG_FLD_ts_enable_HI 0 157 #define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */ 158 #define ATTR_CFG_FLD_pa_enable_LO 1 159 #define ATTR_CFG_FLD_pa_enable_HI 1 160 #define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */ 161 #define ATTR_CFG_FLD_pct_enable_LO 2 162 #define ATTR_CFG_FLD_pct_enable_HI 2 163 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */ 164 #define ATTR_CFG_FLD_jitter_LO 16 165 #define ATTR_CFG_FLD_jitter_HI 16 166 #define ATTR_CFG_FLD_branch_filter_CFG config /* PMSFCR_EL1.B */ 167 #define ATTR_CFG_FLD_branch_filter_LO 32 168 #define ATTR_CFG_FLD_branch_filter_HI 32 169 #define ATTR_CFG_FLD_load_filter_CFG config /* PMSFCR_EL1.LD */ 170 #define ATTR_CFG_FLD_load_filter_LO 33 171 #define ATTR_CFG_FLD_load_filter_HI 33 172 #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */ 173 #define ATTR_CFG_FLD_store_filter_LO 34 174 #define ATTR_CFG_FLD_store_filter_HI 34 175 176 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */ 177 #define ATTR_CFG_FLD_event_filter_LO 0 178 #define ATTR_CFG_FLD_event_filter_HI 63 179 180 #define ATTR_CFG_FLD_min_latency_CFG config2 /* PMSLATFR_EL1.MINLAT */ 181 #define ATTR_CFG_FLD_min_latency_LO 0 182 #define ATTR_CFG_FLD_min_latency_HI 11 183 184 /* Why does everything I do descend into this? */ 185 #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ 186 (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi 187 188 #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ 189 __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) 190 191 #define GEN_PMU_FORMAT_ATTR(name) \ 192 PMU_FORMAT_ATTR(name, \ 193 _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \ 194 ATTR_CFG_FLD_##name##_LO, \ 195 ATTR_CFG_FLD_##name##_HI)) 196 197 #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \ 198 ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0)) 199 200 #define ATTR_CFG_GET_FLD(attr, name) \ 201 _ATTR_CFG_GET_FLD(attr, \ 202 ATTR_CFG_FLD_##name##_CFG, \ 203 ATTR_CFG_FLD_##name##_LO, \ 204 ATTR_CFG_FLD_##name##_HI) 205 206 GEN_PMU_FORMAT_ATTR(ts_enable); 207 GEN_PMU_FORMAT_ATTR(pa_enable); 208 GEN_PMU_FORMAT_ATTR(pct_enable); 209 GEN_PMU_FORMAT_ATTR(jitter); 210 GEN_PMU_FORMAT_ATTR(branch_filter); 211 GEN_PMU_FORMAT_ATTR(load_filter); 212 GEN_PMU_FORMAT_ATTR(store_filter); 213 GEN_PMU_FORMAT_ATTR(event_filter); 214 GEN_PMU_FORMAT_ATTR(min_latency); 215 216 static struct attribute *arm_spe_pmu_formats_attr[] = { 217 &format_attr_ts_enable.attr, 218 &format_attr_pa_enable.attr, 219 &format_attr_pct_enable.attr, 220 &format_attr_jitter.attr, 221 &format_attr_branch_filter.attr, 222 &format_attr_load_filter.attr, 223 &format_attr_store_filter.attr, 224 &format_attr_event_filter.attr, 225 &format_attr_min_latency.attr, 226 NULL, 227 }; 228 229 static const struct attribute_group arm_spe_pmu_format_group = { 230 .name = "format", 231 .attrs = arm_spe_pmu_formats_attr, 232 }; 233 234 static ssize_t cpumask_show(struct device *dev, 235 struct device_attribute *attr, char *buf) 236 { 237 struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); 238 239 return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus); 240 } 241 static DEVICE_ATTR_RO(cpumask); 242 243 static struct attribute *arm_spe_pmu_attrs[] = { 244 &dev_attr_cpumask.attr, 245 NULL, 246 }; 247 248 static const struct attribute_group arm_spe_pmu_group = { 249 .attrs = arm_spe_pmu_attrs, 250 }; 251 252 static const struct attribute_group *arm_spe_pmu_attr_groups[] = { 253 &arm_spe_pmu_group, 254 &arm_spe_pmu_cap_group, 255 &arm_spe_pmu_format_group, 256 NULL, 257 }; 258 259 /* Convert between user ABI and register values */ 260 static u64 arm_spe_event_to_pmscr(struct perf_event *event) 261 { 262 struct perf_event_attr *attr = &event->attr; 263 u64 reg = 0; 264 265 reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; 266 reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; 267 reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; 268 269 if (!attr->exclude_user) 270 reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); 271 272 if (!attr->exclude_kernel) 273 reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); 274 275 if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable()) 276 reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); 277 278 return reg; 279 } 280 281 static void arm_spe_event_sanitise_period(struct perf_event *event) 282 { 283 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 284 u64 period = event->hw.sample_period; 285 u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK 286 << SYS_PMSIRR_EL1_INTERVAL_SHIFT; 287 288 if (period < spe_pmu->min_period) 289 period = spe_pmu->min_period; 290 else if (period > max_period) 291 period = max_period; 292 else 293 period &= max_period; 294 295 event->hw.sample_period = period; 296 } 297 298 static u64 arm_spe_event_to_pmsirr(struct perf_event *event) 299 { 300 struct perf_event_attr *attr = &event->attr; 301 u64 reg = 0; 302 303 arm_spe_event_sanitise_period(event); 304 305 reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; 306 reg |= event->hw.sample_period; 307 308 return reg; 309 } 310 311 static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) 312 { 313 struct perf_event_attr *attr = &event->attr; 314 u64 reg = 0; 315 316 reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; 317 reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; 318 reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; 319 320 if (reg) 321 reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT); 322 323 if (ATTR_CFG_GET_FLD(attr, event_filter)) 324 reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT); 325 326 if (ATTR_CFG_GET_FLD(attr, min_latency)) 327 reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT); 328 329 return reg; 330 } 331 332 static u64 arm_spe_event_to_pmsevfr(struct perf_event *event) 333 { 334 struct perf_event_attr *attr = &event->attr; 335 return ATTR_CFG_GET_FLD(attr, event_filter); 336 } 337 338 static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) 339 { 340 struct perf_event_attr *attr = &event->attr; 341 return ATTR_CFG_GET_FLD(attr, min_latency) 342 << SYS_PMSLATFR_EL1_MINLAT_SHIFT; 343 } 344 345 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) 346 { 347 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 348 u64 head = PERF_IDX2OFF(handle->head, buf); 349 350 memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len); 351 if (!buf->snapshot) 352 perf_aux_output_skip(handle, len); 353 } 354 355 static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle) 356 { 357 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 358 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu); 359 u64 head = PERF_IDX2OFF(handle->head, buf); 360 u64 limit = buf->nr_pages * PAGE_SIZE; 361 362 /* 363 * The trace format isn't parseable in reverse, so clamp 364 * the limit to half of the buffer size in snapshot mode 365 * so that the worst case is half a buffer of records, as 366 * opposed to a single record. 367 */ 368 if (head < limit >> 1) 369 limit >>= 1; 370 371 /* 372 * If we're within max_record_sz of the limit, we must 373 * pad, move the head index and recompute the limit. 374 */ 375 if (limit - head < spe_pmu->max_record_sz) { 376 arm_spe_pmu_pad_buf(handle, limit - head); 377 handle->head = PERF_IDX2OFF(limit, buf); 378 limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head; 379 } 380 381 return limit; 382 } 383 384 static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle) 385 { 386 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu); 387 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 388 const u64 bufsize = buf->nr_pages * PAGE_SIZE; 389 u64 limit = bufsize; 390 u64 head, tail, wakeup; 391 392 /* 393 * The head can be misaligned for two reasons: 394 * 395 * 1. The hardware left PMBPTR pointing to the first byte after 396 * a record when generating a buffer management event. 397 * 398 * 2. We used perf_aux_output_skip to consume handle->size bytes 399 * and CIRC_SPACE was used to compute the size, which always 400 * leaves one entry free. 401 * 402 * Deal with this by padding to the next alignment boundary and 403 * moving the head index. If we run out of buffer space, we'll 404 * reduce handle->size to zero and end up reporting truncation. 405 */ 406 head = PERF_IDX2OFF(handle->head, buf); 407 if (!IS_ALIGNED(head, spe_pmu->align)) { 408 unsigned long delta = roundup(head, spe_pmu->align) - head; 409 410 delta = min(delta, handle->size); 411 arm_spe_pmu_pad_buf(handle, delta); 412 head = PERF_IDX2OFF(handle->head, buf); 413 } 414 415 /* If we've run out of free space, then nothing more to do */ 416 if (!handle->size) 417 goto no_space; 418 419 /* Compute the tail and wakeup indices now that we've aligned head */ 420 tail = PERF_IDX2OFF(handle->head + handle->size, buf); 421 wakeup = PERF_IDX2OFF(handle->wakeup, buf); 422 423 /* 424 * Avoid clobbering unconsumed data. We know we have space, so 425 * if we see head == tail we know that the buffer is empty. If 426 * head > tail, then there's nothing to clobber prior to 427 * wrapping. 428 */ 429 if (head < tail) 430 limit = round_down(tail, PAGE_SIZE); 431 432 /* 433 * Wakeup may be arbitrarily far into the future. If it's not in 434 * the current generation, either we'll wrap before hitting it, 435 * or it's in the past and has been handled already. 436 * 437 * If there's a wakeup before we wrap, arrange to be woken up by 438 * the page boundary following it. Keep the tail boundary if 439 * that's lower. 440 */ 441 if (handle->wakeup < (handle->head + handle->size) && head <= wakeup) 442 limit = min(limit, round_up(wakeup, PAGE_SIZE)); 443 444 if (limit > head) 445 return limit; 446 447 arm_spe_pmu_pad_buf(handle, handle->size); 448 no_space: 449 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 450 perf_aux_output_end(handle, 0); 451 return 0; 452 } 453 454 static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle) 455 { 456 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 457 struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu); 458 u64 limit = __arm_spe_pmu_next_off(handle); 459 u64 head = PERF_IDX2OFF(handle->head, buf); 460 461 /* 462 * If the head has come too close to the end of the buffer, 463 * then pad to the end and recompute the limit. 464 */ 465 if (limit && (limit - head < spe_pmu->max_record_sz)) { 466 arm_spe_pmu_pad_buf(handle, limit - head); 467 limit = __arm_spe_pmu_next_off(handle); 468 } 469 470 return limit; 471 } 472 473 static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, 474 struct perf_event *event) 475 { 476 u64 base, limit; 477 struct arm_spe_pmu_buf *buf; 478 479 /* Start a new aux session */ 480 buf = perf_aux_output_begin(handle, event); 481 if (!buf) { 482 event->hw.state |= PERF_HES_STOPPED; 483 /* 484 * We still need to clear the limit pointer, since the 485 * profiler might only be disabled by virtue of a fault. 486 */ 487 limit = 0; 488 goto out_write_limit; 489 } 490 491 limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) 492 : arm_spe_pmu_next_off(handle); 493 if (limit) 494 limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT); 495 496 limit += (u64)buf->base; 497 base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); 498 write_sysreg_s(base, SYS_PMBPTR_EL1); 499 500 out_write_limit: 501 write_sysreg_s(limit, SYS_PMBLIMITR_EL1); 502 } 503 504 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle) 505 { 506 struct arm_spe_pmu_buf *buf = perf_get_aux(handle); 507 u64 offset, size; 508 509 offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base; 510 size = offset - PERF_IDX2OFF(handle->head, buf); 511 512 if (buf->snapshot) 513 handle->head = offset; 514 515 perf_aux_output_end(handle, size); 516 } 517 518 static void arm_spe_pmu_disable_and_drain_local(void) 519 { 520 /* Disable profiling at EL0 and EL1 */ 521 write_sysreg_s(0, SYS_PMSCR_EL1); 522 isb(); 523 524 /* Drain any buffered data */ 525 psb_csync(); 526 dsb(nsh); 527 528 /* Disable the profiling buffer */ 529 write_sysreg_s(0, SYS_PMBLIMITR_EL1); 530 isb(); 531 } 532 533 /* IRQ handling */ 534 static enum arm_spe_pmu_buf_fault_action 535 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) 536 { 537 const char *err_str; 538 u64 pmbsr; 539 enum arm_spe_pmu_buf_fault_action ret; 540 541 /* 542 * Ensure new profiling data is visible to the CPU and any external 543 * aborts have been resolved. 544 */ 545 psb_csync(); 546 dsb(nsh); 547 548 /* Ensure hardware updates to PMBPTR_EL1 are visible */ 549 isb(); 550 551 /* Service required? */ 552 pmbsr = read_sysreg_s(SYS_PMBSR_EL1); 553 if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) 554 return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; 555 556 /* 557 * If we've lost data, disable profiling and also set the PARTIAL 558 * flag to indicate that the last record is corrupted. 559 */ 560 if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) 561 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | 562 PERF_AUX_FLAG_PARTIAL); 563 564 /* Report collisions to userspace so that it can up the period */ 565 if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) 566 perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); 567 568 /* We only expect buffer management events */ 569 switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) { 570 case SYS_PMBSR_EL1_EC_BUF: 571 /* Handled below */ 572 break; 573 case SYS_PMBSR_EL1_EC_FAULT_S1: 574 case SYS_PMBSR_EL1_EC_FAULT_S2: 575 err_str = "Unexpected buffer fault"; 576 goto out_err; 577 default: 578 err_str = "Unknown error code"; 579 goto out_err; 580 } 581 582 /* Buffer management event */ 583 switch (pmbsr & 584 (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) { 585 case SYS_PMBSR_EL1_BUF_BSC_FULL: 586 ret = SPE_PMU_BUF_FAULT_ACT_OK; 587 goto out_stop; 588 default: 589 err_str = "Unknown buffer status code"; 590 } 591 592 out_err: 593 pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n", 594 err_str, smp_processor_id(), pmbsr, 595 read_sysreg_s(SYS_PMBPTR_EL1), 596 read_sysreg_s(SYS_PMBLIMITR_EL1)); 597 ret = SPE_PMU_BUF_FAULT_ACT_FATAL; 598 599 out_stop: 600 arm_spe_perf_aux_output_end(handle); 601 return ret; 602 } 603 604 static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev) 605 { 606 struct perf_output_handle *handle = dev; 607 struct perf_event *event = handle->event; 608 enum arm_spe_pmu_buf_fault_action act; 609 610 if (!perf_get_aux(handle)) 611 return IRQ_NONE; 612 613 act = arm_spe_pmu_buf_get_fault_act(handle); 614 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS) 615 return IRQ_NONE; 616 617 /* 618 * Ensure perf callbacks have completed, which may disable the 619 * profiling buffer in response to a TRUNCATION flag. 620 */ 621 irq_work_run(); 622 623 switch (act) { 624 case SPE_PMU_BUF_FAULT_ACT_FATAL: 625 /* 626 * If a fatal exception occurred then leaving the profiling 627 * buffer enabled is a recipe waiting to happen. Since 628 * fatal faults don't always imply truncation, make sure 629 * that the profiling buffer is disabled explicitly before 630 * clearing the syndrome register. 631 */ 632 arm_spe_pmu_disable_and_drain_local(); 633 break; 634 case SPE_PMU_BUF_FAULT_ACT_OK: 635 /* 636 * We handled the fault (the buffer was full), so resume 637 * profiling as long as we didn't detect truncation. 638 * PMBPTR might be misaligned, but we'll burn that bridge 639 * when we get to it. 640 */ 641 if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) { 642 arm_spe_perf_aux_output_begin(handle, event); 643 isb(); 644 } 645 break; 646 case SPE_PMU_BUF_FAULT_ACT_SPURIOUS: 647 /* We've seen you before, but GCC has the memory of a sieve. */ 648 break; 649 } 650 651 /* The buffer pointers are now sane, so resume profiling. */ 652 write_sysreg_s(0, SYS_PMBSR_EL1); 653 return IRQ_HANDLED; 654 } 655 656 static u64 arm_spe_pmsevfr_res0(u16 pmsver) 657 { 658 switch (pmsver) { 659 case ID_AA64DFR0_PMSVER_8_2: 660 return SYS_PMSEVFR_EL1_RES0_8_2; 661 case ID_AA64DFR0_PMSVER_8_3: 662 /* Return the highest version we support in default */ 663 default: 664 return SYS_PMSEVFR_EL1_RES0_8_3; 665 } 666 } 667 668 /* Perf callbacks */ 669 static int arm_spe_pmu_event_init(struct perf_event *event) 670 { 671 u64 reg; 672 struct perf_event_attr *attr = &event->attr; 673 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 674 675 /* This is, of course, deeply driver-specific */ 676 if (attr->type != event->pmu->type) 677 return -ENOENT; 678 679 if (event->cpu >= 0 && 680 !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus)) 681 return -ENOENT; 682 683 if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver)) 684 return -EOPNOTSUPP; 685 686 if (attr->exclude_idle) 687 return -EOPNOTSUPP; 688 689 /* 690 * Feedback-directed frequency throttling doesn't work when we 691 * have a buffer of samples. We'd need to manually count the 692 * samples in the buffer when it fills up and adjust the event 693 * count to reflect that. Instead, just force the user to specify 694 * a sample period. 695 */ 696 if (attr->freq) 697 return -EINVAL; 698 699 reg = arm_spe_event_to_pmsfcr(event); 700 if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && 701 !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) 702 return -EOPNOTSUPP; 703 704 if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && 705 !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) 706 return -EOPNOTSUPP; 707 708 if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && 709 !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) 710 return -EOPNOTSUPP; 711 712 reg = arm_spe_event_to_pmscr(event); 713 if (!perfmon_capable() && 714 (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | 715 BIT(SYS_PMSCR_EL1_CX_SHIFT) | 716 BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) 717 return -EACCES; 718 719 return 0; 720 } 721 722 static void arm_spe_pmu_start(struct perf_event *event, int flags) 723 { 724 u64 reg; 725 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 726 struct hw_perf_event *hwc = &event->hw; 727 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle); 728 729 hwc->state = 0; 730 arm_spe_perf_aux_output_begin(handle, event); 731 if (hwc->state) 732 return; 733 734 reg = arm_spe_event_to_pmsfcr(event); 735 write_sysreg_s(reg, SYS_PMSFCR_EL1); 736 737 reg = arm_spe_event_to_pmsevfr(event); 738 write_sysreg_s(reg, SYS_PMSEVFR_EL1); 739 740 reg = arm_spe_event_to_pmslatfr(event); 741 write_sysreg_s(reg, SYS_PMSLATFR_EL1); 742 743 if (flags & PERF_EF_RELOAD) { 744 reg = arm_spe_event_to_pmsirr(event); 745 write_sysreg_s(reg, SYS_PMSIRR_EL1); 746 isb(); 747 reg = local64_read(&hwc->period_left); 748 write_sysreg_s(reg, SYS_PMSICR_EL1); 749 } 750 751 reg = arm_spe_event_to_pmscr(event); 752 isb(); 753 write_sysreg_s(reg, SYS_PMSCR_EL1); 754 } 755 756 static void arm_spe_pmu_stop(struct perf_event *event, int flags) 757 { 758 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 759 struct hw_perf_event *hwc = &event->hw; 760 struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle); 761 762 /* If we're already stopped, then nothing to do */ 763 if (hwc->state & PERF_HES_STOPPED) 764 return; 765 766 /* Stop all trace generation */ 767 arm_spe_pmu_disable_and_drain_local(); 768 769 if (flags & PERF_EF_UPDATE) { 770 /* 771 * If there's a fault pending then ensure we contain it 772 * to this buffer, since we might be on the context-switch 773 * path. 774 */ 775 if (perf_get_aux(handle)) { 776 enum arm_spe_pmu_buf_fault_action act; 777 778 act = arm_spe_pmu_buf_get_fault_act(handle); 779 if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS) 780 arm_spe_perf_aux_output_end(handle); 781 else 782 write_sysreg_s(0, SYS_PMBSR_EL1); 783 } 784 785 /* 786 * This may also contain ECOUNT, but nobody else should 787 * be looking at period_left, since we forbid frequency 788 * based sampling. 789 */ 790 local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1)); 791 hwc->state |= PERF_HES_UPTODATE; 792 } 793 794 hwc->state |= PERF_HES_STOPPED; 795 } 796 797 static int arm_spe_pmu_add(struct perf_event *event, int flags) 798 { 799 int ret = 0; 800 struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); 801 struct hw_perf_event *hwc = &event->hw; 802 int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu; 803 804 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus)) 805 return -ENOENT; 806 807 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 808 809 if (flags & PERF_EF_START) { 810 arm_spe_pmu_start(event, PERF_EF_RELOAD); 811 if (hwc->state & PERF_HES_STOPPED) 812 ret = -EINVAL; 813 } 814 815 return ret; 816 } 817 818 static void arm_spe_pmu_del(struct perf_event *event, int flags) 819 { 820 arm_spe_pmu_stop(event, PERF_EF_UPDATE); 821 } 822 823 static void arm_spe_pmu_read(struct perf_event *event) 824 { 825 } 826 827 static void *arm_spe_pmu_setup_aux(struct perf_event *event, void **pages, 828 int nr_pages, bool snapshot) 829 { 830 int i, cpu = event->cpu; 831 struct page **pglist; 832 struct arm_spe_pmu_buf *buf; 833 834 /* We need at least two pages for this to work. */ 835 if (nr_pages < 2) 836 return NULL; 837 838 /* 839 * We require an even number of pages for snapshot mode, so that 840 * we can effectively treat the buffer as consisting of two equal 841 * parts and give userspace a fighting chance of getting some 842 * useful data out of it. 843 */ 844 if (snapshot && (nr_pages & 1)) 845 return NULL; 846 847 if (cpu == -1) 848 cpu = raw_smp_processor_id(); 849 850 buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu)); 851 if (!buf) 852 return NULL; 853 854 pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL); 855 if (!pglist) 856 goto out_free_buf; 857 858 for (i = 0; i < nr_pages; ++i) 859 pglist[i] = virt_to_page(pages[i]); 860 861 buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL); 862 if (!buf->base) 863 goto out_free_pglist; 864 865 buf->nr_pages = nr_pages; 866 buf->snapshot = snapshot; 867 868 kfree(pglist); 869 return buf; 870 871 out_free_pglist: 872 kfree(pglist); 873 out_free_buf: 874 kfree(buf); 875 return NULL; 876 } 877 878 static void arm_spe_pmu_free_aux(void *aux) 879 { 880 struct arm_spe_pmu_buf *buf = aux; 881 882 vunmap(buf->base); 883 kfree(buf); 884 } 885 886 /* Initialisation and teardown functions */ 887 static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu) 888 { 889 static atomic_t pmu_idx = ATOMIC_INIT(-1); 890 891 int idx; 892 char *name; 893 struct device *dev = &spe_pmu->pdev->dev; 894 895 spe_pmu->pmu = (struct pmu) { 896 .module = THIS_MODULE, 897 .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, 898 .attr_groups = arm_spe_pmu_attr_groups, 899 /* 900 * We hitch a ride on the software context here, so that 901 * we can support per-task profiling (which is not possible 902 * with the invalid context as it doesn't get sched callbacks). 903 * This requires that userspace either uses a dummy event for 904 * perf_event_open, since the aux buffer is not setup until 905 * a subsequent mmap, or creates the profiling event in a 906 * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it 907 * once the buffer has been created. 908 */ 909 .task_ctx_nr = perf_sw_context, 910 .event_init = arm_spe_pmu_event_init, 911 .add = arm_spe_pmu_add, 912 .del = arm_spe_pmu_del, 913 .start = arm_spe_pmu_start, 914 .stop = arm_spe_pmu_stop, 915 .read = arm_spe_pmu_read, 916 .setup_aux = arm_spe_pmu_setup_aux, 917 .free_aux = arm_spe_pmu_free_aux, 918 }; 919 920 idx = atomic_inc_return(&pmu_idx); 921 name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx); 922 if (!name) { 923 dev_err(dev, "failed to allocate name for pmu %d\n", idx); 924 return -ENOMEM; 925 } 926 927 return perf_pmu_register(&spe_pmu->pmu, name, -1); 928 } 929 930 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu) 931 { 932 perf_pmu_unregister(&spe_pmu->pmu); 933 } 934 935 static void __arm_spe_pmu_dev_probe(void *info) 936 { 937 int fld; 938 u64 reg; 939 struct arm_spe_pmu *spe_pmu = info; 940 struct device *dev = &spe_pmu->pdev->dev; 941 942 fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1), 943 ID_AA64DFR0_PMSVER_SHIFT); 944 if (!fld) { 945 dev_err(dev, 946 "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n", 947 fld, smp_processor_id()); 948 return; 949 } 950 spe_pmu->pmsver = (u16)fld; 951 952 /* Read PMBIDR first to determine whether or not we have access */ 953 reg = read_sysreg_s(SYS_PMBIDR_EL1); 954 if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { 955 dev_err(dev, 956 "profiling buffer owned by higher exception level\n"); 957 return; 958 } 959 960 /* Minimum alignment. If it's out-of-range, then fail the probe */ 961 fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; 962 spe_pmu->align = 1 << fld; 963 if (spe_pmu->align > SZ_2K) { 964 dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", 965 fld, smp_processor_id()); 966 return; 967 } 968 969 /* It's now safe to read PMSIDR and figure out what we've got */ 970 reg = read_sysreg_s(SYS_PMSIDR_EL1); 971 if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) 972 spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; 973 974 if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) 975 spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP; 976 977 if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) 978 spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT; 979 980 if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) 981 spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST; 982 983 if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) 984 spe_pmu->features |= SPE_PMU_FEAT_LDS; 985 986 if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) 987 spe_pmu->features |= SPE_PMU_FEAT_ERND; 988 989 /* This field has a spaced out encoding, so just use a look-up */ 990 fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK; 991 switch (fld) { 992 case 0: 993 spe_pmu->min_period = 256; 994 break; 995 case 2: 996 spe_pmu->min_period = 512; 997 break; 998 case 3: 999 spe_pmu->min_period = 768; 1000 break; 1001 case 4: 1002 spe_pmu->min_period = 1024; 1003 break; 1004 case 5: 1005 spe_pmu->min_period = 1536; 1006 break; 1007 case 6: 1008 spe_pmu->min_period = 2048; 1009 break; 1010 case 7: 1011 spe_pmu->min_period = 3072; 1012 break; 1013 default: 1014 dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n", 1015 fld); 1016 fallthrough; 1017 case 8: 1018 spe_pmu->min_period = 4096; 1019 } 1020 1021 /* Maximum record size. If it's out-of-range, then fail the probe */ 1022 fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; 1023 spe_pmu->max_record_sz = 1 << fld; 1024 if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { 1025 dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", 1026 fld, smp_processor_id()); 1027 return; 1028 } 1029 1030 fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK; 1031 switch (fld) { 1032 default: 1033 dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", 1034 fld); 1035 fallthrough; 1036 case 2: 1037 spe_pmu->counter_sz = 12; 1038 break; 1039 case 3: 1040 spe_pmu->counter_sz = 16; 1041 } 1042 1043 dev_info(dev, 1044 "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n", 1045 cpumask_pr_args(&spe_pmu->supported_cpus), 1046 spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features); 1047 1048 spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED; 1049 } 1050 1051 static void __arm_spe_pmu_reset_local(void) 1052 { 1053 /* 1054 * This is probably overkill, as we have no idea where we're 1055 * draining any buffered data to... 1056 */ 1057 arm_spe_pmu_disable_and_drain_local(); 1058 1059 /* Reset the buffer base pointer */ 1060 write_sysreg_s(0, SYS_PMBPTR_EL1); 1061 isb(); 1062 1063 /* Clear any pending management interrupts */ 1064 write_sysreg_s(0, SYS_PMBSR_EL1); 1065 isb(); 1066 } 1067 1068 static void __arm_spe_pmu_setup_one(void *info) 1069 { 1070 struct arm_spe_pmu *spe_pmu = info; 1071 1072 __arm_spe_pmu_reset_local(); 1073 enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE); 1074 } 1075 1076 static void __arm_spe_pmu_stop_one(void *info) 1077 { 1078 struct arm_spe_pmu *spe_pmu = info; 1079 1080 disable_percpu_irq(spe_pmu->irq); 1081 __arm_spe_pmu_reset_local(); 1082 } 1083 1084 static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node) 1085 { 1086 struct arm_spe_pmu *spe_pmu; 1087 1088 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node); 1089 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus)) 1090 return 0; 1091 1092 __arm_spe_pmu_setup_one(spe_pmu); 1093 return 0; 1094 } 1095 1096 static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node) 1097 { 1098 struct arm_spe_pmu *spe_pmu; 1099 1100 spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node); 1101 if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus)) 1102 return 0; 1103 1104 __arm_spe_pmu_stop_one(spe_pmu); 1105 return 0; 1106 } 1107 1108 static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu) 1109 { 1110 int ret; 1111 cpumask_t *mask = &spe_pmu->supported_cpus; 1112 1113 /* Make sure we probe the hardware on a relevant CPU */ 1114 ret = smp_call_function_any(mask, __arm_spe_pmu_dev_probe, spe_pmu, 1); 1115 if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED)) 1116 return -ENXIO; 1117 1118 /* Request our PPIs (note that the IRQ is still disabled) */ 1119 ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME, 1120 spe_pmu->handle); 1121 if (ret) 1122 return ret; 1123 1124 /* 1125 * Register our hotplug notifier now so we don't miss any events. 1126 * This will enable the IRQ for any supported CPUs that are already 1127 * up. 1128 */ 1129 ret = cpuhp_state_add_instance(arm_spe_pmu_online, 1130 &spe_pmu->hotplug_node); 1131 if (ret) 1132 free_percpu_irq(spe_pmu->irq, spe_pmu->handle); 1133 1134 return ret; 1135 } 1136 1137 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu) 1138 { 1139 cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node); 1140 free_percpu_irq(spe_pmu->irq, spe_pmu->handle); 1141 } 1142 1143 /* Driver and device probing */ 1144 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu) 1145 { 1146 struct platform_device *pdev = spe_pmu->pdev; 1147 int irq = platform_get_irq(pdev, 0); 1148 1149 if (irq < 0) 1150 return -ENXIO; 1151 1152 if (!irq_is_percpu(irq)) { 1153 dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq); 1154 return -EINVAL; 1155 } 1156 1157 if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) { 1158 dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq); 1159 return -EINVAL; 1160 } 1161 1162 spe_pmu->irq = irq; 1163 return 0; 1164 } 1165 1166 static const struct of_device_id arm_spe_pmu_of_match[] = { 1167 { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 }, 1168 { /* Sentinel */ }, 1169 }; 1170 MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match); 1171 1172 static const struct platform_device_id arm_spe_match[] = { 1173 { ARMV8_SPE_PDEV_NAME, 0}, 1174 { } 1175 }; 1176 MODULE_DEVICE_TABLE(platform, arm_spe_match); 1177 1178 static int arm_spe_pmu_device_probe(struct platform_device *pdev) 1179 { 1180 int ret; 1181 struct arm_spe_pmu *spe_pmu; 1182 struct device *dev = &pdev->dev; 1183 1184 /* 1185 * If kernelspace is unmapped when running at EL0, then the SPE 1186 * buffer will fault and prematurely terminate the AUX session. 1187 */ 1188 if (arm64_kernel_unmapped_at_el0()) { 1189 dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n"); 1190 return -EPERM; 1191 } 1192 1193 spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL); 1194 if (!spe_pmu) 1195 return -ENOMEM; 1196 1197 spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle)); 1198 if (!spe_pmu->handle) 1199 return -ENOMEM; 1200 1201 spe_pmu->pdev = pdev; 1202 platform_set_drvdata(pdev, spe_pmu); 1203 1204 ret = arm_spe_pmu_irq_probe(spe_pmu); 1205 if (ret) 1206 goto out_free_handle; 1207 1208 ret = arm_spe_pmu_dev_init(spe_pmu); 1209 if (ret) 1210 goto out_free_handle; 1211 1212 ret = arm_spe_pmu_perf_init(spe_pmu); 1213 if (ret) 1214 goto out_teardown_dev; 1215 1216 return 0; 1217 1218 out_teardown_dev: 1219 arm_spe_pmu_dev_teardown(spe_pmu); 1220 out_free_handle: 1221 free_percpu(spe_pmu->handle); 1222 return ret; 1223 } 1224 1225 static int arm_spe_pmu_device_remove(struct platform_device *pdev) 1226 { 1227 struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev); 1228 1229 arm_spe_pmu_perf_destroy(spe_pmu); 1230 arm_spe_pmu_dev_teardown(spe_pmu); 1231 free_percpu(spe_pmu->handle); 1232 return 0; 1233 } 1234 1235 static struct platform_driver arm_spe_pmu_driver = { 1236 .id_table = arm_spe_match, 1237 .driver = { 1238 .name = DRVNAME, 1239 .of_match_table = of_match_ptr(arm_spe_pmu_of_match), 1240 .suppress_bind_attrs = true, 1241 }, 1242 .probe = arm_spe_pmu_device_probe, 1243 .remove = arm_spe_pmu_device_remove, 1244 }; 1245 1246 static int __init arm_spe_pmu_init(void) 1247 { 1248 int ret; 1249 1250 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME, 1251 arm_spe_pmu_cpu_startup, 1252 arm_spe_pmu_cpu_teardown); 1253 if (ret < 0) 1254 return ret; 1255 arm_spe_pmu_online = ret; 1256 1257 ret = platform_driver_register(&arm_spe_pmu_driver); 1258 if (ret) 1259 cpuhp_remove_multi_state(arm_spe_pmu_online); 1260 1261 return ret; 1262 } 1263 1264 static void __exit arm_spe_pmu_exit(void) 1265 { 1266 platform_driver_unregister(&arm_spe_pmu_driver); 1267 cpuhp_remove_multi_state(arm_spe_pmu_online); 1268 } 1269 1270 module_init(arm_spe_pmu_init); 1271 module_exit(arm_spe_pmu_exit); 1272 1273 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension"); 1274 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); 1275 MODULE_LICENSE("GPL v2"); 1276