1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARMv8 PMUv3 Performance Events handling code. 4 * 5 * Copyright (C) 2012 ARM Limited 6 * Author: Will Deacon <will.deacon@arm.com> 7 * 8 * This code is based heavily on the ARMv7 perf event code. 9 */ 10 11 #include <asm/irq_regs.h> 12 #include <asm/perf_event.h> 13 #include <asm/virt.h> 14 15 #include <clocksource/arm_arch_timer.h> 16 17 #include <linux/acpi.h> 18 #include <linux/bitfield.h> 19 #include <linux/clocksource.h> 20 #include <linux/of.h> 21 #include <linux/perf/arm_pmu.h> 22 #include <linux/perf/arm_pmuv3.h> 23 #include <linux/platform_device.h> 24 #include <linux/sched_clock.h> 25 #include <linux/smp.h> 26 #include <linux/nmi.h> 27 28 /* ARMv8 Cortex-A53 specific event types. */ 29 #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 30 31 /* ARMv8 Cavium ThunderX specific event types. */ 32 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9 33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA 34 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB 35 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC 36 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED 37 38 /* 39 * ARMv8 Architectural defined events, not all of these may 40 * be supported on any given implementation. Unsupported events will 41 * be disabled at run-time based on the PMCEID registers. 42 */ 43 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { 44 PERF_MAP_ALL_UNSUPPORTED, 45 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, 46 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, 47 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 48 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 49 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 50 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, 51 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, 52 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, 53 }; 54 55 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 56 [PERF_COUNT_HW_CACHE_OP_MAX] 57 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 58 PERF_CACHE_MAP_ALL_UNSUPPORTED, 59 60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 62 63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, 64 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, 65 66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, 67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB, 68 69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, 70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB, 71 72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD, 73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD, 74 75 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, 76 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 77 }; 78 79 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 80 [PERF_COUNT_HW_CACHE_OP_MAX] 81 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 82 PERF_CACHE_MAP_ALL_UNSUPPORTED, 83 84 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL, 85 86 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 87 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 88 }; 89 90 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 91 [PERF_COUNT_HW_CACHE_OP_MAX] 92 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 93 PERF_CACHE_MAP_ALL_UNSUPPORTED, 94 95 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 96 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 97 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 98 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 99 100 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 101 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 102 103 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 104 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 105 }; 106 107 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 108 [PERF_COUNT_HW_CACHE_OP_MAX] 109 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 110 PERF_CACHE_MAP_ALL_UNSUPPORTED, 111 112 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 113 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 114 }; 115 116 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 117 [PERF_COUNT_HW_CACHE_OP_MAX] 118 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 119 PERF_CACHE_MAP_ALL_UNSUPPORTED, 120 121 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 122 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 123 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 124 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST, 125 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS, 126 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS, 127 128 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, 129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, 130 131 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 132 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 133 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 134 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 135 }; 136 137 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 138 [PERF_COUNT_HW_CACHE_OP_MAX] 139 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 140 PERF_CACHE_MAP_ALL_UNSUPPORTED, 141 142 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 143 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 144 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 145 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 146 147 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 148 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 149 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 150 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 151 152 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 153 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 154 }; 155 156 static ssize_t 157 armv8pmu_events_sysfs_show(struct device *dev, 158 struct device_attribute *attr, char *page) 159 { 160 struct perf_pmu_events_attr *pmu_attr; 161 162 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 163 164 return sprintf(page, "event=0x%04llx\n", pmu_attr->id); 165 } 166 167 #define ARMV8_EVENT_ATTR(name, config) \ 168 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config) 169 170 static struct attribute *armv8_pmuv3_event_attrs[] = { 171 /* 172 * Don't expose the sw_incr event in /sys. It's not usable as writes to 173 * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation 174 * means we don't have a fixed event<->counter relationship regardless. 175 */ 176 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), 177 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), 178 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), 179 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE), 180 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL), 181 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED), 182 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED), 183 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED), 184 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN), 185 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN), 186 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED), 187 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED), 188 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED), 189 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED), 190 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED), 191 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED), 192 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES), 193 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED), 194 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS), 195 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE), 196 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB), 197 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE), 198 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL), 199 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB), 200 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS), 201 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR), 202 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC), 203 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED), 204 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES), 205 /* Don't expose the chain event in /sys, since it's useless in isolation */ 206 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE), 207 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE), 208 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED), 209 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED), 210 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND), 211 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND), 212 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB), 213 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB), 214 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE), 215 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL), 216 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE), 217 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL), 218 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE), 219 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB), 220 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL), 221 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL), 222 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB), 223 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB), 224 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS), 225 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE), 226 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS), 227 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK), 228 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK), 229 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD), 230 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD), 231 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD), 232 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD), 233 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED), 234 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC), 235 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL), 236 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND), 237 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND), 238 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT), 239 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP), 240 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED), 241 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE), 242 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION), 243 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES), 244 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM), 245 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS), 246 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD), 247 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS), 248 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD), 249 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP), 250 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG), 251 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0), 252 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1), 253 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2), 254 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3), 255 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4), 256 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5), 257 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6), 258 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7), 259 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT), 260 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT), 261 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT), 262 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED), 263 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD), 264 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR), 265 NULL, 266 }; 267 268 static umode_t 269 armv8pmu_event_attr_is_visible(struct kobject *kobj, 270 struct attribute *attr, int unused) 271 { 272 struct device *dev = kobj_to_dev(kobj); 273 struct pmu *pmu = dev_get_drvdata(dev); 274 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 275 struct perf_pmu_events_attr *pmu_attr; 276 277 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); 278 279 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 280 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) 281 return attr->mode; 282 283 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { 284 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; 285 286 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 287 test_bit(id, cpu_pmu->pmceid_ext_bitmap)) 288 return attr->mode; 289 } 290 291 return 0; 292 } 293 294 static const struct attribute_group armv8_pmuv3_events_attr_group = { 295 .name = "events", 296 .attrs = armv8_pmuv3_event_attrs, 297 .is_visible = armv8pmu_event_attr_is_visible, 298 }; 299 300 /* User ABI */ 301 #define ATTR_CFG_FLD_event_CFG config 302 #define ATTR_CFG_FLD_event_LO 0 303 #define ATTR_CFG_FLD_event_HI 15 304 #define ATTR_CFG_FLD_long_CFG config1 305 #define ATTR_CFG_FLD_long_LO 0 306 #define ATTR_CFG_FLD_long_HI 0 307 #define ATTR_CFG_FLD_rdpmc_CFG config1 308 #define ATTR_CFG_FLD_rdpmc_LO 1 309 #define ATTR_CFG_FLD_rdpmc_HI 1 310 #define ATTR_CFG_FLD_threshold_count_CFG config1 /* PMEVTYPER.TC[0] */ 311 #define ATTR_CFG_FLD_threshold_count_LO 2 312 #define ATTR_CFG_FLD_threshold_count_HI 2 313 #define ATTR_CFG_FLD_threshold_compare_CFG config1 /* PMEVTYPER.TC[2:1] */ 314 #define ATTR_CFG_FLD_threshold_compare_LO 3 315 #define ATTR_CFG_FLD_threshold_compare_HI 4 316 #define ATTR_CFG_FLD_threshold_CFG config1 /* PMEVTYPER.TH */ 317 #define ATTR_CFG_FLD_threshold_LO 5 318 #define ATTR_CFG_FLD_threshold_HI 16 319 320 GEN_PMU_FORMAT_ATTR(event); 321 GEN_PMU_FORMAT_ATTR(long); 322 GEN_PMU_FORMAT_ATTR(rdpmc); 323 GEN_PMU_FORMAT_ATTR(threshold_count); 324 GEN_PMU_FORMAT_ATTR(threshold_compare); 325 GEN_PMU_FORMAT_ATTR(threshold); 326 327 static int sysctl_perf_user_access __read_mostly; 328 329 static bool armv8pmu_event_is_64bit(struct perf_event *event) 330 { 331 return ATTR_CFG_GET_FLD(&event->attr, long); 332 } 333 334 static bool armv8pmu_event_want_user_access(struct perf_event *event) 335 { 336 return ATTR_CFG_GET_FLD(&event->attr, rdpmc); 337 } 338 339 static u32 armv8pmu_event_get_threshold(struct perf_event_attr *attr) 340 { 341 return ATTR_CFG_GET_FLD(attr, threshold); 342 } 343 344 static u8 armv8pmu_event_threshold_control(struct perf_event_attr *attr) 345 { 346 u8 th_compare = ATTR_CFG_GET_FLD(attr, threshold_compare); 347 u8 th_count = ATTR_CFG_GET_FLD(attr, threshold_count); 348 349 /* 350 * The count bit is always the bottom bit of the full control field, and 351 * the comparison is the upper two bits, but it's not explicitly 352 * labelled in the Arm ARM. For the Perf interface we split it into two 353 * fields, so reconstruct it here. 354 */ 355 return (th_compare << 1) | th_count; 356 } 357 358 static struct attribute *armv8_pmuv3_format_attrs[] = { 359 &format_attr_event.attr, 360 &format_attr_long.attr, 361 &format_attr_rdpmc.attr, 362 &format_attr_threshold.attr, 363 &format_attr_threshold_compare.attr, 364 &format_attr_threshold_count.attr, 365 NULL, 366 }; 367 368 static const struct attribute_group armv8_pmuv3_format_attr_group = { 369 .name = "format", 370 .attrs = armv8_pmuv3_format_attrs, 371 }; 372 373 static ssize_t slots_show(struct device *dev, struct device_attribute *attr, 374 char *page) 375 { 376 struct pmu *pmu = dev_get_drvdata(dev); 377 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 378 u32 slots = FIELD_GET(ARMV8_PMU_SLOTS, cpu_pmu->reg_pmmir); 379 380 return sysfs_emit(page, "0x%08x\n", slots); 381 } 382 383 static DEVICE_ATTR_RO(slots); 384 385 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr, 386 char *page) 387 { 388 struct pmu *pmu = dev_get_drvdata(dev); 389 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 390 u32 bus_slots = FIELD_GET(ARMV8_PMU_BUS_SLOTS, cpu_pmu->reg_pmmir); 391 392 return sysfs_emit(page, "0x%08x\n", bus_slots); 393 } 394 395 static DEVICE_ATTR_RO(bus_slots); 396 397 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr, 398 char *page) 399 { 400 struct pmu *pmu = dev_get_drvdata(dev); 401 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 402 u32 bus_width = FIELD_GET(ARMV8_PMU_BUS_WIDTH, cpu_pmu->reg_pmmir); 403 u32 val = 0; 404 405 /* Encoded as Log2(number of bytes), plus one */ 406 if (bus_width > 2 && bus_width < 13) 407 val = 1 << (bus_width - 1); 408 409 return sysfs_emit(page, "0x%08x\n", val); 410 } 411 412 static DEVICE_ATTR_RO(bus_width); 413 414 static u32 threshold_max(struct arm_pmu *cpu_pmu) 415 { 416 /* 417 * PMMIR.THWIDTH is readable and non-zero on aarch32, but it would be 418 * impossible to write the threshold in the upper 32 bits of PMEVTYPER. 419 */ 420 if (IS_ENABLED(CONFIG_ARM)) 421 return 0; 422 423 /* 424 * The largest value that can be written to PMEVTYPER<n>_EL0.TH is 425 * (2 ^ PMMIR.THWIDTH) - 1. 426 */ 427 return (1 << FIELD_GET(ARMV8_PMU_THWIDTH, cpu_pmu->reg_pmmir)) - 1; 428 } 429 430 static ssize_t threshold_max_show(struct device *dev, 431 struct device_attribute *attr, char *page) 432 { 433 struct pmu *pmu = dev_get_drvdata(dev); 434 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 435 436 return sysfs_emit(page, "0x%08x\n", threshold_max(cpu_pmu)); 437 } 438 439 static DEVICE_ATTR_RO(threshold_max); 440 441 static struct attribute *armv8_pmuv3_caps_attrs[] = { 442 &dev_attr_slots.attr, 443 &dev_attr_bus_slots.attr, 444 &dev_attr_bus_width.attr, 445 &dev_attr_threshold_max.attr, 446 NULL, 447 }; 448 449 static const struct attribute_group armv8_pmuv3_caps_attr_group = { 450 .name = "caps", 451 .attrs = armv8_pmuv3_caps_attrs, 452 }; 453 454 /* 455 * We unconditionally enable ARMv8.5-PMU long event counter support 456 * (64-bit events) where supported. Indicate if this arm_pmu has long 457 * event counter support. 458 * 459 * On AArch32, long counters make no sense (you can't access the top 460 * bits), so we only enable this on AArch64. 461 */ 462 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) 463 { 464 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver)); 465 } 466 467 static bool armv8pmu_event_has_user_read(struct perf_event *event) 468 { 469 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT; 470 } 471 472 /* 473 * We must chain two programmable counters for 64 bit events, 474 * except when we have allocated the 64bit cycle counter (for CPU 475 * cycles event) or when user space counter access is enabled. 476 */ 477 static bool armv8pmu_event_is_chained(struct perf_event *event) 478 { 479 int idx = event->hw.idx; 480 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 481 482 return !armv8pmu_event_has_user_read(event) && 483 armv8pmu_event_is_64bit(event) && 484 !armv8pmu_has_long_event(cpu_pmu) && 485 (idx < ARMV8_PMU_MAX_GENERAL_COUNTERS); 486 } 487 488 /* 489 * ARMv8 low level PMU access 490 */ 491 static u64 armv8pmu_pmcr_read(void) 492 { 493 return read_pmcr(); 494 } 495 496 static void armv8pmu_pmcr_write(u64 val) 497 { 498 val &= ARMV8_PMU_PMCR_MASK; 499 isb(); 500 write_pmcr(val); 501 } 502 503 static int armv8pmu_has_overflowed(u64 pmovsr) 504 { 505 return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK); 506 } 507 508 static int armv8pmu_counter_has_overflowed(u64 pmnc, int idx) 509 { 510 return !!(pmnc & BIT(idx)); 511 } 512 513 static u64 armv8pmu_read_evcntr(int idx) 514 { 515 return read_pmevcntrn(idx); 516 } 517 518 static u64 armv8pmu_read_hw_counter(struct perf_event *event) 519 { 520 int idx = event->hw.idx; 521 u64 val = armv8pmu_read_evcntr(idx); 522 523 if (armv8pmu_event_is_chained(event)) 524 val = (val << 32) | armv8pmu_read_evcntr(idx - 1); 525 return val; 526 } 527 528 /* 529 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP 530 * is set the event counters also become 64-bit counters. Unless the 531 * user has requested a long counter (attr.config1) then we want to 532 * interrupt upon 32-bit overflow - we achieve this by applying a bias. 533 */ 534 static bool armv8pmu_event_needs_bias(struct perf_event *event) 535 { 536 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 537 struct hw_perf_event *hwc = &event->hw; 538 int idx = hwc->idx; 539 540 if (armv8pmu_event_is_64bit(event)) 541 return false; 542 543 if (armv8pmu_has_long_event(cpu_pmu) || 544 idx >= ARMV8_PMU_MAX_GENERAL_COUNTERS) 545 return true; 546 547 return false; 548 } 549 550 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value) 551 { 552 if (armv8pmu_event_needs_bias(event)) 553 value |= GENMASK_ULL(63, 32); 554 555 return value; 556 } 557 558 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value) 559 { 560 if (armv8pmu_event_needs_bias(event)) 561 value &= ~GENMASK_ULL(63, 32); 562 563 return value; 564 } 565 566 static u64 armv8pmu_read_counter(struct perf_event *event) 567 { 568 struct hw_perf_event *hwc = &event->hw; 569 int idx = hwc->idx; 570 u64 value; 571 572 if (idx == ARMV8_PMU_CYCLE_IDX) 573 value = read_pmccntr(); 574 else if (idx == ARMV8_PMU_INSTR_IDX) 575 value = read_pmicntr(); 576 else 577 value = armv8pmu_read_hw_counter(event); 578 579 return armv8pmu_unbias_long_counter(event, value); 580 } 581 582 static void armv8pmu_write_evcntr(int idx, u64 value) 583 { 584 write_pmevcntrn(idx, value); 585 } 586 587 static void armv8pmu_write_hw_counter(struct perf_event *event, 588 u64 value) 589 { 590 int idx = event->hw.idx; 591 592 if (armv8pmu_event_is_chained(event)) { 593 armv8pmu_write_evcntr(idx, upper_32_bits(value)); 594 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value)); 595 } else { 596 armv8pmu_write_evcntr(idx, value); 597 } 598 } 599 600 static void armv8pmu_write_counter(struct perf_event *event, u64 value) 601 { 602 struct hw_perf_event *hwc = &event->hw; 603 int idx = hwc->idx; 604 605 value = armv8pmu_bias_long_counter(event, value); 606 607 if (idx == ARMV8_PMU_CYCLE_IDX) 608 write_pmccntr(value); 609 else if (idx == ARMV8_PMU_INSTR_IDX) 610 write_pmicntr(value); 611 else 612 armv8pmu_write_hw_counter(event, value); 613 } 614 615 static void armv8pmu_write_evtype(int idx, unsigned long val) 616 { 617 unsigned long mask = ARMV8_PMU_EVTYPE_EVENT | 618 ARMV8_PMU_INCLUDE_EL2 | 619 ARMV8_PMU_EXCLUDE_EL0 | 620 ARMV8_PMU_EXCLUDE_EL1; 621 622 if (IS_ENABLED(CONFIG_ARM64)) 623 mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; 624 625 val &= mask; 626 write_pmevtypern(idx, val); 627 } 628 629 static void armv8pmu_write_event_type(struct perf_event *event) 630 { 631 struct hw_perf_event *hwc = &event->hw; 632 int idx = hwc->idx; 633 634 /* 635 * For chained events, the low counter is programmed to count 636 * the event of interest and the high counter is programmed 637 * with CHAIN event code with filters set to count at all ELs. 638 */ 639 if (armv8pmu_event_is_chained(event)) { 640 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN | 641 ARMV8_PMU_INCLUDE_EL2; 642 643 armv8pmu_write_evtype(idx - 1, hwc->config_base); 644 armv8pmu_write_evtype(idx, chain_evt); 645 } else { 646 if (idx == ARMV8_PMU_CYCLE_IDX) 647 write_pmccfiltr(hwc->config_base); 648 else if (idx == ARMV8_PMU_INSTR_IDX) 649 write_pmicfiltr(hwc->config_base); 650 else 651 armv8pmu_write_evtype(idx, hwc->config_base); 652 } 653 } 654 655 static u64 armv8pmu_event_cnten_mask(struct perf_event *event) 656 { 657 int counter = event->hw.idx; 658 u64 mask = BIT(counter); 659 660 if (armv8pmu_event_is_chained(event)) 661 mask |= BIT(counter - 1); 662 return mask; 663 } 664 665 static void armv8pmu_enable_counter(u64 mask) 666 { 667 /* 668 * Make sure event configuration register writes are visible before we 669 * enable the counter. 670 * */ 671 isb(); 672 write_pmcntenset(mask); 673 } 674 675 static void armv8pmu_enable_event_counter(struct perf_event *event) 676 { 677 struct perf_event_attr *attr = &event->attr; 678 u64 mask = armv8pmu_event_cnten_mask(event); 679 680 kvm_set_pmu_events(mask, attr); 681 682 /* We rely on the hypervisor switch code to enable guest counters */ 683 if (!kvm_pmu_counter_deferred(attr)) 684 armv8pmu_enable_counter(mask); 685 } 686 687 static void armv8pmu_disable_counter(u64 mask) 688 { 689 write_pmcntenclr(mask); 690 /* 691 * Make sure the effects of disabling the counter are visible before we 692 * start configuring the event. 693 */ 694 isb(); 695 } 696 697 static void armv8pmu_disable_event_counter(struct perf_event *event) 698 { 699 struct perf_event_attr *attr = &event->attr; 700 u64 mask = armv8pmu_event_cnten_mask(event); 701 702 kvm_clr_pmu_events(mask); 703 704 /* We rely on the hypervisor switch code to disable guest counters */ 705 if (!kvm_pmu_counter_deferred(attr)) 706 armv8pmu_disable_counter(mask); 707 } 708 709 static void armv8pmu_enable_intens(u64 mask) 710 { 711 write_pmintenset(mask); 712 } 713 714 static void armv8pmu_enable_event_irq(struct perf_event *event) 715 { 716 armv8pmu_enable_intens(BIT(event->hw.idx)); 717 } 718 719 static void armv8pmu_disable_intens(u64 mask) 720 { 721 write_pmintenclr(mask); 722 isb(); 723 /* Clear the overflow flag in case an interrupt is pending. */ 724 write_pmovsclr(mask); 725 isb(); 726 } 727 728 static void armv8pmu_disable_event_irq(struct perf_event *event) 729 { 730 armv8pmu_disable_intens(BIT(event->hw.idx)); 731 } 732 733 static u64 armv8pmu_getreset_flags(void) 734 { 735 u64 value; 736 737 /* Read */ 738 value = read_pmovsclr(); 739 740 /* Write to clear flags */ 741 value &= ARMV8_PMU_OVERFLOWED_MASK; 742 write_pmovsclr(value); 743 744 return value; 745 } 746 747 static void update_pmuserenr(u64 val) 748 { 749 lockdep_assert_irqs_disabled(); 750 751 /* 752 * The current PMUSERENR_EL0 value might be the value for the guest. 753 * If that's the case, have KVM keep tracking of the register value 754 * for the host EL0 so that KVM can restore it before returning to 755 * the host EL0. Otherwise, update the register now. 756 */ 757 if (kvm_set_pmuserenr(val)) 758 return; 759 760 write_pmuserenr(val); 761 } 762 763 static void armv8pmu_disable_user_access(void) 764 { 765 update_pmuserenr(0); 766 } 767 768 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) 769 { 770 int i; 771 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 772 773 /* Clear any unused counters to avoid leaking their contents */ 774 for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, 775 ARMPMU_MAX_HWEVENTS) { 776 if (i == ARMV8_PMU_CYCLE_IDX) 777 write_pmccntr(0); 778 else if (i == ARMV8_PMU_INSTR_IDX) 779 write_pmicntr(0); 780 else 781 armv8pmu_write_evcntr(i, 0); 782 } 783 784 update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR); 785 } 786 787 static void armv8pmu_enable_event(struct perf_event *event) 788 { 789 /* 790 * Enable counter and interrupt, and set the counter to count 791 * the event that we're interested in. 792 */ 793 armv8pmu_disable_event_counter(event); 794 armv8pmu_write_event_type(event); 795 armv8pmu_enable_event_irq(event); 796 armv8pmu_enable_event_counter(event); 797 } 798 799 static void armv8pmu_disable_event(struct perf_event *event) 800 { 801 armv8pmu_disable_event_counter(event); 802 armv8pmu_disable_event_irq(event); 803 } 804 805 static void armv8pmu_start(struct arm_pmu *cpu_pmu) 806 { 807 struct perf_event_context *ctx; 808 int nr_user = 0; 809 810 ctx = perf_cpu_task_ctx(); 811 if (ctx) 812 nr_user = ctx->nr_user; 813 814 if (sysctl_perf_user_access && nr_user) 815 armv8pmu_enable_user_access(cpu_pmu); 816 else 817 armv8pmu_disable_user_access(); 818 819 /* Enable all counters */ 820 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); 821 822 kvm_vcpu_pmu_resync_el0(); 823 } 824 825 static void armv8pmu_stop(struct arm_pmu *cpu_pmu) 826 { 827 /* Disable all counters */ 828 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); 829 } 830 831 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) 832 { 833 u64 pmovsr; 834 struct perf_sample_data data; 835 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 836 struct pt_regs *regs; 837 int idx; 838 839 /* 840 * Get and reset the IRQ flags 841 */ 842 pmovsr = armv8pmu_getreset_flags(); 843 844 /* 845 * Did an overflow occur? 846 */ 847 if (!armv8pmu_has_overflowed(pmovsr)) 848 return IRQ_NONE; 849 850 /* 851 * Handle the counter(s) overflow(s) 852 */ 853 regs = get_irq_regs(); 854 855 /* 856 * Stop the PMU while processing the counter overflows 857 * to prevent skews in group events. 858 */ 859 armv8pmu_stop(cpu_pmu); 860 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { 861 struct perf_event *event = cpuc->events[idx]; 862 struct hw_perf_event *hwc; 863 864 /* Ignore if we don't have an event. */ 865 if (!event) 866 continue; 867 868 /* 869 * We have a single interrupt for all counters. Check that 870 * each counter has overflowed before we process it. 871 */ 872 if (!armv8pmu_counter_has_overflowed(pmovsr, idx)) 873 continue; 874 875 hwc = &event->hw; 876 armpmu_event_update(event); 877 perf_sample_data_init(&data, 0, hwc->last_period); 878 if (!armpmu_event_set_period(event)) 879 continue; 880 881 /* 882 * Perf event overflow will queue the processing of the event as 883 * an irq_work which will be taken care of in the handling of 884 * IPI_IRQ_WORK. 885 */ 886 if (perf_event_overflow(event, &data, regs)) 887 cpu_pmu->disable(event); 888 } 889 armv8pmu_start(cpu_pmu); 890 891 return IRQ_HANDLED; 892 } 893 894 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc, 895 struct arm_pmu *cpu_pmu) 896 { 897 int idx; 898 899 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { 900 if (!test_and_set_bit(idx, cpuc->used_mask)) 901 return idx; 902 } 903 return -EAGAIN; 904 } 905 906 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, 907 struct arm_pmu *cpu_pmu) 908 { 909 int idx; 910 911 /* 912 * Chaining requires two consecutive event counters, where 913 * the lower idx must be even. 914 */ 915 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { 916 if (!(idx & 0x1)) 917 continue; 918 if (!test_and_set_bit(idx, cpuc->used_mask)) { 919 /* Check if the preceding even counter is available */ 920 if (!test_and_set_bit(idx - 1, cpuc->used_mask)) 921 return idx; 922 /* Release the Odd counter */ 923 clear_bit(idx, cpuc->used_mask); 924 } 925 } 926 return -EAGAIN; 927 } 928 929 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, 930 struct perf_event *event) 931 { 932 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 933 struct hw_perf_event *hwc = &event->hw; 934 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; 935 936 /* Always prefer to place a cycle counter into the cycle counter. */ 937 if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && 938 !armv8pmu_event_get_threshold(&event->attr)) { 939 if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) 940 return ARMV8_PMU_CYCLE_IDX; 941 else if (armv8pmu_event_is_64bit(event) && 942 armv8pmu_event_want_user_access(event) && 943 !armv8pmu_has_long_event(cpu_pmu)) 944 return -EAGAIN; 945 } 946 947 /* 948 * Always prefer to place a instruction counter into the instruction counter, 949 * but don't expose the instruction counter to userspace access as userspace 950 * may not know how to handle it. 951 */ 952 if ((evtype == ARMV8_PMUV3_PERFCTR_INST_RETIRED) && 953 !armv8pmu_event_get_threshold(&event->attr) && 954 test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) && 955 !armv8pmu_event_want_user_access(event)) { 956 if (!test_and_set_bit(ARMV8_PMU_INSTR_IDX, cpuc->used_mask)) 957 return ARMV8_PMU_INSTR_IDX; 958 } 959 960 /* 961 * Otherwise use events counters 962 */ 963 if (armv8pmu_event_is_chained(event)) 964 return armv8pmu_get_chain_idx(cpuc, cpu_pmu); 965 else 966 return armv8pmu_get_single_idx(cpuc, cpu_pmu); 967 } 968 969 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, 970 struct perf_event *event) 971 { 972 int idx = event->hw.idx; 973 974 clear_bit(idx, cpuc->used_mask); 975 if (armv8pmu_event_is_chained(event)) 976 clear_bit(idx - 1, cpuc->used_mask); 977 } 978 979 static int armv8pmu_user_event_idx(struct perf_event *event) 980 { 981 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event)) 982 return 0; 983 984 return event->hw.idx + 1; 985 } 986 987 /* 988 * Add an event filter to a given event. 989 */ 990 static int armv8pmu_set_event_filter(struct hw_perf_event *event, 991 struct perf_event_attr *attr) 992 { 993 unsigned long config_base = 0; 994 struct perf_event *perf_event = container_of(attr, struct perf_event, 995 attr); 996 struct arm_pmu *cpu_pmu = to_arm_pmu(perf_event->pmu); 997 u32 th; 998 999 if (attr->exclude_idle) { 1000 pr_debug("ARM performance counters do not support mode exclusion\n"); 1001 return -EOPNOTSUPP; 1002 } 1003 1004 /* 1005 * If we're running in hyp mode, then we *are* the hypervisor. 1006 * Therefore we ignore exclude_hv in this configuration, since 1007 * there's no hypervisor to sample anyway. This is consistent 1008 * with other architectures (x86 and Power). 1009 */ 1010 if (is_kernel_in_hyp_mode()) { 1011 if (!attr->exclude_kernel && !attr->exclude_host) 1012 config_base |= ARMV8_PMU_INCLUDE_EL2; 1013 if (attr->exclude_guest) 1014 config_base |= ARMV8_PMU_EXCLUDE_EL1; 1015 if (attr->exclude_host) 1016 config_base |= ARMV8_PMU_EXCLUDE_EL0; 1017 } else { 1018 if (!attr->exclude_hv && !attr->exclude_host) 1019 config_base |= ARMV8_PMU_INCLUDE_EL2; 1020 } 1021 1022 /* 1023 * Filter out !VHE kernels and guest kernels 1024 */ 1025 if (attr->exclude_kernel) 1026 config_base |= ARMV8_PMU_EXCLUDE_EL1; 1027 1028 if (attr->exclude_user) 1029 config_base |= ARMV8_PMU_EXCLUDE_EL0; 1030 1031 /* 1032 * If FEAT_PMUv3_TH isn't implemented, then THWIDTH (threshold_max) will 1033 * be 0 and will also trigger this check, preventing it from being used. 1034 */ 1035 th = armv8pmu_event_get_threshold(attr); 1036 if (th > threshold_max(cpu_pmu)) { 1037 pr_debug("PMU event threshold exceeds max value\n"); 1038 return -EINVAL; 1039 } 1040 1041 if (th) { 1042 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TH, th); 1043 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TC, 1044 armv8pmu_event_threshold_control(attr)); 1045 } 1046 1047 /* 1048 * Install the filter into config_base as this is used to 1049 * construct the event type. 1050 */ 1051 event->config_base = config_base; 1052 1053 return 0; 1054 } 1055 1056 static void armv8pmu_reset(void *info) 1057 { 1058 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 1059 u64 pmcr, mask; 1060 1061 bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); 1062 1063 /* The counter and interrupt enable registers are unknown at reset. */ 1064 armv8pmu_disable_counter(mask); 1065 armv8pmu_disable_intens(mask); 1066 1067 /* Clear the counters we flip at guest entry/exit */ 1068 kvm_clr_pmu_events(mask); 1069 1070 /* 1071 * Initialize & Reset PMNC. Request overflow interrupt for 1072 * 64 bit cycle counter but cheat in armv8pmu_write_counter(). 1073 */ 1074 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC; 1075 1076 /* Enable long event counter support where available */ 1077 if (armv8pmu_has_long_event(cpu_pmu)) 1078 pmcr |= ARMV8_PMU_PMCR_LP; 1079 1080 armv8pmu_pmcr_write(pmcr); 1081 } 1082 1083 static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu, 1084 struct perf_event *event) 1085 { 1086 if (event->attr.type == PERF_TYPE_HARDWARE && 1087 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) { 1088 1089 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED, 1090 armpmu->pmceid_bitmap)) 1091 return ARMV8_PMUV3_PERFCTR_BR_RETIRED; 1092 1093 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED, 1094 armpmu->pmceid_bitmap)) 1095 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED; 1096 1097 return HW_OP_UNSUPPORTED; 1098 } 1099 1100 return armpmu_map_event(event, &armv8_pmuv3_perf_map, 1101 &armv8_pmuv3_perf_cache_map, 1102 ARMV8_PMU_EVTYPE_EVENT); 1103 } 1104 1105 static int __armv8_pmuv3_map_event(struct perf_event *event, 1106 const unsigned (*extra_event_map) 1107 [PERF_COUNT_HW_MAX], 1108 const unsigned (*extra_cache_map) 1109 [PERF_COUNT_HW_CACHE_MAX] 1110 [PERF_COUNT_HW_CACHE_OP_MAX] 1111 [PERF_COUNT_HW_CACHE_RESULT_MAX]) 1112 { 1113 int hw_event_id; 1114 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); 1115 1116 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event); 1117 1118 /* 1119 * CHAIN events only work when paired with an adjacent counter, and it 1120 * never makes sense for a user to open one in isolation, as they'll be 1121 * rotated arbitrarily. 1122 */ 1123 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN) 1124 return -EINVAL; 1125 1126 if (armv8pmu_event_is_64bit(event)) 1127 event->hw.flags |= ARMPMU_EVT_64BIT; 1128 1129 /* 1130 * User events must be allocated into a single counter, and so 1131 * must not be chained. 1132 * 1133 * Most 64-bit events require long counter support, but 64-bit 1134 * CPU_CYCLES events can be placed into the dedicated cycle 1135 * counter when this is free. 1136 */ 1137 if (armv8pmu_event_want_user_access(event)) { 1138 if (!(event->attach_state & PERF_ATTACH_TASK)) 1139 return -EINVAL; 1140 if (armv8pmu_event_is_64bit(event) && 1141 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && 1142 !armv8pmu_has_long_event(armpmu)) 1143 return -EOPNOTSUPP; 1144 1145 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; 1146 } 1147 1148 /* Only expose micro/arch events supported by this PMU */ 1149 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) 1150 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) { 1151 return hw_event_id; 1152 } 1153 1154 return armpmu_map_event(event, extra_event_map, extra_cache_map, 1155 ARMV8_PMU_EVTYPE_EVENT); 1156 } 1157 1158 static int armv8_pmuv3_map_event(struct perf_event *event) 1159 { 1160 return __armv8_pmuv3_map_event(event, NULL, NULL); 1161 } 1162 1163 static int armv8_a53_map_event(struct perf_event *event) 1164 { 1165 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map); 1166 } 1167 1168 static int armv8_a57_map_event(struct perf_event *event) 1169 { 1170 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map); 1171 } 1172 1173 static int armv8_a73_map_event(struct perf_event *event) 1174 { 1175 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map); 1176 } 1177 1178 static int armv8_thunder_map_event(struct perf_event *event) 1179 { 1180 return __armv8_pmuv3_map_event(event, NULL, 1181 &armv8_thunder_perf_cache_map); 1182 } 1183 1184 static int armv8_vulcan_map_event(struct perf_event *event) 1185 { 1186 return __armv8_pmuv3_map_event(event, NULL, 1187 &armv8_vulcan_perf_cache_map); 1188 } 1189 1190 struct armv8pmu_probe_info { 1191 struct arm_pmu *pmu; 1192 bool present; 1193 }; 1194 1195 static void __armv8pmu_probe_pmu(void *info) 1196 { 1197 struct armv8pmu_probe_info *probe = info; 1198 struct arm_pmu *cpu_pmu = probe->pmu; 1199 u64 pmceid_raw[2]; 1200 u32 pmceid[2]; 1201 int pmuver; 1202 1203 pmuver = read_pmuver(); 1204 if (!pmuv3_implemented(pmuver)) 1205 return; 1206 1207 cpu_pmu->pmuver = pmuver; 1208 probe->present = true; 1209 1210 /* Read the nb of CNTx counters supported from PMNC */ 1211 bitmap_set(cpu_pmu->cntr_mask, 1212 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); 1213 1214 /* Add the CPU cycles counter */ 1215 set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask); 1216 1217 /* Add the CPU instructions counter */ 1218 if (pmuv3_has_icntr()) 1219 set_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask); 1220 1221 pmceid[0] = pmceid_raw[0] = read_pmceid0(); 1222 pmceid[1] = pmceid_raw[1] = read_pmceid1(); 1223 1224 bitmap_from_arr32(cpu_pmu->pmceid_bitmap, 1225 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1226 1227 pmceid[0] = pmceid_raw[0] >> 32; 1228 pmceid[1] = pmceid_raw[1] >> 32; 1229 1230 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap, 1231 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1232 1233 /* store PMMIR register for sysfs */ 1234 if (is_pmuv3p4(pmuver)) 1235 cpu_pmu->reg_pmmir = read_pmmir(); 1236 else 1237 cpu_pmu->reg_pmmir = 0; 1238 } 1239 1240 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) 1241 { 1242 struct armv8pmu_probe_info probe = { 1243 .pmu = cpu_pmu, 1244 .present = false, 1245 }; 1246 int ret; 1247 1248 ret = smp_call_function_any(&cpu_pmu->supported_cpus, 1249 __armv8pmu_probe_pmu, 1250 &probe, 1); 1251 if (ret) 1252 return ret; 1253 1254 return probe.present ? 0 : -ENODEV; 1255 } 1256 1257 static void armv8pmu_disable_user_access_ipi(void *unused) 1258 { 1259 armv8pmu_disable_user_access(); 1260 } 1261 1262 static int armv8pmu_proc_user_access_handler(const struct ctl_table *table, int write, 1263 void *buffer, size_t *lenp, loff_t *ppos) 1264 { 1265 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 1266 if (ret || !write || sysctl_perf_user_access) 1267 return ret; 1268 1269 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1); 1270 return 0; 1271 } 1272 1273 static struct ctl_table armv8_pmu_sysctl_table[] = { 1274 { 1275 .procname = "perf_user_access", 1276 .data = &sysctl_perf_user_access, 1277 .maxlen = sizeof(unsigned int), 1278 .mode = 0644, 1279 .proc_handler = armv8pmu_proc_user_access_handler, 1280 .extra1 = SYSCTL_ZERO, 1281 .extra2 = SYSCTL_ONE, 1282 }, 1283 }; 1284 1285 static void armv8_pmu_register_sysctl_table(void) 1286 { 1287 static u32 tbl_registered = 0; 1288 1289 if (!cmpxchg_relaxed(&tbl_registered, 0, 1)) 1290 register_sysctl("kernel", armv8_pmu_sysctl_table); 1291 } 1292 1293 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, 1294 int (*map_event)(struct perf_event *event)) 1295 { 1296 int ret = armv8pmu_probe_pmu(cpu_pmu); 1297 if (ret) 1298 return ret; 1299 1300 cpu_pmu->handle_irq = armv8pmu_handle_irq; 1301 cpu_pmu->enable = armv8pmu_enable_event; 1302 cpu_pmu->disable = armv8pmu_disable_event; 1303 cpu_pmu->read_counter = armv8pmu_read_counter; 1304 cpu_pmu->write_counter = armv8pmu_write_counter; 1305 cpu_pmu->get_event_idx = armv8pmu_get_event_idx; 1306 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx; 1307 cpu_pmu->start = armv8pmu_start; 1308 cpu_pmu->stop = armv8pmu_stop; 1309 cpu_pmu->reset = armv8pmu_reset; 1310 cpu_pmu->set_event_filter = armv8pmu_set_event_filter; 1311 1312 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx; 1313 1314 cpu_pmu->name = name; 1315 cpu_pmu->map_event = map_event; 1316 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &armv8_pmuv3_events_attr_group; 1317 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv8_pmuv3_format_attr_group; 1318 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = &armv8_pmuv3_caps_attr_group; 1319 armv8_pmu_register_sysctl_table(); 1320 return 0; 1321 } 1322 1323 #define PMUV3_INIT_SIMPLE(name) \ 1324 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1325 { \ 1326 return armv8_pmu_init(cpu_pmu, #name, armv8_pmuv3_map_event); \ 1327 } 1328 1329 #define PMUV3_INIT_MAP_EVENT(name, map_event) \ 1330 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1331 { \ 1332 return armv8_pmu_init(cpu_pmu, #name, map_event); \ 1333 } 1334 1335 PMUV3_INIT_SIMPLE(armv8_pmuv3) 1336 1337 PMUV3_INIT_SIMPLE(armv8_cortex_a34) 1338 PMUV3_INIT_SIMPLE(armv8_cortex_a55) 1339 PMUV3_INIT_SIMPLE(armv8_cortex_a65) 1340 PMUV3_INIT_SIMPLE(armv8_cortex_a75) 1341 PMUV3_INIT_SIMPLE(armv8_cortex_a76) 1342 PMUV3_INIT_SIMPLE(armv8_cortex_a77) 1343 PMUV3_INIT_SIMPLE(armv8_cortex_a78) 1344 PMUV3_INIT_SIMPLE(armv9_cortex_a510) 1345 PMUV3_INIT_SIMPLE(armv9_cortex_a520) 1346 PMUV3_INIT_SIMPLE(armv9_cortex_a710) 1347 PMUV3_INIT_SIMPLE(armv9_cortex_a715) 1348 PMUV3_INIT_SIMPLE(armv9_cortex_a720) 1349 PMUV3_INIT_SIMPLE(armv9_cortex_a725) 1350 PMUV3_INIT_SIMPLE(armv8_cortex_x1) 1351 PMUV3_INIT_SIMPLE(armv9_cortex_x2) 1352 PMUV3_INIT_SIMPLE(armv9_cortex_x3) 1353 PMUV3_INIT_SIMPLE(armv9_cortex_x4) 1354 PMUV3_INIT_SIMPLE(armv9_cortex_x925) 1355 PMUV3_INIT_SIMPLE(armv8_neoverse_e1) 1356 PMUV3_INIT_SIMPLE(armv8_neoverse_n1) 1357 PMUV3_INIT_SIMPLE(armv9_neoverse_n2) 1358 PMUV3_INIT_SIMPLE(armv9_neoverse_n3) 1359 PMUV3_INIT_SIMPLE(armv8_neoverse_v1) 1360 PMUV3_INIT_SIMPLE(armv8_neoverse_v2) 1361 PMUV3_INIT_SIMPLE(armv8_neoverse_v3) 1362 PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) 1363 1364 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) 1365 PMUV3_INIT_SIMPLE(armv8_nvidia_denver) 1366 1367 PMUV3_INIT_MAP_EVENT(armv8_cortex_a35, armv8_a53_map_event) 1368 PMUV3_INIT_MAP_EVENT(armv8_cortex_a53, armv8_a53_map_event) 1369 PMUV3_INIT_MAP_EVENT(armv8_cortex_a57, armv8_a57_map_event) 1370 PMUV3_INIT_MAP_EVENT(armv8_cortex_a72, armv8_a57_map_event) 1371 PMUV3_INIT_MAP_EVENT(armv8_cortex_a73, armv8_a73_map_event) 1372 PMUV3_INIT_MAP_EVENT(armv8_cavium_thunder, armv8_thunder_map_event) 1373 PMUV3_INIT_MAP_EVENT(armv8_brcm_vulcan, armv8_vulcan_map_event) 1374 1375 static const struct of_device_id armv8_pmu_of_device_ids[] = { 1376 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, 1377 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init}, 1378 {.compatible = "arm,cortex-a35-pmu", .data = armv8_cortex_a35_pmu_init}, 1379 {.compatible = "arm,cortex-a53-pmu", .data = armv8_cortex_a53_pmu_init}, 1380 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init}, 1381 {.compatible = "arm,cortex-a57-pmu", .data = armv8_cortex_a57_pmu_init}, 1382 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init}, 1383 {.compatible = "arm,cortex-a72-pmu", .data = armv8_cortex_a72_pmu_init}, 1384 {.compatible = "arm,cortex-a73-pmu", .data = armv8_cortex_a73_pmu_init}, 1385 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init}, 1386 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, 1387 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, 1388 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, 1389 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init}, 1390 {.compatible = "arm,cortex-a520-pmu", .data = armv9_cortex_a520_pmu_init}, 1391 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init}, 1392 {.compatible = "arm,cortex-a715-pmu", .data = armv9_cortex_a715_pmu_init}, 1393 {.compatible = "arm,cortex-a720-pmu", .data = armv9_cortex_a720_pmu_init}, 1394 {.compatible = "arm,cortex-a725-pmu", .data = armv9_cortex_a725_pmu_init}, 1395 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init}, 1396 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init}, 1397 {.compatible = "arm,cortex-x3-pmu", .data = armv9_cortex_x3_pmu_init}, 1398 {.compatible = "arm,cortex-x4-pmu", .data = armv9_cortex_x4_pmu_init}, 1399 {.compatible = "arm,cortex-x925-pmu", .data = armv9_cortex_x925_pmu_init}, 1400 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, 1401 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, 1402 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init}, 1403 {.compatible = "arm,neoverse-n3-pmu", .data = armv9_neoverse_n3_pmu_init}, 1404 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init}, 1405 {.compatible = "arm,neoverse-v2-pmu", .data = armv8_neoverse_v2_pmu_init}, 1406 {.compatible = "arm,neoverse-v3-pmu", .data = armv8_neoverse_v3_pmu_init}, 1407 {.compatible = "arm,neoverse-v3ae-pmu", .data = armv8_neoverse_v3ae_pmu_init}, 1408 {.compatible = "cavium,thunder-pmu", .data = armv8_cavium_thunder_pmu_init}, 1409 {.compatible = "brcm,vulcan-pmu", .data = armv8_brcm_vulcan_pmu_init}, 1410 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, 1411 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init}, 1412 {}, 1413 }; 1414 1415 static int armv8_pmu_device_probe(struct platform_device *pdev) 1416 { 1417 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL); 1418 } 1419 1420 static struct platform_driver armv8_pmu_driver = { 1421 .driver = { 1422 .name = ARMV8_PMU_PDEV_NAME, 1423 .of_match_table = armv8_pmu_of_device_ids, 1424 .suppress_bind_attrs = true, 1425 }, 1426 .probe = armv8_pmu_device_probe, 1427 }; 1428 1429 static int __init armv8_pmu_driver_init(void) 1430 { 1431 int ret; 1432 1433 if (acpi_disabled) 1434 ret = platform_driver_register(&armv8_pmu_driver); 1435 else 1436 ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); 1437 1438 if (!ret) 1439 lockup_detector_retry_init(); 1440 1441 return ret; 1442 } 1443 device_initcall(armv8_pmu_driver_init) 1444 1445 void arch_perf_update_userpage(struct perf_event *event, 1446 struct perf_event_mmap_page *userpg, u64 now) 1447 { 1448 struct clock_read_data *rd; 1449 unsigned int seq; 1450 u64 ns; 1451 1452 userpg->cap_user_time = 0; 1453 userpg->cap_user_time_zero = 0; 1454 userpg->cap_user_time_short = 0; 1455 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event); 1456 1457 if (userpg->cap_user_rdpmc) { 1458 if (event->hw.flags & ARMPMU_EVT_64BIT) 1459 userpg->pmc_width = 64; 1460 else 1461 userpg->pmc_width = 32; 1462 } 1463 1464 do { 1465 rd = sched_clock_read_begin(&seq); 1466 1467 if (rd->read_sched_clock != arch_timer_read_counter) 1468 return; 1469 1470 userpg->time_mult = rd->mult; 1471 userpg->time_shift = rd->shift; 1472 userpg->time_zero = rd->epoch_ns; 1473 userpg->time_cycles = rd->epoch_cyc; 1474 userpg->time_mask = rd->sched_clock_mask; 1475 1476 /* 1477 * Subtract the cycle base, such that software that 1478 * doesn't know about cap_user_time_short still 'works' 1479 * assuming no wraps. 1480 */ 1481 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift); 1482 userpg->time_zero -= ns; 1483 1484 } while (sched_clock_read_retry(seq)); 1485 1486 userpg->time_offset = userpg->time_zero - now; 1487 1488 /* 1489 * time_shift is not expected to be greater than 31 due to 1490 * the original published conversion algorithm shifting a 1491 * 32-bit value (now specifies a 64-bit value) - refer 1492 * perf_event_mmap_page documentation in perf_event.h. 1493 */ 1494 if (userpg->time_shift == 32) { 1495 userpg->time_shift = 31; 1496 userpg->time_mult >>= 1; 1497 } 1498 1499 /* 1500 * Internal timekeeping for enabled/running/stopped times 1501 * is always computed with the sched_clock. 1502 */ 1503 userpg->cap_user_time = 1; 1504 userpg->cap_user_time_zero = 1; 1505 userpg->cap_user_time_short = 1; 1506 } 1507