1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ARMv8 PMUv3 Performance Events handling code. 4 * 5 * Copyright (C) 2012 ARM Limited 6 * Author: Will Deacon <will.deacon@arm.com> 7 * 8 * This code is based heavily on the ARMv7 perf event code. 9 */ 10 11 #include <asm/cputype.h> 12 #include <asm/irq_regs.h> 13 #include <asm/perf_event.h> 14 #include <asm/virt.h> 15 16 #include <clocksource/arm_arch_timer.h> 17 18 #include <linux/acpi.h> 19 #include <linux/bitfield.h> 20 #include <linux/clocksource.h> 21 #include <linux/of.h> 22 #include <linux/perf/arm_pmu.h> 23 #include <linux/perf/arm_pmuv3.h> 24 #include <linux/platform_device.h> 25 #include <linux/sched_clock.h> 26 #include <linux/smp.h> 27 #include <linux/nmi.h> 28 29 #include "arm_brbe.h" 30 31 /* ARMv8 Cortex-A53 specific event types. */ 32 #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2 33 34 /* ARMv8 Cavium ThunderX specific event types. */ 35 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9 36 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA 37 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB 38 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC 39 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED 40 41 /* 42 * ARMv8 Architectural defined events, not all of these may 43 * be supported on any given implementation. Unsupported events will 44 * be disabled at run-time based on the PMCEID registers. 45 */ 46 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = { 47 PERF_MAP_ALL_UNSUPPORTED, 48 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES, 49 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED, 50 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 51 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 52 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 53 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, 54 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, 55 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, 56 }; 57 58 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 59 [PERF_COUNT_HW_CACHE_OP_MAX] 60 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 61 PERF_CACHE_MAP_ALL_UNSUPPORTED, 62 63 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE, 64 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL, 65 66 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, 67 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, 68 69 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, 70 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB, 71 72 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL, 73 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB, 74 75 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD, 76 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD, 77 78 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED, 79 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED, 80 }; 81 82 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 83 [PERF_COUNT_HW_CACHE_OP_MAX] 84 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 85 PERF_CACHE_MAP_ALL_UNSUPPORTED, 86 87 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL, 88 89 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 90 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 91 }; 92 93 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 94 [PERF_COUNT_HW_CACHE_OP_MAX] 95 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 96 PERF_CACHE_MAP_ALL_UNSUPPORTED, 97 98 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 99 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 100 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 101 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 102 103 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 104 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 105 106 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 107 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 108 }; 109 110 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 111 [PERF_COUNT_HW_CACHE_OP_MAX] 112 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 113 PERF_CACHE_MAP_ALL_UNSUPPORTED, 114 115 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 116 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 117 }; 118 119 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 120 [PERF_COUNT_HW_CACHE_OP_MAX] 121 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 122 PERF_CACHE_MAP_ALL_UNSUPPORTED, 123 124 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 125 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 126 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 127 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST, 128 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS, 129 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS, 130 131 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, 132 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, 133 134 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 135 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 136 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 137 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 138 }; 139 140 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 141 [PERF_COUNT_HW_CACHE_OP_MAX] 142 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 143 PERF_CACHE_MAP_ALL_UNSUPPORTED, 144 145 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, 146 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD, 147 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, 148 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR, 149 150 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD, 151 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR, 152 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD, 153 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR, 154 155 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, 156 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, 157 }; 158 159 static ssize_t 160 armv8pmu_events_sysfs_show(struct device *dev, 161 struct device_attribute *attr, char *page) 162 { 163 struct perf_pmu_events_attr *pmu_attr; 164 165 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 166 167 return sprintf(page, "event=0x%04llx\n", pmu_attr->id); 168 } 169 170 #define ARMV8_EVENT_ATTR(name, config) \ 171 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config) 172 173 static struct attribute *armv8_pmuv3_event_attrs[] = { 174 /* 175 * Don't expose the sw_incr event in /sys. It's not usable as writes to 176 * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation 177 * means we don't have a fixed event<->counter relationship regardless. 178 */ 179 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL), 180 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL), 181 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL), 182 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE), 183 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL), 184 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED), 185 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED), 186 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED), 187 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN), 188 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN), 189 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED), 190 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED), 191 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED), 192 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED), 193 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED), 194 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED), 195 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES), 196 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED), 197 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS), 198 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE), 199 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB), 200 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE), 201 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL), 202 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB), 203 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS), 204 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR), 205 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC), 206 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED), 207 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES), 208 /* Don't expose the chain event in /sys, since it's useless in isolation */ 209 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE), 210 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE), 211 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED), 212 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED), 213 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND), 214 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND), 215 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB), 216 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB), 217 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE), 218 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL), 219 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE), 220 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL), 221 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE), 222 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB), 223 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL), 224 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL), 225 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB), 226 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB), 227 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS), 228 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE), 229 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS), 230 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK), 231 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK), 232 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD), 233 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD), 234 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD), 235 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD), 236 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED), 237 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC), 238 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL), 239 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND), 240 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND), 241 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT), 242 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP), 243 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED), 244 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE), 245 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION), 246 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES), 247 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM), 248 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS), 249 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD), 250 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS), 251 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD), 252 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP), 253 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG), 254 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0), 255 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1), 256 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2), 257 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3), 258 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4), 259 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5), 260 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6), 261 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7), 262 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT), 263 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT), 264 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT), 265 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED), 266 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD), 267 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR), 268 NULL, 269 }; 270 271 static umode_t 272 armv8pmu_event_attr_is_visible(struct kobject *kobj, 273 struct attribute *attr, int unused) 274 { 275 struct device *dev = kobj_to_dev(kobj); 276 struct pmu *pmu = dev_get_drvdata(dev); 277 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 278 struct perf_pmu_events_attr *pmu_attr; 279 280 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); 281 282 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 283 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) 284 return attr->mode; 285 286 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { 287 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; 288 289 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && 290 test_bit(id, cpu_pmu->pmceid_ext_bitmap)) 291 return attr->mode; 292 } 293 294 return 0; 295 } 296 297 static const struct attribute_group armv8_pmuv3_events_attr_group = { 298 .name = "events", 299 .attrs = armv8_pmuv3_event_attrs, 300 .is_visible = armv8pmu_event_attr_is_visible, 301 }; 302 303 /* User ABI */ 304 #define ATTR_CFG_FLD_event_CFG config 305 #define ATTR_CFG_FLD_event_LO 0 306 #define ATTR_CFG_FLD_event_HI 15 307 #define ATTR_CFG_FLD_long_CFG config1 308 #define ATTR_CFG_FLD_long_LO 0 309 #define ATTR_CFG_FLD_long_HI 0 310 #define ATTR_CFG_FLD_rdpmc_CFG config1 311 #define ATTR_CFG_FLD_rdpmc_LO 1 312 #define ATTR_CFG_FLD_rdpmc_HI 1 313 #define ATTR_CFG_FLD_threshold_count_CFG config1 /* PMEVTYPER.TC[0] */ 314 #define ATTR_CFG_FLD_threshold_count_LO 2 315 #define ATTR_CFG_FLD_threshold_count_HI 2 316 #define ATTR_CFG_FLD_threshold_compare_CFG config1 /* PMEVTYPER.TC[2:1] */ 317 #define ATTR_CFG_FLD_threshold_compare_LO 3 318 #define ATTR_CFG_FLD_threshold_compare_HI 4 319 #define ATTR_CFG_FLD_threshold_CFG config1 /* PMEVTYPER.TH */ 320 #define ATTR_CFG_FLD_threshold_LO 5 321 #define ATTR_CFG_FLD_threshold_HI 16 322 323 GEN_PMU_FORMAT_ATTR(event); 324 GEN_PMU_FORMAT_ATTR(long); 325 GEN_PMU_FORMAT_ATTR(rdpmc); 326 GEN_PMU_FORMAT_ATTR(threshold_count); 327 GEN_PMU_FORMAT_ATTR(threshold_compare); 328 GEN_PMU_FORMAT_ATTR(threshold); 329 330 static int sysctl_perf_user_access __read_mostly; 331 332 static bool armv8pmu_event_is_64bit(struct perf_event *event) 333 { 334 return ATTR_CFG_GET_FLD(&event->attr, long); 335 } 336 337 static bool armv8pmu_event_want_user_access(struct perf_event *event) 338 { 339 return ATTR_CFG_GET_FLD(&event->attr, rdpmc); 340 } 341 342 static u32 armv8pmu_event_get_threshold(struct perf_event_attr *attr) 343 { 344 return ATTR_CFG_GET_FLD(attr, threshold); 345 } 346 347 static u8 armv8pmu_event_threshold_control(struct perf_event_attr *attr) 348 { 349 u8 th_compare = ATTR_CFG_GET_FLD(attr, threshold_compare); 350 u8 th_count = ATTR_CFG_GET_FLD(attr, threshold_count); 351 352 /* 353 * The count bit is always the bottom bit of the full control field, and 354 * the comparison is the upper two bits, but it's not explicitly 355 * labelled in the Arm ARM. For the Perf interface we split it into two 356 * fields, so reconstruct it here. 357 */ 358 return (th_compare << 1) | th_count; 359 } 360 361 static struct attribute *armv8_pmuv3_format_attrs[] = { 362 &format_attr_event.attr, 363 &format_attr_long.attr, 364 &format_attr_rdpmc.attr, 365 &format_attr_threshold.attr, 366 &format_attr_threshold_compare.attr, 367 &format_attr_threshold_count.attr, 368 NULL, 369 }; 370 371 static const struct attribute_group armv8_pmuv3_format_attr_group = { 372 .name = "format", 373 .attrs = armv8_pmuv3_format_attrs, 374 }; 375 376 static ssize_t slots_show(struct device *dev, struct device_attribute *attr, 377 char *page) 378 { 379 struct pmu *pmu = dev_get_drvdata(dev); 380 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 381 u32 slots = FIELD_GET(ARMV8_PMU_SLOTS, cpu_pmu->reg_pmmir); 382 383 return sysfs_emit(page, "0x%08x\n", slots); 384 } 385 386 static DEVICE_ATTR_RO(slots); 387 388 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr, 389 char *page) 390 { 391 struct pmu *pmu = dev_get_drvdata(dev); 392 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 393 u32 bus_slots = FIELD_GET(ARMV8_PMU_BUS_SLOTS, cpu_pmu->reg_pmmir); 394 395 return sysfs_emit(page, "0x%08x\n", bus_slots); 396 } 397 398 static DEVICE_ATTR_RO(bus_slots); 399 400 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr, 401 char *page) 402 { 403 struct pmu *pmu = dev_get_drvdata(dev); 404 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 405 u32 bus_width = FIELD_GET(ARMV8_PMU_BUS_WIDTH, cpu_pmu->reg_pmmir); 406 u32 val = 0; 407 408 /* Encoded as Log2(number of bytes), plus one */ 409 if (bus_width > 2 && bus_width < 13) 410 val = 1 << (bus_width - 1); 411 412 return sysfs_emit(page, "0x%08x\n", val); 413 } 414 415 static DEVICE_ATTR_RO(bus_width); 416 417 static u32 threshold_max(struct arm_pmu *cpu_pmu) 418 { 419 /* 420 * PMMIR.THWIDTH is readable and non-zero on aarch32, but it would be 421 * impossible to write the threshold in the upper 32 bits of PMEVTYPER. 422 */ 423 if (IS_ENABLED(CONFIG_ARM)) 424 return 0; 425 426 /* 427 * The largest value that can be written to PMEVTYPER<n>_EL0.TH is 428 * (2 ^ PMMIR.THWIDTH) - 1. 429 */ 430 return (1 << FIELD_GET(ARMV8_PMU_THWIDTH, cpu_pmu->reg_pmmir)) - 1; 431 } 432 433 static ssize_t threshold_max_show(struct device *dev, 434 struct device_attribute *attr, char *page) 435 { 436 struct pmu *pmu = dev_get_drvdata(dev); 437 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 438 439 return sysfs_emit(page, "0x%08x\n", threshold_max(cpu_pmu)); 440 } 441 442 static DEVICE_ATTR_RO(threshold_max); 443 444 static ssize_t branches_show(struct device *dev, 445 struct device_attribute *attr, char *page) 446 { 447 struct pmu *pmu = dev_get_drvdata(dev); 448 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 449 450 return sysfs_emit(page, "%d\n", brbe_num_branch_records(cpu_pmu)); 451 } 452 453 static DEVICE_ATTR_RO(branches); 454 455 static struct attribute *armv8_pmuv3_caps_attrs[] = { 456 &dev_attr_branches.attr, 457 &dev_attr_slots.attr, 458 &dev_attr_bus_slots.attr, 459 &dev_attr_bus_width.attr, 460 &dev_attr_threshold_max.attr, 461 NULL, 462 }; 463 464 static umode_t caps_is_visible(struct kobject *kobj, struct attribute *attr, int i) 465 { 466 struct device *dev = kobj_to_dev(kobj); 467 struct pmu *pmu = dev_get_drvdata(dev); 468 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); 469 470 if (i == 0) 471 return brbe_num_branch_records(cpu_pmu) ? attr->mode : 0; 472 473 return attr->mode; 474 } 475 476 static const struct attribute_group armv8_pmuv3_caps_attr_group = { 477 .name = "caps", 478 .attrs = armv8_pmuv3_caps_attrs, 479 .is_visible = caps_is_visible, 480 }; 481 482 /* 483 * We unconditionally enable ARMv8.5-PMU long event counter support 484 * (64-bit events) where supported. Indicate if this arm_pmu has long 485 * event counter support. 486 * 487 * On AArch32, long counters make no sense (you can't access the top 488 * bits), so we only enable this on AArch64. 489 */ 490 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu) 491 { 492 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver)); 493 } 494 495 static bool armv8pmu_event_has_user_read(struct perf_event *event) 496 { 497 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT; 498 } 499 500 /* 501 * We must chain two programmable counters for 64 bit events, 502 * except when we have allocated the 64bit cycle counter (for CPU 503 * cycles event) or when user space counter access is enabled. 504 */ 505 static bool armv8pmu_event_is_chained(struct perf_event *event) 506 { 507 int idx = event->hw.idx; 508 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 509 510 return !armv8pmu_event_has_user_read(event) && 511 armv8pmu_event_is_64bit(event) && 512 !armv8pmu_has_long_event(cpu_pmu) && 513 (idx < ARMV8_PMU_MAX_GENERAL_COUNTERS); 514 } 515 516 /* 517 * ARMv8 low level PMU access 518 */ 519 static u64 armv8pmu_pmcr_read(void) 520 { 521 return read_pmcr(); 522 } 523 524 static void armv8pmu_pmcr_write(u64 val) 525 { 526 val &= ARMV8_PMU_PMCR_MASK; 527 isb(); 528 write_pmcr(val); 529 } 530 531 static int armv8pmu_has_overflowed(u64 pmovsr) 532 { 533 return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK); 534 } 535 536 static int armv8pmu_counter_has_overflowed(u64 pmnc, int idx) 537 { 538 return !!(pmnc & BIT(idx)); 539 } 540 541 static u64 armv8pmu_read_evcntr(int idx) 542 { 543 return read_pmevcntrn(idx); 544 } 545 546 static u64 armv8pmu_read_hw_counter(struct perf_event *event) 547 { 548 int idx = event->hw.idx; 549 u64 val = armv8pmu_read_evcntr(idx); 550 551 if (armv8pmu_event_is_chained(event)) 552 val = (val << 32) | armv8pmu_read_evcntr(idx - 1); 553 return val; 554 } 555 556 /* 557 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP 558 * is set the event counters also become 64-bit counters. Unless the 559 * user has requested a long counter (attr.config1) then we want to 560 * interrupt upon 32-bit overflow - we achieve this by applying a bias. 561 */ 562 static bool armv8pmu_event_needs_bias(struct perf_event *event) 563 { 564 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 565 struct hw_perf_event *hwc = &event->hw; 566 int idx = hwc->idx; 567 568 if (armv8pmu_event_is_64bit(event)) 569 return false; 570 571 if (armv8pmu_has_long_event(cpu_pmu) || 572 idx >= ARMV8_PMU_MAX_GENERAL_COUNTERS) 573 return true; 574 575 return false; 576 } 577 578 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value) 579 { 580 if (armv8pmu_event_needs_bias(event)) 581 value |= GENMASK_ULL(63, 32); 582 583 return value; 584 } 585 586 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value) 587 { 588 if (armv8pmu_event_needs_bias(event)) 589 value &= ~GENMASK_ULL(63, 32); 590 591 return value; 592 } 593 594 static u64 armv8pmu_read_counter(struct perf_event *event) 595 { 596 struct hw_perf_event *hwc = &event->hw; 597 int idx = hwc->idx; 598 u64 value; 599 600 if (idx == ARMV8_PMU_CYCLE_IDX) 601 value = read_pmccntr(); 602 else if (idx == ARMV8_PMU_INSTR_IDX) 603 value = read_pmicntr(); 604 else 605 value = armv8pmu_read_hw_counter(event); 606 607 return armv8pmu_unbias_long_counter(event, value); 608 } 609 610 static void armv8pmu_write_evcntr(int idx, u64 value) 611 { 612 write_pmevcntrn(idx, value); 613 } 614 615 static void armv8pmu_write_hw_counter(struct perf_event *event, 616 u64 value) 617 { 618 int idx = event->hw.idx; 619 620 if (armv8pmu_event_is_chained(event)) { 621 armv8pmu_write_evcntr(idx, upper_32_bits(value)); 622 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value)); 623 } else { 624 armv8pmu_write_evcntr(idx, value); 625 } 626 } 627 628 static void armv8pmu_write_counter(struct perf_event *event, u64 value) 629 { 630 struct hw_perf_event *hwc = &event->hw; 631 int idx = hwc->idx; 632 633 value = armv8pmu_bias_long_counter(event, value); 634 635 if (idx == ARMV8_PMU_CYCLE_IDX) 636 write_pmccntr(value); 637 else if (idx == ARMV8_PMU_INSTR_IDX) 638 write_pmicntr(value); 639 else 640 armv8pmu_write_hw_counter(event, value); 641 } 642 643 static void armv8pmu_write_evtype(int idx, unsigned long val) 644 { 645 unsigned long mask = ARMV8_PMU_EVTYPE_EVENT | 646 ARMV8_PMU_INCLUDE_EL2 | 647 ARMV8_PMU_EXCLUDE_EL0 | 648 ARMV8_PMU_EXCLUDE_EL1; 649 650 if (IS_ENABLED(CONFIG_ARM64)) 651 mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; 652 653 val &= mask; 654 write_pmevtypern(idx, val); 655 } 656 657 static void armv8pmu_write_event_type(struct perf_event *event) 658 { 659 struct hw_perf_event *hwc = &event->hw; 660 int idx = hwc->idx; 661 662 /* 663 * For chained events, the low counter is programmed to count 664 * the event of interest and the high counter is programmed 665 * with CHAIN event code with filters set to count at all ELs. 666 */ 667 if (armv8pmu_event_is_chained(event)) { 668 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN | 669 ARMV8_PMU_INCLUDE_EL2; 670 671 armv8pmu_write_evtype(idx - 1, hwc->config_base); 672 armv8pmu_write_evtype(idx, chain_evt); 673 } else { 674 if (idx == ARMV8_PMU_CYCLE_IDX) 675 write_pmccfiltr(hwc->config_base); 676 else if (idx == ARMV8_PMU_INSTR_IDX) 677 write_pmicfiltr(hwc->config_base); 678 else 679 armv8pmu_write_evtype(idx, hwc->config_base); 680 } 681 } 682 683 static u64 armv8pmu_event_cnten_mask(struct perf_event *event) 684 { 685 int counter = event->hw.idx; 686 u64 mask = BIT(counter); 687 688 if (armv8pmu_event_is_chained(event)) 689 mask |= BIT(counter - 1); 690 return mask; 691 } 692 693 static void armv8pmu_enable_counter(u64 mask) 694 { 695 /* 696 * Make sure event configuration register writes are visible before we 697 * enable the counter. 698 * */ 699 isb(); 700 write_pmcntenset(mask); 701 } 702 703 static void armv8pmu_enable_event_counter(struct perf_event *event) 704 { 705 struct perf_event_attr *attr = &event->attr; 706 u64 mask = armv8pmu_event_cnten_mask(event); 707 708 kvm_set_pmu_events(mask, attr); 709 710 /* We rely on the hypervisor switch code to enable guest counters */ 711 if (!kvm_pmu_counter_deferred(attr)) 712 armv8pmu_enable_counter(mask); 713 } 714 715 static void armv8pmu_disable_counter(u64 mask) 716 { 717 write_pmcntenclr(mask); 718 /* 719 * Make sure the effects of disabling the counter are visible before we 720 * start configuring the event. 721 */ 722 isb(); 723 } 724 725 static void armv8pmu_disable_event_counter(struct perf_event *event) 726 { 727 struct perf_event_attr *attr = &event->attr; 728 u64 mask = armv8pmu_event_cnten_mask(event); 729 730 kvm_clr_pmu_events(mask); 731 732 /* We rely on the hypervisor switch code to disable guest counters */ 733 if (!kvm_pmu_counter_deferred(attr)) 734 armv8pmu_disable_counter(mask); 735 } 736 737 static void armv8pmu_enable_intens(u64 mask) 738 { 739 write_pmintenset(mask); 740 } 741 742 static void armv8pmu_enable_event_irq(struct perf_event *event) 743 { 744 armv8pmu_enable_intens(BIT(event->hw.idx)); 745 } 746 747 static void armv8pmu_disable_intens(u64 mask) 748 { 749 write_pmintenclr(mask); 750 isb(); 751 /* Clear the overflow flag in case an interrupt is pending. */ 752 write_pmovsclr(mask); 753 isb(); 754 } 755 756 static void armv8pmu_disable_event_irq(struct perf_event *event) 757 { 758 armv8pmu_disable_intens(BIT(event->hw.idx)); 759 } 760 761 static u64 armv8pmu_getreset_flags(void) 762 { 763 u64 value; 764 765 /* Read */ 766 value = read_pmovsclr(); 767 768 /* Write to clear flags */ 769 value &= ARMV8_PMU_OVERFLOWED_MASK; 770 write_pmovsclr(value); 771 772 return value; 773 } 774 775 static void update_pmuserenr(u64 val) 776 { 777 lockdep_assert_irqs_disabled(); 778 779 /* 780 * The current PMUSERENR_EL0 value might be the value for the guest. 781 * If that's the case, have KVM keep tracking of the register value 782 * for the host EL0 so that KVM can restore it before returning to 783 * the host EL0. Otherwise, update the register now. 784 */ 785 if (kvm_set_pmuserenr(val)) 786 return; 787 788 write_pmuserenr(val); 789 } 790 791 static void armv8pmu_disable_user_access(void) 792 { 793 update_pmuserenr(0); 794 } 795 796 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) 797 { 798 int i; 799 u64 userenr = ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_UEN; 800 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 801 802 if (is_pmuv3p9(cpu_pmu->pmuver)) { 803 u64 mask = 0; 804 for_each_set_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { 805 if (armv8pmu_event_has_user_read(cpuc->events[i])) 806 mask |= BIT(i); 807 } 808 write_pmuacr(mask); 809 } else { 810 /* Clear any unused counters to avoid leaking their contents */ 811 for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, 812 ARMPMU_MAX_HWEVENTS) { 813 if (i == ARMV8_PMU_CYCLE_IDX) 814 write_pmccntr(0); 815 else if (i == ARMV8_PMU_INSTR_IDX) 816 write_pmicntr(0); 817 else 818 armv8pmu_write_evcntr(i, 0); 819 } 820 } 821 822 if (!cpu_pmu->avoid_pmccntr) 823 userenr |= ARMV8_PMU_USERENR_CR; 824 825 update_pmuserenr(userenr); 826 } 827 828 static void armv8pmu_enable_event(struct perf_event *event) 829 { 830 armv8pmu_write_event_type(event); 831 armv8pmu_enable_event_irq(event); 832 armv8pmu_enable_event_counter(event); 833 } 834 835 static void armv8pmu_disable_event(struct perf_event *event) 836 { 837 armv8pmu_disable_event_counter(event); 838 armv8pmu_disable_event_irq(event); 839 } 840 841 static void armv8pmu_start(struct arm_pmu *cpu_pmu) 842 { 843 struct perf_event_context *ctx; 844 struct pmu_hw_events *hw_events = this_cpu_ptr(cpu_pmu->hw_events); 845 int nr_user = 0; 846 847 ctx = perf_cpu_task_ctx(); 848 if (ctx) 849 nr_user = ctx->nr_user; 850 851 if (sysctl_perf_user_access && nr_user) 852 armv8pmu_enable_user_access(cpu_pmu); 853 else 854 armv8pmu_disable_user_access(); 855 856 kvm_vcpu_pmu_resync_el0(); 857 858 if (hw_events->branch_users) 859 brbe_enable(cpu_pmu); 860 861 /* Enable all counters */ 862 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E); 863 } 864 865 static void armv8pmu_stop(struct arm_pmu *cpu_pmu) 866 { 867 struct pmu_hw_events *hw_events = this_cpu_ptr(cpu_pmu->hw_events); 868 869 if (hw_events->branch_users) 870 brbe_disable(); 871 872 /* Disable all counters */ 873 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E); 874 } 875 876 static void read_branch_records(struct pmu_hw_events *cpuc, 877 struct perf_event *event, 878 struct perf_sample_data *data) 879 { 880 struct perf_branch_stack *branch_stack = cpuc->branch_stack; 881 882 brbe_read_filtered_entries(branch_stack, event); 883 perf_sample_save_brstack(data, event, branch_stack, NULL); 884 } 885 886 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) 887 { 888 u64 pmovsr; 889 struct perf_sample_data data; 890 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 891 struct pt_regs *regs; 892 int idx; 893 894 /* 895 * Get and reset the IRQ flags 896 */ 897 pmovsr = armv8pmu_getreset_flags(); 898 899 /* 900 * Did an overflow occur? 901 */ 902 if (!armv8pmu_has_overflowed(pmovsr)) 903 return IRQ_NONE; 904 905 /* 906 * Handle the counter(s) overflow(s) 907 */ 908 regs = get_irq_regs(); 909 910 /* 911 * Stop the PMU while processing the counter overflows 912 * to prevent skews in group events. 913 */ 914 armv8pmu_stop(cpu_pmu); 915 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { 916 struct perf_event *event = cpuc->events[idx]; 917 struct hw_perf_event *hwc; 918 919 /* Ignore if we don't have an event. */ 920 if (!event) 921 continue; 922 923 /* 924 * We have a single interrupt for all counters. Check that 925 * each counter has overflowed before we process it. 926 */ 927 if (!armv8pmu_counter_has_overflowed(pmovsr, idx)) 928 continue; 929 930 hwc = &event->hw; 931 armpmu_event_update(event); 932 perf_sample_data_init(&data, 0, hwc->last_period); 933 if (!armpmu_event_set_period(event)) 934 continue; 935 936 if (has_branch_stack(event)) 937 read_branch_records(cpuc, event, &data); 938 939 /* 940 * Perf event overflow will queue the processing of the event as 941 * an irq_work which will be taken care of in the handling of 942 * IPI_IRQ_WORK. 943 */ 944 perf_event_overflow(event, &data, regs); 945 } 946 armv8pmu_start(cpu_pmu); 947 948 return IRQ_HANDLED; 949 } 950 951 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc, 952 struct arm_pmu *cpu_pmu) 953 { 954 int idx; 955 956 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { 957 if (!test_and_set_bit(idx, cpuc->used_mask)) 958 return idx; 959 } 960 return -EAGAIN; 961 } 962 963 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, 964 struct arm_pmu *cpu_pmu) 965 { 966 int idx; 967 968 /* 969 * Chaining requires two consecutive event counters, where 970 * the lower idx must be even. 971 */ 972 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { 973 if (!(idx & 0x1)) 974 continue; 975 if (!test_and_set_bit(idx, cpuc->used_mask)) { 976 /* Check if the preceding even counter is available */ 977 if (!test_and_set_bit(idx - 1, cpuc->used_mask)) 978 return idx; 979 /* Release the Odd counter */ 980 clear_bit(idx, cpuc->used_mask); 981 } 982 } 983 return -EAGAIN; 984 } 985 986 static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc, 987 struct perf_event *event) 988 { 989 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 990 struct hw_perf_event *hwc = &event->hw; 991 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; 992 993 if (evtype != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) 994 return false; 995 996 /* 997 * A CPU_CYCLES event with threshold counting cannot use PMCCNTR_EL0 998 * since it lacks threshold support. 999 */ 1000 if (armv8pmu_event_get_threshold(&event->attr)) 1001 return false; 1002 1003 /* 1004 * PMCCNTR_EL0 is not affected by BRBE controls like BRBCR_ELx.FZP. 1005 * So don't use it for branch events. 1006 */ 1007 if (has_branch_stack(event)) 1008 return false; 1009 1010 if (cpu_pmu->avoid_pmccntr) 1011 return false; 1012 1013 return true; 1014 } 1015 1016 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, 1017 struct perf_event *event) 1018 { 1019 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1020 struct hw_perf_event *hwc = &event->hw; 1021 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; 1022 1023 /* Always prefer to place a cycle counter into the cycle counter. */ 1024 if (armv8pmu_can_use_pmccntr(cpuc, event)) { 1025 if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) 1026 return ARMV8_PMU_CYCLE_IDX; 1027 else if (armv8pmu_event_is_64bit(event) && 1028 armv8pmu_event_want_user_access(event) && 1029 !armv8pmu_has_long_event(cpu_pmu)) 1030 return -EAGAIN; 1031 } 1032 1033 /* 1034 * Always prefer to place a instruction counter into the instruction counter, 1035 * but don't expose the instruction counter to userspace access as userspace 1036 * may not know how to handle it. 1037 */ 1038 if ((evtype == ARMV8_PMUV3_PERFCTR_INST_RETIRED) && 1039 !armv8pmu_event_get_threshold(&event->attr) && 1040 test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) && 1041 !armv8pmu_event_want_user_access(event)) { 1042 if (!test_and_set_bit(ARMV8_PMU_INSTR_IDX, cpuc->used_mask)) 1043 return ARMV8_PMU_INSTR_IDX; 1044 } 1045 1046 /* 1047 * Otherwise use events counters 1048 */ 1049 if (armv8pmu_event_is_chained(event)) 1050 return armv8pmu_get_chain_idx(cpuc, cpu_pmu); 1051 else 1052 return armv8pmu_get_single_idx(cpuc, cpu_pmu); 1053 } 1054 1055 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1056 struct perf_event *event) 1057 { 1058 int idx = event->hw.idx; 1059 1060 clear_bit(idx, cpuc->used_mask); 1061 if (armv8pmu_event_is_chained(event)) 1062 clear_bit(idx - 1, cpuc->used_mask); 1063 } 1064 1065 static int armv8pmu_user_event_idx(struct perf_event *event) 1066 { 1067 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event)) 1068 return 0; 1069 1070 return event->hw.idx + 1; 1071 } 1072 1073 static void armv8pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, 1074 struct task_struct *task, bool sched_in) 1075 { 1076 struct arm_pmu *armpmu = to_arm_pmu(pmu_ctx->pmu); 1077 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events); 1078 1079 if (!hw_events->branch_users) 1080 return; 1081 1082 if (sched_in) 1083 brbe_invalidate(); 1084 } 1085 1086 /* 1087 * Add an event filter to a given event. 1088 */ 1089 static int armv8pmu_set_event_filter(struct hw_perf_event *event, 1090 struct perf_event_attr *attr) 1091 { 1092 unsigned long config_base = 0; 1093 struct perf_event *perf_event = container_of(attr, struct perf_event, 1094 attr); 1095 struct arm_pmu *cpu_pmu = to_arm_pmu(perf_event->pmu); 1096 u32 th; 1097 1098 if (attr->exclude_idle) { 1099 pr_debug("ARM performance counters do not support mode exclusion\n"); 1100 return -EOPNOTSUPP; 1101 } 1102 1103 if (has_branch_stack(perf_event)) { 1104 if (!brbe_num_branch_records(cpu_pmu) || !brbe_branch_attr_valid(perf_event)) 1105 return -EOPNOTSUPP; 1106 1107 perf_event->attach_state |= PERF_ATTACH_SCHED_CB; 1108 } 1109 1110 /* 1111 * If we're running in hyp mode, then we *are* the hypervisor. 1112 * Therefore we ignore exclude_hv in this configuration, since 1113 * there's no hypervisor to sample anyway. This is consistent 1114 * with other architectures (x86 and Power). 1115 */ 1116 if (is_kernel_in_hyp_mode()) { 1117 if (!attr->exclude_kernel && !attr->exclude_host) 1118 config_base |= ARMV8_PMU_INCLUDE_EL2; 1119 if (attr->exclude_guest) 1120 config_base |= ARMV8_PMU_EXCLUDE_EL1; 1121 if (attr->exclude_host) 1122 config_base |= ARMV8_PMU_EXCLUDE_EL0; 1123 } else { 1124 if (!attr->exclude_hv && !attr->exclude_host) 1125 config_base |= ARMV8_PMU_INCLUDE_EL2; 1126 } 1127 1128 /* 1129 * Filter out !VHE kernels and guest kernels 1130 */ 1131 if (attr->exclude_kernel) 1132 config_base |= ARMV8_PMU_EXCLUDE_EL1; 1133 1134 if (attr->exclude_user) 1135 config_base |= ARMV8_PMU_EXCLUDE_EL0; 1136 1137 /* 1138 * If FEAT_PMUv3_TH isn't implemented, then THWIDTH (threshold_max) will 1139 * be 0 and will also trigger this check, preventing it from being used. 1140 */ 1141 th = armv8pmu_event_get_threshold(attr); 1142 if (th > threshold_max(cpu_pmu)) { 1143 pr_debug("PMU event threshold exceeds max value\n"); 1144 return -EINVAL; 1145 } 1146 1147 if (th) { 1148 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TH, th); 1149 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TC, 1150 armv8pmu_event_threshold_control(attr)); 1151 } 1152 1153 /* 1154 * Install the filter into config_base as this is used to 1155 * construct the event type. 1156 */ 1157 event->config_base = config_base; 1158 1159 return 0; 1160 } 1161 1162 static void armv8pmu_reset(void *info) 1163 { 1164 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 1165 u64 pmcr, mask; 1166 1167 bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS); 1168 1169 /* The counter and interrupt enable registers are unknown at reset. */ 1170 armv8pmu_disable_counter(mask); 1171 armv8pmu_disable_intens(mask); 1172 1173 /* Clear the counters we flip at guest entry/exit */ 1174 kvm_clr_pmu_events(mask); 1175 1176 if (brbe_num_branch_records(cpu_pmu)) { 1177 brbe_disable(); 1178 brbe_invalidate(); 1179 } 1180 1181 /* 1182 * Initialize & Reset PMNC. Request overflow interrupt for 1183 * 64 bit cycle counter but cheat in armv8pmu_write_counter(). 1184 */ 1185 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC; 1186 1187 /* Enable long event counter support where available */ 1188 if (armv8pmu_has_long_event(cpu_pmu)) 1189 pmcr |= ARMV8_PMU_PMCR_LP; 1190 1191 armv8pmu_pmcr_write(pmcr); 1192 } 1193 1194 static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu, 1195 struct perf_event *event) 1196 { 1197 if (event->attr.type == PERF_TYPE_HARDWARE && 1198 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) { 1199 1200 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED, 1201 armpmu->pmceid_bitmap)) 1202 return ARMV8_PMUV3_PERFCTR_BR_RETIRED; 1203 1204 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED, 1205 armpmu->pmceid_bitmap)) 1206 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED; 1207 1208 return HW_OP_UNSUPPORTED; 1209 } 1210 1211 return armpmu_map_event(event, &armv8_pmuv3_perf_map, 1212 &armv8_pmuv3_perf_cache_map, 1213 ARMV8_PMU_EVTYPE_EVENT); 1214 } 1215 1216 static int __armv8_pmuv3_map_event(struct perf_event *event, 1217 const unsigned (*extra_event_map) 1218 [PERF_COUNT_HW_MAX], 1219 const unsigned (*extra_cache_map) 1220 [PERF_COUNT_HW_CACHE_MAX] 1221 [PERF_COUNT_HW_CACHE_OP_MAX] 1222 [PERF_COUNT_HW_CACHE_RESULT_MAX]) 1223 { 1224 int hw_event_id; 1225 struct arm_pmu *armpmu = to_arm_pmu(event->pmu); 1226 1227 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event); 1228 1229 /* 1230 * CHAIN events only work when paired with an adjacent counter, and it 1231 * never makes sense for a user to open one in isolation, as they'll be 1232 * rotated arbitrarily. 1233 */ 1234 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN) 1235 return -EINVAL; 1236 1237 if (armv8pmu_event_is_64bit(event)) 1238 event->hw.flags |= ARMPMU_EVT_64BIT; 1239 1240 /* 1241 * User events must be allocated into a single counter, and so 1242 * must not be chained. 1243 * 1244 * Most 64-bit events require long counter support, but 64-bit 1245 * CPU_CYCLES events can be placed into the dedicated cycle 1246 * counter when this is free. 1247 */ 1248 if (armv8pmu_event_want_user_access(event)) { 1249 if (!(event->attach_state & PERF_ATTACH_TASK)) 1250 return -EINVAL; 1251 if (armv8pmu_event_is_64bit(event) && 1252 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES || 1253 armpmu->avoid_pmccntr) && 1254 !armv8pmu_has_long_event(armpmu)) 1255 return -EOPNOTSUPP; 1256 1257 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; 1258 } 1259 1260 /* Only expose micro/arch events supported by this PMU */ 1261 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) 1262 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) { 1263 return hw_event_id; 1264 } 1265 1266 return armpmu_map_event(event, extra_event_map, extra_cache_map, 1267 ARMV8_PMU_EVTYPE_EVENT); 1268 } 1269 1270 static int armv8_pmuv3_map_event(struct perf_event *event) 1271 { 1272 return __armv8_pmuv3_map_event(event, NULL, NULL); 1273 } 1274 1275 static int armv8_a53_map_event(struct perf_event *event) 1276 { 1277 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map); 1278 } 1279 1280 static int armv8_a57_map_event(struct perf_event *event) 1281 { 1282 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map); 1283 } 1284 1285 static int armv8_a73_map_event(struct perf_event *event) 1286 { 1287 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map); 1288 } 1289 1290 static int armv8_thunder_map_event(struct perf_event *event) 1291 { 1292 return __armv8_pmuv3_map_event(event, NULL, 1293 &armv8_thunder_perf_cache_map); 1294 } 1295 1296 static int armv8_vulcan_map_event(struct perf_event *event) 1297 { 1298 return __armv8_pmuv3_map_event(event, NULL, 1299 &armv8_vulcan_perf_cache_map); 1300 } 1301 1302 #ifdef CONFIG_ARM64 1303 /* 1304 * List of CPUs that should avoid using PMCCNTR_EL0. 1305 */ 1306 static struct midr_range armv8pmu_avoid_pmccntr_cpus[] = { 1307 /* 1308 * NVIDIA Olympus may expose different WFI/WFE behaviour between the 1309 * PMCCNTR_EL0 and the CPU_CYCLES event on programmable counters. 1310 * While the CPU is in WFI/WFE state, the PMCCNTR_EL0 may still increment 1311 * but the programmable counter may not. This is an implementation specific 1312 * behavior and not an erratum. Perf assumes those two paths are 1313 * interchangeable, so avoid using PMCCNTR_EL0 for CPU_CYCLES event. 1314 * 1315 * From ARM DDI0487 D14.4: 1316 * It is IMPLEMENTATION SPECIFIC whether CPU_CYCLES and PMCCNTR count 1317 * when the PE is in WFI or WFE state, even if the clocks are not stopped. 1318 * 1319 * From ARM DDI0487 D24.5.2: 1320 * All counters are subject to any changes in clock frequency, including 1321 * clock stopping caused by the WFI and WFE instructions. 1322 * This means that it is CONSTRAINED UNPREDICTABLE whether or not 1323 * PMCCNTR_EL0 continues to increment when clocks are stopped by WFI and 1324 * WFE instructions. 1325 */ 1326 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 1327 {} 1328 }; 1329 1330 static bool armv8pmu_is_in_avoid_pmccntr_cpus(void) 1331 { 1332 return is_midr_in_range_list(armv8pmu_avoid_pmccntr_cpus); 1333 } 1334 #else 1335 static bool armv8pmu_is_in_avoid_pmccntr_cpus(void) 1336 { 1337 return false; 1338 } 1339 #endif 1340 1341 struct armv8pmu_probe_info { 1342 struct arm_pmu *pmu; 1343 bool present; 1344 }; 1345 1346 static void __armv8pmu_probe_pmu(void *info) 1347 { 1348 struct armv8pmu_probe_info *probe = info; 1349 struct arm_pmu *cpu_pmu = probe->pmu; 1350 u64 pmceid_raw[2]; 1351 u32 pmceid[2]; 1352 int pmuver; 1353 1354 pmuver = read_pmuver(); 1355 if (!pmuv3_implemented(pmuver)) 1356 return; 1357 1358 cpu_pmu->pmuver = pmuver; 1359 probe->present = true; 1360 1361 /* Read the nb of CNTx counters supported from PMNC */ 1362 bitmap_set(cpu_pmu->cntr_mask, 1363 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); 1364 1365 /* Add the CPU cycles counter */ 1366 set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask); 1367 1368 /* Add the CPU instructions counter */ 1369 if (pmuv3_has_icntr()) 1370 set_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask); 1371 1372 pmceid[0] = pmceid_raw[0] = read_pmceid0(); 1373 pmceid[1] = pmceid_raw[1] = read_pmceid1(); 1374 1375 bitmap_from_arr32(cpu_pmu->pmceid_bitmap, 1376 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1377 1378 pmceid[0] = pmceid_raw[0] >> 32; 1379 pmceid[1] = pmceid_raw[1] >> 32; 1380 1381 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap, 1382 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); 1383 1384 /* store PMMIR register for sysfs */ 1385 if (is_pmuv3p4(pmuver)) 1386 cpu_pmu->reg_pmmir = read_pmmir(); 1387 else 1388 cpu_pmu->reg_pmmir = 0; 1389 1390 /* 1391 * On some CPUs, PMCCNTR_EL0 does not match the behavior of CPU_CYCLES 1392 * programmable counter, so avoid routing cycles through PMCCNTR_EL0 to 1393 * prevent inconsistency in the results. 1394 */ 1395 cpu_pmu->avoid_pmccntr |= armv8pmu_is_in_avoid_pmccntr_cpus(); 1396 1397 brbe_probe(cpu_pmu); 1398 } 1399 1400 static int branch_records_alloc(struct arm_pmu *armpmu) 1401 { 1402 size_t size = struct_size_t(struct perf_branch_stack, entries, 1403 brbe_num_branch_records(armpmu)); 1404 int cpu; 1405 1406 for_each_cpu(cpu, &armpmu->supported_cpus) { 1407 struct pmu_hw_events *events_cpu; 1408 1409 events_cpu = per_cpu_ptr(armpmu->hw_events, cpu); 1410 events_cpu->branch_stack = kzalloc(size, GFP_KERNEL); 1411 if (!events_cpu->branch_stack) 1412 return -ENOMEM; 1413 } 1414 return 0; 1415 } 1416 1417 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu) 1418 { 1419 struct armv8pmu_probe_info probe = { 1420 .pmu = cpu_pmu, 1421 .present = false, 1422 }; 1423 int ret; 1424 1425 ret = smp_call_function_any(&cpu_pmu->supported_cpus, 1426 __armv8pmu_probe_pmu, 1427 &probe, 1); 1428 if (ret) 1429 return ret; 1430 1431 if (!probe.present) 1432 return -ENODEV; 1433 1434 if (brbe_num_branch_records(cpu_pmu)) { 1435 ret = branch_records_alloc(cpu_pmu); 1436 if (ret) 1437 return ret; 1438 } 1439 return 0; 1440 } 1441 1442 static void armv8pmu_disable_user_access_ipi(void *unused) 1443 { 1444 armv8pmu_disable_user_access(); 1445 } 1446 1447 static int armv8pmu_proc_user_access_handler(const struct ctl_table *table, int write, 1448 void *buffer, size_t *lenp, loff_t *ppos) 1449 { 1450 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 1451 if (ret || !write || sysctl_perf_user_access) 1452 return ret; 1453 1454 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1); 1455 return 0; 1456 } 1457 1458 static const struct ctl_table armv8_pmu_sysctl_table[] = { 1459 { 1460 .procname = "perf_user_access", 1461 .data = &sysctl_perf_user_access, 1462 .maxlen = sizeof(unsigned int), 1463 .mode = 0644, 1464 .proc_handler = armv8pmu_proc_user_access_handler, 1465 .extra1 = SYSCTL_ZERO, 1466 .extra2 = SYSCTL_ONE, 1467 }, 1468 }; 1469 1470 static void armv8_pmu_register_sysctl_table(void) 1471 { 1472 static u32 tbl_registered = 0; 1473 1474 if (!cmpxchg_relaxed(&tbl_registered, 0, 1)) 1475 register_sysctl("kernel", armv8_pmu_sysctl_table); 1476 } 1477 1478 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, 1479 int (*map_event)(struct perf_event *event)) 1480 { 1481 int ret = armv8pmu_probe_pmu(cpu_pmu); 1482 if (ret) 1483 return ret; 1484 1485 cpu_pmu->handle_irq = armv8pmu_handle_irq; 1486 cpu_pmu->enable = armv8pmu_enable_event; 1487 cpu_pmu->disable = armv8pmu_disable_event; 1488 cpu_pmu->read_counter = armv8pmu_read_counter; 1489 cpu_pmu->write_counter = armv8pmu_write_counter; 1490 cpu_pmu->get_event_idx = armv8pmu_get_event_idx; 1491 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx; 1492 cpu_pmu->start = armv8pmu_start; 1493 cpu_pmu->stop = armv8pmu_stop; 1494 cpu_pmu->reset = armv8pmu_reset; 1495 cpu_pmu->set_event_filter = armv8pmu_set_event_filter; 1496 1497 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx; 1498 if (brbe_num_branch_records(cpu_pmu)) 1499 cpu_pmu->pmu.sched_task = armv8pmu_sched_task; 1500 1501 cpu_pmu->name = name; 1502 cpu_pmu->map_event = map_event; 1503 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &armv8_pmuv3_events_attr_group; 1504 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv8_pmuv3_format_attr_group; 1505 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = &armv8_pmuv3_caps_attr_group; 1506 armv8_pmu_register_sysctl_table(); 1507 return 0; 1508 } 1509 1510 #define PMUV3_INIT_SIMPLE(name) \ 1511 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1512 { \ 1513 return armv8_pmu_init(cpu_pmu, #name, armv8_pmuv3_map_event); \ 1514 } 1515 1516 #define PMUV3_INIT_MAP_EVENT(name, map_event) \ 1517 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \ 1518 { \ 1519 return armv8_pmu_init(cpu_pmu, #name, map_event); \ 1520 } 1521 1522 PMUV3_INIT_SIMPLE(armv8_pmuv3) 1523 1524 PMUV3_INIT_SIMPLE(armv8_c1_nano) 1525 PMUV3_INIT_SIMPLE(armv8_c1_premium) 1526 PMUV3_INIT_SIMPLE(armv8_c1_pro) 1527 PMUV3_INIT_SIMPLE(armv8_c1_ultra) 1528 PMUV3_INIT_SIMPLE(armv8_cortex_a34) 1529 PMUV3_INIT_SIMPLE(armv8_cortex_a55) 1530 PMUV3_INIT_SIMPLE(armv8_cortex_a65) 1531 PMUV3_INIT_SIMPLE(armv8_cortex_a75) 1532 PMUV3_INIT_SIMPLE(armv8_cortex_a76) 1533 PMUV3_INIT_SIMPLE(armv8_cortex_a77) 1534 PMUV3_INIT_SIMPLE(armv8_cortex_a78) 1535 PMUV3_INIT_SIMPLE(armv9_cortex_a320) 1536 PMUV3_INIT_SIMPLE(armv9_cortex_a510) 1537 PMUV3_INIT_SIMPLE(armv9_cortex_a520) 1538 PMUV3_INIT_SIMPLE(armv9_cortex_a520ae) 1539 PMUV3_INIT_SIMPLE(armv9_cortex_a710) 1540 PMUV3_INIT_SIMPLE(armv9_cortex_a715) 1541 PMUV3_INIT_SIMPLE(armv9_cortex_a720) 1542 PMUV3_INIT_SIMPLE(armv9_cortex_a720ae) 1543 PMUV3_INIT_SIMPLE(armv9_cortex_a725) 1544 PMUV3_INIT_SIMPLE(armv8_cortex_x1) 1545 PMUV3_INIT_SIMPLE(armv9_cortex_x2) 1546 PMUV3_INIT_SIMPLE(armv9_cortex_x3) 1547 PMUV3_INIT_SIMPLE(armv9_cortex_x4) 1548 PMUV3_INIT_SIMPLE(armv9_cortex_x925) 1549 PMUV3_INIT_SIMPLE(armv8_neoverse_e1) 1550 PMUV3_INIT_SIMPLE(armv8_neoverse_n1) 1551 PMUV3_INIT_SIMPLE(armv9_neoverse_n2) 1552 PMUV3_INIT_SIMPLE(armv9_neoverse_n3) 1553 PMUV3_INIT_SIMPLE(armv8_neoverse_v1) 1554 PMUV3_INIT_SIMPLE(armv8_neoverse_v2) 1555 PMUV3_INIT_SIMPLE(armv8_neoverse_v3) 1556 PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) 1557 PMUV3_INIT_SIMPLE(armv8_rainier) 1558 1559 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) 1560 PMUV3_INIT_SIMPLE(armv8_nvidia_denver) 1561 1562 PMUV3_INIT_SIMPLE(armv8_samsung_mongoose) 1563 1564 PMUV3_INIT_MAP_EVENT(armv8_cortex_a35, armv8_a53_map_event) 1565 PMUV3_INIT_MAP_EVENT(armv8_cortex_a53, armv8_a53_map_event) 1566 PMUV3_INIT_MAP_EVENT(armv8_cortex_a57, armv8_a57_map_event) 1567 PMUV3_INIT_MAP_EVENT(armv8_cortex_a72, armv8_a57_map_event) 1568 PMUV3_INIT_MAP_EVENT(armv8_cortex_a73, armv8_a73_map_event) 1569 PMUV3_INIT_MAP_EVENT(armv8_cavium_thunder, armv8_thunder_map_event) 1570 PMUV3_INIT_MAP_EVENT(armv8_brcm_vulcan, armv8_vulcan_map_event) 1571 1572 static const struct of_device_id armv8_pmu_of_device_ids[] = { 1573 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init}, 1574 {.compatible = "arm,c1-nano-pmu", .data = armv8_c1_nano_pmu_init}, 1575 {.compatible = "arm,c1-premium-pmu", .data = armv8_c1_premium_pmu_init}, 1576 {.compatible = "arm,c1-pro-pmu", .data = armv8_c1_pro_pmu_init}, 1577 {.compatible = "arm,c1-ultra-pmu", .data = armv8_c1_ultra_pmu_init}, 1578 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init}, 1579 {.compatible = "arm,cortex-a35-pmu", .data = armv8_cortex_a35_pmu_init}, 1580 {.compatible = "arm,cortex-a53-pmu", .data = armv8_cortex_a53_pmu_init}, 1581 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init}, 1582 {.compatible = "arm,cortex-a57-pmu", .data = armv8_cortex_a57_pmu_init}, 1583 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init}, 1584 {.compatible = "arm,cortex-a72-pmu", .data = armv8_cortex_a72_pmu_init}, 1585 {.compatible = "arm,cortex-a73-pmu", .data = armv8_cortex_a73_pmu_init}, 1586 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init}, 1587 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init}, 1588 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init}, 1589 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init}, 1590 {.compatible = "arm,cortex-a320-pmu", .data = armv9_cortex_a320_pmu_init}, 1591 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init}, 1592 {.compatible = "arm,cortex-a520-pmu", .data = armv9_cortex_a520_pmu_init}, 1593 {.compatible = "arm,cortex-a520ae-pmu", .data = armv9_cortex_a520ae_pmu_init}, 1594 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init}, 1595 {.compatible = "arm,cortex-a715-pmu", .data = armv9_cortex_a715_pmu_init}, 1596 {.compatible = "arm,cortex-a720-pmu", .data = armv9_cortex_a720_pmu_init}, 1597 {.compatible = "arm,cortex-a720ae-pmu", .data = armv9_cortex_a720ae_pmu_init}, 1598 {.compatible = "arm,cortex-a725-pmu", .data = armv9_cortex_a725_pmu_init}, 1599 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init}, 1600 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init}, 1601 {.compatible = "arm,cortex-x3-pmu", .data = armv9_cortex_x3_pmu_init}, 1602 {.compatible = "arm,cortex-x4-pmu", .data = armv9_cortex_x4_pmu_init}, 1603 {.compatible = "arm,cortex-x925-pmu", .data = armv9_cortex_x925_pmu_init}, 1604 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init}, 1605 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init}, 1606 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init}, 1607 {.compatible = "arm,neoverse-n3-pmu", .data = armv9_neoverse_n3_pmu_init}, 1608 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init}, 1609 {.compatible = "arm,neoverse-v2-pmu", .data = armv8_neoverse_v2_pmu_init}, 1610 {.compatible = "arm,neoverse-v3-pmu", .data = armv8_neoverse_v3_pmu_init}, 1611 {.compatible = "arm,neoverse-v3ae-pmu", .data = armv8_neoverse_v3ae_pmu_init}, 1612 {.compatible = "arm,rainier-pmu", .data = armv8_rainier_pmu_init}, 1613 {.compatible = "cavium,thunder-pmu", .data = armv8_cavium_thunder_pmu_init}, 1614 {.compatible = "brcm,vulcan-pmu", .data = armv8_brcm_vulcan_pmu_init}, 1615 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init}, 1616 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init}, 1617 {.compatible = "samsung,mongoose-pmu", .data = armv8_samsung_mongoose_pmu_init}, 1618 {}, 1619 }; 1620 1621 static int armv8_pmu_device_probe(struct platform_device *pdev) 1622 { 1623 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL); 1624 } 1625 1626 static struct platform_driver armv8_pmu_driver = { 1627 .driver = { 1628 .name = ARMV8_PMU_PDEV_NAME, 1629 .of_match_table = armv8_pmu_of_device_ids, 1630 .suppress_bind_attrs = true, 1631 }, 1632 .probe = armv8_pmu_device_probe, 1633 }; 1634 1635 static int __init armv8_pmu_driver_init(void) 1636 { 1637 int ret; 1638 1639 if (acpi_disabled) 1640 ret = platform_driver_register(&armv8_pmu_driver); 1641 else 1642 ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); 1643 1644 if (!ret) 1645 lockup_detector_retry_init(); 1646 1647 return ret; 1648 } 1649 device_initcall(armv8_pmu_driver_init) 1650 1651 void arch_perf_update_userpage(struct perf_event *event, 1652 struct perf_event_mmap_page *userpg, u64 now) 1653 { 1654 struct clock_read_data *rd; 1655 unsigned int seq; 1656 u64 ns; 1657 1658 userpg->cap_user_time = 0; 1659 userpg->cap_user_time_zero = 0; 1660 userpg->cap_user_time_short = 0; 1661 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event); 1662 1663 if (userpg->cap_user_rdpmc) { 1664 if (event->hw.flags & ARMPMU_EVT_64BIT) 1665 userpg->pmc_width = 64; 1666 else 1667 userpg->pmc_width = 32; 1668 } 1669 1670 do { 1671 rd = sched_clock_read_begin(&seq); 1672 1673 if (rd->read_sched_clock != arch_timer_read_counter) 1674 return; 1675 1676 userpg->time_mult = rd->mult; 1677 userpg->time_shift = rd->shift; 1678 userpg->time_zero = rd->epoch_ns; 1679 userpg->time_cycles = rd->epoch_cyc; 1680 userpg->time_mask = rd->sched_clock_mask; 1681 1682 /* 1683 * Subtract the cycle base, such that software that 1684 * doesn't know about cap_user_time_short still 'works' 1685 * assuming no wraps. 1686 */ 1687 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift); 1688 userpg->time_zero -= ns; 1689 1690 } while (sched_clock_read_retry(seq)); 1691 1692 userpg->time_offset = userpg->time_zero - now; 1693 1694 /* 1695 * time_shift is not expected to be greater than 31 due to 1696 * the original published conversion algorithm shifting a 1697 * 32-bit value (now specifies a 64-bit value) - refer 1698 * perf_event_mmap_page documentation in perf_event.h. 1699 */ 1700 if (userpg->time_shift == 32) { 1701 userpg->time_shift = 31; 1702 userpg->time_mult >>= 1; 1703 } 1704 1705 /* 1706 * Internal timekeeping for enabled/running/stopped times 1707 * is always computed with the sched_clock. 1708 */ 1709 userpg->cap_user_time = 1; 1710 userpg->cap_user_time_zero = 1; 1711 userpg->cap_user_time_short = 1; 1712 } 1713